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AlexKlimajAlexKlimaj
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boards: new ARK Septentrio GPS CAN node(ark_septentrio-gps)
* update gps submodule with sbf fix * ARK Septentrio GPS initial commit
1 parent b355c16 commit 31bbda0

25 files changed

+1846
-1
lines changed

‎.github/workflows/compile_nuttx.yml

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@@ -25,6 +25,7 @@ jobs:
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ark_can-rtk-gps,
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ark_cannode,
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ark_fmu-v6x,
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ark_septentrio-gps,
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atl_mantis-edu,
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av_x-v1,
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bitcraze_crazyflie,

‎.vscode/cmake-variants.yaml

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@@ -151,6 +151,16 @@ CONFIG:
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buildType: MinSizeRel
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settings:
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CONFIG: ark_can-rtk-gps_canbootloader
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ark_septentrio_gps_default:
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short: ark_septentrio_gps_default
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buildType: MinSizeRel
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settings:
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CONFIG: ark_septentrio_gps_default
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ark_septentrio_gps_canbootloader:
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short: ark_septentrio_gps_canbootloader
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buildType: MinSizeRel
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settings:
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CONFIG: ark_septentrio_gps_canbootloader
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ark_cannode_default:
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short: ark_cannode_default
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buildType: MinSizeRel

‎boards/ark/septentrio-gps/canbootloader.px4board

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CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
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CONFIG_BOARD_ARCHITECTURE="cortex-m4"
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CONFIG_BOARD_ROMFSROOT=""
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CONFIG_BOARD_CONSTRAINED_MEMORY=y
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CONFIG_DRIVERS_BOOTLOADERS=y

‎boards/ark/septentrio-gps/default.px4board

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CONFIG_BOARD_TOOLCHAIN="arm-none-eabi"
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CONFIG_BOARD_ARCHITECTURE="cortex-m4"
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CONFIG_BOARD_ROMFSROOT="cannode"
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CONFIG_BOARD_NO_HELP=y
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CONFIG_BOARD_CONSTRAINED_MEMORY=y
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CONFIG_DRIVERS_BAROMETER_BMP388=y
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CONFIG_DRIVERS_BOOTLOADERS=y
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CONFIG_DRIVERS_GPS=y
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CONFIG_DRIVERS_IMU_INVENSENSE_ICM42688P=y
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CONFIG_DRIVERS_MAGNETOMETER_BOSCH_BMM150=y
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CONFIG_DRIVERS_SAFETY_BUTTON=y
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CONFIG_DRIVERS_TONE_ALARM=y
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CONFIG_BOARD_UAVCAN_INTERFACES=1
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CONFIG_DRIVERS_UAVCANNODE=y
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CONFIG_UAVCANNODE_BEEP_COMMAND=y
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CONFIG_UAVCANNODE_GNSS_FIX=y
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CONFIG_UAVCANNODE_LIGHTS_COMMAND=y
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CONFIG_UAVCANNODE_MAGNETIC_FIELD_STRENGTH=y
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CONFIG_UAVCANNODE_RTK_DATA=y
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CONFIG_UAVCANNODE_SAFETY_BUTTON=y
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CONFIG_UAVCANNODE_STATIC_PRESSURE=y
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CONFIG_UAVCANNODE_STATIC_TEMPERATURE=y
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CONFIG_MODULES_GYRO_CALIBRATION=y
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CONFIG_MODULES_MAG_BIAS_ESTIMATOR=y
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CONFIG_MODULES_SENSORS=y
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# CONFIG_SENSORS_VEHICLE_AIRSPEED is not set
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# CONFIG_SENSORS_VEHICLE_AIR_DATA is not set
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# CONFIG_SENSORS_VEHICLE_GPS_POSITION is not set
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CONFIG_SYSTEMCMDS_PARAM=y
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CONFIG_SYSTEMCMDS_PERF=y
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CONFIG_SYSTEMCMDS_REBOOT=y
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CONFIG_SYSTEMCMDS_SYSTEM_TIME=y
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CONFIG_SYSTEMCMDS_TOP=y
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CONFIG_SYSTEMCMDS_TOPIC_LISTENER=y
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CONFIG_SYSTEMCMDS_UORB=y
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CONFIG_SYSTEMCMDS_VER=y
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CONFIG_SYSTEMCMDS_WORK_QUEUE=y

‎boards/ark/septentrio-gps/firmware.prototype

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{
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"board_id": 84,
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"magic": "PX4FWv1",
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"description": "Firmware for the ARK Septentrio GPS board",
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"image": "",
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"build_time": 0,
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"summary": "ARKSEPTENTRIOGPS",
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"version": "0.1",
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"image_size": 0,
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"image_maxsize": 2080768,
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"git_identity": "",
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"board_revision": 0
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}

‎boards/ark/septentrio-gps/init/rc.board_defaults

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#!/bin/sh
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#
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# board specific defaults
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#------------------------------------------------------------------------------
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param set-default CBRK_IO_SAFETY 0
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param set-default CANNODE_SUB_MBD 1
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param set-default CANNODE_SUB_RTCM 1
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param set-default MBE_ENABLE 1
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param set-default SENS_IMU_CLPNOTI 0
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safety_button start
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tone_alarm start

‎boards/ark/septentrio-gps/init/rc.board_sensors

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#!/bin/sh
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#
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# board sensors init
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#------------------------------------------------------------------------------
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gps start -d /dev/ttyS0 -p sbf
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icm42688p -R 0 -s start
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bmp388 -I -b 1 start
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bmm150 -I -b 1 start

‎boards/ark/septentrio-gps/nuttx-config/canbootloader/defconfig

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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD_CUSTOM=y
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CONFIG_ARCH_BOARD_CUSTOM_DIR="../../../../boards/ark/septentrio-gps/nuttx-config"
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CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y
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CONFIG_ARCH_BOARD_CUSTOM_NAME="px4"
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CONFIG_ARCH_CHIP="stm32"
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CONFIG_ARCH_CHIP_STM32=y
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CONFIG_ARCH_CHIP_STM32F412CE=y
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CONFIG_ARCH_INTERRUPTSTACK=4096
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CONFIG_ARMV7M_MEMCPY=y
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CONFIG_ARMV7M_USEBASEPRI=y
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CONFIG_BINFMT_DISABLE=y
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CONFIG_BOARDCTL=y
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CONFIG_BOARD_LOOPSPERMSEC=16717
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEBUG_TCBINFO=y
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CONFIG_DEFAULT_SMALL=y
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CONFIG_DISABLE_MOUNTPOINT=y
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CONFIG_EXPERIMENTAL=y
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CONFIG_FDCLONE_DISABLE=y
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CONFIG_FDCLONE_STDIO=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_IDLETHREAD_STACKSIZE=4096
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CONFIG_INIT_STACKSIZE=4096
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CONFIG_LIBC_FLOATINGPOINT=y
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CONFIG_LIBC_LONG_LONG=y
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CONFIG_LIBC_STRERROR=y
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CONFIG_MM_REGIONS=2
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CONFIG_NAME_MAX=0
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CONFIG_NUNGET_CHARS=0
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CONFIG_PREALLOC_TIMERS=0
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CONFIG_PTHREAD_STACK_MIN=512
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CONFIG_RAM_SIZE=262144
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CONFIG_RAM_START=0x20010000
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CONFIG_RAW_BINARY=y
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CONFIG_SIG_DEFAULT=y
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CONFIG_SIG_SIGALRM_ACTION=y
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CONFIG_SIG_SIGUSR1_ACTION=y
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CONFIG_SIG_SIGUSR2_ACTION=y
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CONFIG_STACK_COLORATION=y
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CONFIG_START_DAY=30
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CONFIG_START_MONTH=11
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CONFIG_STDIO_DISABLE_BUFFERING=y
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CONFIG_STM32_NOEXT_VECTORS=y
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CONFIG_STM32_TIM8=y
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CONFIG_TASK_NAME_SIZE=0
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CONFIG_USEC_PER_TICK=1000

‎boards/ark/septentrio-gps/nuttx-config/include/board.h

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/************************************************************************************
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* configs/px4fmu/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <[email protected]>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#include "board_dma_map.h"
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#ifndef __ARCH_BOARD_BOARD_H
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#define __ARCH_BOARD_BOARD_H
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include <stm32.h>
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/* HSI - 8 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - 8 MHz Crystal
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* LSE - not installed
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*/
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#define STM32_BOARD_USEHSE 1
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#define STM32_BOARD_XTAL 8000000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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/* Main PLL Configuration */
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/
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#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL
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#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
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#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
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#define STM32_SYSCLK_FREQUENCY 96000000ul
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/* AHB clock (HCLK) is SYSCLK (96MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (96MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
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/* Timers driven from APB2 will be PCLK2 since no prescale division */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
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#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
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/* Alternate function pin selections ************************************************/
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/* UARTs */
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#define GPIO_USART1_RX GPIO_USART1_RX_2
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#define GPIO_USART1_TX GPIO_USART1_TX_3
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#define GPIO_USART2_RX GPIO_USART2_RX_1
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#define GPIO_USART2_TX GPIO_USART2_TX_1
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/* CAN */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_1
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#define GPIO_CAN1_TX GPIO_CAN1_TX_1
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/* I2C */
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#define GPIO_MCU_I2C1_SCL
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#define GPIO_MCU_I2C1_SDA
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
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#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
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#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4
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#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
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#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
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/* SPI */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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#endif /* __ARCH_BOARD_BOARD_H */

‎boards/ark/septentrio-gps/nuttx-config/include/board_dma_map.h

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/****************************************************************************
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*
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* Copyright (c) 2021 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
10+
* notice, this list of conditions and the following disclaimer.
11+
* 2. Redistributions in binary form must reproduce the above copyright
12+
* notice, this list of conditions and the following disclaimer in
13+
* the documentation and/or other materials provided with the
14+
* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
17+
* without specific prior written permission.
18+
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20+
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
23+
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
24+
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
25+
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
26+
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
27+
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28+
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
29+
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30+
* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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// DMA1 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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// DMA2 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3
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#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3
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#define DMACHAN_USART1_RX DMAMAP_USART1_RX_1 // DMA2, Stream 2, Channel 4
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#define DMAMAP_USART1_RX DMAMAP_USART1_RX_1
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//#define DMACHAN_USART1_TX DMAMAP_USART1_TX // DMA2, Stream 7, Channel 4

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