Merge pull request #9 from FPGAArcade/dyn_clock_freq

Add support for updating the 68060 CPU clock

Author: erique

Replay_Boot/fpga.c

@@ -751,9 +751,11 @@ void FPGA_ClockMon(status_t* currentStatus)
 
     if (stat != old_stat) {
         old_stat = stat;
-        DEBUG(0, "Clock change : %02X", stat);
+        DEBUG(0, "RTG Clock change : %02X", stat);
         DEBUG(0, " status %04X", (uint16_t)OSD_ConfigReadStatus());
 
+        clockconfig_t clkcfg = currentStatus->clock_cfg; // copy
+
         if (stat == 0 || stat == 8) { // default clock
             // (RTG enabled with sys clock is 8, but we could change the filters etc)
 
@@ -768,8 +770,6 @@ void FPGA_ClockMon(status_t* currentStatus)
 
             Configure_VidBuf(3, currentStatus->filter_cfg.stc, currentStatus->filter_cfg.lpf, currentStatus->filter_cfg.mode);
 
-            Configure_ClockGen(&currentStatus->clock_cfg);
-
         } else {
 
             // coder off
@@ -780,9 +780,6 @@ void FPGA_ClockMon(status_t* currentStatus)
             Configure_VidBuf(2, 0, 3, 3);
             Configure_VidBuf(3, 0, 3, 3);
 
-            // jump to light speed
-            clockconfig_t clkcfg = currentStatus->clock_cfg; // copy
-
             switch (stat & 0x07) { // ignore top bit
                 //27 *  280/ 33  N/M
                 case 6 : // 114.50 MHz
@@ -835,9 +832,11 @@ void FPGA_ClockMon(status_t* currentStatus)
 
             }
 
-            Configure_ClockGen(&clkcfg);
         }
 
+        // Configure_ClockGen(&clkcfg);
+        UpdatePLL(3, clkcfg.pll3_m, clkcfg.pll3_n, clkcfg.p_sel[4], clkcfg.p_div[4], 4);
+
         // let clock settle
         Timer_Wait(100);
 
@@ -866,6 +865,38 @@ void FPGA_ClockMon(status_t* currentStatus)
         OSD_Reset(OSDCMD_CTRL_RES_VID);
 
     }
+
+
+    static uint8_t old_cpu = 0x00;
+    uint8_t cpu = (OSD_ConfigReadStatus()) & 0xff;
+
+    if (cpu != old_cpu) {
+        old_cpu = cpu;
+        DEBUG(0, "CPU Clock change : %02X", cpu);
+        DEBUG(0, " status %04X", (uint16_t)OSD_ConfigReadStatus());
+
+        clockconfig_t clkcfg = currentStatus->clock_cfg; // copy
+
+        if (cpu != 0)
+        {
+            uint32_t div = 2;
+            while(cpu*div < 80)
+                div++;
+
+            DEBUG(0, "CPU Freq: %d", cpu);
+            DEBUG(0, "DIV: %d", div);
+            DEBUG(0, "N2: %d", cpu*div);        
+
+            clkcfg.pll2_m = 27;
+            clkcfg.pll2_n = cpu*div;
+            clkcfg.p_sel[2] = 2; // pll2
+            clkcfg.p_div[2] = div; // div
+            clkcfg.y_sel[2] = 1; // on
+
+        }
+
+        UpdatePLL(2, clkcfg.pll2_m, clkcfg.pll2_n, clkcfg.p_sel[2], clkcfg.p_div[2], 2);
+    }
 }
 
 //

Replay_Boot/twi.c

@@ -421,6 +421,115 @@ void Configure_ClockGen(const clockconfig_t* config)
     // 74.25                        M= 2  N=11   Fvco=148.5 p=2  output = 74.25  (vfo=0)
 }
 
+void UpdatePLL(uint32_t pll, uint32_t m, uint32_t n, uint32_t pll_sel, uint32_t div, uint32_t y)
+{
+    // pll = {1,2,3}
+    // m = {1,511}
+    // n = {1,4095}
+    // div = {1,127}
+    // y = {0,5}
+/*
+1. Disable Y output
+2. Bypass PLLx
+3. Write new N/M values
+4. Disable bypass
+5. Set source PLL (Switch A)
+6. Write new Ydiv value
+7. Wait some arbitrary amount of time
+8. Re-enable Y (Switch B)
+*/
+    DEBUG(0, "SetPLL(pll = %d, m = %d, n= %d, pll_sel = %d, div = %d, y = %d)", pll, m, n, pll_sel, div, y);
+
+    // This PLL bit position is used in both register 3 and register 6
+    const uint8_t pll_conf_bit = 1 << (8-pll);
+
+    DEBUG(2, "Reading regs before switch");
+    for (uint8_t addr = 0; addr < 24; addr++) {
+        Read_CDCE906(addr+1);
+    }
+
+    DEBUG(2, "Making the switch");
+
+    // Disable Y (keep nominal slew, non-inverted; Y div selection is reset)
+    Write_CDCE906(19 + y, 0x30);
+
+    // Bypass PLLx (read/modify/write to enable VCO bypass in the PLL MUX)
+    uint8_t reg3 = Read_CDCE906(3);
+    reg3 |= pll_conf_bit;
+    Write_CDCE906(3, reg3);
+
+    // Update M/N
+    uint8_t lo_m = m & 0xff;        // separate lower bytes
+    uint8_t lo_n = n & 0xff;
+
+    uint8_t hi_m = (m >> 8) & 1;    // isolate upper bits (1 for M, 4 for N)
+    uint8_t hi_n = (n >> (8-1)) & (0xf << 1); // and move into place
+
+    uint8_t mn_base = 1+(pll-1)*3;  // base register for PLL M/N settings
+
+    // read/modify/write keeping the upper 3 bits, which holds MUX/fVCOsel/PLL selection
+    uint8_t hi = Read_CDCE906(mn_base+2) & 0xe0;
+
+    Write_CDCE906(mn_base+0, lo_m);
+    Write_CDCE906(mn_base+1, lo_n);
+    Write_CDCE906(mn_base+2, hi | hi_n | hi_m);
+
+    // Update VCO filter (read/modify/write, above 190Mhz we enable the fVCO filter)
+    const uint32_t fvco = 27000 * n / m;
+    DEBUG(0, "freq = %d", fvco/div);
+    uint8_t reg6 = Read_CDCE906(6);
+    reg6 &= ~pll_conf_bit;
+    reg6 |= (fvco > 190000) ? pll_conf_bit : 0;
+    Write_CDCE906(6, reg6);
+
+    // Update source PLL (setting is split over registers 9 through 12)
+    uint8_t regPx = 9+y;
+    uint8_t shiftPx = 5;
+    switch(y)
+    {
+        case 2: // reg 11
+        case 3: // reg 11
+        case 4: // reg 12
+        case 5: // reg 12
+            regPx = 11+y/4; // write reg 11/12
+            shiftPx = ((y&1) ? 3 : 0); // odd Px in upper position
+          break;
+    }
+
+    // Read/modify/write, updating the SWAPxy /Px
+    uint32_t valPx = Read_CDCE906(regPx);
+    valPx &= ~(0x7 << shiftPx);
+    valPx |= (pll_sel << shiftPx);
+    Write_CDCE906(regPx, valPx);
+
+    // Update Ydiv
+    Write_CDCE906(13 + y, (div & 0x7f));
+
+    // let clock settle
+    Timer_Wait(100);
+
+    // Disable bypass PLLx (read/modify/write to mask the VCO bypass bit)
+    reg3 = Read_CDCE906(3);
+    reg3 &= ~pll_conf_bit;
+    Write_CDCE906(3, reg3);
+
+    // let clock settle
+    Timer_Wait(100);
+
+    // Enable Y (nominal slew, non-inverted, static Ydiv selection, Yx enabled)
+    Write_CDCE906(19 + y, 0x30 | 0x08 | (y & 7));
+
+    // let clock settle
+    Timer_Wait(100);
+
+    DEBUG(2, "Reading regs after switch");
+    for (uint8_t addr = 0; addr < 24; addr++) {
+        Read_CDCE906(addr+1);
+    }
+
+    DEBUG(1, "Switch done");
+}
+
 void Write_CH7301(uint8_t address, uint8_t data)
 {
     uint8_t rab = 0x80 | (address & 0x7F);

Replay_Boot/twi.h

@@ -76,6 +76,8 @@ void    Write_CDCE906(uint8_t Address, uint8_t Data);
 void Configure_VidBuf(uint8_t chan, uint8_t stc, uint8_t lpf, uint8_t mode);
 void Configure_ClockGen(const clockconfig_t* config);
 
+void UpdatePLL(uint32_t pll, uint32_t m, uint32_t n, uint32_t pll_sel, uint32_t div, uint32_t y);
+
 void Write_CH7301(uint8_t address, uint8_t data);
 uint8_t Read_CH7301(uint8_t address);
 void Configure_CH7301(const vidconfig_t* config);