KiCad example loading

[gh-jmg]

Hi,
Nice project. Checking the nice KiCad ported files you have I see some small issues

a) SCH files open, but minus some symbols.
I need to go Preferences.Component Libraries, and add your local library to the list.
Then, all symbols render OK

b) icezum.KiCad_pcb seems load parts and outline correctly, but looks to be 100% unrouted ? (no traces?)
Or, is it intentional this is unrouted ?

[Obijuan]

Hi!

Thanks for you feedback

a) Checkout the develop branch and test it again: https://github.com/FPGAwars/icezum/tree/develop

The library should be automatically loaded. If not, please, tell me in this issue

b) The board is currently being routed in the develop branch. All the placement is finished, all the 3D component have modeled (in freecad) and the routing is 20% (only the first layer). I hope that the migration to kicad will be finished in around two weeks

Any feedback is welcome :-)

[gh-jmg]

Hi Juan,

a) Checkout the develop branch and test it again:

https://github.com/FPGAwars/icezum/tree/develop

The library should be automatically loaded. If not, please, tell me in
this issue

I'll check this tomorrow.

b) The board is currently being routed in the develop branch. All the
placement is finished, all the 3D component have modeled (in freecad) and
the routing is 20% (only the first layer). I hope that the migration to
kicad will be finished in around two weeks

ok, I was not sure if that unrouted was accidental.Look forward to seeing
the finished design.
If you do this in Altium, you could consider release of both P-CAD and
KiCad formats, as the kiCad PCAD importer is being improved all the time.
That also allows Eagle users to import the design too.

Did you consider doing anything with the Lattice 48 pin QFN iCE5x series ?
They still lack an eval board for those....

[Obijuan]

If you do this in Altium, you could consider release of both P-CAD and KiCad formats, as the kiCad PCAD importer is being improved all the time. That also allows Eagle users to import the design too.

Thanks for the tip!

Did you consider doing anything with the Lattice 48 pin QFN iCE5x series ? They still lack an eval board for those....

I am not sure if that series are supported by the opensource icestorm toolschain. If not, they will be in the future, I am sure

[gh-jmg]

Hi Juan,

b) The board is currently being routed in the develop branch. All the

placement is finished, all the 3D component have modeled (in freecad) and
the routing is 20% (only the first layer). I hope that the migration to
kicad will be finished in around two week

I can see progress in this :)
I'm curious, if you have this routed in Altium, why do you need to re-route
it in KiCad ?
Did the porting/translation pathways have some issues ?

-jg

[Obijuan]

I am just routing it myself for learning Kicad. Also for learning all the icezum details. The board was routed by Eladio, a college of mine, in Altium. I want to re-do it again in Kicad, for having in mind all the details.

[gh-jmg]

HI Juan,

I am just routing it myself for learning Kicad.

Ah, that makes sense.

Also for learning all the icezum details.

The board was routed by Eladio, a college of mine, in Altium.

I want to re-do it again in Kicad, for having in mind all the details.

You should be able to import from Altium, but I guess it depends on how
many changes are also merged in.
I've found KiCad seems to tolerate small end alignment deviations, (ie
slightly off exact pad centre)

I'm also new to KiCad, but it is growing on me,
The Shove router is very nice, and has better cleaning algorithms than
Mentors.
The mouse wheel navigation with rate-based zoom is also novel, and the more
I use that, the more adept I get and the more I like it. One hand for
navigate and one hand for commands, is nice.

[gh-jmg]

Hi Juan, I see a finished? design recently posted - looks nice :) Some comments/observations C31 is labeled 4.7nF, but maybe meant 4.7uF ? When I use MicroUSB, I choose ones with through-holes (eg 4x) on the outer framework. Usually those are short, (< 1.6mm), but give both location and more strength and less likely to 'rip-off' from accidents. regards Jim G. ​

[Obijuan]

see a finished? design recently posted - looks nice :)

Thanks! It is almost finished

Some comments/observations C31 is labeled 4.7nF, but maybe meant 4.7uF ?

Yeah! It is a bug. I've already fix it in this commit. Thanks a lot for reporting:-)

When I use MicroUSB, I choose ones with through-holes (eg 4x) on the outer framework. Usually those are short, (< 1.6mm), but give both location and more strength and less likely to 'rip-off' from accidents

Thanks for the advice. It makes more sense to use your MicroUSB. We will use them in future versions

I will close this issue. If you have further comments or bugs, please do not hesitate on filling a issue

Thanks for you help ;-)

[gh-jmg]

Hi Juan,

Using this design as a nice test for kiCad scripts, I notice a couple of
things :

a) There are a few thermal vias, that have imported as parts from Altium

This gives a skew to the BOM and netlist
BOM has ~ 26 extra parts like this...
VIA** pad-via
VIA** pad-via
Netlist has 26 extra nodes
VIA**.~

BOM and Netlist will be cleaner, & need less manual cleanup, if those
Thermal Vias can be swallowed into the footprints ?
​
b) Some entities are modules with zero pads, so I added a test to skip
these.
(These can also confuse the BOM )
These may be just dummy place keepers ?

REMARK Skipped doc1 (has 0 Pads)
REMARK Skipped DOC1 (has 0 Pads)
REMARK Skipped doc7 (has 0 Pads)
REMARK Skipped doc2 (has 0 Pads)
REMARK Skipped doc3 (has 0 Pads)
REMARK Skipped doc10 (has 0 Pads)
REMARK Skipped DOC3 (has 0 Pads)
REMARK Skipped doc4 (has 0 Pads)
REMARK Skipped doc5 (has 0 Pads)
REMARK Skipped doc6 (has 0 Pads)
REMARK Skipped doc8 (has 0 Pads)
REMARK Skipped doc9 (has 0 Pads)
REMARK Skipped JPM1 (has 0 Pads)
REMARK Skipped DOC4 (has 0 Pads)
REMARK Skipped DOC5 (has 0 Pads)
REMARK Skipped G*** (has 0 Pads)
REMARK Skipped REF*** (has 0 Pads)
REMARK Skipped DRILL2 (has 0 Pads)
REMARK Skipped DRILL4 (has 0 Pads)
REMARK Skipped DRILL3 (has 0 Pads)
REMARK Skipped DRILL1 (has 0 Pads)

regards
Jim G

[Obijuan]

Hi @gh-jmg !

I've created two new issues to discuss there: #28 and #29

Thanks a lot!

[gh-jmg]

Hi Juan,

FYI, I just came across this
http://www.zofzpcb.com/

A 3D Gerber viewer, quite impressive.
I plotted using Altium GBR names, which it seems to better sense of, & I
drop a .D356 file into the GBR directory.

It can also load IPC356, and check a design.

So, I feed latest Icezum into this.... just to see what happens...

See attached image - it has mostly inferred correct 3D info :)

The Via** parts have confused it a little, as it thinks they are all one
part, so it makes a single, large rectangle covering all Via**, and it
also thinks they are pins, so renders as that, with 'bonus spines'.

Moving those thermal vias into footprints, (or even just as manual Vias) as
suggested before, should clean that up.

It renders non-trace holes differently from trace-holes for some strange
reason, I think a ZofzPCB bug ?

It renders U6 with a strange angle spin, not sure why ?

Hmm, looking closely, U6 is unusual, and it has guessed a ~SO16N (almost,
pin pitch is not same on each side ?), and maybe the pin-centroid is
skewed (tho centroid seems square to me ?)
That may be a ZofzPCB quirk, but is is doing a quite good job of inferring
3D onto the Gerber + IPC info

Attached is the Screen grab, and the IPC error report.

​I see some Gerbers from your github have teardrops - were those Kicad
plotted ?

There is this
https://forum.kicad.info/t/yet-another-python-teardrop-script-adds-and-deletes-teardrops-to-a-pcb-v0-3-0/3388
I suggested he add Curved Teardrops, and they are now in :) - I've not
tested this yet.

ICP356 Netlis v.s. PCB copper test
965 total testpoints processed

27 of No-copper testpoint errors
No copper for Testpoint +5V_P layer both at (41.7, 43.8)mm
No copper for Testpoint +5V_P layer both at (39.1, 43.8)mm
No copper for Testpoint +5V_P layer both at (36.6, 43.8)mm
No copper for Testpoint +5V_P layer both at (34.0, 43.8)mm
No copper for Testpoint +5V_P layer both at (31.5, 43.8)mm
No copper for Testpoint +5V_P layer both at (29.0, 43.8)mm
No copper for Testpoint +5V_P layer both at (47.0, 9.5)mm
No copper for Testpoint +5V_P layer both at (49.5, 9.5)mm
No copper for Testpoint +5V_P layer both at (52.1, 9.5)mm
No copper for Testpoint +5V_P layer both at (54.6, 9.5)mm
No copper for Testpoint +5V_P layer both at (57.2, 9.5)mm
No copper for Testpoint +5V_P layer both at (59.7, 9.5)mm
No copper for Testpoint +5V_P layer both at (63.5, 43.8)mm
No copper for Testpoint +5V_P layer both at (61.0, 43.8)mm
No copper for Testpoint +5V_P layer both at (58.4, 43.8)mm
No copper for Testpoint +5V_P layer both at (55.9, 43.8)mm
No copper for Testpoint +5V_P layer both at (53.3, 43.8)mm
No copper for Testpoint +5V_P layer both at (50.8, 43.8)mm
No copper for Testpoint +5V_P layer both at (48.3, 43.8)mm
No copper for Testpoint +5V_P layer both at (45.7, 43.8)mm
No copper for Testpoint NET-(J5-PAD1) layer both at (27.9, 2.5)mm
No copper for Testpoint +5V_P layer both at (64.2, 28.4)mm
No copper for Testpoint +5V_P layer both at (64.2, 25.9)mm
No copper for Testpoint +5V_P layer both at (64.2, 23.3)mm
No copper for Testpoint +5V_P layer both at (64.2, 20.8)mm
No copper for Testpoint NET-(J18-PAD2) layer both at (8.7, 3.6)mm
No copper for Testpoint NET-(SW3-PAD1) layer both at (18.6, 5.2)mm

0 of Short-Circuit errors

64 of Broken Net error(s)
IPC356 net "+1V2" is broken into 5 subnets:
subnet 1:
TP3-1 U1-27 C14-1
subnet 2:
U1-51 U1-92 C13-1 C16-1
subnet 3:
U1-111 C15-1
subnet 4:
U11-6 C64-1
subnet 5:
R9-2
IPC356 net "+1V8_FT" is broken into 4 subnets:
subnet 1:
U3-64 C21-1
subnet 2:
U3-12 C19-1
subnet 3:
U3-37 C20-1
subnet 4:
U3-49 C31-1
IPC356 net "+3V3" is broken into 26 subnets:
subnet 1:
TP2-1 U3-50 C30-1 R13-1 R12-1 R14-1
subnet 2:
U8-10 U1-72 C10-1
subnet 3:
U8-2 C47-2
subnet 4:
U9-10
subnet 5:
U9-2 D1-2 C49-2
subnet 6:
U1-89 C7-1 R21-2
subnet 7:
L3-1
subnet 8:
U1-30 C5-1
subnet 9:
U10-1 C59-1
subnet 10:
U1-100 C8-1
subnet 11:
U4-4 U4-1 C32-1
subnet 12:
U5-6 U5-8 C33-1
subnet 13:
U3-20 C29-1
subnet 14:
U3-31 C28-1 R3-2
subnet 15:
U3-42 C27-1
subnet 16:
U3-56 C26-1
subnet 17:
U7-1 U7-16 C45-1 R20-2
subnet 18:
U1-46 C3-1
subnet 19:
U6-8
subnet 20:
U6-2 C36-2
subnet 21:
U2-8 C9-1 R7-1 R5-1 R8-1 R6-1
subnet 22:
U1-57 C4-1 R1-2
subnet 23:
U1-6 C6-1
subnet 24:
L1-1 R10-1
subnet 25:
U1-123 C1-1
subnet 26:
U1-133 C2-1
IPC356 net "+3V3_AUX" is broken into 2 subnets:
subnet 1:
TP4-1 U11-5 C65-1
subnet 2:
J5-4 J5-4
IPC356 net "+5V" is broken into 7 subnets:
subnet 1:
TP1-1 U8-19 J5-2 J5-2 L5-2 Q4-1 Q4-2 U10-8 U11-2 C69-1 C68-1 C48-1 R34-1 R31-1 R30-1 R22-2 R23-2 JP1-1 JP1-1
subnet 2:
U9-19 C50-1
subnet 3:
Q3-3
subnet 4:
R36-2
subnet 5:
U12-7
subnet 6:
U12-14
subnet 7:
U6-15 C37-1
IPC356 net "+5V_P" is broken into 2 subnets:
subnet 1:
TP5-1 Q4-4 Q4-5 Q4-6 Q4-6
subnet 2:
J5-5 J5-5
IPC356 net "ADC_INT" is broken into 2 subnets:
subnet 1:
U1-93
subnet 2:
U7-2
IPC356 net "ATIONS/FT_DATA" is broken into 2 subnets:
subnet 1:
U5-3 R15-1
subnet 2:
U3-61
IPC356 net "CATIONS/FT_CLK" is broken into 2 subnets:
subnet 1:
U5-2 R13-2
subnet 2:
U3-62
IPC356 net "FPGA_39" is broken into 2 subnets:
subnet 1:
U1-39
subnet 2:
J19-3 J19-3
IPC356 net "FPGA_41" is broken into 2 subnets:
subnet 1:
U1-41
subnet 2:
J19-4 J19-4
IPC356 net "FPGA_42" is broken into 2 subnets:
subnet 1:
U1-42
subnet 2:
J19-5 J19-5
IPC356 net "FPGA_43" is broken into 2 subnets:
subnet 1:
U1-43
subnet 2:
J19-6 J19-6
IPC356 net "FPGA_49_GBIN5" is broken into 2 subnets:
subnet 1:
U1-49
subnet 2:
J19-7 J19-7
IPC356 net "FPGA_50_GBIN4" is broken into 2 subnets:
subnet 1:
U1-50
subnet 2:
J19-8 J19-8
IPC356 net "FPGA_87" is broken into 2 subnets:
subnet 1:
U8-4
subnet 2:
U1-87
IPC356 net "FPGA_88" is broken into 2 subnets:
subnet 1:
U8-5
subnet 2:
U1-88
IPC356 net "FPGA_112" is broken into 2 subnets:
subnet 1:
U9-1
subnet 2:
U1-112
IPC356 net "FPGA_113" is broken into 2 subnets:
subnet 1:
U1-113
subnet 2:
U9-3
IPC356 net "FPGA_114" is broken into 2 subnets:
subnet 1:
U9-4
subnet 2:
U1-114
IPC356 net "FPGA_115" is broken into 2 subnets:
subnet 1:
U9-5
subnet 2:
U1-115
IPC356 net "FPGA_116" is broken into 2 subnets:
subnet 1:
U1-116
subnet 2:
U9-6
IPC356 net "FPGA_117" is broken into 2 subnets:
subnet 1:
U9-7
subnet 2:
U1-117
IPC356 net "FPGA_118" is broken into 2 subnets:
subnet 1:
U9-8
subnet 2:
U1-118
IPC356 net "FPGA_119" is broken into 2 subnets:
subnet 1:
U9-9
subnet 2:
U1-119
IPC356 net "FPGA_144" is broken into 2 subnets:
subnet 1:
U6-1
subnet 2:
U1-144
IPC356 net "FPGA_RESET" is broken into 3 subnets:
subnet 1:
R2-1 R3-1
subnet 2:
U1-66
subnet 3:
R35-2
IPC356 net "GNDREF" is broken into 34 subnets:
subnet 1:
D2-K D3-K D4-K D5-K D6-K D7-K D8-K D9-K SW1-2 SW2-2 D12-K U9-21 U9-11 J4-7 J4-7 J3-1 J3-1 J3-2 J3-2 J3-3 J3-3 J3-4 J3-4 J3-5 J3-5 J8-1 J8-1 J8-2 J8-2 J8-3 J8-3 J8-4 J8-4 J8-5 J8-5 J8-6 J8-6 J8-7 J8-7 J8-8 J8-8 J16-1 J16-1 J16-2 J16-2 J16-3 J16-3 J16-4 J16-4 J18-3 J18-3 SW3-3 SW3-3 U5-5 D10-A U3-1 U12-5 U12-6 U12-8 U12-15 U12-16 U12-17 SW4-2 SW4-2 C69-2 C67-2 C66-2 C70-2 C71-2 C41-1 C33-2 C21-2 C35-1 C36-1 C34-1 C37-2 C68-2 C46-1 C15-2 C58-2 VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~
subnet 2:
C24-2 C25-2 R11-1
subnet 3:
U3-35 C5-2 C14-2 C20-2 C28-2 C29-2
subnet 4:
U8-21 U8-11 U1-69 C10-2 C48-2 C47-1 VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~
subnet 5:
U11-4 C64-2 C65-2 C9-2
subnet 6:
R25-1
subnet 7:
J3-6 J3-6 U6-9 C44-2 C39-2 C43-2 C38-2 C42-2 C40-2
subnet 8:
U7-5 U7-6 U7-8 U7-17 U1-59 U1-86 C4-2 C7-2 VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~
subnet 9:
J14-1 J14-1 J5-6 J5-6 J5-7 J5-7
subnet 10:
J14-2 J14-2
subnet 11:
J14-3 J14-3
subnet 12:
J14-4 J14-4
subnet 13:
J14-5 J14-5 J14-6 J14-6
subnet 14:
U1-103 C16-2 C45-2 C8-2 C49-1 C50-2
subnet 15:
C54-2 C55-2
subnet 16:
C53-2
subnet 17:
U10-4 U10-9 U2-4 C59-2 C3-2 C13-2
subnet 18:
C27-2
subnet 19:
J1-S2 J1-5 J1-4 J1-S1 J1-S4 J1-S6 J1-S5 J1-S3 C22-2 C17-2 C23-2
subnet 20:
U3-51 C26-2 C30-2
subnet 21:
U4-2 C32-2
subnet 22:
F2-2
subnet 23:
D13-2 R29-1 R39-1
subnet 24:
U3-5 U3-10 U3-11 C18-2
subnet 25:
C51-2 C56-2
subnet 26:
U3-13 U3-15 C19-2
subnet 27:
U3-25
subnet 28:
U3-47 C31-2
subnet 29:
R4-2
subnet 30:
U1-13 U1-14 U1-132 U1-140 C1-2 C2-2
subnet 31:
C52-2 C57-2
subnet 32:
U1-5 C6-2
subnet 33:
J4-7 J4-7 J3-1 J3-1 J3-2 J3-2 J3-3 J3-3 J3-4 J3-4 J3-5 J3-5 J3-6 J3-6 J8-1 J8-1 J8-2 J8-2 J8-3 J8-3 J8-4 J8-4 J8-5 J8-5 J8-6 J8-6 J8-7 J8-7 J8-8 J8-8 J16-1 J16-1 J16-2 J16-2 J16-3 J16-3 J16-4 J16-4 J18-3 J18-3 SW3-3 SW3-3 SW4-2 SW4-2 VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~
subnet 34:
J14-1 J14-1 J14-2 J14-2 J14-3 J14-3 J14-4 J14-4 J14-5 J14-5 J14-6 J14-6 J5-6 J5-6 J5-7 J5-7
IPC356 net "ICE_CDONE" is broken into 2 subnets:
subnet 1:
U3-23
subnet 2:
U1-65 R1-1
IPC356 net "ICE_MISO" is broken into 2 subnets:
subnet 1:
U1-68 U2-2
subnet 2:
U3-18
IPC356 net "ICE_MOSI" is broken into 3 subnets:
subnet 1:
U2-5
subnet 2:
U1-67
subnet 3:
U3-17
IPC356 net "ICE_SCK" is broken into 4 subnets:
subnet 1:
U2-6
subnet 2:
U1-70
subnet 3:
U3-16
subnet 4:
R5-2
IPC356 net "ICE_SS_B" is broken into 3 subnets:
subnet 1:
U3-21
subnet 2:
U2-1 R6-2
subnet 3:
U1-71
IPC356 net "INO?SOCKETS/D7" is broken into 3 subnets:
subnet 1:
U9-20
subnet 2:
J10-8 J10-8 J9-8 J9-8 C58-1
subnet 3:
J9-8 J9-8
IPC356 net "INO?SOCKETS/D8" is broken into 3 subnets:
subnet 1:
J4-1 J4-1 J6-1 J6-1
subnet 2:
U6-10 C40-1
subnet 3:
J4-1 J4-1
IPC356 net "INO?SOCKETS/D9" is broken into 3 subnets:
subnet 1:
J4-2 J4-2 J6-2 J6-2
subnet 2:
U6-11 C42-1
subnet 3:
J4-2 J4-2
IPC356 net "LED0" is broken into 2 subnets:
subnet 1:
U1-95
subnet 2:
R17-1
IPC356 net "LED1" is broken into 2 subnets:
subnet 1:
R17-2
subnet 2:
U1-96
IPC356 net "LED2" is broken into 2 subnets:
subnet 1:
R17-3
subnet 2:
U1-97
IPC356 net "LED3" is broken into 2 subnets:
subnet 1:
R17-4
subnet 2:
U1-98
IPC356 net "LED4" is broken into 2 subnets:
subnet 1:
R18-1
subnet 2:
U1-99
IPC356 net "LED5" is broken into 2 subnets:
subnet 1:
R18-2
subnet 2:
U1-101
IPC356 net "LED6" is broken into 2 subnets:
subnet 1:
R18-3
subnet 2:
U1-102
IPC356 net "LED7" is broken into 2 subnets:
subnet 1:
R18-4
subnet 2:
U1-104
IPC356 net "LY/FPGA_PWR_EN" is broken into 4 subnets:
subnet 1:
R32-2 R30-2
subnet 2:
U11-1
subnet 3:
R33-2
subnet 4:
U10-5
IPC356 net "NET-(C22-PAD1)" is broken into 2 subnets:
subnet 1:
F2-5
subnet 2:
J1-1 L2-1 C22-1
IPC356 net "NET-(C62-PAD1)" is broken into 2 subnets:
subnet 1:
C62-1 R27-2 R24-1
subnet 2:
Q2-3
IPC356 net "NET-(C71-PAD1)" is broken into 2 subnets:
subnet 1:
C71-1
subnet 2:
U12-9
IPC356 net "NET-(D11-PAD3)" is broken into 2 subnets:
subnet 1:
D11-3
subnet 2:
SW3-2 SW3-2
IPC356 net "NET-(Q4-PAD3)" is broken into 2 subnets:
subnet 1:
R37-2 R36-1
subnet 2:
Q4-3
IPC356 net "NET-(R7-PAD2)" is broken into 2 subnets:
subnet 1:
R7-2
subnet 2:
U2-7
IPC356 net "NET-(R8-PAD2)" is broken into 2 subnets:
subnet 1:
U2-3
subnet 2:
R8-2
IPC356 net "NET-(R16-PAD1)" is broken into 2 subnets:
subnet 1:
U4-3 U3-2
subnet 2:
R16-1
IPC356 net "NET-(U6-PAD17)" is broken into 5 subnets:
subnet 1:
U6-17 VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~ VIA**-~
subnet 2:
VIA**-~ VIA**-~
subnet 3:
VIA**-~ VIA**-~
subnet 4:
VIA**-~ VIA**-~
subnet 5:
VIA**-~ VIA**-~
IPC356 net "NO?SOCKETS/D10" is broken into 3 subnets:
subnet 1:
J4-3 J4-3 J6-3 J6-3
subnet 2:
U6-12 C38-1
subnet 3:
J4-3 J4-3
IPC356 net "NO?SOCKETS/D11" is broken into 3 subnets:
subnet 1:
J4-4 J4-4 J6-4 J6-4
subnet 2:
U6-13 C43-1
subnet 3:
J4-4 J4-4
IPC356 net "NO?SOCKETS/D12" is broken into 3 subnets:
subnet 1:
J4-5 J4-5 J6-5 J6-5
subnet 2:
U6-14 C39-1
subnet 3:
J4-5 J4-5
IPC356 net "NO?SOCKETS/D13" is broken into 2 subnets:
subnet 1:
J4-6 J4-6 J6-6 J6-6 C44-1
subnet 2:
U6-16
IPC356 net "NO?SOCKETS/DD4" is broken into 2 subnets:
subnet 1:
U8-16 J12-5 J12-5 J11-5 J11-5 R23-1
subnet 2:
J4-9 J4-9 J12-5 J12-5
IPC356 net "NO?SOCKETS/DD5" is broken into 2 subnets:
subnet 1:
U8-17 J12-6 J12-6 J11-6 J11-6 R22-1
subnet 2:
J4-10 J4-10 J12-6 J12-6
IPC356 net "POWER" is broken into 3 subnets:
subnet 1:
TP6-1 J5-8 J5-8
subnet 2:
Q5-2 C60-1
subnet 3:
Q2-4 Q2-5 Q2-6 Q2-6 L4-1 C66-1
IPC356 net "SYS_RESET" is broken into 2 subnets:
subnet 1:
SW4-1 SW4-1 R35-1 R33-1
subnet 2:
J5-3 J5-3 SW4-1 SW4-1
IPC356 net "USB_5V" is broken into 2 subnets:
subnet 1:
TP7-1 F1-2
subnet 2:
Q3-2 R39-2 R38-2
IPC356 net "U_SW1" is broken into 2 subnets:
subnet 1:
SW1-1 C34-2
subnet 2:
U1-10