From bc6e1cee9e99386579c7fa7a68c0264ea1c9382e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?D=C3=A1vid=20H=C3=A1zi?= Date: Thu, 11 Apr 2024 14:03:07 +0200 Subject: [PATCH] build: Bump FreeRTOS-Plus-TCP commit hash MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CS315 support have been added to the FreeRTOS-Plus-TCP. Bumped the submodule's commit hash to the one which added the new platform. Signed-off-by: Dávid Házi --- .../freertos_plus_tcp/CMakeLists.txt | 9 - .../integration/src/network_startup.c | 2 +- .../connectivity/freertos_plus_tcp/library | 2 +- ...01-platform-Add-Corstone-315-support.patch | 14405 ---------------- manifest.yml | 2 +- release_changes/202404111359.change | 1 + 6 files changed, 4 insertions(+), 14417 deletions(-) delete mode 100644 components/connectivity/freertos_plus_tcp/patches/0001-platform-Add-Corstone-315-support.patch create mode 100644 release_changes/202404111359.change diff --git a/components/connectivity/freertos_plus_tcp/CMakeLists.txt b/components/connectivity/freertos_plus_tcp/CMakeLists.txt index e13dafe7..bc43b12e 100644 --- a/components/connectivity/freertos_plus_tcp/CMakeLists.txt +++ b/components/connectivity/freertos_plus_tcp/CMakeLists.txt @@ -8,15 +8,6 @@ set(freertos_plus_tcp_SOURCE_DIR "Path to FreeRTOS-Plus-TCP source code" ) -include(ApplyPatches) - -set(PATCH_FILES_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/patches") -set(PATCH_FILES - "${PATCH_FILES_DIRECTORY}/0001-platform-Add-Corstone-315-support.patch" -) -iot_reference_arm_corstone3xx_apply_patches("${freertos_plus_tcp_SOURCE_DIR}" "${PATCH_FILES}") - - if (${ARM_CORSTONE_BSP_TARGET_PLATFORM} STREQUAL "corstone300" OR ${ARM_CORSTONE_BSP_TARGET_PLATFORM} STREQUAL "corstone310") set(FREERTOS_PLUS_TCP_NETWORK_IF "MPS3_AN552" CACHE STRING "FreeRTOS Plus TCP Network Interface selection") elseif (${ARM_CORSTONE_BSP_TARGET_PLATFORM} STREQUAL "corstone315") diff --git a/components/connectivity/freertos_plus_tcp/integration/src/network_startup.c b/components/connectivity/freertos_plus_tcp/integration/src/network_startup.c index f1a3e1b1..c585f3a1 100644 --- a/components/connectivity/freertos_plus_tcp/integration/src/network_startup.c +++ b/components/connectivity/freertos_plus_tcp/integration/src/network_startup.c @@ -93,7 +93,7 @@ int32_t network_startup( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); + memcpy( xEndPoints[ 0 ].xMACAddress.ucBytes, ucMACAddress, sizeof( ucMACAddress ) ); FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ diff --git a/components/connectivity/freertos_plus_tcp/library b/components/connectivity/freertos_plus_tcp/library index 3d5ee0e8..7b68a91f 160000 --- a/components/connectivity/freertos_plus_tcp/library +++ b/components/connectivity/freertos_plus_tcp/library @@ -1 +1 @@ -Subproject commit 3d5ee0e821cab38cb6e6265fcf1ce7552a54519d +Subproject commit 7b68a91f0870f9bcff444bb14e441d6a08658377 diff --git a/components/connectivity/freertos_plus_tcp/patches/0001-platform-Add-Corstone-315-support.patch b/components/connectivity/freertos_plus_tcp/patches/0001-platform-Add-Corstone-315-support.patch deleted file mode 100644 index f0956cc3..00000000 --- a/components/connectivity/freertos_plus_tcp/patches/0001-platform-Add-Corstone-315-support.patch +++ /dev/null @@ -1,14405 +0,0 @@ -From 76852fca0866308c4b430b3cf69527891272069c Mon Sep 17 00:00:00 2001 -From: Dávid Házi -Date: Sun, 3 Mar 2024 14:38:35 +0100 -Subject: [PATCH] platform: Add Corstone-315 support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Corstone-315 has got different memory map than the previous -Corstone platforms, that's why we can't use the existing -AN552 port. Added the new platform with the right headers. - -Signed-off-by: Dávid Házi ---- - .../MPS4_CS315/CMSIS_Driver/CMakeLists.txt | 13 + - .../MPS4_CS315/CMSIS_Driver/Driver_Common.h | 77 + - .../MPS4_CS315/CMSIS_Driver/Driver_ETH.h | 95 + - .../MPS4_CS315/CMSIS_Driver/Driver_ETH_MAC.h | 318 ++ - .../MPS4_CS315/CMSIS_Driver/Driver_ETH_PHY.h | 151 + - .../MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.c | 1202 ++++ - .../MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.h | 319 ++ - .../MPS4_CS315/CMakeLists.txt | 32 + - .../MPS4_CS315/Device/Include/SSE315.h | 92 + - .../MPS4_CS315/Device/Include/cachel1_armv7.h | 449 ++ - .../Device/Include/cmsis_armclang.h | 1518 +++++ - .../Device/Include/cmsis_compiler.h | 310 ++ - .../MPS4_CS315/Device/Include/cmsis_gcc.h | 2225 ++++++++ - .../MPS4_CS315/Device/Include/cmsis_version.h | 47 + - .../MPS4_CS315/Device/Include/core_cm55.h | 4920 +++++++++++++++++ - .../MPS4_CS315/Device/Include/mpu_armv8.h | 430 ++ - .../Device/Include/platform_base_address.h | 303 + - .../MPS4_CS315/Device/Include/platform_irq.h | 119 + - .../MPS4_CS315/Device/Include/platform_pins.h | 114 + - .../MPS4_CS315/Device/Include/platform_regs.h | 510 ++ - .../MPS4_CS315/Device/Include/pmu_armv8.h | 345 ++ - .../MPS4_CS315/Device/Include/system_SSE315.h | 53 + - .../MPS4_CS315/NetworkInterface.c | 548 ++ - 23 files changed, 14190 insertions(+) - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/CMakeLists.txt - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_Common.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_MAC.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_PHY.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.c - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/CMakeLists.txt - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/SSE315.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/cachel1_armv7.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_armclang.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_compiler.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_gcc.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_version.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/core_cm55.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/mpu_armv8.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_base_address.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_irq.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_pins.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_regs.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/pmu_armv8.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/Device/Include/system_SSE315.h - create mode 100644 source/portable/NetworkInterface/MPS4_CS315/NetworkInterface.c - -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/CMakeLists.txt b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/CMakeLists.txt -new file mode 100644 -index 0000000..5bfaeb1 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/CMakeLists.txt -@@ -0,0 +1,13 @@ -+# Copyright 2023 Arm Limited and/or its affiliates -+# -+# SPDX-License-Identifier: MIT -+ -+target_sources( freertos_plus_tcp_network_if -+ PRIVATE -+ ETH_LAN91C111.c -+) -+ -+target_include_directories( freertos_plus_tcp_network_if -+ PRIVATE -+ . -+) -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_Common.h b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_Common.h -new file mode 100644 -index 0000000..5ab9d36 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_Common.h -@@ -0,0 +1,77 @@ -+/* *INDENT-OFF* */ -+ -+/* -+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ * -+ * $Date: 2. Feb 2017 -+ * $Revision: V2.0 -+ * -+ * Project: Common Driver definitions -+ */ -+ -+/* History: -+ * Version 2.0 -+ * Changed prefix ARM_DRV -> ARM_DRIVER -+ * Added General return codes definitions -+ * Version 1.10 -+ * Namespace prefix ARM_ added -+ * Version 1.00 -+ * Initial release -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Driver/Include/Driver_Common.h -+*/ -+ -+#ifndef DRIVER_COMMON_H_ -+#define DRIVER_COMMON_H_ -+ -+#include -+#include -+#include -+ -+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) -+ -+/** -+\brief Driver Version -+*/ -+typedef struct _ARM_DRIVER_VERSION { -+ uint16_t api; ///< API version -+ uint16_t drv; ///< Driver version -+} ARM_DRIVER_VERSION; -+ -+/* General return codes */ -+#define ARM_DRIVER_OK 0 ///< Operation succeeded -+#define ARM_DRIVER_ERROR -1 ///< Unspecified error -+#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy -+#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred -+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported -+#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error -+#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors -+ -+/** -+\brief General power states -+*/ -+typedef enum _ARM_POWER_STATE { -+ ARM_POWER_OFF, ///< Power off: no operation possible -+ ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events -+ ARM_POWER_FULL ///< Power on: full operation at maximum performance -+} ARM_POWER_STATE; -+ -+#endif /* DRIVER_COMMON_H_ */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH.h b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH.h -new file mode 100644 -index 0000000..cf1378b ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH.h -@@ -0,0 +1,95 @@ -+/* *INDENT-OFF* */ -+ -+/* -+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ * -+ * $Date: 24. January 2020 -+ * $Revision: V2.2 -+ * -+ * Project: Ethernet PHY and MAC Driver common definitions -+ */ -+ -+/* History: -+ * Version 2.2 -+ * Removed volatile from ARM_ETH_LINK_INFO -+ * Version 2.1 -+ * ARM_ETH_LINK_INFO made volatile -+ * Version 2.0 -+ * Removed ARM_ETH_STATUS enumerator -+ * Removed ARM_ETH_MODE enumerator -+ * Version 1.10 -+ * Namespace prefix ARM_ added -+ * Version 1.00 -+ * Initial release -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Driver/Include/Driver_ETH.h -+*/ -+ -+#ifndef DRIVER_ETH_H_ -+#define DRIVER_ETH_H_ -+ -+#include "Driver_Common.h" -+ -+/** -+\brief Ethernet Media Interface type -+*/ -+#define ARM_ETH_INTERFACE_MII (0U) ///< Media Independent Interface (MII) -+#define ARM_ETH_INTERFACE_RMII (1U) ///< Reduced Media Independent Interface (RMII) -+#define ARM_ETH_INTERFACE_SMII (2U) ///< Serial Media Independent Interface (SMII) -+ -+/** -+\brief Ethernet link speed -+*/ -+#define ARM_ETH_SPEED_10M (0U) ///< 10 Mbps link speed -+#define ARM_ETH_SPEED_100M (1U) ///< 100 Mbps link speed -+#define ARM_ETH_SPEED_1G (2U) ///< 1 Gpbs link speed -+ -+/** -+\brief Ethernet duplex mode -+*/ -+#define ARM_ETH_DUPLEX_HALF (0U) ///< Half duplex link -+#define ARM_ETH_DUPLEX_FULL (1U) ///< Full duplex link -+ -+/** -+\brief Ethernet link state -+*/ -+typedef enum _ARM_ETH_LINK_STATE { -+ ARM_ETH_LINK_DOWN, ///< Link is down -+ ARM_ETH_LINK_UP ///< Link is up -+} ARM_ETH_LINK_STATE; -+ -+/** -+\brief Ethernet link information -+*/ -+typedef struct _ARM_ETH_LINK_INFO { -+ uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit -+ uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full -+ uint32_t reserved : 29; -+} ARM_ETH_LINK_INFO; -+ -+/** -+\brief Ethernet MAC Address -+*/ -+typedef struct _ARM_ETH_MAC_ADDR { -+ uint8_t b[6]; ///< MAC Address (6 bytes), MSB first -+} ARM_ETH_MAC_ADDR; -+ -+#endif /* DRIVER_ETH_H_ */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_MAC.h b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_MAC.h -new file mode 100644 -index 0000000..865ccb8 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_MAC.h -@@ -0,0 +1,318 @@ -+/* *INDENT-OFF* */ -+ -+/* -+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ * -+ * $Date: 24. January 2020 -+ * $Revision: V2.2 -+ * -+ * Project: Ethernet MAC (Media Access Control) Driver definitions -+ */ -+ -+/* History: -+ * Version 2.2 -+ * Removed volatile from ARM_ETH_LINK_INFO -+ * Version 2.1 -+ * Added ARM_ETH_MAC_SLEEP Control -+ * Version 2.0 -+ * Changed MAC Address handling: -+ * moved from ARM_ETH_MAC_Initialize -+ * to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress -+ * Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter -+ * Extended ARM_ETH_MAC_SendFrame function with flags -+ * Added ARM_ETH_MAC_Control function: -+ * more control options (Broadcast, Multicast, Checksum offload, VLAN, ...) -+ * replaces ARM_ETH_MAC_SetMode -+ * replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx -+ * Added optional event on transmitted frame -+ * Added support for PTP (Precision Time Protocol) through new functions: -+ * ARM_ETH_MAC_ControlTimer -+ * ARM_ETH_MAC_GetRxFrameTime -+ * ARM_ETH_MAC_GetTxFrameTime -+ * Changed prefix ARM_DRV -> ARM_DRIVER -+ * Changed return values of some functions to int32_t -+ * Version 1.10 -+ * Name space prefix ARM_ added -+ * Version 1.01 -+ * Renamed capabilities items for checksum offload -+ * Version 1.00 -+ * Initial release -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Driver/Include/Driver_ETH_MAC.h -+*/ -+ -+#ifndef DRIVER_ETH_MAC_H_ -+#define DRIVER_ETH_MAC_H_ -+ -+#ifdef __cplusplus -+extern "C" -+{ -+#endif -+ -+#include "Driver_ETH.h" -+ -+#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */ -+ -+ -+#define _ARM_Driver_ETH_MAC_(n) Driver_ETH_MAC##n -+#define ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n) -+ -+ -+/****** Ethernet MAC Control Codes *****/ -+ -+#define ARM_ETH_MAC_CONFIGURE (0x01UL) ///< Configure MAC; arg = configuration -+#define ARM_ETH_MAC_CONTROL_TX (0x02UL) ///< Transmitter; arg: 0=disabled (default), 1=enabled -+#define ARM_ETH_MAC_CONTROL_RX (0x03UL) ///< Receiver; arg: 0=disabled (default), 1=enabled -+#define ARM_ETH_MAC_FLUSH (0x04UL) ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_... -+#define ARM_ETH_MAC_SLEEP (0x05UL) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit -+#define ARM_ETH_MAC_VLAN_FILTER (0x06UL) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default) -+ -+/*----- Ethernet MAC Configuration -----*/ -+#define ARM_ETH_MAC_SPEED_Pos 0 -+#define ARM_ETH_MAC_SPEED_Msk (3UL << ARM_ETH_MAC_SPEED_Pos) -+#define ARM_ETH_MAC_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed -+#define ARM_ETH_MAC_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed -+#define ARM_ETH_MAC_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed -+#define ARM_ETH_MAC_DUPLEX_Pos 2 -+#define ARM_ETH_MAC_DUPLEX_Msk (1UL << ARM_ETH_MAC_DUPLEX_Pos) -+#define ARM_ETH_MAC_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link -+#define ARM_ETH_MAC_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link -+#define ARM_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode -+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload -+#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload -+#define ARM_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address -+#define ARM_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address -+#define ARM_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode) -+ -+/*----- Ethernet MAC Flush Flags -----*/ -+#define ARM_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer -+#define ARM_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer -+ -+/*----- Ethernet MAC VLAN Filter Flag -----*/ -+#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit) -+ -+ -+/****** Ethernet MAC Frame Transmit Flags *****/ -+#define ARM_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment -+#define ARM_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted -+#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp -+ -+ -+/****** Ethernet MAC Timer Control Codes *****/ -+#define ARM_ETH_MAC_TIMER_GET_TIME (0x01UL) ///< Get current time -+#define ARM_ETH_MAC_TIMER_SET_TIME (0x02UL) ///< Set new time -+#define ARM_ETH_MAC_TIMER_INC_TIME (0x03UL) ///< Increment current time -+#define ARM_ETH_MAC_TIMER_DEC_TIME (0x04UL) ///< Decrement current time -+#define ARM_ETH_MAC_TIMER_SET_ALARM (0x05UL) ///< Set alarm time -+#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK (0x06UL) ///< Adjust clock frequency; time->ns: correction factor * 2^31 -+ -+ -+/** -+\brief Ethernet MAC Time -+*/ -+typedef struct _ARM_ETH_MAC_TIME { -+ uint32_t ns; ///< Nano seconds -+ uint32_t sec; ///< Seconds -+} ARM_ETH_MAC_TIME; -+ -+ -+/****** Ethernet MAC Event *****/ -+#define ARM_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received -+#define ARM_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted -+#define ARM_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet) -+#define ARM_ETH_MAC_EVENT_TIMER_ALARM (1UL << 3) ///< Timer Alarm -+ -+ -+// Function documentation -+/** -+ \fn ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void) -+ \brief Get driver version. -+ \return \ref ARM_DRIVER_VERSION -+*/ -+/** -+ \fn ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void) -+ \brief Get driver capabilities. -+ \return \ref ARM_ETH_MAC_CAPABILITIES -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event) -+ \brief Initialize Ethernet MAC Device. -+ \param[in] cb_event Pointer to \ref ARM_ETH_MAC_SignalEvent -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_Uninitialize (void) -+ \brief De-initialize Ethernet MAC Device. -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state) -+ \brief Control Ethernet MAC Device Power. -+ \param[in] state Power state -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) -+ \brief Get Ethernet MAC Address. -+ \param[in] ptr_addr Pointer to address -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) -+ \brief Set Ethernet MAC Address. -+ \param[in] ptr_addr Pointer to address -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, -+ uint32_t num_addr) -+ \brief Configure Address Filter. -+ \param[in] ptr_addr Pointer to addresses -+ \param[in] num_addr Number of addresses to configure -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) -+ \brief Send Ethernet frame. -+ \param[in] frame Pointer to frame buffer with data to send -+ \param[in] len Frame buffer length in bytes -+ \param[in] flags Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...) -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len) -+ \brief Read data of received Ethernet frame. -+ \param[in] frame Pointer to frame buffer for data to read into -+ \param[in] len Frame buffer length in bytes -+ \return number of data bytes read or execution status -+ - value >= 0: number of data bytes read -+ - value < 0: error occurred, value is execution status as defined with \ref execution_status -+*/ -+/** -+ \fn uint32_t ARM_ETH_MAC_GetRxFrameSize (void) -+ \brief Get size of received Ethernet frame. -+ \return number of bytes in received frame -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time) -+ \brief Get time of received Ethernet frame. -+ \param[in] time Pointer to time structure for data to read into -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time) -+ \brief Get time of transmitted Ethernet frame. -+ \param[in] time Pointer to time structure for data to read into -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg) -+ \brief Control Ethernet Interface. -+ \param[in] control Operation -+ \param[in] arg Argument of operation (optional) -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) -+ \brief Control Precision Timer. -+ \param[in] control Operation -+ \param[in] time Pointer to time structure -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) -+ \brief Read Ethernet PHY Register through Management Interface. -+ \param[in] phy_addr 5-bit device address -+ \param[in] reg_addr 5-bit register address -+ \param[out] data Pointer where the result is written to -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) -+ \brief Write Ethernet PHY Register through Management Interface. -+ \param[in] phy_addr 5-bit device address -+ \param[in] reg_addr 5-bit register address -+ \param[in] data 16-bit data to write -+ \return \ref execution_status -+*/ -+ -+/** -+ \fn void ARM_ETH_MAC_SignalEvent (uint32_t event) -+ \brief Callback function that signals a Ethernet Event. -+ \param[in] event event notification mask -+ \return none -+*/ -+ -+typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event. -+ -+ -+/** -+\brief Ethernet MAC Capabilities -+*/ -+typedef struct _ARM_ETH_MAC_CAPABILITIES { -+ uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive -+ uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive -+ uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive -+ uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive -+ uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive -+ uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit -+ uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit -+ uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit -+ uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit -+ uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit -+ uint32_t media_interface : 2; ///< Ethernet Media Interface type -+ uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address -+ uint32_t event_rx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated -+ uint32_t event_tx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated -+ uint32_t event_wakeup : 1; ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated -+ uint32_t precision_timer : 1; ///< 1 = Precision Timer supported -+ uint32_t reserved : 15; ///< Reserved (must be zero) -+} ARM_ETH_MAC_CAPABILITIES; -+ -+ -+/** -+\brief Access structure of the Ethernet MAC Driver -+*/ -+typedef struct _ARM_DRIVER_ETH_MAC { -+ ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version. -+ ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities. -+ int32_t (*Initialize) (ARM_ETH_MAC_SignalEvent_t cb_event); ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device. -+ int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device. -+ int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power. -+ int32_t (*GetMacAddress) ( ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address. -+ int32_t (*SetMacAddress) (const ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address. -+ int32_t (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter. -+ int32_t (*SendFrame) (const uint8_t *frame, uint32_t len, uint32_t flags); ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame. -+ int32_t (*ReadFrame) ( uint8_t *frame, uint32_t len); ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame. -+ uint32_t (*GetRxFrameSize) (void); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame. -+ int32_t (*GetRxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame. -+ int32_t (*GetTxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame. -+ int32_t (*ControlTimer) (uint32_t control, ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer. -+ int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface. -+ int32_t (*PHY_Read) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface. -+ int32_t (*PHY_Write) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface. -+} const ARM_DRIVER_ETH_MAC; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* DRIVER_ETH_MAC_H_ */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_PHY.h b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_PHY.h -new file mode 100644 -index 0000000..d6ca30e ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/Driver_ETH_PHY.h -@@ -0,0 +1,151 @@ -+/* *INDENT-OFF* */ -+ -+/* -+ * Copyright (c) 2013-2020 ARM Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ * -+ * $Date: 24. January 2020 -+ * $Revision: V2.2 -+ * -+ * Project: Ethernet PHY (Physical Transceiver) Driver definitions -+ */ -+ -+/* History: -+ * Version 2.2 -+ * Removed volatile from ARM_ETH_LINK_INFO -+ * Version 2.1 -+ * ARM_ETH_LINK_INFO made volatile -+ * Version 2.0 -+ * changed parameter "mode" in function ARM_ETH_PHY_SetMode -+ * Changed prefix ARM_DRV -> ARM_DRIVER -+ * Changed return values of some functions to int32_t -+ * Version 1.10 -+ * Namespace prefix ARM_ added -+ * Version 1.00 -+ * Initial release -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Driver/Include/Driver_ETH_PHY.h -+*/ -+ -+#ifndef DRIVER_ETH_PHY_H_ -+#define DRIVER_ETH_PHY_H_ -+ -+#ifdef __cplusplus -+extern "C" -+{ -+#endif -+ -+#include "Driver_ETH.h" -+ -+#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */ -+ -+ -+#define _ARM_Driver_ETH_PHY_(n) Driver_ETH_PHY##n -+#define ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n) -+ -+ -+/****** Ethernet PHY Mode *****/ -+#define ARM_ETH_PHY_SPEED_Pos 0 -+#define ARM_ETH_PHY_SPEED_Msk (3UL << ARM_ETH_PHY_SPEED_Pos) -+#define ARM_ETH_PHY_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed -+#define ARM_ETH_PHY_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed -+#define ARM_ETH_PHY_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed -+#define ARM_ETH_PHY_DUPLEX_Pos 2 -+#define ARM_ETH_PHY_DUPLEX_Msk (1UL << ARM_ETH_PHY_DUPLEX_Pos) -+#define ARM_ETH_PHY_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link -+#define ARM_ETH_PHY_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link -+#define ARM_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode -+#define ARM_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode -+#define ARM_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface -+ -+ -+// Function documentation -+/** -+ \fn ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void) -+ \brief Get driver version. -+ \return \ref ARM_DRIVER_VERSION -+*/ -+/** -+ \fn int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read, -+ ARM_ETH_PHY_Write_t fn_write) -+ \brief Initialize Ethernet PHY Device. -+ \param[in] fn_read Pointer to \ref ARM_ETH_MAC_PHY_Read -+ \param[in] fn_write Pointer to \ref ARM_ETH_MAC_PHY_Write -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_PHY_Uninitialize (void) -+ \brief De-initialize Ethernet PHY Device. -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state) -+ \brief Control Ethernet PHY Device Power. -+ \param[in] state Power state -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_PHY_SetInterface (uint32_t interface) -+ \brief Set Ethernet Media Interface. -+ \param[in] interface Media Interface type -+ \return \ref execution_status -+*/ -+/** -+ \fn int32_t ARM_ETH_PHY_SetMode (uint32_t mode) -+ \brief Set Ethernet PHY Device Operation mode. -+ \param[in] mode Operation Mode -+ \return \ref execution_status -+*/ -+/** -+ \fn ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void) -+ \brief Get Ethernet PHY Device Link state. -+ \return current link status \ref ARM_ETH_LINK_STATE -+*/ -+/** -+ \fn ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void) -+ \brief Get Ethernet PHY Device Link information. -+ \return current link parameters \ref ARM_ETH_LINK_INFO -+*/ -+ -+ -+typedef int32_t (*ARM_ETH_PHY_Read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register. -+typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register. -+ -+ -+/** -+\brief Access structure of the Ethernet PHY Driver -+*/ -+typedef struct _ARM_DRIVER_ETH_PHY { -+ ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version. -+ int32_t (*Initialize) (ARM_ETH_PHY_Read_t fn_read, -+ ARM_ETH_PHY_Write_t fn_write); ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device. -+ int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device. -+ int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power. -+ int32_t (*SetInterface) (uint32_t interface); ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface. -+ int32_t (*SetMode) (uint32_t mode); ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode. -+ ARM_ETH_LINK_STATE (*GetLinkState) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state. -+ ARM_ETH_LINK_INFO (*GetLinkInfo) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information. -+} const ARM_DRIVER_ETH_PHY; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* DRIVER_ETH_PHY_H_ */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.c b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.c -new file mode 100644 -index 0000000..3070b53 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.c -@@ -0,0 +1,1202 @@ -+/* *INDENT-OFF* */ -+ -+/* -+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ * -+ * ----------------------------------------------------------------------- -+ * -+ * $Date: 2. September 2021 -+ * $Revision: V1.0 -+ * -+ * Driver: Driver_ETH_MACn (default: Driver_ETH_MAC0), -+ * Driver_ETH_PHYn (default: Driver_ETH_PHY0) -+ * Project: Ethernet Media Access (MAC) Driver and -+ * Ethernet Physical Layer Transceiver (PHY) Driver -+ * for LAN91C111 on MPS2 platform -+ * ----------------------------------------------------------------------- -+ * Use the following configuration settings in the middleware component -+ * to connect to this driver. -+ * -+ * Configuration Setting Value -+ * --------------------- ----- -+ * Connect to hardware via Driver_ETH_MAC# = n (default: 0) -+ * Driver_ETH_PHY# = n (default: 0) -+ * -------------------------------------------------------------------- */ -+ -+/* History: -+ * Version 1.0 -+ * Initial release -+ */ -+ -+/* This file is based on -+ * https://github.com/ARM-software/CMSIS-Driver/blob/b91908d907b647bd212920e30b383b03809d68e0/ETH/ETH_LAN91C111.c -+*/ -+ -+#include -+ -+#include -+ -+#include "SSE315.h" -+#include "Driver_ETH_MAC.h" -+#include "Driver_ETH_PHY.h" -+#include "ETH_LAN91C111.h" -+ -+#include "FreeRTOS.h" -+ -+#define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* driver version */ -+#define ARM_ETH_PHY_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* driver version */ -+ -+ -+/* Ethernet MAC driver number (default) */ -+#ifndef ETH_MAC_NUM -+#define ETH_MAC_NUM 0 -+#endif -+ -+/* Ethernet PHY driver number (default) */ -+#ifndef ETH_PHY_NUM -+#define ETH_PHY_NUM 0 -+#endif -+ -+/* Ethernet base address */ -+#if __CORTEX_M > 7U -+/* MPS3 platform */ -+#define CMSDK_ETH_BASE ETHERNET_BASE_NS -+#else -+/* MPS2 platform */ -+#ifndef CMSDK_ETH_BASE -+#define CMSDK_ETH_BASE (0x40200000UL) -+#endif -+#endif -+ -+/* LAN91C111 Register Access */ -+#define LREG(object, reg) (*((object volatile *)(CMSDK_ETH_BASE+reg))) -+ -+#ifdef __clang__ -+ #define __rbit( v ) __builtin_arm_rbit( v ) -+#elif defined( __GNUC__ ) -+ #define __rbit( v ) __RBIT( v ) -+#endif -+ -+/* Memory Buffer configuration */ -+#define ETH_BUF_SIZE 1536 /* Packet Transmit buffer size */ -+ -+/* Driver Version */ -+static const ARM_DRIVER_VERSION MAC_DriverVersion = { -+ ARM_ETH_MAC_API_VERSION, -+ ARM_ETH_MAC_DRV_VERSION -+}; -+ -+/* Driver Capabilities */ -+static const ARM_ETH_MAC_CAPABILITIES MAC_DriverCapabilities = { -+ 0, /* checksum_offload_rx_ip4 */ -+ 0, /* checksum_offload_rx_ip6 */ -+ 0, /* checksum_offload_rx_udp */ -+ 0, /* checksum_offload_rx_tcp */ -+ 0, /* checksum_offload_rx_icmp */ -+ 0, /* checksum_offload_tx_ip4 */ -+ 0, /* checksum_offload_tx_ip6 */ -+ 0, /* checksum_offload_tx_udp */ -+ 0, /* checksum_offload_tx_tcp */ -+ 0, /* checksum_offload_tx_icmp */ -+ 0, /* media_interface */ -+ 1, /* mac_address */ -+ 1, /* event_rx_frame */ -+ 0, /* event_tx_frame */ -+ 0, /* event_wakeup */ -+ 0, /* precision_timer */ -+ 0 /* reserved */ -+}; -+ -+/* Local variables */ -+static ETH_CTRL ETH = { 0, 0, 0, 0, 0 }; -+static uint8_t tx_buf[ETH_BUF_SIZE]; -+ -+/* Local functions */ -+static void MAC_SelectBank (uint8_t bank); -+static uint32_t crc32_8bit_rev (uint32_t crc32, uint8_t val); -+static uint32_t crc32_data (const uint8_t *data, uint32_t len); -+static void output_MDO (uint32_t val, uint32_t num); -+static void turnaround_MDO (void); -+static uint32_t input_MDI (void); -+ -+/** -+ \fn void MAC_SelectBank (uint8_t bank) -+ \brief Select IO register bank. -+ \param[in] bank register bank -+ \return none. -+*/ -+static void MAC_SelectBank (uint8_t bank) { -+ LREG(uint16_t, BSR) = BSR_UPPER | (bank & BSR_MASK); -+} -+ -+/** -+ \fn uint32_t crc32_8bit_rev (uint32_t crc32, uint8_t val) -+ \brief Calculate 32-bit CRC (Polynom: 0x04C11DB7, data bit-reversed). -+ \param[in] crc32 CRC initial value -+ \param[in] val Input value -+ \return Calculated CRC value -+*/ -+static uint32_t crc32_8bit_rev (uint32_t crc32, uint8_t val) { -+ uint32_t n; -+ -+ crc32 ^= __rbit (val); -+ for (n = 8; n; n--) { -+ if (crc32 & 0x80000000) { -+ crc32 <<= 1; -+ crc32 ^= 0x04C11DB7; -+ } else { -+ crc32 <<= 1; -+ } -+ } -+ return (crc32); -+} -+ -+/** -+ \fn uint32_t crc32_data (const uint8_t *data, uint32_t len) -+ \brief Calculate standard 32-bit Ethernet CRC. -+ \param[in] data Pointer to buffer containing the data -+ \param[in] len Data length in bytes -+ \return Calculated CRC value -+*/ -+static uint32_t crc32_data (const uint8_t *data, uint32_t len) { -+ uint32_t crc; -+ -+ for (crc = 0xFFFFFFFF; len; len--) { -+ crc = crc32_8bit_rev (crc, *data++); -+ } -+ return (crc); -+} -+ -+/** -+ \fn void output_MDO (uint32_t val, uint32_t n) -+ \brief Output a value to the MII PHY management interface. -+ \param[in] val Pointer to buffer containing the data -+ \param[in] num Data length in bytes -+ \return none. -+*/ -+static void output_MDO (uint32_t val, uint32_t num) { -+ uint16_t rval; -+ -+ for (val <<= (32U - num); num; val <<= 1, num--) { -+ rval = MGMT_DEFAULT | MGMT_MDOE; -+ if (val & 0x80000000U) { -+ rval |= MGMT_MDO; -+ } -+ LREG(uint16_t, B3_MGMT) = rval; -+ LREG(uint16_t, B3_MGMT) = rval | MGMT_MCLK; -+ LREG(uint16_t, B3_MGMT) = rval; -+ } -+} -+ -+/** -+ \fn void turnaround_MDO (void) -+ \brief Turnaround MDO is tristated. -+ \return none. -+*/ -+static void turnaround_MDO (void) { -+ uint16_t rval = MGMT_DEFAULT; -+ -+ LREG(uint16_t, B3_MGMT) = rval; -+ LREG(uint16_t, B3_MGMT) = rval | MGMT_MCLK; -+ LREG(uint16_t, B3_MGMT) = rval; -+} -+ -+/** -+ \fn uint32_t input_MDI (void) -+ \brief Input a value from the MII PHY management interface. -+ \return none. -+*/ -+static uint32_t input_MDI (void) { -+ uint16_t rval = MGMT_DEFAULT; -+ uint32_t i,val = 0U; -+ -+ for (i = 0U; i < 16U; i++) { -+ LREG(uint16_t, B3_MGMT) = rval; -+ LREG(uint16_t, B3_MGMT) = rval | MGMT_MCLK; -+ LREG(uint16_t, B3_MGMT) = rval; -+ val <<= 1; -+ if (LREG(uint16_t, B3_MGMT) & MGMT_MDI) { -+ val |= 1U; -+ } -+ } -+ return (val); -+} -+ -+ -+/* Ethernet Driver functions */ -+ -+/** -+ \fn ARM_DRIVER_VERSION GetVersion (void) -+ \brief Get driver version. -+ \return \ref ARM_DRIVER_VERSION -+*/ -+static ARM_DRIVER_VERSION MAC_GetVersion (void) { -+ return MAC_DriverVersion; -+} -+ -+/** -+ \fn ARM_ETH_MAC_CAPABILITIES GetCapabilities (void) -+ \brief Get driver capabilities. -+ \return \ref ARM_ETH_MAC_CAPABILITIES -+*/ -+static ARM_ETH_MAC_CAPABILITIES MAC_GetCapabilities (void) { -+ return MAC_DriverCapabilities; -+} -+ -+/** -+ \fn int32_t Initialize (ARM_ETH_MAC_SignalEvent_t cb_event) -+ \brief Initialize Ethernet MAC Device. -+ \param[in] cb_event Pointer to \ref ARM_ETH_MAC_SignalEvent -+ \return \ref execution_status -+*/ -+static int32_t MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event) { -+ -+ if (ETH.flags & ETH_FLAG_INIT) { -+ return ARM_DRIVER_OK; -+ } -+ -+ /* Clear control structure */ -+ memset (Ð, 0, sizeof (ETH_CTRL)); -+ -+ ETH.cb_event = cb_event; -+ ETH.flags = ETH_FLAG_INIT; -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t Uninitialize (void) -+ \brief De-initialize Ethernet MAC Device. -+ \return \ref execution_status -+*/ -+static int32_t MAC_Uninitialize (void) { -+ -+ ETH.flags = 0U; -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t PowerControl (ARM_POWER_STATE state) -+ \brief Control Ethernet MAC Device Power. -+ \param[in] state Power state -+ \return \ref execution_status -+*/ -+static int32_t MAC_PowerControl (ARM_POWER_STATE state) { -+ uint32_t val; -+ -+ switch ((int32_t)state) { -+ case ARM_POWER_OFF: -+ /* Disable interrupts */ -+ NVIC_DisableIRQ(ETHERNET_IRQn); -+ -+ /* Power down */ -+ MAC_SelectBank (1); -+ LREG(uint16_t, B1_CR) = CR_DEFAULT; -+ -+ ETH.flags &= ~ETH_FLAG_POWER; -+ break; -+ -+ case ARM_POWER_LOW: -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ -+ case ARM_POWER_FULL: -+ if ((ETH.flags & ETH_FLAG_INIT) == 0) { -+ return ARM_DRIVER_ERROR; -+ } -+ if (ETH.flags & ETH_FLAG_POWER) { -+ return ARM_DRIVER_OK; -+ } -+ -+ /* Check device ID */ -+ MAC_SelectBank (3); -+ val = LREG(uint16_t, B3_REV); -+ if ((val & 0xFFF0) != REV_CHIP_ID) { -+ /* Invalid ID */ -+ return ARM_DRIVER_ERROR; -+ } -+ -+ /* Clear Interrupt Mask */ -+ MAC_SelectBank (2); -+ LREG(uint8_t, B2_MSK) = 0; -+ -+ /* Reset receiver */ -+ MAC_SelectBank (0); -+ LREG(uint16_t, B0_RCR) = RCR_SOFT_RST; -+ -+ /* Configure LEDs */ -+ LREG(uint16_t, B0_RPCR)= LEDA_10M_100M | LEDB_TX_RX; -+ -+ /* Clear control registers */ -+ LREG(uint16_t, B0_RCR) = 0; -+ LREG(uint16_t, B0_TCR) = 0; -+ -+ /* Write Configuration */ -+ MAC_SelectBank (1); -+ LREG(uint16_t, B1_CR) = CR_EPH_POW_EN | CR_DEFAULT; -+ LREG(uint16_t, B1_CTR) = CTR_LE_ENABLE | CTR_CR_ENABLE | CTR_TE_ENABLE | CTR_AUTO_REL | CTR_DEFAULT; -+ -+ /* Reset MMU */ -+ MAC_SelectBank(2); -+ LREG(uint16_t, B2_MMUCR) = MMU_RESET; -+ while (LREG(uint16_t, B2_MMUCR) & MMUCR_BUSY); -+ -+ /* Configure Interrupt Mask */ -+ MAC_SelectBank (2); -+ LREG(uint8_t, B2_MSK) = MSK_RCV; -+ -+ /* Enable interrupts */ -+ NVIC_ClearPendingIRQ(ETHERNET_IRQn); -+ NVIC_SetPriority( ETHERNET_IRQn, configMAC_INTERRUPT_PRIORITY ); -+ NVIC_EnableIRQ(ETHERNET_IRQn); -+ -+ ETH.flags |= ETH_FLAG_POWER; -+ break; -+ -+ default: -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) -+ \brief Get Ethernet MAC Address. -+ \param[in] ptr_addr Pointer to address -+ \return \ref execution_status -+*/ -+static int32_t MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) { -+ uint16_t val; -+ -+ if (ptr_addr == NULL) { -+ return ARM_DRIVER_ERROR_PARAMETER; -+ } -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ MAC_SelectBank (1); -+ -+ val = LREG(uint16_t, B1_IAR0); -+ ptr_addr->b[0] = (uint8_t)val; -+ ptr_addr->b[1] = (uint8_t)(val >> 8); -+ -+ val = LREG(uint16_t, B1_IAR2); -+ ptr_addr->b[2] = (uint8_t)val; -+ ptr_addr->b[3] = (uint8_t)(val >> 8); -+ -+ val = LREG(uint16_t, B1_IAR4); -+ ptr_addr->b[4] = (uint8_t)val; -+ ptr_addr->b[5] = (uint8_t)(val >> 8); -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) -+ \brief Set Ethernet MAC Address. -+ \param[in] ptr_addr Pointer to address -+ \return \ref execution_status -+*/ -+static int32_t MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) { -+ uint16_t val; -+ -+ if (ptr_addr == NULL) { -+ return ARM_DRIVER_ERROR_PARAMETER; -+ } -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ MAC_SelectBank (1); -+ -+ val = (uint16_t) ptr_addr->b[0]; -+ val |= (uint16_t)(ptr_addr->b[1] << 8); -+ LREG(uint16_t, B1_IAR0) = val; -+ -+ val = (uint16_t) ptr_addr->b[2]; -+ val |= (uint16_t)(ptr_addr->b[3] << 8); -+ LREG(uint16_t, B1_IAR2) = val; -+ -+ val = (uint16_t) ptr_addr->b[4]; -+ val |= (uint16_t)(ptr_addr->b[5] << 8); -+ LREG(uint16_t, B1_IAR4) = val; -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, -+ uint32_t num_addr) -+ \brief Configure Address Filter. -+ \param[in] ptr_addr Pointer to addresses -+ \param[in] num_addr Number of addresses to configure -+ \return \ref execution_status -+*/ -+static int32_t MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr) { -+ uint32_t crc, hi, lo; -+ -+ if ((ptr_addr == NULL) && (num_addr != 0U)) { -+ return ARM_DRIVER_ERROR_PARAMETER; -+ } -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ hi = 0U; -+ lo = 0U; -+ -+ if (num_addr != 0U) { -+ /* Calculate 64-bit Hash table for MAC addresses */ -+ while (num_addr > 0U) { -+ crc = crc32_data (&ptr_addr->b[0], 6) >> 26; -+ if (crc & 0x20) { -+ hi |= (1 << (crc & 0x1F)); -+ } else { -+ lo |= (1 << crc); -+ } -+ -+ ptr_addr++; -+ num_addr--; -+ } -+ } -+ -+ /* Set hash registers */ -+ MAC_SelectBank (3); -+ LREG(uint16_t, B3_MT0) = (uint16_t)lo; -+ LREG(uint16_t, B3_MT2) = (uint16_t)(lo >> 16); -+ LREG(uint16_t, B3_MT4) = (uint16_t)hi; -+ LREG(uint16_t, B3_MT6) = (uint16_t)(hi >> 16); -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) -+ \brief Send Ethernet frame. -+ \param[in] frame Pointer to frame buffer with data to send -+ \param[in] len Frame buffer length in bytes -+ \param[in] flags Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...) -+ \return \ref execution_status -+*/ -+static int32_t MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) { -+ uint8_t packnr; -+ uint32_t i,sz; -+ -+ if ((frame == NULL) || (len == 0U)) { -+ return ARM_DRIVER_ERROR_PARAMETER; -+ } -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ if ((ETH.tx_len + len) > ETH_BUF_SIZE) { -+ /* Frame size invalid */ -+ return ARM_DRIVER_ERROR; -+ } -+ -+ if (flags & ARM_ETH_MAC_TX_FRAME_FRAGMENT) { -+ memcpy (&tx_buf[ETH.tx_len], frame, len); -+ ETH.tx_len += len; -+ return ARM_DRIVER_OK; -+ } -+ -+ /* Last fragment, send frame */ -+ MAC_SelectBank(2); -+ -+ /* MMU allocate memory for transmitting */ -+ LREG(uint16_t, B2_MMUCR) = MMU_ALLOC_TX; -+ -+ if ((LREG(uint8_t, B2_IST) & IST_ALLOC_INT) == 0U) { -+ /* Not enough space, FIFO is busy transmitting */ -+ return ARM_DRIVER_ERROR_BUSY; -+ } -+ -+ memcpy (&tx_buf[ETH.tx_len], frame, len); -+ ETH.tx_len += len; -+ -+ /* Set TX packet number */ -+ packnr = LREG(uint8_t, B2_ARR); -+ LREG(uint8_t, B2_PNR) = packnr; -+ LREG(uint16_t, B2_PTR) = PTR_AUTO_INCR; -+ -+ /* Reserve space for Status Word */ -+ LREG(uint16_t, B2_DATA0) = 0x0000; -+ /* Set Total Size */ -+ LREG(uint16_t, B2_DATA0) = ETH.tx_len + 6; -+ -+ /* Send content from the intermediate buffer */ -+ for (i = 0U, sz = ETH.tx_len; sz > 1; i += 2U, sz -= 2U) { -+ LREG(uint16_t, B2_DATA0) = __UNALIGNED_UINT16_READ(&tx_buf[i]); -+ } -+ -+ /* Add control word and odd data byte */ -+ if (sz > 0U) { -+ LREG(uint16_t, B2_DATA0) = RFC_CRC | RFC_ODD | tx_buf[i]; -+ } else { -+ LREG(uint16_t, B2_DATA0) = RFC_CRC; -+ } -+ -+ /* Enable transmitter */ -+ MAC_SelectBank (0); -+ LREG(uint16_t, B0_TCR) = TCR_TXENA | TCR_PAD_EN; -+ -+ /* Enqueue the packet */ -+ MAC_SelectBank (2); -+ LREG(uint16_t, B2_MMUCR) = MMU_ENQ_TX; -+ -+ ETH.tx_len = 0U; -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t ReadFrame (uint8_t *frame, uint32_t len) -+ \brief Read data of received Ethernet frame. -+ \param[in] frame Pointer to frame buffer for data to read into -+ \param[in] len Frame buffer length in bytes -+ \return number of data bytes read or execution status -+ - value >= 0: number of data bytes read -+ - value < 0: error occurred, value is execution status as defined with \ref execution_status -+*/ -+static int32_t MAC_ReadFrame (uint8_t *frame, uint32_t len) { -+ uint32_t stat,sz,data; -+ -+ if ((frame == NULL) && (len != 0U)) { -+ return ARM_DRIVER_ERROR_PARAMETER; -+ } -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ MAC_SelectBank (2); -+ -+ if ((frame == NULL) && (len == 0U)) { -+ /* Discard received frame */ -+ LREG(uint16_t, B2_MMUCR) = MMU_REMV_REL_RX; -+ -+ /* Re-enable RCV interrupts */ -+ stat = LREG(uint16_t, B2_FIFO); -+ if (stat & FIFO_REMPTY) { -+ LREG(uint8_t, B2_MSK) = MSK_RCV; -+ } -+ return (0); -+ } -+ -+ /* Pointer Register set to RCV + Auto Increase + Read access */ -+ LREG(uint16_t, B2_PTR) = PTR_RCV | PTR_AUTO_INCR | PTR_READ; -+ -+ /* Read status word and packet length */ -+ stat = LREG(uint32_t, B2_DATA); -+ sz = (stat >> 16) - ((stat & RFS_ODDFRM) ? 5 : 6); -+ -+ if (sz != len) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ /* Copy aligned bytes */ -+ for ( ; sz > 3U; frame += 4U, sz -= 4U) { -+ __UNALIGNED_UINT32_WRITE(&frame[0], LREG(uint32_t, B2_DATA)); -+ } -+ -+ /* Copy remaining bytes */ -+ if (sz > 0U) { -+ data = LREG(uint32_t, B2_DATA); -+ for ( ; sz > 0U; frame++, sz--) { -+ frame[0] = (uint8_t)data; -+ data >>= 8U; -+ } -+ } -+ -+ /* MMU free packet */ -+ LREG(uint16_t, B2_MMUCR) = MMU_REMV_REL_RX; -+ -+ /* Re-enable RCV interrupts */ -+ stat = LREG(uint16_t, B2_FIFO); -+ if (stat & FIFO_REMPTY) { -+ LREG(uint8_t, B2_MSK) = MSK_RCV; -+ } -+ -+ return ((int32_t)len); -+} -+ -+/** -+ \fn uint32_t GetRxFrameSize (void) -+ \brief Get size of received Ethernet frame. -+ \return number of bytes in received frame -+*/ -+static uint32_t MAC_GetRxFrameSize (void) { -+ uint32_t stat; -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return (0U); -+ } -+ -+ MAC_SelectBank (2); -+ stat = LREG(uint16_t, B2_FIFO); -+ if (stat & FIFO_REMPTY) { -+ /* RX Status FIFO empty */ -+ return (0U); -+ } -+ -+ /* Pointer Register set to RCV + Auto Increase + Read access */ -+ LREG(uint16_t, B2_PTR) = PTR_RCV | PTR_AUTO_INCR | PTR_READ; -+ -+ /* Read frame status and length */ -+ stat = LREG(uint32_t, B2_DATA); -+ if (stat & (RFS_ALGNERR | RFS_BADCRC | RFS_TOOLNG | RFS_TOOSHORT)) { -+ /* Error, this frame is invalid */ -+ return (0xFFFFFFFF); -+ } -+ if ((stat >> 16) < 22U) { -+ /* Error, this frame is too short */ -+ return (0xFFFFFFFF); -+ } -+ -+ /* Return data length */ -+ return ((stat >> 16) - ((stat & RFS_ODDFRM) ? 5 : 6)); -+} -+ -+/** -+ \fn int32_t GetRxFrameTime (ARM_ETH_MAC_TIME *time) -+ \brief Get time of received Ethernet frame. -+ \param[in] time Pointer to time structure for data to read into -+ \return \ref execution_status -+*/ -+static int32_t MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time) { -+ (void)time; -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+} -+ -+/** -+ \fn int32_t GetTxFrameTime (ARM_ETH_MAC_TIME *time) -+ \brief Get time of transmitted Ethernet frame. -+ \param[in] time Pointer to time structure for data to read into -+ \return \ref execution_status -+*/ -+static int32_t MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time) { -+ (void)time; -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+} -+ -+/** -+ \fn int32_t ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) -+ \brief Control Precision Timer. -+ \param[in] control Operation -+ \param[in] time Pointer to time structure -+ \return \ref execution_status -+*/ -+static int32_t MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) { -+ (void)control; -+ (void)time; -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+} -+ -+/** -+ \fn int32_t Control (uint32_t control, uint32_t arg) -+ \brief Control Ethernet Interface. -+ \param[in] control Operation -+ \param[in] arg Argument of operation (optional) -+ \return \ref execution_status -+*/ -+static int32_t MAC_Control (uint32_t control, uint32_t arg) { -+ uint16_t mac_tcr, mac_rcr, mac_rpcr; -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ switch (control) { -+ case ARM_ETH_MAC_CONFIGURE: -+ if ((arg & ARM_ETH_MAC_SPEED_Msk) == ARM_ETH_MAC_SPEED_1G) { -+ /* 1Gbit is not supported */ -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ -+ MAC_SelectBank (0); -+ mac_tcr = LREG(uint16_t, B0_TCR); -+ mac_rcr = LREG(uint16_t, B0_RCR); -+ mac_rpcr = LREG(uint16_t, B0_RPCR); -+ -+ if ((arg & ARM_ETH_MAC_DUPLEX_Msk) == ARM_ETH_MAC_DUPLEX_FULL) { -+ /* Enable full duplex mode */ -+ mac_rpcr |= RPCR_DPLX; -+ } else { -+ /* Enable half duplex mode */ -+ mac_rpcr &= ~RPCR_DPLX; -+ } -+ -+ if ((arg & ARM_ETH_MAC_LOOPBACK) != 0) { -+ /* Enable loopback mode */ -+ mac_tcr |= TCR_EPH_LOOP; -+ } else { -+ mac_tcr &= ~TCR_EPH_LOOP; -+ } -+ -+ if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) || -+ (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX)) { -+ /* Checksum offload is not supported */ -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ -+ if ((arg & ARM_ETH_MAC_ADDRESS_BROADCAST) != 0) { -+ /* Enable broadcast frame receive */ -+ /* Not used, always enabled */ -+ } -+ -+ if ((arg & ARM_ETH_MAC_ADDRESS_MULTICAST) != 0) { -+ /* Enable all multicast frame receive */ -+ mac_rcr |= RCR_ALMUL; -+ } else { -+ mac_rcr &= ~RCR_ALMUL; -+ } -+ -+ if ((arg & ARM_ETH_MAC_ADDRESS_ALL) != 0) { -+ /* Enable all frame receive (Promiscuous mode) */ -+ mac_rcr |= RCR_PRMS; -+ } else { -+ mac_rcr &= ~RCR_PRMS; -+ } -+ -+ /* Set configuration */ -+ LREG(uint16_t, B0_TCR) = mac_tcr; -+ LREG(uint16_t, B0_RCR) = mac_rcr; -+ LREG(uint16_t, B0_RPCR) = mac_rpcr; -+ break; -+ -+ case ARM_ETH_MAC_CONTROL_TX: -+ /* Enable/disable MAC transmitter */ -+ MAC_SelectBank (0); -+ mac_tcr = LREG(uint16_t, B0_TCR); -+ -+ if (arg != 0) { -+ mac_tcr |= TCR_TXENA; -+ } else { -+ mac_tcr &= ~TCR_TXENA; -+ } -+ -+ LREG(uint16_t, B0_TCR) = mac_tcr; -+ break; -+ -+ case ARM_ETH_MAC_CONTROL_RX: -+ /* Enable/disable MAC receiver */ -+ MAC_SelectBank (0); -+ mac_rcr = LREG(uint16_t, B0_RCR); -+ -+ if (arg != 0) { -+ mac_rcr |= RCR_RXEN; -+ } else { -+ mac_rcr &= ~RCR_RXEN; -+ } -+ -+ LREG(uint16_t, B0_RCR) = mac_rcr; -+ break; -+ -+ case ARM_ETH_MAC_FLUSH: -+ /* Flush Tx and Rx buffers */ -+ if ((arg & ARM_ETH_MAC_FLUSH_RX) != 0) { -+ MAC_SelectBank (0); -+ mac_rcr = LREG(uint16_t, B0_RCR); -+ -+ /* Disable Rx */ -+ LREG(uint16_t, B0_RCR) = (mac_rcr | RCR_SOFT_RST) & ~RCR_RXEN; -+ -+ MAC_SelectBank (2); -+ while ((LREG(uint16_t, B2_FIFO) & FIFO_REMPTY) == 0U) { -+ /* Force MMU Rx Discard */ -+ LREG(uint16_t, B2_MMUCR) = MMU_REMV_REL_RX; -+ while (LREG(uint16_t, B2_MMUCR) & MMUCR_BUSY); -+ } -+ -+ MAC_SelectBank (0); -+ LREG(uint16_t, B0_RCR) = mac_rcr; -+ } -+ -+ if ((arg & ARM_ETH_MAC_FLUSH_TX) != 0) { -+ MAC_SelectBank (0); -+ mac_tcr = LREG(uint16_t, B0_TCR); -+ -+ /* Disable Tx */ -+ LREG(uint16_t, B0_TCR) = mac_tcr & ~TCR_TXENA; -+ -+ MAC_SelectBank (2); -+ LREG(uint16_t, B2_MMUCR) = MMU_RESET_TX; -+ while (LREG(uint16_t, B2_MMUCR) & MMUCR_BUSY); -+ -+ MAC_SelectBank (0); -+ LREG(uint16_t, B0_TCR) = mac_tcr; -+ } -+ break; -+ -+ default: -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn void ETHERNET_Handler (void) -+ \brief Ethernet Interrupt handler. -+*/ -+extern void ETHERNET_Handler(void); -+void ETHERNET_Handler(void) { -+ uint32_t event = 0U; -+ uint16_t bank; -+ uint8_t stat; -+ -+ /* Preserve current bank selection */ -+ bank = LREG(uint16_t, BSR); -+ MAC_SelectBank (2); -+ stat = LREG(uint8_t, B2_IST); -+ if ((stat & IST_RCV_INT) != 0) { -+ /* Receive interrupt */ -+ event |= ARM_ETH_MAC_EVENT_RX_FRAME; -+ /* Clear Interrupt Mask */ -+ LREG(uint8_t, B2_MSK) = 0; -+ } -+ MAC_SelectBank ((uint8_t)bank); -+ -+ /* Callback event notification */ -+ if (event && ETH.cb_event) { -+ ETH.cb_event (event); -+ } -+} -+ -+/** -+ \fn int32_t PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) -+ \brief Read Ethernet PHY Register through Management Interface. -+ \param[in] phy_addr 5-bit device address -+ \param[in] reg_addr 5-bit register address -+ \param[out] data Pointer where the result is written to -+ \return \ref execution_status -+*/ -+static int32_t PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) { -+ -+ MAC_SelectBank(3); -+ -+ /* 32 consecutive ones on MDO to establish sync */ -+ output_MDO (0xFFFFFFFFU, 32U); -+ -+ /* start code (01), read command (10) */ -+ output_MDO (0x06U, 4U); -+ -+ /* write PHY address */ -+ output_MDO (phy_addr, 5U); -+ -+ /* write the PHY register to write */ -+ output_MDO (reg_addr, 5U); -+ -+ /* turnaround MDO is tristated */ -+ turnaround_MDO (); -+ -+ /* read the data value */ -+ *data = (uint16_t)input_MDI (); -+ -+ /* turnaround MDO is tristated */ -+ turnaround_MDO (); -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) -+ \brief Write Ethernet PHY Register through Management Interface. -+ \param[in] phy_addr 5-bit device address -+ \param[in] reg_addr 5-bit register address -+ \param[in] data 16-bit data to write -+ \return \ref execution_status -+*/ -+static int32_t PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) { -+ -+ MAC_SelectBank(3); -+ -+ /* 32 consecutive ones on MDO to establish sync */ -+ output_MDO (0xFFFFFFFFU, 32U); -+ -+ /* start code (01), write command (01) */ -+ output_MDO (0x05U, 4U); -+ -+ /* write PHY address */ -+ output_MDO (phy_addr, 5U); -+ -+ /* write the PHY register to write */ -+ output_MDO (reg_addr, 5U); -+ -+ /* turnaround MDO (1,0)*/ -+ output_MDO (0x02U, 2U); -+ -+ /* write the data value */ -+ output_MDO (data, 16U); -+ -+ /* turnaround MDO is tristated */ -+ turnaround_MDO (); -+ -+ return ARM_DRIVER_OK; -+} -+ -+ -+/* MAC Driver Control Block */ -+extern -+ARM_DRIVER_ETH_MAC ARM_Driver_ETH_MAC_(ETH_MAC_NUM); -+ARM_DRIVER_ETH_MAC ARM_Driver_ETH_MAC_(ETH_MAC_NUM) = { -+ MAC_GetVersion, -+ MAC_GetCapabilities, -+ MAC_Initialize, -+ MAC_Uninitialize, -+ MAC_PowerControl, -+ MAC_GetMacAddress, -+ MAC_SetMacAddress, -+ MAC_SetAddressFilter, -+ MAC_SendFrame, -+ MAC_ReadFrame, -+ MAC_GetRxFrameSize, -+ MAC_GetRxFrameTime, -+ MAC_GetTxFrameTime, -+ MAC_ControlTimer, -+ MAC_Control, -+ PHY_Read, -+ PHY_Write -+}; -+ -+ -+/* Driver Version */ -+static const ARM_DRIVER_VERSION PHY_DriverVersion = { -+ ARM_ETH_PHY_API_VERSION, -+ ARM_ETH_PHY_DRV_VERSION -+}; -+ -+/** -+ \fn ARM_DRV_VERSION GetVersion (void) -+ \brief Get driver version. -+ \return \ref ARM_DRV_VERSION -+*/ -+static ARM_DRIVER_VERSION PHY_GetVersion (void) { -+ return PHY_DriverVersion; -+} -+ -+/** -+ \fn int32_t Initialize (ARM_ETH_PHY_Read_t fn_read, -+ ARM_ETH_PHY_Write_t fn_write) -+ \brief Initialize Ethernet PHY Device. -+ \param[in] fn_read Pointer to \ref ARM_ETH_MAC_PHY_Read -+ \param[in] fn_write Pointer to \ref ARM_ETH_MAC_PHY_Write -+ \return \ref execution_status -+*/ -+static int32_t PHY_Initialize (ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write) { -+ /* PHY_Read and PHY_Write will be re-used, no need to register them again */ -+ uint16_t val; -+ (void)fn_read; -+ (void)fn_write; -+ -+ /* Reset PHY */ -+ PHY_Write (ETH_PHY_ADDR, PHY_CR, PHY_CR_RST); -+ -+ /* Clear PHY status */ -+ PHY_Read (ETH_PHY_ADDR, PHY_SO, &val); -+ -+ ETH.phy_cr = 0U; -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t Uninitialize (void) -+ \brief De-initialize Ethernet PHY Device. -+ \return \ref execution_status -+*/ -+static int32_t PHY_Uninitialize (void) { -+ -+ ETH.phy_cr = 0U; -+ -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t PowerControl (ARM_POWER_STATE state) -+ \brief Control Ethernet PHY Device Power. -+ \param[in] state Power state -+ \return \ref execution_status -+*/ -+static int32_t PHY_PowerControl (ARM_POWER_STATE state) { -+ uint16_t val; -+ -+ switch ((int32_t)state) { -+ case ARM_POWER_OFF: -+ /* Select Power Saving Mode */ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ ETH.phy_cr = PHY_CR_PDN; -+ break; -+ case ARM_POWER_FULL: -+ /* Select Normal Operation Mode */ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ /* Check Device Identification. */ -+ PHY_Read (ETH_PHY_ADDR, PHY_ID1, &val); -+ if (val != PHY_CHIP_ID1) { -+ /* Invalid PHY ID1 */ -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ PHY_Read (ETH_PHY_ADDR, PHY_ID2, &val); -+ if ((val & 0xFFF0) != PHY_CHIP_ID2) { -+ /* Invalid PHY ID2 */ -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ -+ ETH.phy_cr = 0U; -+ break; -+ case ARM_POWER_LOW: -+ default: -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ -+ return PHY_Write (ETH_PHY_ADDR, PHY_CR, ETH.phy_cr); -+} -+ -+/** -+ \fn int32_t SetInterface (uint32_t interface) -+ \brief Set Ethernet Media Interface. -+ \param[in] interface Media Interface type -+ \return \ref execution_status -+*/ -+static int32_t PHY_SetInterface (uint32_t interface) { -+ /* Not used in this driver */ -+ (void)interface; -+ return ARM_DRIVER_OK; -+} -+ -+/** -+ \fn int32_t SetMode (uint32_t mode) -+ \brief Set Ethernet PHY Device Operation mode. -+ \param[in] mode Operation Mode -+ \return \ref execution_status -+*/ -+static int32_t PHY_SetMode (uint32_t mode) { -+ uint16_t val; -+ -+ if ((ETH.flags & ETH_FLAG_POWER) == 0U) { -+ return ARM_DRIVER_ERROR; -+ } -+ -+ val = ETH.phy_cr & PHY_CR_PDN; -+ -+ switch (mode & ARM_ETH_PHY_SPEED_Msk) { -+ case ARM_ETH_PHY_SPEED_10M: -+ break; -+ case ARM_ETH_PHY_SPEED_100M: -+ val |= PHY_CR_SPEED; -+ break; -+ default: -+ return ARM_DRIVER_ERROR_UNSUPPORTED; -+ } -+ -+ switch (mode & ARM_ETH_PHY_DUPLEX_Msk) { -+ case ARM_ETH_PHY_DUPLEX_HALF: -+ break; -+ case ARM_ETH_PHY_DUPLEX_FULL: -+ val |= PHY_CR_DPLX; -+ break; -+ } -+ -+ if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE) { -+ val |= PHY_CR_ANEG_EN; -+ } -+ if (mode & ARM_ETH_PHY_LOOPBACK) { -+ val |= PHY_CR_LPBK; -+ } -+ if (mode & ARM_ETH_PHY_ISOLATE) { -+ val |= PHY_CR_MII_DIS; -+ } -+ -+ ETH.phy_cr = val; -+ -+ /* Apply configured mode */ -+ return PHY_Write (ETH_PHY_ADDR, PHY_CR, val); -+} -+ -+/** -+ \fn ARM_ETH_LINK_STATE GetLinkState (void) -+ \brief Get Ethernet PHY Device Link state. -+ \return current link status \ref ARM_ETH_LINK_STATE -+*/ -+static ARM_ETH_LINK_STATE PHY_GetLinkState (void) { -+ ARM_ETH_LINK_STATE state = ARM_ETH_LINK_DOWN; -+ uint16_t val = 0U; -+ -+ if (ETH.flags & ETH_FLAG_POWER) { -+ PHY_Read (ETH_PHY_ADDR, PHY_SR, &val); -+ } -+ if (val & PHY_SR_LINK) { -+ /* Link Status bit is set */ -+ state = ARM_ETH_LINK_UP; -+ } -+ return (state); -+} -+ -+/** -+ \fn ARM_ETH_LINK_INFO GetLinkInfo (void) -+ \brief Get Ethernet PHY Device Link information. -+ \return current link parameters \ref ARM_ETH_LINK_INFO -+*/ -+static ARM_ETH_LINK_INFO PHY_GetLinkInfo (void) { -+ ARM_ETH_LINK_INFO info; -+ uint32_t speed, duplex; -+ uint16_t val = 0U; -+ -+ speed = ARM_ETH_SPEED_10M; -+ duplex = ARM_ETH_DUPLEX_HALF; -+ -+ if (ETH.flags & ETH_FLAG_POWER) { -+ PHY_Read (ETH_PHY_ADDR, PHY_SO, &val); -+ } -+ if (val & PHY_SO_SPDDET) { -+ speed = ARM_ETH_SPEED_100M; -+ } -+ if (val & PHY_SO_DPLXDET) { -+ duplex = ARM_ETH_DUPLEX_FULL; -+ } -+ -+ /* Link must be up to get valid state */ -+ info.speed = speed; -+ info.duplex = duplex; -+ -+ return (info); -+} -+ -+/* PHY Driver Control Block */ -+extern -+ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_(ETH_PHY_NUM); -+ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_(ETH_PHY_NUM) = { -+ PHY_GetVersion, -+ PHY_Initialize, -+ PHY_Uninitialize, -+ PHY_PowerControl, -+ PHY_SetInterface, -+ PHY_SetMode, -+ PHY_GetLinkState, -+ PHY_GetLinkInfo -+}; -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.h b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.h -new file mode 100644 -index 0000000..1a09ead ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMSIS_Driver/ETH_LAN91C111.h -@@ -0,0 +1,319 @@ -+/* *INDENT-OFF* */ -+ -+/* -+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ * -+ * ----------------------------------------------------------------------- -+ * -+ * $Date: 2. September 2021 -+ * $Revision: V1.0 -+ * -+ * Project: Register Interface Definitions for LAN91C111 -+ * -------------------------------------------------------------------- */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS-Driver/blob/b91908d907b647bd212920e30b383b03809d68e0/ETH/ETH_LAN91C111.h -+*/ -+ -+#ifndef ETH_LAN91C111_H__ -+#define ETH_LAN91C111_H__ -+ -+#include -+#include "Driver_ETH_MAC.h" -+ -+/* Bank Select Register */ -+#define BSR 0x0E // Bank Select register common to all banks -+#define BSR_MASK 0x03 // Mask constant part of bank register -+#define BSR_UPPER 0x3300 // Constant value for upper byte of BSR -+ -+/* Bank 0 Registers */ -+#define B0_TCR 0x00 // Transmit Control Register -+#define B0_EPHSR 0x02 // EPH Status Register -+#define B0_RCR 0x04 // Receive Control Register -+#define B0_ECR 0x06 // Counter Register -+#define B0_MIR 0x08 // Memory Information Register -+#define B0_RPCR 0x0A // Receive/Phy Control Register -+#define B0_RES 0x0C // Reserved -+ -+/* Bank 1 Registers */ -+#define B1_CR 0x00 // Configuration Register -+#define B1_BAR 0x02 // Base Address Register -+#define B1_IAR 0x04 // Individual Address Registers -+#define B1_IAR0 0x04 // Individual Address Bytes 0-1 -+#define B1_IAR2 0x06 // Individual Address Bytes 2-3 -+#define B1_IAR4 0x08 // Individual Address Bytes 4-5 -+#define B1_GPR 0x0A // General Purpose Register -+#define B1_CTR 0x0C // Control Register -+ -+/* Bank 2 Registers */ -+#define B2_MMUCR 0x00 // MMU Command Register -+#define B2_PNR 0x02 // Packet Number Register (8 bit) -+#define B2_ARR 0x03 // Allocation Result Register (8 bit) -+#define B2_FIFO 0x04 // FIFO Ports Register -+#define B2_TX_FIFO 0x04 // Tx FIFO Packet Number (8 bit) -+#define B2_RX_FIFO 0x05 // Rx FIFO Packet Number (8 bit) -+#define B2_PTR 0x06 // Pointer Register -+#define B2_DATA 0x08 // Data Register (8/16/32 bit) -+#define B2_DATA0 0x08 // Data Register Word 0 -+#define B2_DATA1 0x0A // Data Register Word 1 -+#define B2_IST 0x0C // Interrupt Status Register (8 bit) -+#define B2_ACK 0x0C // Interrupt Ack Register (8 bit) -+#define B2_MSK 0x0D // Interrupt Mask Register (8 bit) -+ -+/* Bank 3 Registers */ -+#define B3_MT 0x00 // Multicast Hash Table -+#define B3_MT0 0x00 // Multicast Hash Table 0-1 -+#define B3_MT2 0x02 // Multicast Hash Table 2-3 -+#define B3_MT4 0x04 // Multicast Hash Table 4-5 -+#define B3_MT6 0x06 // Multicast Hash Table 6-7 -+#define B3_MGMT 0x08 // Management Interface PHY -+#define B3_REV 0x0A // Revision Register (Chip Id/Revision) -+#define B3_ERCV 0x0C // Early Receive Register -+ -+/* Transmit Control Register */ -+#define TCR_SWFDUP 0x8000 // Switched Full Duplex Mode -+#define TCR_EPH_LOOP 0x2000 // Internal Loopback at the EPH block -+#define TCR_STP_SQET 0x1000 // Stop transmit on SQET error -+#define TCR_FDUPLX 0x0800 // Full duplex mode (receive own frames) -+#define TCR_MON_CSN 0x0400 // Monitor carrier while transmitting -+#define TCR_NOCRC 0x0100 // Don't append CRC to tx frames -+#define TCR_PAD_EN 0x0080 // Pad short frames -+#define TCR_FORCOL 0x0004 // Force collision -+#define TCR_LOOP 0x0002 // PHY Local loopback -+#define TCR_TXENA 0x0001 // Enable transmitter -+ -+/* EPH Status Register */ -+#define EPHSR_TXUNRN 0x8000 // Transmit Underrun -+#define EPHSR_LINK_OK 0x4000 // General purpose input driven by nLNK pin -+#define EPHSR_CTR_ROL 0x1000 // Counter Roll Over -+#define EPHSR_EXC_DEF 0x0800 // Excessive Deferral -+#define EPHSR_LOST_CARR 0x0400 // Lost Carrier Sense -+#define EPHSR_LATCOL 0x0200 // Late Collision Detected -+#define EPHSR_TX_DEFR 0x0080 // Transmit Deferred -+#define EPHSR_LTX_BRD 0x0040 // Last Tx Frame was a broadcast -+#define EPHSR_SQET 0x0020 // Signal Quality Error Test -+#define EPHSR_16COL 0x0010 // 16 collisions reached -+#define EPHSR_LTX_MULT 0x0008 // Last transmit frame was a multicast -+#define EPHSR_MULCOL 0x0004 // Multiple collision detected -+#define EPHSR_SNGLCOL 0x0002 // Single collision detected -+#define EPHSR_TX_SUC 0x0001 // Last transmit was successful -+ -+/* Receive Control Register */ -+#define RCR_SOFT_RST 0x8000 // Software Reset -+#define RCR_FILT_CAR 0x4000 // Filter Carrier -+#define RCR_ABORT_ENB 0x2000 // Enable Rx Abort when collision -+#define RCR_STRIP_CRC 0x0200 // Strip CRC of received frames -+#define RCR_RXEN 0x0100 // Enable Receiver -+#define RCR_ALMUL 0x0004 // Accept all multicast (no filtering) -+#define RCR_PRMS 0x0002 // Promiscuous mode -+#define RCR_RX_ABORT 0x0001 // Receive frame aborted (too long) -+ -+/* Receive/Phy Control Register */ -+#define RPCR_SPEED 0x2000 // Speed select input (10/100 MBps) -+#define RPCR_DPLX 0x1000 // Duplex Select (Full/Half Duplex) -+#define RPCR_ANEG 0x0800 // Auto-Negotiation mode select -+#define RPCR_LEDA_MASK 0x00E0 // LEDA signal mode select -+#define RPCR_LEDB_MASK 0x001C // LEDB signal mode select -+ -+/* RPCR LEDA mode */ -+#define LEDA_10M_100M 0x0000 // 10 MB or 100 MB link detected -+#define LEDA_10M 0x0040 // 10 MB link detected -+#define LEDA_FDUPLX 0x0060 // Full Duplex Mode enabled -+#define LEDA_TX_RX 0x0080 // Transmit or Receive packet occurred -+#define LEDA_100M 0x00A0 // 100 MB link detected -+#define LEDA_RX 0x00C0 // Receive packet occurred -+#define LEDA_TX 0x00E0 // Transmit packet occurred -+ -+/* RPCR LEDB mode */ -+#define LEDB_10M_100M 0x0000 // 10 MB or 100 MB link detected -+#define LEDB_10M 0x0008 // 10 MB link detected -+#define LEDB_FDUPLX 0x000C // Full Duplex Mode enabled -+#define LEDB_TX_RX 0x0010 // Transmit/Receive packet occurred -+#define LEDB_100M 0x0014 // 100 MB link detected -+#define LEDB_RX 0x0018 // Receive packet occurred -+#define LEDB_TX 0x001C // Transmit packet occurred -+ -+/* Configuration Register */ -+#define CR_EPH_POW_EN 0x8000 // EPH Power Enable (0= power down PHY) -+#define CR_NO_WAIT 0x1000 // No wait states -+#define CR_GPCNTRL 0x0400 // General purpose Output drives nCNTRL pin -+#define CR_EXT_PHY 0x0200 // External PHY enabled (0= internal PHY) -+#define CR_DEFAULT 0x20B1 // Default bits set to 1 for write -+ -+/* Control Register */ -+#define CTR_RCV_BADCRC 0x4000 // Bad CRC packet receive -+#define CTR_AUTO_REL 0x0800 // Auto-release Tx memory -+#define CTR_LE_ENABLE 0x0080 // Link error enable (mux into EPH int) -+#define CTR_CR_ENABLE 0x0040 // Counter rollover enable (mux into EPH int) -+#define CTR_TE_ENABLE 0x0020 // Transmit error enable (mux into EPH int) -+#define CTR_EEPROM_SEL 0x0004 // EEPROM select -+#define CTR_RELOAD 0x0002 // Reload from EEPROM -+#define CTR_STORE 0x0001 // Store to EEPROM -+#define CTR_DEFAULT 0x1210 // Default bits set to 1 for write -+ -+/* MMU Command Register */ -+#define MMUCR_CMD_MASK 0x00E0 // MMU Command mask -+#define MMUCR_BUSY 0x0001 // MMU processing a release command -+ -+/* MMUCR Commands */ -+#define MMU_NOOP 0x0000 // No operation -+#define MMU_ALLOC_TX 0x0020 // Allocate memory for Tx -+#define MMU_RESET 0x0040 // Reset MMU to initial state -+#define MMU_REMV_RX 0x0060 // Remove frame from top of Rx FIFO -+#define MMU_REMV_REL_RX 0x0080 // Remove and Release top of Rx FIFO -+#define MMU_REL_PKT 0x00A0 // Release specific packet -+#define MMU_ENQ_TX 0x00C0 // Enqueue packet number into Tx FIFO -+#define MMU_RESET_TX 0x00E0 // Reset Tx FIFO -+ -+/* FIFO status */ -+#define FIFO_REMPTY 0x8000 // No receive packets queued in Rx FIFO -+#define FIFO_TEMPTY 0x0080 // No transmit packets in completion queue -+ -+/* Pointer Register */ -+#define PTR_RCV 0x8000 // Address refers to Rx area (0= Tx area) -+#define PTR_AUTO_INCR 0x4000 // Auto increment on access -+#define PTR_READ 0x2000 // Read access (0= write access) -+#define PTR_ETEN 0x1000 // Enable early transmit underrun detection -+#define PTR_NOT_EMPTY 0x0800 // Data FIFO not empty yet (read only bit) -+#define PTR_MASK 0x07FF // Mask pointer value -+ -+/* Interrupt Status Register */ -+#define IST_MDINT 0x80 // PHY MI Register 18 change status interrupt -+#define IST_ERCV_INT 0x40 // Early Receive interrupt -+#define IST_EPH_INT 0x20 // EPH Type interrupt -+#define IST_RX_OVRN 0x10 // Receive Overrun interrupt -+#define IST_ALLOC_INT 0x08 // Tx ram Allocation interrupt -+#define IST_TX_EMPTY 0x04 // Tx FIFO empty interrupt -+#define IST_TX_INT 0x02 // Tx Complete interrupt -+#define IST_RCV_INT 0x01 // Rx Complete intererupt -+ -+/* Interrupt Ack Register */ -+#define ACK_MDINT 0x80 // PHY MI Register 18 change int. ack -+#define ACK_ERCV_INT 0x40 // Early Receive int. ack -+#define ACK_RX_OVRN 0x10 // Receive Overrun int. ack -+#define ACK_TX_EMPTY 0x04 // Tx FIFO empty int. ack -+#define ACK_TX_INT 0x02 // Tx Complete int. ack -+ -+/* Interrupt Mask Register */ -+#define MSK_MDINT 0x80 // PHY MI Register 18 change int. mask -+#define MSK_ERCV_INT 0x40 // Early Receive int. mask -+#define MSK_EPH_INT 0x20 // EPH Type int. mask -+#define MSK_RX_OVRN 0x10 // Receive Overrun int. mask -+#define MSK_ALLOC_INT 0x08 // Tx ram Allocation int. mask -+#define MSK_TX_EMPTY 0x04 // Tx FIFO empty int. mask -+#define MSK_TX_INT 0x02 // Tx Complete int. mask -+#define MSK_RCV 0x01 // Rx Complete int. mask -+ -+/* PHY Management Interface */ -+#define MGMT_MSK_CRS100 0x0040 // Disables CRS100 detection in Tx Half Dup. -+#define MGMT_MDOE 0x0008 // MII - 1= MDO pin output, 0= MDO tristated -+#define MGMT_MCLK 0x0004 // MII - Value drives MDCLK pin -+#define MGMT_MDI 0x0002 // MII - Value of MDI pin when read -+#define MGMT_MDO 0x0001 // MII - Value drives MDO pin -+#define MGMT_DEFAULT 0x3330 // Default bits set to 1 for write -+ -+/* Receive Frame Status */ -+#define RFS_ALGNERR 0x8000 // Frame alignment error -+#define RFS_BROADCAST 0x4000 // Broadcast frame received -+#define RFS_BADCRC 0x2000 // Bad CRC error -+#define RFS_ODDFRM 0x1000 // Frame with Odd number of bytes received -+#define RFS_TOOLNG 0x0800 // Too long frame received (max. 1518 bytes) -+#define RFS_TOOSHORT 0x0400 // Too short frame received (min. 64 bytes) -+#define RFS_MULTCAST 0x0001 // Multicast frame received -+#define RFS_HASH_MASK 0x007E // Hash value index for multicast registers -+ -+/* Receive Frame Control */ -+#define RFC_ODD 0x2000 // Odd number of bytes in frame -+#define RFC_CRC 0x1000 // Append CRC (valid when TCR_NOCRC = 1) -+ -+/* Revision Register */ -+#define REV_CHIP_ID 0x3390 // Chip identification -+ -+/* PHY Registers */ -+#define PHY_CR 0 // Control Register -+#define PHY_SR 1 // Status Register -+#define PHY_ID1 2 // PHY Identifier 1 -+#define PHY_ID2 3 // PHY Identifier 2 -+#define PHY_ANA 4 // Auto-Negotiation Advertisement -+#define PHY_ANRC 5 // Auto-Neg. Remote Capability -+ -+/* Vendor-specific Registers */ -+#define PHY_CFG1 16 // Configuration 1 -+#define PHY_CFG2 17 // Configuration 2 -+#define PHY_SO 18 // Status Output -+#define PHY_MASK 19 // Interrupt Mask -+ -+/* Control Register */ -+#define PHY_CR_RST 0x8000 // Software Reset -+#define PHY_CR_LPBK 0x4000 // Loopback mode -+#define PHY_CR_SPEED 0x2000 // Speed Select (1=100Mb/s) -+#define PHY_CR_ANEG_EN 0x1000 // Auto Negotiation Enable -+#define PHY_CR_PDN 0x0800 // Power Down (1=power down) -+#define PHY_CR_MII_DIS 0x0400 // Isolate Media interface -+#define PHY_CR_ANEG_RST 0x0200 // Restart Auto Negotiation -+#define PHY_CR_DPLX 0x0100 // Duplex Mode (1=Full duplex) -+#define PHY_CR_COLST 0x0080 // Enable Collision Test -+ -+/* Status Register */ -+#define PHY_SR_CAP_T4 0x8000 // 100BASE-T4 Capable -+#define PHY_SR_CAP_TXF 0x4000 // 100BASE-TX Full Duplex Capable -+#define PHY_SR_CAP_TXH 0x2000 // 100BASE-TX Half Duplex Capable -+#define PHY_SR_CAP_TF 0x1000 // 10BASE-T Full Duplex Capable -+#define PHY_SR_CAP_TH 0x0800 // 10BASE-T Half Duplex Capable -+#define PHY_SR_CAP_SUPR 0x0040 // MI Preamble Suppression Capable -+#define PHY_SR_ANEG_ACK 0x0020 // Auto Negotiation Acknowledgment -+#define PHY_SR_REM_FLT 0x0010 // Remote Fault Detect -+#define PHY_SR_CAP_ANEG 0x0008 // Auto Negotiation Capable -+#define PHY_SR_LINK 0x0004 // Link Status (1=link up) -+#define PHY_SR_JAB 0x0002 // Jabber Detect -+#define PHY_SR_EXREG 0x0001 // Extended Capability Register -+ -+/* Status Output Register */ -+#define PHY_SO_INT 0x8000 // Interrupt Detect -+#define PHY_SO_LNKFAIL 0x4000 // Link Fail Detect -+#define PHY_SO_LOSSSYNC 0x2000 // Descrambler Loss of Sync Detect -+#define PHY_SO_CWRD 0x1000 // Codeword Error Detect -+#define PHY_SO_SSD 0x0800 // Start of Stream Error Detect -+#define PHY_SO_ESD 0x0400 // End of Stream Error Detect -+#define PHY_SO_RPOL 0x0200 // Reverse Polarity Detect -+#define PHY_SO_JAB 0x0100 // Jabber Detect -+#define PHY_SO_SPDDET 0x0080 // 100/10 Speed Detect -+#define PHY_SO_DPLXDET 0x0040 // Duplex Detect -+ -+/* PHY address */ -+#define ETH_PHY_ADDR 0 // LAN91C111 PHY address -+ -+/* PHY Identifier */ -+#define PHY_CHIP_ID1 0x0016 // PHY Chip identifier 1 -+#define PHY_CHIP_ID2 0xF840 // PHY Chip identifier 2 -+ -+/* ETH Driver state flags */ -+#define ETH_FLAG_INIT 0x01 // Driver initialized -+#define ETH_FLAG_POWER 0x02 // Driver powered -+ -+/* ETH Driver Control Information */ -+typedef struct { -+ ARM_ETH_MAC_SignalEvent_t cb_event; // Event callback -+ uint16_t flags; // Control and state flags -+ uint16_t tx_len; // Transmit length of data -+ uint16_t phy_cr; // PHY Control shadow register -+ uint16_t reserved; -+} ETH_CTRL; -+ -+#endif /* ETH_LAN91C111_H__ */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/CMakeLists.txt b/source/portable/NetworkInterface/MPS4_CS315/CMakeLists.txt -new file mode 100644 -index 0000000..9e6634b ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/CMakeLists.txt -@@ -0,0 +1,32 @@ -+# Copyright 2023 Arm Limited and/or its affiliates -+# -+# SPDX-License-Identifier: MIT -+ -+if (NOT (FREERTOS_PLUS_TCP_NETWORK_IF STREQUAL "MPS4_CS315") ) -+ return() -+endif() -+ -+#------------------------------------------------------------------------------ -+add_library( freertos_plus_tcp_network_if STATIC ) -+ -+# CMSIS Ethernet driver for LAN91C111 -+add_subdirectory(CMSIS_Driver) -+ -+target_sources( freertos_plus_tcp_network_if -+ PRIVATE -+ NetworkInterface.c -+) -+ -+target_include_directories( freertos_plus_tcp_network_if -+ PRIVATE -+ Device/Include -+) -+ -+target_link_libraries( freertos_plus_tcp_network_if -+ PUBLIC -+ freertos_plus_tcp_port -+ freertos_plus_tcp_network_if_common -+ PRIVATE -+ freertos_kernel -+ freertos_plus_tcp -+) -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/SSE315.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/SSE315.h -new file mode 100644 -index 0000000..ea99a03 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/SSE315.h -@@ -0,0 +1,92 @@ -+/* -+ * Copyright (c) 2024 Arm Limited. All rights reserved. -+ * -+ * Licensed under the Apache License Version 2.0 (the "License"); -+ * you may not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * http://www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing software -+ * distributed under the License is distributed on an "AS IS" BASIS -+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+#ifndef __CORSTONE315_H__ -+#define __CORSTONE315_H__ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* ====================== Start of section using anonymous unions ============== */ -+#if defined (__CC_ARM) -+ #pragma push -+ #pragma anon_unions -+#elif defined (__ICCARM__) -+ #pragma language=extended -+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -+ #pragma clang diagnostic push -+ #pragma clang diagnostic ignored "-Wc11-extensions" -+ #pragma clang diagnostic ignored "-Wreserved-id-macro" -+#elif defined (__GNUC__) -+ /* anonymous unions are enabled by default */ -+#elif defined (__TMS470__) -+ /* anonymous unions are enabled by default */ -+#elif defined (__TASKING__) -+ #pragma warning 586 -+#elif defined (__CSMC__) -+ /* anonymous unions are enabled by default */ -+#else -+ #warning Not supported compiler type -+#endif -+ -+ -+/* ======== Configuration of Core Peripherals ================================== */ -+#define __CM85_REV 0x0002U /* Core revision r0p2 */ -+#define __SAUREGION_PRESENT 1U /* SAU regions present */ -+#define __MPU_PRESENT 1U /* MPU present */ -+#define __VTOR_PRESENT 1U /* VTOR present */ -+#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ -+#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -+#define __FPU_PRESENT 1U /* FPU present */ -+#define __FPU_DP 1U /* double precision FPU */ -+#define __DSP_PRESENT 1U /* DSP extension present */ -+#define __PMU_PRESENT 1U /* PMU present */ -+#define __PMU_NUM_EVENTCNT 8U /* Number of PMU event counters */ -+#define __ICACHE_PRESENT 1U /* Instruction Cache present */ -+#define __DCACHE_PRESENT 1U /* Data Cache present */ -+ -+#include "../../Board/Platform/platform_irq.h" -+#include "core_cm85.h" /* Processor and core peripherals */ -+#include "../../Board/Platform/platform_base_address.h" -+#include "../../Board/Platform/platform_regs.h" -+#include "../../Board/Platform/platform_pins.h" -+#include "system_SSE315.h" -+ -+/* ===================== End of section using anonymous unions ================ */ -+#if defined (__CC_ARM) -+ #pragma pop -+#elif defined (__ICCARM__) -+ /* leave anonymous unions enabled */ -+#elif (__ARMCC_VERSION >= 6010050) -+ #pragma clang diagnostic pop -+#elif defined (__GNUC__) -+ /* anonymous unions are enabled by default */ -+#elif defined (__TMS470__) -+ /* anonymous unions are enabled by default */ -+#elif defined (__TASKING__) -+ #pragma warning restore -+#elif defined (__CSMC__) -+ /* anonymous unions are enabled by default */ -+#else -+ #warning Not supported compiler type -+#endif -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __CORSTONE315_H__ */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cachel1_armv7.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cachel1_armv7.h -new file mode 100644 -index 0000000..855439c ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cachel1_armv7.h -@@ -0,0 +1,449 @@ -+/* *INDENT-OFF* */ -+ -+/****************************************************************************** -+ * @file cachel1_armv7.h -+ * @brief CMSIS Level 1 Cache API for Armv7-M and later -+ * @version V1.0.3 -+ * @date 17. March 2023 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/cachel1_armv7.h -+*/ -+ -+#if defined ( __ICCARM__ ) -+ #pragma system_include /* treat file as system include file for MISRA check */ -+#elif defined (__clang__) -+ #pragma clang system_header /* treat file as system include file */ -+#endif -+ -+#ifndef ARM_CACHEL1_ARMV7_H -+#define ARM_CACHEL1_ARMV7_H -+ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_CacheFunctions Cache Functions -+ \brief Functions that configure Instruction and Data cache. -+ @{ -+ */ -+ -+/* Cache Size ID Register Macros */ -+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -+ -+#ifndef __SCB_DCACHE_LINE_SIZE -+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -+#endif -+ -+#ifndef __SCB_ICACHE_LINE_SIZE -+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -+#endif -+ -+/** -+ \brief Enable I-Cache -+ \details Turns on I-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_EnableICache (void) -+{ -+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) -+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ -+ -+ __DSB(); -+ __ISB(); -+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ -+ __DSB(); -+ __ISB(); -+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief Disable I-Cache -+ \details Turns off I-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_DisableICache (void) -+{ -+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) -+ __DSB(); -+ __ISB(); -+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ -+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief Invalidate I-Cache -+ \details Invalidates I-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -+{ -+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) -+ __DSB(); -+ __ISB(); -+ SCB->ICIALLU = 0UL; -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief I-Cache Invalidate by address -+ \details Invalidates I-Cache for the given address. -+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. -+ I-Cache memory blocks which are part of given address + given size are invalidated. -+ \param[in] addr address -+ \param[in] isize size of memory block (in number of bytes) -+*/ -+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) -+{ -+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) -+ if ( isize > 0 ) { -+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); -+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; -+ -+ __DSB(); -+ -+ do { -+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ -+ op_addr += __SCB_ICACHE_LINE_SIZE; -+ op_size -= __SCB_ICACHE_LINE_SIZE; -+ } while ( op_size > 0 ); -+ -+ __DSB(); -+ __ISB(); -+ } -+ #endif -+} -+ -+ -+/** -+ \brief Enable D-Cache -+ \details Turns on D-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_EnableDCache (void) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ uint32_t ccsidr; -+ uint32_t sets; -+ uint32_t ways; -+ -+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ -+ -+ SCB->CSSELR = 0U; /* select Level 1 data cache */ -+ __DSB(); -+ -+ ccsidr = SCB->CCSIDR; -+ -+ /* invalidate D-Cache */ -+ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); -+ do { -+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); -+ do { -+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | -+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); -+ #if defined ( __CC_ARM ) -+ __schedule_barrier(); -+ #endif -+ } while (ways-- != 0U); -+ } while(sets-- != 0U); -+ __DSB(); -+ -+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ -+ -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief Disable D-Cache -+ \details Turns off D-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_DisableDCache (void) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ struct { -+ uint32_t ccsidr; -+ uint32_t sets; -+ uint32_t ways; -+ } locals -+ #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) -+ __ALIGNED(__SCB_DCACHE_LINE_SIZE) -+ #endif -+ ; -+ -+ SCB->CSSELR = 0U; /* select Level 1 data cache */ -+ __DSB(); -+ -+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ -+ __DSB(); -+ -+ #if !defined(__OPTIMIZE__) -+ /* -+ * For the endless loop issue with no optimization builds. -+ * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 -+ * -+ * The issue only happens when local variables are in stack. If -+ * local variables are saved in general purpose register, then the function -+ * is OK. -+ * -+ * When local variables are in stack, after disabling the cache, flush the -+ * local variables cache line for data consistency. -+ */ -+ /* Clean and invalidate the local variable cache. */ -+ #if defined(__ICCARM__) -+ /* As we can't align the stack to the cache line size, invalidate each of the variables */ -+ SCB->DCCIMVAC = (uint32_t)&locals.sets; -+ SCB->DCCIMVAC = (uint32_t)&locals.ways; -+ SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; -+ #else -+ SCB->DCCIMVAC = (uint32_t)&locals; -+ #endif -+ __DSB(); -+ __ISB(); -+ #endif -+ -+ locals.ccsidr = SCB->CCSIDR; -+ /* clean & invalidate D-Cache */ -+ locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); -+ do { -+ locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); -+ do { -+ SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | -+ ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); -+ #if defined ( __CC_ARM ) -+ __schedule_barrier(); -+ #endif -+ } while (locals.ways-- != 0U); -+ } while(locals.sets-- != 0U); -+ -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief Invalidate D-Cache -+ \details Invalidates D-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ uint32_t ccsidr; -+ uint32_t sets; -+ uint32_t ways; -+ -+ SCB->CSSELR = 0U; /* select Level 1 data cache */ -+ __DSB(); -+ -+ ccsidr = SCB->CCSIDR; -+ -+ /* invalidate D-Cache */ -+ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); -+ do { -+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); -+ do { -+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | -+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); -+ #if defined ( __CC_ARM ) -+ __schedule_barrier(); -+ #endif -+ } while (ways-- != 0U); -+ } while(sets-- != 0U); -+ -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief Clean D-Cache -+ \details Cleans D-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_CleanDCache (void) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ uint32_t ccsidr; -+ uint32_t sets; -+ uint32_t ways; -+ -+ SCB->CSSELR = 0U; /* select Level 1 data cache */ -+ __DSB(); -+ -+ ccsidr = SCB->CCSIDR; -+ -+ /* clean D-Cache */ -+ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); -+ do { -+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); -+ do { -+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | -+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); -+ #if defined ( __CC_ARM ) -+ __schedule_barrier(); -+ #endif -+ } while (ways-- != 0U); -+ } while(sets-- != 0U); -+ -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief Clean & Invalidate D-Cache -+ \details Cleans and Invalidates D-Cache -+ */ -+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ uint32_t ccsidr; -+ uint32_t sets; -+ uint32_t ways; -+ -+ SCB->CSSELR = 0U; /* select Level 1 data cache */ -+ __DSB(); -+ -+ ccsidr = SCB->CCSIDR; -+ -+ /* clean & invalidate D-Cache */ -+ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); -+ do { -+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); -+ do { -+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | -+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); -+ #if defined ( __CC_ARM ) -+ __schedule_barrier(); -+ #endif -+ } while (ways-- != 0U); -+ } while(sets-- != 0U); -+ -+ __DSB(); -+ __ISB(); -+ #endif -+} -+ -+ -+/** -+ \brief D-Cache Invalidate by address -+ \details Invalidates D-Cache for the given address. -+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. -+ D-Cache memory blocks which are part of given address + given size are invalidated. -+ \param[in] addr address -+ \param[in] dsize size of memory block (in number of bytes) -+*/ -+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ if ( dsize > 0 ) { -+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); -+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; -+ -+ __DSB(); -+ -+ do { -+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ -+ op_addr += __SCB_DCACHE_LINE_SIZE; -+ op_size -= __SCB_DCACHE_LINE_SIZE; -+ } while ( op_size > 0 ); -+ -+ __DSB(); -+ __ISB(); -+ } -+ #endif -+} -+ -+ -+/** -+ \brief D-Cache Clean by address -+ \details Cleans D-Cache for the given address -+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. -+ D-Cache memory blocks which are part of given address + given size are cleaned. -+ \param[in] addr address -+ \param[in] dsize size of memory block (in number of bytes) -+*/ -+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ if ( dsize > 0 ) { -+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); -+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; -+ -+ __DSB(); -+ -+ do { -+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ -+ op_addr += __SCB_DCACHE_LINE_SIZE; -+ op_size -= __SCB_DCACHE_LINE_SIZE; -+ } while ( op_size > 0 ); -+ -+ __DSB(); -+ __ISB(); -+ } -+ #endif -+} -+ -+ -+/** -+ \brief D-Cache Clean and Invalidate by address -+ \details Cleans and invalidates D_Cache for the given address -+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. -+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. -+ \param[in] addr address (aligned to 32-byte boundary) -+ \param[in] dsize size of memory block (in number of bytes) -+*/ -+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -+{ -+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) -+ if ( dsize > 0 ) { -+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); -+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; -+ -+ __DSB(); -+ -+ do { -+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ -+ op_addr += __SCB_DCACHE_LINE_SIZE; -+ op_size -= __SCB_DCACHE_LINE_SIZE; -+ } while ( op_size > 0 ); -+ -+ __DSB(); -+ __ISB(); -+ } -+ #endif -+} -+ -+/*@} end of CMSIS_Core_CacheFunctions */ -+ -+#endif /* ARM_CACHEL1_ARMV7_H */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_armclang.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_armclang.h -new file mode 100644 -index 0000000..a45156c ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_armclang.h -@@ -0,0 +1,1518 @@ -+/* *INDENT-OFF* */ -+ -+/**************************************************************************//** -+ * @file cmsis_armclang.h -+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file -+ * @version V5.5.0 -+ * @date 20. January 2023 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/cmsis_armclang.h -+*/ -+ -+#ifndef __CMSIS_ARMCLANG_H -+#define __CMSIS_ARMCLANG_H -+ -+#pragma clang system_header /* treat file as system include file */ -+ -+/* CMSIS compiler specific defines */ -+#ifndef __ASM -+ #define __ASM __asm -+#endif -+#ifndef __INLINE -+ #define __INLINE __inline -+#endif -+#ifndef __STATIC_INLINE -+ #define __STATIC_INLINE static __inline -+#endif -+#ifndef __STATIC_FORCEINLINE -+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -+#endif -+#ifndef __NO_RETURN -+ #define __NO_RETURN __attribute__((__noreturn__)) -+#endif -+#ifndef __USED -+ #define __USED __attribute__((used)) -+#endif -+#ifndef __WEAK -+ #define __WEAK __attribute__((weak)) -+#endif -+#ifndef __PACKED -+ #define __PACKED __attribute__((packed, aligned(1))) -+#endif -+#ifndef __PACKED_STRUCT -+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -+#endif -+#ifndef __PACKED_UNION -+ #define __PACKED_UNION union __attribute__((packed, aligned(1))) -+#endif -+#ifndef __UNALIGNED_UINT32 /* deprecated */ -+ #pragma clang diagnostic push -+ #pragma clang diagnostic ignored "-Wpacked" -+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ -+ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; -+ #pragma clang diagnostic pop -+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -+#endif -+#ifndef __UNALIGNED_UINT16_WRITE -+ #pragma clang diagnostic push -+ #pragma clang diagnostic ignored "-Wpacked" -+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ -+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; -+ #pragma clang diagnostic pop -+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -+#endif -+#ifndef __UNALIGNED_UINT16_READ -+ #pragma clang diagnostic push -+ #pragma clang diagnostic ignored "-Wpacked" -+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ -+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; -+ #pragma clang diagnostic pop -+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -+#endif -+#ifndef __UNALIGNED_UINT32_WRITE -+ #pragma clang diagnostic push -+ #pragma clang diagnostic ignored "-Wpacked" -+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ -+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; -+ #pragma clang diagnostic pop -+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -+#endif -+#ifndef __UNALIGNED_UINT32_READ -+ #pragma clang diagnostic push -+ #pragma clang diagnostic ignored "-Wpacked" -+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ -+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; -+ #pragma clang diagnostic pop -+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -+#endif -+#ifndef __ALIGNED -+ #define __ALIGNED(x) __attribute__((aligned(x))) -+#endif -+#ifndef __RESTRICT -+ #define __RESTRICT __restrict -+#endif -+#ifndef __COMPILER_BARRIER -+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -+#endif -+#ifndef __NO_INIT -+ #define __NO_INIT __attribute__ ((section (".bss.noinit"))) -+#endif -+#ifndef __ALIAS -+ #define __ALIAS(x) __attribute__ ((alias(x))) -+#endif -+ -+ -+/* ######################### Startup and Lowlevel Init ######################## */ -+ -+#ifndef __PROGRAM_START -+#define __PROGRAM_START __main -+#endif -+ -+#ifndef __INITIAL_SP -+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -+#endif -+ -+#ifndef __STACK_LIMIT -+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -+#endif -+ -+#ifndef __VECTOR_TABLE -+#define __VECTOR_TABLE __Vectors -+#endif -+ -+#ifndef __VECTOR_TABLE_ATTRIBUTE -+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -+#endif -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+#ifndef __STACK_SEAL -+#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -+#endif -+ -+#ifndef __TZ_STACK_SEAL_SIZE -+#define __TZ_STACK_SEAL_SIZE 8U -+#endif -+ -+#ifndef __TZ_STACK_SEAL_VALUE -+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -+#endif -+ -+ -+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { -+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -+} -+#endif -+ -+ -+/* ########################## Core Instruction Access ######################### */ -+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface -+ Access to dedicated instructions -+ @{ -+*/ -+ -+/* Define macros for porting to both thumb1 and thumb2. -+ * For thumb1, use low register (r0-r7), specified by constraint "l" -+ * Otherwise, use general registers, specified by constraint "r" */ -+#if defined (__thumb__) && !defined (__thumb2__) -+#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -+#define __CMSIS_GCC_RW_REG(r) "+l" (r) -+#define __CMSIS_GCC_USE_REG(r) "l" (r) -+#else -+#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -+#define __CMSIS_GCC_RW_REG(r) "+r" (r) -+#define __CMSIS_GCC_USE_REG(r) "r" (r) -+#endif -+ -+/** -+ \brief No Operation -+ \details No Operation does nothing. This instruction can be used for code alignment purposes. -+ */ -+#define __NOP __builtin_arm_nop -+ -+/** -+ \brief Wait For Interrupt -+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. -+ */ -+#define __WFI __builtin_arm_wfi -+ -+ -+/** -+ \brief Wait For Event -+ \details Wait For Event is a hint instruction that permits the processor to enter -+ a low-power state until one of a number of events occurs. -+ */ -+#define __WFE __builtin_arm_wfe -+ -+ -+/** -+ \brief Send Event -+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. -+ */ -+#define __SEV __builtin_arm_sev -+ -+ -+/** -+ \brief Instruction Synchronization Barrier -+ \details Instruction Synchronization Barrier flushes the pipeline in the processor, -+ so that all instructions following the ISB are fetched from cache or memory, -+ after the instruction has been completed. -+ */ -+#define __ISB() __builtin_arm_isb(0xF) -+ -+/** -+ \brief Data Synchronization Barrier -+ \details Acts as a special kind of Data Memory Barrier. -+ It completes when all explicit memory accesses before this instruction complete. -+ */ -+#define __DSB() __builtin_arm_dsb(0xF) -+ -+ -+/** -+ \brief Data Memory Barrier -+ \details Ensures the apparent order of the explicit memory operations before -+ and after the instruction, without ensuring their completion. -+ */ -+#define __DMB() __builtin_arm_dmb(0xF) -+ -+ -+/** -+ \brief Reverse byte order (32 bit) -+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+#define __REV(value) __builtin_bswap32(value) -+ -+ -+/** -+ \brief Reverse byte order (16 bit) -+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+#define __REV16(value) __ROR(__REV(value), 16) -+ -+ -+/** -+ \brief Reverse byte order (16 bit) -+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+#define __REVSH(value) (int16_t)__builtin_bswap16(value) -+ -+ -+/** -+ \brief Rotate Right in unsigned value (32 bit) -+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. -+ \param [in] op1 Value to rotate -+ \param [in] op2 Number of Bits to rotate -+ \return Rotated value -+ */ -+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -+{ -+ op2 %= 32U; -+ if (op2 == 0U) -+ { -+ return op1; -+ } -+ return (op1 >> op2) | (op1 << (32U - op2)); -+} -+ -+ -+/** -+ \brief Breakpoint -+ \details Causes the processor to enter Debug state. -+ Debug tools can use this to investigate system state when the instruction at a particular address is reached. -+ \param [in] value is ignored by the processor. -+ If required, a debugger can use it to store additional information about the breakpoint. -+ */ -+#define __BKPT(value) __ASM volatile ("bkpt "#value) -+ -+ -+/** -+ \brief Reverse bit order of value -+ \details Reverses the bit order of the given value. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+#define __RBIT __builtin_arm_rbit -+ -+/** -+ \brief Count leading zeros -+ \details Counts the number of leading zeros of a data value. -+ \param [in] value Value to count the leading zeros -+ \return number of leading zeros in value -+ */ -+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -+{ -+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally -+ __builtin_clz(0) is undefined behaviour, so handle this case specially. -+ This guarantees ARM-compatible results if happening to compile on a non-ARM -+ target, and ensures the compiler doesn't decide to activate any -+ optimisations using the logic "value was passed to __builtin_clz, so it -+ is non-zero". -+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a -+ single CLZ instruction. -+ */ -+ if (value == 0U) -+ { -+ return 32U; -+ } -+ return __builtin_clz(value); -+} -+ -+ -+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -+ -+/** -+ \brief LDR Exclusive (8 bit) -+ \details Executes a exclusive LDR instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+#define __LDREXB (uint8_t)__builtin_arm_ldrex -+ -+ -+/** -+ \brief LDR Exclusive (16 bit) -+ \details Executes a exclusive LDR instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+#define __LDREXH (uint16_t)__builtin_arm_ldrex -+ -+ -+/** -+ \brief LDR Exclusive (32 bit) -+ \details Executes a exclusive LDR instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+#define __LDREXW (uint32_t)__builtin_arm_ldrex -+ -+ -+/** -+ \brief STR Exclusive (8 bit) -+ \details Executes a exclusive STR instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+#define __STREXB (uint32_t)__builtin_arm_strex -+ -+ -+/** -+ \brief STR Exclusive (16 bit) -+ \details Executes a exclusive STR instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+#define __STREXH (uint32_t)__builtin_arm_strex -+ -+ -+/** -+ \brief STR Exclusive (32 bit) -+ \details Executes a exclusive STR instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+#define __STREXW (uint32_t)__builtin_arm_strex -+ -+ -+/** -+ \brief Remove the exclusive lock -+ \details Removes the exclusive lock which is created by LDREX. -+ */ -+#define __CLREX __builtin_arm_clrex -+ -+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -+ -+ -+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -+ -+/** -+ \brief Signed Saturate -+ \details Saturates a signed value. -+ \param [in] value Value to be saturated -+ \param [in] sat Bit position to saturate to (1..32) -+ \return Saturated value -+ */ -+#define __SSAT __builtin_arm_ssat -+ -+ -+/** -+ \brief Unsigned Saturate -+ \details Saturates an unsigned value. -+ \param [in] value Value to be saturated -+ \param [in] sat Bit position to saturate to (0..31) -+ \return Saturated value -+ */ -+#define __USAT __builtin_arm_usat -+ -+ -+/** -+ \brief Rotate Right with Extend (32 bit) -+ \details Moves each bit of a bitstring right by one bit. -+ The carry input is shifted in at the left end of the bitstring. -+ \param [in] value Value to rotate -+ \return Rotated value -+ */ -+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); -+ return(result); -+} -+ -+ -+/** -+ \brief LDRT Unprivileged (8 bit) -+ \details Executes a Unprivileged LDRT instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -+ return ((uint8_t) result); /* Add explicit type cast here */ -+} -+ -+ -+/** -+ \brief LDRT Unprivileged (16 bit) -+ \details Executes a Unprivileged LDRT instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -+ return ((uint16_t) result); /* Add explicit type cast here */ -+} -+ -+ -+/** -+ \brief LDRT Unprivileged (32 bit) -+ \details Executes a Unprivileged LDRT instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); -+ return(result); -+} -+ -+ -+/** -+ \brief STRT Unprivileged (8 bit) -+ \details Executes a Unprivileged STRT instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -+{ -+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -+} -+ -+ -+/** -+ \brief STRT Unprivileged (16 bit) -+ \details Executes a Unprivileged STRT instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -+{ -+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -+} -+ -+ -+/** -+ \brief STRT Unprivileged (32 bit) -+ \details Executes a Unprivileged STRT instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -+{ -+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -+} -+ -+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -+ -+/** -+ \brief Signed Saturate -+ \details Saturates a signed value. -+ \param [in] value Value to be saturated -+ \param [in] sat Bit position to saturate to (1..32) -+ \return Saturated value -+ */ -+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -+{ -+ if ((sat >= 1U) && (sat <= 32U)) -+ { -+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); -+ const int32_t min = -1 - max ; -+ if (val > max) -+ { -+ return max; -+ } -+ else if (val < min) -+ { -+ return min; -+ } -+ } -+ return val; -+} -+ -+/** -+ \brief Unsigned Saturate -+ \details Saturates an unsigned value. -+ \param [in] value Value to be saturated -+ \param [in] sat Bit position to saturate to (0..31) -+ \return Saturated value -+ */ -+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -+{ -+ if (sat <= 31U) -+ { -+ const uint32_t max = ((1U << sat) - 1U); -+ if (val > (int32_t)max) -+ { -+ return max; -+ } -+ else if (val < 0) -+ { -+ return 0U; -+ } -+ } -+ return (uint32_t)val; -+} -+ -+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -+ -+ -+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -+ -+/** -+ \brief Load-Acquire (8 bit) -+ \details Executes a LDAB instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return ((uint8_t) result); -+} -+ -+ -+/** -+ \brief Load-Acquire (16 bit) -+ \details Executes a LDAH instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return ((uint16_t) result); -+} -+ -+ -+/** -+ \brief Load-Acquire (32 bit) -+ \details Executes a LDA instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return(result); -+} -+ -+ -+/** -+ \brief Store-Release (8 bit) -+ \details Executes a STLB instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -+{ -+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+} -+ -+ -+/** -+ \brief Store-Release (16 bit) -+ \details Executes a STLH instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -+{ -+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+} -+ -+ -+/** -+ \brief Store-Release (32 bit) -+ \details Executes a STL instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -+{ -+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+} -+ -+ -+/** -+ \brief Load-Acquire Exclusive (8 bit) -+ \details Executes a LDAB exclusive instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+#define __LDAEXB (uint8_t)__builtin_arm_ldaex -+ -+ -+/** -+ \brief Load-Acquire Exclusive (16 bit) -+ \details Executes a LDAH exclusive instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+#define __LDAEXH (uint16_t)__builtin_arm_ldaex -+ -+ -+/** -+ \brief Load-Acquire Exclusive (32 bit) -+ \details Executes a LDA exclusive instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+#define __LDAEX (uint32_t)__builtin_arm_ldaex -+ -+ -+/** -+ \brief Store-Release Exclusive (8 bit) -+ \details Executes a STLB exclusive instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+#define __STLEXB (uint32_t)__builtin_arm_stlex -+ -+ -+/** -+ \brief Store-Release Exclusive (16 bit) -+ \details Executes a STLH exclusive instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+#define __STLEXH (uint32_t)__builtin_arm_stlex -+ -+ -+/** -+ \brief Store-Release Exclusive (32 bit) -+ \details Executes a STL exclusive instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+#define __STLEX (uint32_t)__builtin_arm_stlex -+ -+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -+ -+/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ -+ -+ -+/* ########################### Core Function Access ########################### */ -+/** \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions -+ @{ -+ */ -+ -+/** -+ \brief Enable IRQ Interrupts -+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. -+ Can only be executed in Privileged modes. -+ */ -+#ifndef __ARM_COMPAT_H -+__STATIC_FORCEINLINE void __enable_irq(void) -+{ -+ __ASM volatile ("cpsie i" : : : "memory"); -+} -+#endif -+ -+ -+/** -+ \brief Disable IRQ Interrupts -+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK. -+ Can only be executed in Privileged modes. -+ */ -+#ifndef __ARM_COMPAT_H -+__STATIC_FORCEINLINE void __disable_irq(void) -+{ -+ __ASM volatile ("cpsid i" : : : "memory"); -+} -+#endif -+ -+ -+/** -+ \brief Get Control Register -+ \details Returns the content of the Control Register. -+ \return Control Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, control" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Control Register (non-secure) -+ \details Returns the content of the non-secure Control Register when in secure mode. -+ \return non-secure Control Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Control Register -+ \details Writes the given value to the Control Register. -+ \param [in] control Control Register value to set -+ */ -+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -+{ -+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -+ __ISB(); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Control Register (non-secure) -+ \details Writes the given value to the non-secure Control Register when in secure state. -+ \param [in] control Control Register value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -+{ -+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -+ __ISB(); -+} -+#endif -+ -+ -+/** -+ \brief Get IPSR Register -+ \details Returns the content of the IPSR Register. -+ \return IPSR Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Get APSR Register -+ \details Returns the content of the APSR Register. -+ \return APSR Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_APSR(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, apsr" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Get xPSR Register -+ \details Returns the content of the xPSR Register. -+ \return xPSR Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Get Process Stack Pointer -+ \details Returns the current value of the Process Stack Pointer (PSP). -+ \return PSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_PSP(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, psp" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Process Stack Pointer (non-secure) -+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. -+ \return PSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Process Stack Pointer -+ \details Assigns the given value to the Process Stack Pointer (PSP). -+ \param [in] topOfProcStack Process Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -+{ -+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Process Stack Pointer (non-secure) -+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. -+ \param [in] topOfProcStack Process Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -+{ -+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -+} -+#endif -+ -+ -+/** -+ \brief Get Main Stack Pointer -+ \details Returns the current value of the Main Stack Pointer (MSP). -+ \return MSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_MSP(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, msp" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Main Stack Pointer (non-secure) -+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. -+ \return MSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Main Stack Pointer -+ \details Assigns the given value to the Main Stack Pointer (MSP). -+ \param [in] topOfMainStack Main Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -+{ -+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Main Stack Pointer (non-secure) -+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. -+ \param [in] topOfMainStack Main Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -+{ -+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -+} -+#endif -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Stack Pointer (non-secure) -+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. -+ \return SP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Set Stack Pointer (non-secure) -+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. -+ \param [in] topOfStack Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -+{ -+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -+} -+#endif -+ -+ -+/** -+ \brief Get Priority Mask -+ \details Returns the current state of the priority mask bit from the Priority Mask Register. -+ \return Priority Mask value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, primask" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Priority Mask (non-secure) -+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. -+ \return Priority Mask value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Priority Mask -+ \details Assigns the given value to the Priority Mask Register. -+ \param [in] priMask Priority Mask -+ */ -+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -+{ -+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Priority Mask (non-secure) -+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state. -+ \param [in] priMask Priority Mask -+ */ -+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -+{ -+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -+} -+#endif -+ -+ -+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -+/** -+ \brief Enable FIQ -+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. -+ Can only be executed in Privileged modes. -+ */ -+__STATIC_FORCEINLINE void __enable_fault_irq(void) -+{ -+ __ASM volatile ("cpsie f" : : : "memory"); -+} -+ -+ -+/** -+ \brief Disable FIQ -+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. -+ Can only be executed in Privileged modes. -+ */ -+__STATIC_FORCEINLINE void __disable_fault_irq(void) -+{ -+ __ASM volatile ("cpsid f" : : : "memory"); -+} -+ -+ -+/** -+ \brief Get Base Priority -+ \details Returns the current value of the Base Priority register. -+ \return Base Priority register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, basepri" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Base Priority (non-secure) -+ \details Returns the current value of the non-secure Base Priority register when in secure state. -+ \return Base Priority register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Base Priority -+ \details Assigns the given value to the Base Priority register. -+ \param [in] basePri Base Priority value to set -+ */ -+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -+{ -+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Base Priority (non-secure) -+ \details Assigns the given value to the non-secure Base Priority register when in secure state. -+ \param [in] basePri Base Priority value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -+{ -+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -+} -+#endif -+ -+ -+/** -+ \brief Set Base Priority with condition -+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, -+ or the new value increases the BASEPRI priority level. -+ \param [in] basePri Base Priority value to set -+ */ -+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -+{ -+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -+} -+ -+ -+/** -+ \brief Get Fault Mask -+ \details Returns the current value of the Fault Mask register. -+ \return Fault Mask register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Fault Mask (non-secure) -+ \details Returns the current value of the non-secure Fault Mask register when in secure state. -+ \return Fault Mask register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Fault Mask -+ \details Assigns the given value to the Fault Mask register. -+ \param [in] faultMask Fault Mask value to set -+ */ -+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -+{ -+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Fault Mask (non-secure) -+ \details Assigns the given value to the non-secure Fault Mask register when in secure state. -+ \param [in] faultMask Fault Mask value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -+{ -+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -+} -+#endif -+ -+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -+ -+ -+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -+ -+/** -+ \brief Get Process Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always in non-secure -+ mode. -+ -+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). -+ \return PSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, psplim" : "=r" (result) ); -+ return result; -+#endif -+} -+ -+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Process Stack Pointer Limit (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always in non-secure -+ mode. -+ -+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. -+ \return PSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); -+ return result; -+#endif -+} -+#endif -+ -+ -+/** -+ \brief Set Process Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored in non-secure -+ mode. -+ -+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). -+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set -+ */ -+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ (void)ProcStackPtrLimit; -+#else -+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -+#endif -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Process Stack Pointer (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored in non-secure -+ mode. -+ -+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. -+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ (void)ProcStackPtrLimit; -+#else -+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -+#endif -+} -+#endif -+ -+ -+/** -+ \brief Get Main Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always. -+ -+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). -+ \return MSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, msplim" : "=r" (result) ); -+ return result; -+#endif -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Main Stack Pointer Limit (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always. -+ -+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. -+ \return MSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); -+ return result; -+#endif -+} -+#endif -+ -+ -+/** -+ \brief Set Main Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored. -+ -+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). -+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set -+ */ -+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ (void)MainStackPtrLimit; -+#else -+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -+#endif -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Main Stack Pointer Limit (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored. -+ -+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. -+ \param [in] MainStackPtrLimit Main Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -+{ -+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ (void)MainStackPtrLimit; -+#else -+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -+#endif -+} -+#endif -+ -+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ -+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ -+ -+/** -+ \brief Get FPSCR -+ \details Returns the current value of the Floating Point Status/Control register. -+ \return Floating Point Status/Control register value -+ */ -+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ -+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -+#else -+#define __get_FPSCR() ((uint32_t)0U) -+#endif -+ -+/** -+ \brief Set FPSCR -+ \details Assigns the given value to the Floating Point Status/Control register. -+ \param [in] fpscr Floating Point Status/Control value to set -+ */ -+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ -+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -+#define __set_FPSCR __builtin_arm_set_fpscr -+#else -+#define __set_FPSCR(fpscr) ((void)(fpscr)) -+#endif -+ -+ -+/** @} end of CMSIS_Core_RegAccFunctions */ -+ -+ -+/* ################### Compiler specific Intrinsics ########################### */ -+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics -+ Access to dedicated SIMD instructions -+ @{ -+*/ -+ -+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -+ -+#define __SADD8 __builtin_arm_sadd8 -+#define __QADD8 __builtin_arm_qadd8 -+#define __SHADD8 __builtin_arm_shadd8 -+#define __UADD8 __builtin_arm_uadd8 -+#define __UQADD8 __builtin_arm_uqadd8 -+#define __UHADD8 __builtin_arm_uhadd8 -+#define __SSUB8 __builtin_arm_ssub8 -+#define __QSUB8 __builtin_arm_qsub8 -+#define __SHSUB8 __builtin_arm_shsub8 -+#define __USUB8 __builtin_arm_usub8 -+#define __UQSUB8 __builtin_arm_uqsub8 -+#define __UHSUB8 __builtin_arm_uhsub8 -+#define __SADD16 __builtin_arm_sadd16 -+#define __QADD16 __builtin_arm_qadd16 -+#define __SHADD16 __builtin_arm_shadd16 -+#define __UADD16 __builtin_arm_uadd16 -+#define __UQADD16 __builtin_arm_uqadd16 -+#define __UHADD16 __builtin_arm_uhadd16 -+#define __SSUB16 __builtin_arm_ssub16 -+#define __QSUB16 __builtin_arm_qsub16 -+#define __SHSUB16 __builtin_arm_shsub16 -+#define __USUB16 __builtin_arm_usub16 -+#define __UQSUB16 __builtin_arm_uqsub16 -+#define __UHSUB16 __builtin_arm_uhsub16 -+#define __SASX __builtin_arm_sasx -+#define __QASX __builtin_arm_qasx -+#define __SHASX __builtin_arm_shasx -+#define __UASX __builtin_arm_uasx -+#define __UQASX __builtin_arm_uqasx -+#define __UHASX __builtin_arm_uhasx -+#define __SSAX __builtin_arm_ssax -+#define __QSAX __builtin_arm_qsax -+#define __SHSAX __builtin_arm_shsax -+#define __USAX __builtin_arm_usax -+#define __UQSAX __builtin_arm_uqsax -+#define __UHSAX __builtin_arm_uhsax -+#define __USAD8 __builtin_arm_usad8 -+#define __USADA8 __builtin_arm_usada8 -+#define __SSAT16 __builtin_arm_ssat16 -+#define __USAT16 __builtin_arm_usat16 -+#define __UXTB16 __builtin_arm_uxtb16 -+#define __UXTAB16 __builtin_arm_uxtab16 -+#define __SXTB16 __builtin_arm_sxtb16 -+#define __SXTAB16 __builtin_arm_sxtab16 -+#define __SMUAD __builtin_arm_smuad -+#define __SMUADX __builtin_arm_smuadx -+#define __SMLAD __builtin_arm_smlad -+#define __SMLADX __builtin_arm_smladx -+#define __SMLALD __builtin_arm_smlald -+#define __SMLALDX __builtin_arm_smlaldx -+#define __SMUSD __builtin_arm_smusd -+#define __SMUSDX __builtin_arm_smusdx -+#define __SMLSD __builtin_arm_smlsd -+#define __SMLSDX __builtin_arm_smlsdx -+#define __SMLSLD __builtin_arm_smlsld -+#define __SMLSLDX __builtin_arm_smlsldx -+#define __SEL __builtin_arm_sel -+#define __QADD __builtin_arm_qadd -+#define __QSUB __builtin_arm_qsub -+ -+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ -+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) -+ -+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ -+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) -+ -+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) -+ -+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) -+ -+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -+{ -+ int32_t result; -+ -+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); -+ return(result); -+} -+ -+#endif /* (__ARM_FEATURE_DSP == 1) */ -+/** @} end of group CMSIS_SIMD_intrinsics */ -+ -+ -+#endif /* __CMSIS_ARMCLANG_H */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_compiler.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_compiler.h -new file mode 100644 -index 0000000..68bfe5e ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_compiler.h -@@ -0,0 +1,310 @@ -+/* *INDENT-OFF* */ -+ -+/**************************************************************************//** -+ * @file cmsis_compiler.h -+ * @brief CMSIS compiler generic header file -+ * @version V5.3.0 -+ * @date 04. April 2023 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2009-2023 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/cmsis_compiler.h -+*/ -+ -+#ifndef __CMSIS_COMPILER_H -+#define __CMSIS_COMPILER_H -+ -+#include -+ -+/* -+ * Arm Compiler 4/5 -+ */ -+#if defined ( __CC_ARM ) -+ #include "cmsis_armcc.h" -+ -+ -+/* -+ * Arm Compiler 6.6 LTM (armclang) -+ */ -+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) -+ #include "cmsis_armclang_ltm.h" -+ -+ /* -+ * Arm Compiler above 6.10.1 (armclang) -+ */ -+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) -+ #include "cmsis_armclang.h" -+ -+/* -+ * TI Arm Clang Compiler (tiarmclang) -+ */ -+#elif defined (__ti__) -+ #include "cmsis_tiarmclang.h" -+ -+/* -+ * GNU Compiler -+ */ -+#elif defined ( __GNUC__ ) -+ #include "cmsis_gcc.h" -+ -+ -+/* -+ * IAR Compiler -+ */ -+#elif defined ( __ICCARM__ ) -+ #include -+ -+ -+/* -+ * TI Arm Compiler (armcl) -+ */ -+#elif defined ( __TI_ARM__ ) -+ #include -+ -+ #ifndef __ASM -+ #define __ASM __asm -+ #endif -+ #ifndef __INLINE -+ #define __INLINE inline -+ #endif -+ #ifndef __STATIC_INLINE -+ #define __STATIC_INLINE static inline -+ #endif -+ #ifndef __STATIC_FORCEINLINE -+ #define __STATIC_FORCEINLINE __STATIC_INLINE -+ #endif -+ #ifndef __NO_RETURN -+ #define __NO_RETURN __attribute__((noreturn)) -+ #endif -+ #ifndef __USED -+ #define __USED __attribute__((used)) -+ #endif -+ #ifndef __WEAK -+ #define __WEAK __attribute__((weak)) -+ #endif -+ #ifndef __PACKED -+ #define __PACKED __attribute__((packed)) -+ #endif -+ #ifndef __PACKED_STRUCT -+ #define __PACKED_STRUCT struct __attribute__((packed)) -+ #endif -+ #ifndef __PACKED_UNION -+ #define __PACKED_UNION union __attribute__((packed)) -+ #endif -+ #ifndef __UNALIGNED_UINT32 /* deprecated */ -+ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; -+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -+ #endif -+ #ifndef __UNALIGNED_UINT16_WRITE -+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; -+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) -+ #endif -+ #ifndef __UNALIGNED_UINT16_READ -+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; -+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -+ #endif -+ #ifndef __UNALIGNED_UINT32_WRITE -+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; -+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -+ #endif -+ #ifndef __UNALIGNED_UINT32_READ -+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; -+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -+ #endif -+ #ifndef __ALIGNED -+ #define __ALIGNED(x) __attribute__((aligned(x))) -+ #endif -+ #ifndef __RESTRICT -+ #define __RESTRICT __restrict -+ #endif -+ #ifndef __COMPILER_BARRIER -+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. -+ #define __COMPILER_BARRIER() (void)0 -+ #endif -+ #ifndef __NO_INIT -+ #define __NO_INIT __attribute__ ((section (".bss.noinit"))) -+ #endif -+ #ifndef __ALIAS -+ #define __ALIAS(x) __attribute__ ((alias(x))) -+ #endif -+ -+/* -+ * TASKING Compiler -+ */ -+#elif defined ( __TASKING__ ) -+ /* -+ * The CMSIS functions have been implemented as intrinsics in the compiler. -+ * Please use "carm -?i" to get an up to date list of all intrinsics, -+ * Including the CMSIS ones. -+ */ -+ -+ #ifndef __ASM -+ #define __ASM __asm -+ #endif -+ #ifndef __INLINE -+ #define __INLINE inline -+ #endif -+ #ifndef __STATIC_INLINE -+ #define __STATIC_INLINE static inline -+ #endif -+ #ifndef __STATIC_FORCEINLINE -+ #define __STATIC_FORCEINLINE __STATIC_INLINE -+ #endif -+ #ifndef __NO_RETURN -+ #define __NO_RETURN __attribute__((noreturn)) -+ #endif -+ #ifndef __USED -+ #define __USED __attribute__((used)) -+ #endif -+ #ifndef __WEAK -+ #define __WEAK __attribute__((weak)) -+ #endif -+ #ifndef __PACKED -+ #define __PACKED __packed__ -+ #endif -+ #ifndef __PACKED_STRUCT -+ #define __PACKED_STRUCT struct __packed__ -+ #endif -+ #ifndef __PACKED_UNION -+ #define __PACKED_UNION union __packed__ -+ #endif -+ #ifndef __UNALIGNED_UINT32 /* deprecated */ -+ struct __packed__ T_UINT32 { uint32_t v; }; -+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -+ #endif -+ #ifndef __UNALIGNED_UINT16_WRITE -+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; -+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -+ #endif -+ #ifndef __UNALIGNED_UINT16_READ -+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; -+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -+ #endif -+ #ifndef __UNALIGNED_UINT32_WRITE -+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; -+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -+ #endif -+ #ifndef __UNALIGNED_UINT32_READ -+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; -+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -+ #endif -+ #ifndef __ALIGNED -+ #define __ALIGNED(x) __align(x) -+ #endif -+ #ifndef __RESTRICT -+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. -+ #define __RESTRICT -+ #endif -+ #ifndef __COMPILER_BARRIER -+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. -+ #define __COMPILER_BARRIER() (void)0 -+ #endif -+ #ifndef __NO_INIT -+ #define __NO_INIT __attribute__ ((section (".bss.noinit"))) -+ #endif -+ #ifndef __ALIAS -+ #define __ALIAS(x) __attribute__ ((alias(x))) -+ #endif -+ -+/* -+ * COSMIC Compiler -+ */ -+#elif defined ( __CSMC__ ) -+ #include -+ -+ #ifndef __ASM -+ #define __ASM _asm -+ #endif -+ #ifndef __INLINE -+ #define __INLINE inline -+ #endif -+ #ifndef __STATIC_INLINE -+ #define __STATIC_INLINE static inline -+ #endif -+ #ifndef __STATIC_FORCEINLINE -+ #define __STATIC_FORCEINLINE __STATIC_INLINE -+ #endif -+ #ifndef __NO_RETURN -+ // NO RETURN is automatically detected hence no warning here -+ #define __NO_RETURN -+ #endif -+ #ifndef __USED -+ #warning No compiler specific solution for __USED. __USED is ignored. -+ #define __USED -+ #endif -+ #ifndef __WEAK -+ #define __WEAK __weak -+ #endif -+ #ifndef __PACKED -+ #define __PACKED @packed -+ #endif -+ #ifndef __PACKED_STRUCT -+ #define __PACKED_STRUCT @packed struct -+ #endif -+ #ifndef __PACKED_UNION -+ #define __PACKED_UNION @packed union -+ #endif -+ #ifndef __UNALIGNED_UINT32 /* deprecated */ -+ @packed struct T_UINT32 { uint32_t v; }; -+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -+ #endif -+ #ifndef __UNALIGNED_UINT16_WRITE -+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; -+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -+ #endif -+ #ifndef __UNALIGNED_UINT16_READ -+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; -+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -+ #endif -+ #ifndef __UNALIGNED_UINT32_WRITE -+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; -+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -+ #endif -+ #ifndef __UNALIGNED_UINT32_READ -+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; -+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -+ #endif -+ #ifndef __ALIGNED -+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. -+ #define __ALIGNED(x) -+ #endif -+ #ifndef __RESTRICT -+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. -+ #define __RESTRICT -+ #endif -+ #ifndef __COMPILER_BARRIER -+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. -+ #define __COMPILER_BARRIER() (void)0 -+ #endif -+ #ifndef __NO_INIT -+ #define __NO_INIT __attribute__ ((section (".bss.noinit"))) -+ #endif -+ #ifndef __ALIAS -+ #define __ALIAS(x) __attribute__ ((alias(x))) -+ #endif -+ -+#else -+ #error Unknown compiler. -+#endif -+ -+ -+#endif /* __CMSIS_COMPILER_H */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_gcc.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_gcc.h -new file mode 100644 -index 0000000..ffb718c ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_gcc.h -@@ -0,0 +1,2225 @@ -+/* *INDENT-OFF* */ -+ -+/**************************************************************************//** -+ * @file cmsis_gcc.h -+ * @brief CMSIS compiler GCC header file -+ * @version V5.4.2 -+ * @date 17. December 2022 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/cmsis_gcc.h -+*/ -+ -+#ifndef __CMSIS_GCC_H -+#define __CMSIS_GCC_H -+ -+/* ignore some GCC warnings */ -+#pragma GCC diagnostic push -+#pragma GCC diagnostic ignored "-Wsign-conversion" -+#pragma GCC diagnostic ignored "-Wconversion" -+#pragma GCC diagnostic ignored "-Wunused-parameter" -+ -+/* Fallback for __has_builtin */ -+#ifndef __has_builtin -+ #define __has_builtin(x) (0) -+#endif -+ -+/* CMSIS compiler specific defines */ -+#ifndef __ASM -+ #define __ASM __asm -+#endif -+#ifndef __INLINE -+ #define __INLINE inline -+#endif -+#ifndef __STATIC_INLINE -+ #define __STATIC_INLINE static inline -+#endif -+#ifndef __STATIC_FORCEINLINE -+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -+#endif -+#ifndef __NO_RETURN -+ #define __NO_RETURN __attribute__((__noreturn__)) -+#endif -+#ifndef __USED -+ #define __USED __attribute__((used)) -+#endif -+#ifndef __WEAK -+ #define __WEAK __attribute__((weak)) -+#endif -+#ifndef __PACKED -+ #define __PACKED __attribute__((packed, aligned(1))) -+#endif -+#ifndef __PACKED_STRUCT -+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -+#endif -+#ifndef __PACKED_UNION -+ #define __PACKED_UNION union __attribute__((packed, aligned(1))) -+#endif -+#ifndef __UNALIGNED_UINT32 /* deprecated */ -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wpacked" -+ #pragma GCC diagnostic ignored "-Wattributes" -+ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; -+ #pragma GCC diagnostic pop -+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -+#endif -+#ifndef __UNALIGNED_UINT16_WRITE -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wpacked" -+ #pragma GCC diagnostic ignored "-Wattributes" -+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; -+ #pragma GCC diagnostic pop -+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -+#endif -+#ifndef __UNALIGNED_UINT16_READ -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wpacked" -+ #pragma GCC diagnostic ignored "-Wattributes" -+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; -+ #pragma GCC diagnostic pop -+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -+#endif -+#ifndef __UNALIGNED_UINT32_WRITE -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wpacked" -+ #pragma GCC diagnostic ignored "-Wattributes" -+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; -+ #pragma GCC diagnostic pop -+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -+#endif -+#ifndef __UNALIGNED_UINT32_READ -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wpacked" -+ #pragma GCC diagnostic ignored "-Wattributes" -+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; -+ #pragma GCC diagnostic pop -+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -+#endif -+#ifndef __ALIGNED -+ #define __ALIGNED(x) __attribute__((aligned(x))) -+#endif -+#ifndef __RESTRICT -+ #define __RESTRICT __restrict -+#endif -+#ifndef __COMPILER_BARRIER -+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -+#endif -+#ifndef __NO_INIT -+ #define __NO_INIT __attribute__ ((section (".bss.noinit"))) -+#endif -+#ifndef __ALIAS -+ #define __ALIAS(x) __attribute__ ((alias(x))) -+#endif -+ -+/* ######################### Startup and Lowlevel Init ######################## */ -+ -+#ifndef __PROGRAM_START -+ -+/** -+ \brief Initializes data and bss sections -+ \details This default implementations initialized all data and additional bss -+ sections relying on .copy.table and .zero.table specified properly -+ in the used linker script. -+ -+ */ -+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -+{ -+ extern void _start(void) __NO_RETURN; -+ -+ typedef struct __copy_table { -+ uint32_t const* src; -+ uint32_t* dest; -+ uint32_t wlen; -+ } __copy_table_t; -+ -+ typedef struct __zero_table { -+ uint32_t* dest; -+ uint32_t wlen; -+ } __zero_table_t; -+ -+ extern const __copy_table_t __copy_table_start__; -+ extern const __copy_table_t __copy_table_end__; -+ extern const __zero_table_t __zero_table_start__; -+ extern const __zero_table_t __zero_table_end__; -+ -+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { -+ for(uint32_t i=0u; iwlen; ++i) { -+ pTable->dest[i] = pTable->src[i]; -+ } -+ } -+ -+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { -+ for(uint32_t i=0u; iwlen; ++i) { -+ pTable->dest[i] = 0u; -+ } -+ } -+ -+ _start(); -+} -+ -+#define __PROGRAM_START __cmsis_start -+#endif -+ -+#ifndef __INITIAL_SP -+#define __INITIAL_SP __StackTop -+#endif -+ -+#ifndef __STACK_LIMIT -+#define __STACK_LIMIT __StackLimit -+#endif -+ -+#ifndef __VECTOR_TABLE -+#define __VECTOR_TABLE __Vectors -+#endif -+ -+#ifndef __VECTOR_TABLE_ATTRIBUTE -+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -+#endif -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+#ifndef __STACK_SEAL -+#define __STACK_SEAL __StackSeal -+#endif -+ -+#ifndef __TZ_STACK_SEAL_SIZE -+#define __TZ_STACK_SEAL_SIZE 8U -+#endif -+ -+#ifndef __TZ_STACK_SEAL_VALUE -+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -+#endif -+ -+ -+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { -+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -+} -+#endif -+ -+ -+/* ########################## Core Instruction Access ######################### */ -+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface -+ Access to dedicated instructions -+ @{ -+*/ -+ -+/* Define macros for porting to both thumb1 and thumb2. -+ * For thumb1, use low register (r0-r7), specified by constraint "l" -+ * Otherwise, use general registers, specified by constraint "r" */ -+#if defined (__thumb__) && !defined (__thumb2__) -+#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -+#define __CMSIS_GCC_RW_REG(r) "+l" (r) -+#define __CMSIS_GCC_USE_REG(r) "l" (r) -+#else -+#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -+#define __CMSIS_GCC_RW_REG(r) "+r" (r) -+#define __CMSIS_GCC_USE_REG(r) "r" (r) -+#endif -+ -+/** -+ \brief No Operation -+ \details No Operation does nothing. This instruction can be used for code alignment purposes. -+ */ -+#define __NOP() __ASM volatile ("nop") -+ -+/** -+ \brief Wait For Interrupt -+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. -+ */ -+#define __WFI() __ASM volatile ("wfi":::"memory") -+ -+ -+/** -+ \brief Wait For Event -+ \details Wait For Event is a hint instruction that permits the processor to enter -+ a low-power state until one of a number of events occurs. -+ */ -+#define __WFE() __ASM volatile ("wfe":::"memory") -+ -+ -+/** -+ \brief Send Event -+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. -+ */ -+#define __SEV() __ASM volatile ("sev") -+ -+ -+/** -+ \brief Instruction Synchronization Barrier -+ \details Instruction Synchronization Barrier flushes the pipeline in the processor, -+ so that all instructions following the ISB are fetched from cache or memory, -+ after the instruction has been completed. -+ */ -+__STATIC_FORCEINLINE void __ISB(void) -+{ -+ __ASM volatile ("isb 0xF":::"memory"); -+} -+ -+ -+/** -+ \brief Data Synchronization Barrier -+ \details Acts as a special kind of Data Memory Barrier. -+ It completes when all explicit memory accesses before this instruction complete. -+ */ -+__STATIC_FORCEINLINE void __DSB(void) -+{ -+ __ASM volatile ("dsb 0xF":::"memory"); -+} -+ -+ -+/** -+ \brief Data Memory Barrier -+ \details Ensures the apparent order of the explicit memory operations before -+ and after the instruction, without ensuring their completion. -+ */ -+__STATIC_FORCEINLINE void __DMB(void) -+{ -+ __ASM volatile ("dmb 0xF":::"memory"); -+} -+ -+ -+/** -+ \brief Reverse byte order (32 bit) -+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -+{ -+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) -+ return __builtin_bswap32(value); -+#else -+ uint32_t result; -+ -+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); -+ return result; -+#endif -+} -+ -+ -+/** -+ \brief Reverse byte order (16 bit) -+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -+{ -+ uint32_t result; -+ -+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); -+ return result; -+} -+ -+ -+/** -+ \brief Reverse byte order (16 bit) -+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -+{ -+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) -+ return (int16_t)__builtin_bswap16(value); -+#else -+ int16_t result; -+ -+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); -+ return result; -+#endif -+} -+ -+ -+/** -+ \brief Rotate Right in unsigned value (32 bit) -+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. -+ \param [in] op1 Value to rotate -+ \param [in] op2 Number of Bits to rotate -+ \return Rotated value -+ */ -+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -+{ -+ op2 %= 32U; -+ if (op2 == 0U) -+ { -+ return op1; -+ } -+ return (op1 >> op2) | (op1 << (32U - op2)); -+} -+ -+ -+/** -+ \brief Breakpoint -+ \details Causes the processor to enter Debug state. -+ Debug tools can use this to investigate system state when the instruction at a particular address is reached. -+ \param [in] value is ignored by the processor. -+ If required, a debugger can use it to store additional information about the breakpoint. -+ */ -+#define __BKPT(value) __ASM volatile ("bkpt "#value) -+ -+ -+/** -+ \brief Reverse bit order of value -+ \details Reverses the bit order of the given value. -+ \param [in] value Value to reverse -+ \return Reversed value -+ */ -+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -+{ -+ uint32_t result; -+ -+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -+#else -+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ -+ -+ result = value; /* r will be reversed bits of v; first get LSB of v */ -+ for (value >>= 1U; value != 0U; value >>= 1U) -+ { -+ result <<= 1U; -+ result |= value & 1U; -+ s--; -+ } -+ result <<= s; /* shift when v's highest bits are zero */ -+#endif -+ return result; -+} -+ -+ -+/** -+ \brief Count leading zeros -+ \details Counts the number of leading zeros of a data value. -+ \param [in] value Value to count the leading zeros -+ \return number of leading zeros in value -+ */ -+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -+{ -+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally -+ __builtin_clz(0) is undefined behaviour, so handle this case specially. -+ This guarantees ARM-compatible results if happening to compile on a non-ARM -+ target, and ensures the compiler doesn't decide to activate any -+ optimisations using the logic "value was passed to __builtin_clz, so it -+ is non-zero". -+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a -+ single CLZ instruction. -+ */ -+ if (value == 0U) -+ { -+ return 32U; -+ } -+ return __builtin_clz(value); -+} -+ -+ -+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -+/** -+ \brief LDR Exclusive (8 bit) -+ \details Executes a exclusive LDR instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -+{ -+ uint32_t result; -+ -+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) -+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -+#else -+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not -+ accepted by assembler. So has to use following less efficient pattern. -+ */ -+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -+#endif -+ return ((uint8_t) result); /* Add explicit type cast here */ -+} -+ -+ -+/** -+ \brief LDR Exclusive (16 bit) -+ \details Executes a exclusive LDR instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -+{ -+ uint32_t result; -+ -+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) -+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -+#else -+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not -+ accepted by assembler. So has to use following less efficient pattern. -+ */ -+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -+#endif -+ return ((uint16_t) result); /* Add explicit type cast here */ -+} -+ -+ -+/** -+ \brief LDR Exclusive (32 bit) -+ \details Executes a exclusive LDR instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); -+ return(result); -+} -+ -+ -+/** -+ \brief STR Exclusive (8 bit) -+ \details Executes a exclusive STR instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); -+ return(result); -+} -+ -+ -+/** -+ \brief STR Exclusive (16 bit) -+ \details Executes a exclusive STR instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); -+ return(result); -+} -+ -+ -+/** -+ \brief STR Exclusive (32 bit) -+ \details Executes a exclusive STR instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Remove the exclusive lock -+ \details Removes the exclusive lock which is created by LDREX. -+ */ -+__STATIC_FORCEINLINE void __CLREX(void) -+{ -+ __ASM volatile ("clrex" ::: "memory"); -+} -+ -+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -+ -+ -+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -+/** -+ \brief Signed Saturate -+ \details Saturates a signed value. -+ \param [in] ARG1 Value to be saturated -+ \param [in] ARG2 Bit position to saturate to (1..32) -+ \return Saturated value -+ */ -+#define __SSAT(ARG1, ARG2) \ -+__extension__ \ -+({ \ -+ int32_t __RES, __ARG1 = (ARG1); \ -+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ -+ __RES; \ -+ }) -+ -+ -+/** -+ \brief Unsigned Saturate -+ \details Saturates an unsigned value. -+ \param [in] ARG1 Value to be saturated -+ \param [in] ARG2 Bit position to saturate to (0..31) -+ \return Saturated value -+ */ -+#define __USAT(ARG1, ARG2) \ -+__extension__ \ -+({ \ -+ uint32_t __RES, __ARG1 = (ARG1); \ -+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ -+ __RES; \ -+ }) -+ -+ -+/** -+ \brief Rotate Right with Extend (32 bit) -+ \details Moves each bit of a bitstring right by one bit. -+ The carry input is shifted in at the left end of the bitstring. -+ \param [in] value Value to rotate -+ \return Rotated value -+ */ -+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); -+ return(result); -+} -+ -+ -+/** -+ \brief LDRT Unprivileged (8 bit) -+ \details Executes a Unprivileged LDRT instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -+{ -+ uint32_t result; -+ -+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) -+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -+#else -+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not -+ accepted by assembler. So has to use following less efficient pattern. -+ */ -+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -+#endif -+ return ((uint8_t) result); /* Add explicit type cast here */ -+} -+ -+ -+/** -+ \brief LDRT Unprivileged (16 bit) -+ \details Executes a Unprivileged LDRT instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -+{ -+ uint32_t result; -+ -+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) -+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -+#else -+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not -+ accepted by assembler. So has to use following less efficient pattern. -+ */ -+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -+#endif -+ return ((uint16_t) result); /* Add explicit type cast here */ -+} -+ -+ -+/** -+ \brief LDRT Unprivileged (32 bit) -+ \details Executes a Unprivileged LDRT instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); -+ return(result); -+} -+ -+ -+/** -+ \brief STRT Unprivileged (8 bit) -+ \details Executes a Unprivileged STRT instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -+{ -+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -+} -+ -+ -+/** -+ \brief STRT Unprivileged (16 bit) -+ \details Executes a Unprivileged STRT instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -+{ -+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -+} -+ -+ -+/** -+ \brief STRT Unprivileged (32 bit) -+ \details Executes a Unprivileged STRT instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -+{ -+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -+} -+ -+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ -+ -+/** -+ \brief Signed Saturate -+ \details Saturates a signed value. -+ \param [in] value Value to be saturated -+ \param [in] sat Bit position to saturate to (1..32) -+ \return Saturated value -+ */ -+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -+{ -+ if ((sat >= 1U) && (sat <= 32U)) -+ { -+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); -+ const int32_t min = -1 - max ; -+ if (val > max) -+ { -+ return max; -+ } -+ else if (val < min) -+ { -+ return min; -+ } -+ } -+ return val; -+} -+ -+/** -+ \brief Unsigned Saturate -+ \details Saturates an unsigned value. -+ \param [in] value Value to be saturated -+ \param [in] sat Bit position to saturate to (0..31) -+ \return Saturated value -+ */ -+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -+{ -+ if (sat <= 31U) -+ { -+ const uint32_t max = ((1U << sat) - 1U); -+ if (val > (int32_t)max) -+ { -+ return max; -+ } -+ else if (val < 0) -+ { -+ return 0U; -+ } -+ } -+ return (uint32_t)val; -+} -+ -+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ -+ -+ -+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -+/** -+ \brief Load-Acquire (8 bit) -+ \details Executes a LDAB instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return ((uint8_t) result); -+} -+ -+ -+/** -+ \brief Load-Acquire (16 bit) -+ \details Executes a LDAH instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return ((uint16_t) result); -+} -+ -+ -+/** -+ \brief Load-Acquire (32 bit) -+ \details Executes a LDA instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return(result); -+} -+ -+ -+/** -+ \brief Store-Release (8 bit) -+ \details Executes a STLB instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -+{ -+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+} -+ -+ -+/** -+ \brief Store-Release (16 bit) -+ \details Executes a STLH instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -+{ -+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+} -+ -+ -+/** -+ \brief Store-Release (32 bit) -+ \details Executes a STL instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ */ -+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -+{ -+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+} -+ -+ -+/** -+ \brief Load-Acquire Exclusive (8 bit) -+ \details Executes a LDAB exclusive instruction for 8 bit value. -+ \param [in] ptr Pointer to data -+ \return value of type uint8_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return ((uint8_t) result); -+} -+ -+ -+/** -+ \brief Load-Acquire Exclusive (16 bit) -+ \details Executes a LDAH exclusive instruction for 16 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint16_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return ((uint16_t) result); -+} -+ -+ -+/** -+ \brief Load-Acquire Exclusive (32 bit) -+ \details Executes a LDA exclusive instruction for 32 bit values. -+ \param [in] ptr Pointer to data -+ \return value of type uint32_t at (*ptr) -+ */ -+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); -+ return(result); -+} -+ -+ -+/** -+ \brief Store-Release Exclusive (8 bit) -+ \details Executes a STLB exclusive instruction for 8 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+ return(result); -+} -+ -+ -+/** -+ \brief Store-Release Exclusive (16 bit) -+ \details Executes a STLH exclusive instruction for 16 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+ return(result); -+} -+ -+ -+/** -+ \brief Store-Release Exclusive (32 bit) -+ \details Executes a STL exclusive instruction for 32 bit values. -+ \param [in] value Value to store -+ \param [in] ptr Pointer to location -+ \return 0 Function succeeded -+ \return 1 Function failed -+ */ -+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -+ return(result); -+} -+ -+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -+ -+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ -+ -+ -+/* ########################### Core Function Access ########################### */ -+/** \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions -+ @{ -+ */ -+ -+/** -+ \brief Enable IRQ Interrupts -+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. -+ Can only be executed in Privileged modes. -+ */ -+__STATIC_FORCEINLINE void __enable_irq(void) -+{ -+ __ASM volatile ("cpsie i" : : : "memory"); -+} -+ -+ -+/** -+ \brief Disable IRQ Interrupts -+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK. -+ Can only be executed in Privileged modes. -+ */ -+__STATIC_FORCEINLINE void __disable_irq(void) -+{ -+ __ASM volatile ("cpsid i" : : : "memory"); -+} -+ -+ -+/** -+ \brief Get Control Register -+ \details Returns the content of the Control Register. -+ \return Control Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, control" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Control Register (non-secure) -+ \details Returns the content of the non-secure Control Register when in secure mode. -+ \return non-secure Control Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Control Register -+ \details Writes the given value to the Control Register. -+ \param [in] control Control Register value to set -+ */ -+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -+{ -+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -+ __ISB(); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Control Register (non-secure) -+ \details Writes the given value to the non-secure Control Register when in secure state. -+ \param [in] control Control Register value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -+{ -+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -+ __ISB(); -+} -+#endif -+ -+ -+/** -+ \brief Get IPSR Register -+ \details Returns the content of the IPSR Register. -+ \return IPSR Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Get APSR Register -+ \details Returns the content of the APSR Register. -+ \return APSR Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_APSR(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, apsr" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Get xPSR Register -+ \details Returns the content of the xPSR Register. -+ \return xPSR Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Get Process Stack Pointer -+ \details Returns the current value of the Process Stack Pointer (PSP). -+ \return PSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_PSP(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, psp" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Process Stack Pointer (non-secure) -+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. -+ \return PSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Process Stack Pointer -+ \details Assigns the given value to the Process Stack Pointer (PSP). -+ \param [in] topOfProcStack Process Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -+{ -+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Process Stack Pointer (non-secure) -+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. -+ \param [in] topOfProcStack Process Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -+{ -+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -+} -+#endif -+ -+ -+/** -+ \brief Get Main Stack Pointer -+ \details Returns the current value of the Main Stack Pointer (MSP). -+ \return MSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_MSP(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, msp" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Main Stack Pointer (non-secure) -+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. -+ \return MSP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Main Stack Pointer -+ \details Assigns the given value to the Main Stack Pointer (MSP). -+ \param [in] topOfMainStack Main Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -+{ -+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Main Stack Pointer (non-secure) -+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. -+ \param [in] topOfMainStack Main Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -+{ -+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -+} -+#endif -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Stack Pointer (non-secure) -+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. -+ \return SP Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); -+ return(result); -+} -+ -+ -+/** -+ \brief Set Stack Pointer (non-secure) -+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. -+ \param [in] topOfStack Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -+{ -+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -+} -+#endif -+ -+ -+/** -+ \brief Get Priority Mask -+ \details Returns the current state of the priority mask bit from the Priority Mask Register. -+ \return Priority Mask value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, primask" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Priority Mask (non-secure) -+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. -+ \return Priority Mask value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Priority Mask -+ \details Assigns the given value to the Priority Mask Register. -+ \param [in] priMask Priority Mask -+ */ -+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -+{ -+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Priority Mask (non-secure) -+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state. -+ \param [in] priMask Priority Mask -+ */ -+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -+{ -+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -+} -+#endif -+ -+ -+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -+/** -+ \brief Enable FIQ -+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. -+ Can only be executed in Privileged modes. -+ */ -+__STATIC_FORCEINLINE void __enable_fault_irq(void) -+{ -+ __ASM volatile ("cpsie f" : : : "memory"); -+} -+ -+ -+/** -+ \brief Disable FIQ -+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. -+ Can only be executed in Privileged modes. -+ */ -+__STATIC_FORCEINLINE void __disable_fault_irq(void) -+{ -+ __ASM volatile ("cpsid f" : : : "memory"); -+} -+ -+ -+/** -+ \brief Get Base Priority -+ \details Returns the current value of the Base Priority register. -+ \return Base Priority register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, basepri" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Base Priority (non-secure) -+ \details Returns the current value of the non-secure Base Priority register when in secure state. -+ \return Base Priority register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Base Priority -+ \details Assigns the given value to the Base Priority register. -+ \param [in] basePri Base Priority value to set -+ */ -+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -+{ -+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Base Priority (non-secure) -+ \details Assigns the given value to the non-secure Base Priority register when in secure state. -+ \param [in] basePri Base Priority value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -+{ -+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -+} -+#endif -+ -+ -+/** -+ \brief Set Base Priority with condition -+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, -+ or the new value increases the BASEPRI priority level. -+ \param [in] basePri Base Priority value to set -+ */ -+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -+{ -+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -+} -+ -+ -+/** -+ \brief Get Fault Mask -+ \details Returns the current value of the Fault Mask register. -+ \return Fault Mask register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); -+ return(result); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Fault Mask (non-secure) -+ \details Returns the current value of the non-secure Fault Mask register when in secure state. -+ \return Fault Mask register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); -+ return(result); -+} -+#endif -+ -+ -+/** -+ \brief Set Fault Mask -+ \details Assigns the given value to the Fault Mask register. -+ \param [in] faultMask Fault Mask value to set -+ */ -+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -+{ -+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Fault Mask (non-secure) -+ \details Assigns the given value to the non-secure Fault Mask register when in secure state. -+ \param [in] faultMask Fault Mask value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -+{ -+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -+} -+#endif -+ -+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ -+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ -+ -+ -+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -+ -+/** -+ \brief Get Process Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always in non-secure -+ mode. -+ -+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). -+ \return PSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, psplim" : "=r" (result) ); -+ return result; -+#endif -+} -+ -+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Process Stack Pointer Limit (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always. -+ -+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. -+ \return PSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); -+ return result; -+#endif -+} -+#endif -+ -+ -+/** -+ \brief Set Process Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored in non-secure -+ mode. -+ -+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). -+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set -+ */ -+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ (void)ProcStackPtrLimit; -+#else -+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -+#endif -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Process Stack Pointer (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored. -+ -+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. -+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) -+ // without main extensions, the non-secure PSPLIM is RAZ/WI -+ (void)ProcStackPtrLimit; -+#else -+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -+#endif -+} -+#endif -+ -+ -+/** -+ \brief Get Main Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always in non-secure -+ mode. -+ -+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). -+ \return MSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, msplim" : "=r" (result) ); -+ return result; -+#endif -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Get Main Stack Pointer Limit (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence zero is returned always. -+ -+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. -+ \return MSPLIM Register value -+ */ -+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ return 0U; -+#else -+ uint32_t result; -+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); -+ return result; -+#endif -+} -+#endif -+ -+ -+/** -+ \brief Set Main Stack Pointer Limit -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored in non-secure -+ mode. -+ -+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). -+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set -+ */ -+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ -+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ (void)MainStackPtrLimit; -+#else -+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -+#endif -+} -+ -+ -+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -+/** -+ \brief Set Main Stack Pointer Limit (non-secure) -+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure -+ Stack Pointer Limit register hence the write is silently ignored. -+ -+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. -+ \param [in] MainStackPtrLimit Main Stack Pointer value to set -+ */ -+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -+{ -+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) -+ // without main extensions, the non-secure MSPLIM is RAZ/WI -+ (void)MainStackPtrLimit; -+#else -+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -+#endif -+} -+#endif -+ -+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ -+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ -+ -+ -+/** -+ \brief Get FPSCR -+ \details Returns the current value of the Floating Point Status/Control register. -+ \return Floating Point Status/Control register value -+ */ -+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -+{ -+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ -+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -+#if __has_builtin(__builtin_arm_get_fpscr) -+// Re-enable using built-in when GCC has been fixed -+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) -+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ -+ return __builtin_arm_get_fpscr(); -+#else -+ uint32_t result; -+ -+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); -+ return(result); -+#endif -+#else -+ return(0U); -+#endif -+} -+ -+ -+/** -+ \brief Set FPSCR -+ \details Assigns the given value to the Floating Point Status/Control register. -+ \param [in] fpscr Floating Point Status/Control value to set -+ */ -+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -+{ -+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ -+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -+#if __has_builtin(__builtin_arm_set_fpscr) -+// Re-enable using built-in when GCC has been fixed -+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) -+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ -+ __builtin_arm_set_fpscr(fpscr); -+#else -+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -+#endif -+#else -+ (void)fpscr; -+#endif -+} -+ -+ -+/*@} end of CMSIS_Core_RegAccFunctions */ -+ -+ -+/* ################### Compiler specific Intrinsics ########################### */ -+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics -+ Access to dedicated SIMD instructions -+ @{ -+*/ -+ -+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -+ -+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+ -+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+ -+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -+{ -+ uint32_t result; -+ -+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); -+ return(result); -+} -+ -+#define __SSAT16(ARG1, ARG2) \ -+__extension__ \ -+({ \ -+ int32_t __RES, __ARG1 = (ARG1); \ -+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ -+ __RES; \ -+ }) -+ -+#define __USAT16(ARG1, ARG2) \ -+__extension__ \ -+({ \ -+ uint32_t __RES, __ARG1 = (ARG1); \ -+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ -+ __RES; \ -+ }) -+ -+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -+{ -+ uint32_t result; -+ -+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -+{ -+ uint32_t result; -+ -+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -+{ -+ uint32_t result; -+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { -+ __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); -+ } else { -+ result = __SXTB16(__ROR(op1, rotate)) ; -+ } -+ return result; -+} -+ -+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -+{ -+ uint32_t result; -+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { -+ __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); -+ } else { -+ result = __SXTAB16(op1, __ROR(op2, rotate)); -+ } -+ return result; -+} -+ -+ -+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -+{ -+ union llreg_u{ -+ uint32_t w32[2]; -+ uint64_t w64; -+ } llr; -+ llr.w64 = acc; -+ -+#ifndef __ARMEB__ /* Little endian */ -+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -+#else /* Big endian */ -+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -+#endif -+ -+ return(llr.w64); -+} -+ -+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -+{ -+ union llreg_u{ -+ uint32_t w32[2]; -+ uint64_t w64; -+ } llr; -+ llr.w64 = acc; -+ -+#ifndef __ARMEB__ /* Little endian */ -+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -+#else /* Big endian */ -+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -+#endif -+ -+ return(llr.w64); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -+{ -+ union llreg_u{ -+ uint32_t w32[2]; -+ uint64_t w64; -+ } llr; -+ llr.w64 = acc; -+ -+#ifndef __ARMEB__ /* Little endian */ -+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -+#else /* Big endian */ -+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -+#endif -+ -+ return(llr.w64); -+} -+ -+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -+{ -+ union llreg_u{ -+ uint32_t w32[2]; -+ uint64_t w64; -+ } llr; -+ llr.w64 = acc; -+ -+#ifndef __ARMEB__ /* Little endian */ -+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -+#else /* Big endian */ -+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -+#endif -+ -+ return(llr.w64); -+} -+ -+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -+{ -+ uint32_t result; -+ -+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -+{ -+ int32_t result; -+ -+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -+{ -+ int32_t result; -+ -+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); -+ return(result); -+} -+ -+ -+#define __PKHBT(ARG1,ARG2,ARG3) \ -+__extension__ \ -+({ \ -+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ -+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ -+ __RES; \ -+ }) -+ -+#define __PKHTB(ARG1,ARG2,ARG3) \ -+__extension__ \ -+({ \ -+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ -+ if (ARG3 == 0) \ -+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ -+ else \ -+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ -+ __RES; \ -+ }) -+ -+ -+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -+{ -+ int32_t result; -+ -+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); -+ return(result); -+} -+ -+#endif /* (__ARM_FEATURE_DSP == 1) */ -+/*@} end of group CMSIS_SIMD_intrinsics */ -+ -+ -+#pragma GCC diagnostic pop -+ -+#endif /* __CMSIS_GCC_H */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_version.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_version.h -new file mode 100644 -index 0000000..32d3afb ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/cmsis_version.h -@@ -0,0 +1,47 @@ -+/* *INDENT-OFF* */ -+ -+/**************************************************************************//** -+ * @file cmsis_version.h -+ * @brief CMSIS Core(M) Version definitions -+ * @version V5.0.5 -+ * @date 02. February 2022 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/cmsis_version.h -+*/ -+ -+#if defined ( __ICCARM__ ) -+ #pragma system_include /* treat file as system include file for MISRA check */ -+#elif defined (__clang__) -+ #pragma clang system_header /* treat file as system include file */ -+#endif -+ -+#ifndef __CMSIS_VERSION_H -+#define __CMSIS_VERSION_H -+ -+/* CMSIS Version definitions */ -+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -+#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ -+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ -+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -+#endif -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/core_cm55.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/core_cm55.h -new file mode 100644 -index 0000000..bc49aa5 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/core_cm55.h -@@ -0,0 +1,4920 @@ -+/* *INDENT-OFF* */ -+ -+/**************************************************************************//** -+ * @file core_cm55.h -+ * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File -+ * @version V1.5.2 -+ * @date 19. April 2023 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2018-2023 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/core_cm55.h -+*/ -+ -+ -+#if defined ( __ICCARM__ ) -+ #pragma system_include /* treat file as system include file for MISRA check */ -+#elif defined (__clang__) -+ #pragma clang system_header /* treat file as system include file */ -+#elif defined ( __GNUC__ ) -+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -+#endif -+ -+#ifndef __CORE_CM55_H_GENERIC -+#define __CORE_CM55_H_GENERIC -+ -+#include -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/** -+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions -+ CMSIS violates the following MISRA-C:2004 rules: -+ -+ \li Required Rule 8.5, object/function definition in header file.
-+ Function definitions in header files are used to allow 'inlining'. -+ -+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
-+ Unions are used for effective representation of core registers. -+ -+ \li Advisory Rule 19.7, Function-like macro defined.
-+ Function-like macros are used to allow more efficient code. -+ */ -+ -+ -+/******************************************************************************* -+ * CMSIS definitions -+ ******************************************************************************/ -+/** -+ \ingroup Cortex_M55 -+ @{ -+ */ -+ -+#include "cmsis_version.h" -+ -+/* CMSIS CM55 definitions */ -+#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -+#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -+#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ -+ __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -+ -+#define __CORTEX_M (55U) /*!< Cortex-M Core */ -+ -+#if defined ( __CC_ARM ) -+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture. -+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -+ #if defined __ARM_FP -+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -+ #define __FPU_USED 1U -+ #else -+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -+ #define __FPU_USED 0U -+ #endif -+ #else -+ #define __FPU_USED 0U -+ #endif -+ -+ #if defined(__ARM_FEATURE_DSP) -+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) -+ #define __DSP_USED 1U -+ #else -+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" -+ #define __DSP_USED 0U -+ #endif -+ #else -+ #define __DSP_USED 0U -+ #endif -+ -+#elif defined (__ti__) -+ #if defined (__ARM_FP) -+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -+ #define __FPU_USED 1U -+ #else -+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -+ #define __FPU_USED 0U -+ #endif -+ #else -+ #define __FPU_USED 0U -+ #endif -+ -+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) -+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) -+ #define __DSP_USED 1U -+ #else -+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" -+ #define __DSP_USED 0U -+ #endif -+ #else -+ #define __DSP_USED 0U -+ #endif -+ -+#elif defined ( __GNUC__ ) -+ #if defined (__VFP_FP__) && !defined(__SOFTFP__) -+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -+ #define __FPU_USED 1U -+ #else -+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -+ #define __FPU_USED 0U -+ #endif -+ #else -+ #define __FPU_USED 0U -+ #endif -+ -+ #if defined(__ARM_FEATURE_DSP) -+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) -+ #define __DSP_USED 1U -+ #else -+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" -+ #define __DSP_USED 0U -+ #endif -+ #else -+ #define __DSP_USED 0U -+ #endif -+ -+#elif defined ( __ICCARM__ ) -+ #if defined __ARMVFP__ -+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -+ #define __FPU_USED 1U -+ #else -+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -+ #define __FPU_USED 0U -+ #endif -+ #else -+ #define __FPU_USED 0U -+ #endif -+ -+ #if defined(__ARM_FEATURE_DSP) -+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) -+ #define __DSP_USED 1U -+ #else -+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" -+ #define __DSP_USED 0U -+ #endif -+ #else -+ #define __DSP_USED 0U -+ #endif -+ -+#elif defined ( __TI_ARM__ ) -+ #if defined __TI_VFP_SUPPORT__ -+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -+ #define __FPU_USED 1U -+ #else -+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -+ #define __FPU_USED 0U -+ #endif -+ #else -+ #define __FPU_USED 0U -+ #endif -+ -+#elif defined ( __TASKING__ ) -+ #if defined __FPU_VFP__ -+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -+ #define __FPU_USED 1U -+ #else -+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -+ #define __FPU_USED 0U -+ #endif -+ #else -+ #define __FPU_USED 0U -+ #endif -+ -+#elif defined ( __CSMC__ ) -+ #if ( __CSMC__ & 0x400U) -+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) -+ #define __FPU_USED 1U -+ #else -+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" -+ #define __FPU_USED 0U -+ #endif -+ #else -+ #define __FPU_USED 0U -+ #endif -+ -+#endif -+ -+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ -+ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __CORE_CM55_H_GENERIC */ -+ -+#ifndef __CMSIS_GENERIC -+ -+#ifndef __CORE_CM55_H_DEPENDANT -+#define __CORE_CM55_H_DEPENDANT -+ -+#ifdef __cplusplus -+ extern "C" { -+#endif -+ -+/* check device defines and use defaults */ -+#if defined __CHECK_DEVICE_DEFINES -+ #ifndef __CM55_REV -+ #define __CM55_REV 0x0000U -+ #warning "__CM55_REV not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __FPU_PRESENT -+ #define __FPU_PRESENT 0U -+ #warning "__FPU_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #if __FPU_PRESENT != 0U -+ #ifndef __FPU_DP -+ #define __FPU_DP 0U -+ #warning "__FPU_DP not defined in device header file; using default!" -+ #endif -+ #endif -+ -+ #ifndef __MPU_PRESENT -+ #define __MPU_PRESENT 0U -+ #warning "__MPU_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __ICACHE_PRESENT -+ #define __ICACHE_PRESENT 0U -+ #warning "__ICACHE_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __DCACHE_PRESENT -+ #define __DCACHE_PRESENT 0U -+ #warning "__DCACHE_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __VTOR_PRESENT -+ #define __VTOR_PRESENT 1U -+ #warning "__VTOR_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __PMU_PRESENT -+ #define __PMU_PRESENT 0U -+ #warning "__PMU_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #if __PMU_PRESENT != 0U -+ #ifndef __PMU_NUM_EVENTCNT -+ #define __PMU_NUM_EVENTCNT 8U -+ #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" -+ #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) -+ #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ -+ #endif -+ #endif -+ -+ #ifndef __SAUREGION_PRESENT -+ #define __SAUREGION_PRESENT 0U -+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __DSP_PRESENT -+ #define __DSP_PRESENT 0U -+ #warning "__DSP_PRESENT not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __NVIC_PRIO_BITS -+ #define __NVIC_PRIO_BITS 3U -+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" -+ #endif -+ -+ #ifndef __Vendor_SysTickConfig -+ #define __Vendor_SysTickConfig 0U -+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!" -+ #endif -+#endif -+ -+/* IO definitions (access restrictions to peripheral registers) */ -+/** -+ \defgroup CMSIS_glob_defs CMSIS Global Defines -+ -+ IO Type Qualifiers are used -+ \li to specify the access to peripheral variables. -+ \li for automatic generation of peripheral register debug information. -+*/ -+#ifdef __cplusplus -+ #define __I volatile /*!< Defines 'read only' permissions */ -+#else -+ #define __I volatile const /*!< Defines 'read only' permissions */ -+#endif -+#define __O volatile /*!< Defines 'write only' permissions */ -+#define __IO volatile /*!< Defines 'read / write' permissions */ -+ -+/* following defines should be used for structure members */ -+#define __IM volatile const /*! Defines 'read only' structure member permissions */ -+#define __OM volatile /*! Defines 'write only' structure member permissions */ -+#define __IOM volatile /*! Defines 'read / write' structure member permissions */ -+ -+/*@} end of group Cortex_M55 */ -+ -+ -+ -+/******************************************************************************* -+ * Register Abstraction -+ Core Register contain: -+ - Core Register -+ - Core NVIC Register -+ - Core EWIC Register -+ - Core EWIC Interrupt Status Access Register -+ - Core SCB Register -+ - Core SysTick Register -+ - Core Debug Register -+ - Core PMU Register -+ - Core MPU Register -+ - Core SAU Register -+ - Core FPU Register -+ ******************************************************************************/ -+/** -+ \defgroup CMSIS_core_register Defines and Type Definitions -+ \brief Type definitions and defines for Cortex-M processor based devices. -+*/ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_CORE Status and Control Registers -+ \brief Core Register type definitions. -+ @{ -+ */ -+ -+/** -+ \brief Union type to access the Application Program Status Register (APSR). -+ */ -+typedef union -+{ -+ struct -+ { -+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ -+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ -+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ -+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ -+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ -+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ -+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ -+ } b; /*!< Structure used for bit access */ -+ uint32_t w; /*!< Type used for word access */ -+} APSR_Type; -+ -+/* APSR Register Definitions */ -+#define APSR_N_Pos 31U /*!< APSR: N Position */ -+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ -+ -+#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ -+ -+#define APSR_C_Pos 29U /*!< APSR: C Position */ -+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ -+ -+#define APSR_V_Pos 28U /*!< APSR: V Position */ -+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ -+ -+#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ -+ -+#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ -+ -+ -+/** -+ \brief Union type to access the Interrupt Program Status Register (IPSR). -+ */ -+typedef union -+{ -+ struct -+ { -+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ -+ } b; /*!< Structure used for bit access */ -+ uint32_t w; /*!< Type used for word access */ -+} IPSR_Type; -+ -+/* IPSR Register Definitions */ -+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ -+ -+ -+/** -+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR). -+ */ -+typedef union -+{ -+ struct -+ { -+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ -+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ -+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ -+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ -+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ -+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ -+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ -+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ -+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ -+ } b; /*!< Structure used for bit access */ -+ uint32_t w; /*!< Type used for word access */ -+} xPSR_Type; -+ -+/* xPSR Register Definitions */ -+#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ -+ -+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ -+ -+#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ -+ -+#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ -+ -+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ -+ -+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ -+ -+#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ -+ -+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ -+ -+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ -+ -+ -+/** -+ \brief Union type to access the Control Registers (CONTROL). -+ */ -+typedef union -+{ -+ struct -+ { -+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ -+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ -+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ -+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ -+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ -+ } b; /*!< Structure used for bit access */ -+ uint32_t w; /*!< Type used for word access */ -+} CONTROL_Type; -+ -+/* CONTROL Register Definitions */ -+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ -+ -+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ -+ -+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ -+ -+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ -+ -+/*@} end of group CMSIS_CORE */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) -+ \brief Type definitions for the NVIC Registers -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). -+ */ -+typedef struct -+{ -+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ -+ uint32_t RESERVED0[16U]; -+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ -+ uint32_t RSERVED1[16U]; -+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ -+ uint32_t RESERVED2[16U]; -+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ -+ uint32_t RESERVED3[16U]; -+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ -+ uint32_t RESERVED4[16U]; -+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ -+ uint32_t RESERVED5[16U]; -+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ -+ uint32_t RESERVED6[580U]; -+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -+} NVIC_Type; -+ -+/* Software Triggered Interrupt Register Definitions */ -+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ -+ -+/*@} end of group CMSIS_NVIC */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_SCB System Control Block (SCB) -+ \brief Type definitions for the System Control Block Registers -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the System Control Block (SCB). -+ */ -+typedef struct -+{ -+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ -+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ -+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ -+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ -+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ -+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ -+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ -+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ -+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ -+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ -+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ -+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ -+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ -+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ -+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ -+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ -+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ -+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ -+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ -+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ -+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ -+ uint32_t RESERVED7[21U]; -+ __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ -+ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ -+ uint32_t RESERVED3[69U]; -+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ -+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ -+ uint32_t RESERVED4[14U]; -+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ -+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ -+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ -+ uint32_t RESERVED5[1U]; -+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ -+ uint32_t RESERVED6[1U]; -+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ -+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ -+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ -+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ -+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ -+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ -+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ -+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ -+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -+} SCB_Type; -+ -+/* SCB CPUID Register Definitions */ -+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -+ -+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -+ -+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -+ -+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -+ -+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ -+ -+/* SCB Interrupt Control State Register Definitions */ -+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ -+ -+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ -+ -+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ -+ -+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -+ -+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -+ -+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -+ -+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -+ -+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ -+ -+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -+ -+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -+ -+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -+ -+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -+ -+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ -+ -+/* SCB Vector Table Offset Register Definitions */ -+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -+ -+/* SCB Application Interrupt and Reset Control Register Definitions */ -+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -+ -+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -+ -+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -+ -+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ -+ -+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ -+ -+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -+ -+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ -+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ -+ -+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ -+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ -+ -+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ -+ -+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -+ -+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -+ -+/* SCB System Control Register Definitions */ -+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -+ -+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ -+ -+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -+ -+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ -+ -+/* SCB Configuration Control Register Definitions */ -+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ -+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ -+ -+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ -+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ -+ -+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ -+ -+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ -+ -+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ -+ -+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ -+ -+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -+ -+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -+ -+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -+ -+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -+ -+/* SCB System Handler Control and State Register Definitions */ -+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ -+ -+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ -+ -+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ -+ -+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -+ -+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -+ -+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -+ -+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -+ -+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -+ -+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -+ -+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -+ -+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -+ -+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -+ -+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -+ -+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -+ -+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ -+ -+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ -+ -+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -+ -+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ -+ -+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -+ -+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ -+ -+/* SCB Configurable Fault Status Register Definitions */ -+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -+ -+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -+ -+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ -+ -+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -+ -+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ -+ -+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -+ -+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -+ -+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -+ -+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -+ -+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -+ -+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ -+ -+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -+ -+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -+ -+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -+ -+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -+ -+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -+ -+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -+ -+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -+ -+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ -+ -+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -+ -+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -+ -+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -+ -+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -+ -+/* SCB Hard Fault Status Register Definitions */ -+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -+ -+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -+ -+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ -+ -+/* SCB Debug Fault Status Register Definitions */ -+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ -+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ -+ -+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -+ -+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -+ -+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -+ -+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -+ -+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ -+ -+/* SCB Non-Secure Access Control Register Definitions */ -+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ -+ -+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ -+ -+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ -+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ -+ -+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ -+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ -+ -+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ -+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ -+ -+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ -+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ -+ -+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ -+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ -+ -+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ -+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ -+ -+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ -+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ -+ -+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ -+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ -+ -+/* SCB Debug Feature Register 0 Definitions */ -+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ -+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ -+ -+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ -+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ -+ -+/* SCB Cache Level ID Register Definitions */ -+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ -+ -+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ -+ -+/* SCB Cache Type Register Definitions */ -+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ -+ -+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ -+ -+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ -+ -+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ -+ -+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ -+ -+/* SCB Cache Size ID Register Definitions */ -+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ -+ -+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ -+ -+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ -+ -+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ -+ -+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ -+ -+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ -+ -+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ -+ -+/* SCB Cache Size Selection Register Definitions */ -+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ -+ -+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ -+ -+/* SCB Software Triggered Interrupt Register Definitions */ -+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ -+ -+/* SCB RAS Fault Status Register Definitions */ -+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ -+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ -+ -+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ -+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ -+ -+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ -+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ -+ -+/* SCB D-Cache Invalidate by Set-way Register Definitions */ -+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ -+ -+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ -+ -+/* SCB D-Cache Clean by Set-way Register Definitions */ -+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ -+ -+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ -+ -+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ -+ -+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ -+ -+/*@} end of group CMSIS_SCB */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_ICB Implementation Control Block register (ICB) -+ \brief Type definitions for the Implementation Control Block Register -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Implementation Control Block (ICB). -+ */ -+typedef struct -+{ -+ uint32_t RESERVED0[1U]; -+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -+} ICB_Type; -+ -+/* Auxiliary Control Register Definitions */ -+#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ -+#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ -+ -+#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ -+#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ -+ -+#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -+#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ -+ -+#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ -+#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ -+ -+#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ -+#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ -+ -+#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -+#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ -+ -+#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ -+#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ -+ -+#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -+#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ -+ -+#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ -+#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ -+ -+#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ -+#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ -+ -+#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ -+#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ -+ -+#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ -+#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ -+ -+#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ -+#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ -+ -+#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -+#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -+ -+/* Interrupt Controller Type Register Definitions */ -+#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -+#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ -+ -+/*@} end of group CMSIS_ICB */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_SysTick System Tick Timer (SysTick) -+ \brief Type definitions for the System Timer Registers. -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the System Timer (SysTick). -+ */ -+typedef struct -+{ -+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ -+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ -+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ -+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -+} SysTick_Type; -+ -+/* SysTick Control / Status Register Definitions */ -+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -+ -+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -+ -+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -+ -+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ -+ -+/* SysTick Reload Register Definitions */ -+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ -+ -+/* SysTick Current Register Definitions */ -+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ -+ -+/* SysTick Calibration Register Definitions */ -+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -+ -+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -+ -+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ -+ -+/*@} end of group CMSIS_SysTick */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) -+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). -+ */ -+typedef struct -+{ -+ __OM union -+ { -+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ -+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ -+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ -+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ -+ uint32_t RESERVED0[864U]; -+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ -+ uint32_t RESERVED1[15U]; -+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ -+ uint32_t RESERVED2[15U]; -+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -+ uint32_t RESERVED3[27U]; -+ __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) ITM Integration Read Register */ -+ uint32_t RESERVED4[1U]; -+ __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ -+ uint32_t RESERVED5[1U]; -+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ -+ uint32_t RESERVED6[46U]; -+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ -+ uint32_t RESERVED7[3U]; -+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ -+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ -+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ -+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ -+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ -+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ -+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ -+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ -+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ -+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ -+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ -+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ -+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -+} ITM_Type; -+ -+/* ITM Stimulus Port Register Definitions */ -+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ -+ -+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ -+ -+/* ITM Trace Privilege Register Definitions */ -+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ -+ -+/* ITM Trace Control Register Definitions */ -+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -+ -+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ -+ -+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -+ -+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ -+ -+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ -+ -+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -+ -+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -+ -+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -+ -+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -+ -+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -+ -+/* ITM Integration Read Register Definitions */ -+#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ -+#define ITM_ITREAD_AFVALID_Msk (0x1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ -+ -+#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ -+#define ITM_ITREAD_ATREADY_Msk (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ -+ -+/* ITM Integration Write Register Definitions */ -+#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ -+#define ITM_ITWRITE_AFVALID_Msk (0x1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ -+ -+#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ -+#define ITM_ITWRITE_ATREADY_Msk (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ -+ -+/* ITM Integration Mode Control Register Definitions */ -+#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ -+#define ITM_ITCTRL_IME_Msk (0x1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ -+ -+/*@}*/ /* end of group CMSIS_ITM */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) -+ \brief Type definitions for the Data Watchpoint and Trace (DWT) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT). -+ */ -+typedef struct -+{ -+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ -+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ -+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ -+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ -+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ -+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ -+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ -+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ -+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ -+ uint32_t RESERVED1[1U]; -+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ -+ uint32_t RESERVED2[1U]; -+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ -+ uint32_t RESERVED3[1U]; -+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ -+ __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ -+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ -+ uint32_t RESERVED4[1U]; -+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ -+ uint32_t RESERVED5[1U]; -+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ -+ uint32_t RESERVED6[1U]; -+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -+ __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ -+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ -+ uint32_t RESERVED7[1U]; -+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ -+ uint32_t RESERVED8[1U]; -+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ -+ uint32_t RESERVED9[1U]; -+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ -+ uint32_t RESERVED10[1U]; -+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ -+ uint32_t RESERVED11[1U]; -+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ -+ uint32_t RESERVED12[1U]; -+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ -+ uint32_t RESERVED13[1U]; -+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ -+ uint32_t RESERVED14[968U]; -+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ -+ uint32_t RESERVED15[3U]; -+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -+} DWT_Type; -+ -+/* DWT Control Register Definitions */ -+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -+ -+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -+ -+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -+ -+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -+ -+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -+ -+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ -+ -+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -+ -+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -+ -+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -+ -+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -+ -+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -+ -+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -+ -+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -+ -+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -+ -+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -+ -+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -+ -+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -+ -+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -+ -+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ -+ -+/* DWT CPI Count Register Definitions */ -+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ -+ -+/* DWT Exception Overhead Count Register Definitions */ -+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ -+ -+/* DWT Sleep Count Register Definitions */ -+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ -+ -+/* DWT LSU Count Register Definitions */ -+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ -+ -+/* DWT Folded-instruction Count Register Definitions */ -+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ -+ -+/* DWT Comparator Function Register Definitions */ -+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ -+ -+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -+ -+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -+ -+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ -+ -+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ -+ -+/*@}*/ /* end of group CMSIS_DWT */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) -+ \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). -+ */ -+typedef struct -+{ -+ __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ -+ __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ -+ uint32_t RESERVED1[2U]; -+ __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ -+ __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ -+ __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ -+ uint32_t RESERVED2[313U]; -+ __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ -+ __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ -+ uint32_t RESERVED3[2U]; -+ __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ -+ uint32_t RESERVED4[44U]; -+ __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ -+ __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ -+ uint32_t RESERVED5[2U]; -+ __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ -+} MemSysCtl_Type; -+ -+/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ -+#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ -+#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ -+ -+#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ -+#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ -+ -+#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ -+#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ -+ -+#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ -+#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ -+ -+#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ -+#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ -+ -+#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ -+#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ -+ -+#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ -+#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ -+ -+#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ -+#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ -+ -+/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ -+#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ -+#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ -+ -+#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ -+#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ -+ -+#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ -+#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ -+ -+#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ -+#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ -+ -+/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ -+#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ -+#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ -+ -+#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ -+#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ -+ -+/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ -+#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ -+#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ -+ -+#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ -+#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ -+ -+/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ -+#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ -+#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ -+ -+#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ -+#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ -+ -+/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ -+#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ -+#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ -+ -+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ -+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ -+ -+/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ -+#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ -+#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ -+ -+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ -+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ -+ -+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ -+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ -+ -+/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ -+#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ -+#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ -+ -+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ -+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ -+ -+/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ -+#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ -+#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ -+ -+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ -+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ -+ -+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ -+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ -+ -+ -+/*@}*/ /* end of group MemSysCtl_Type */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup PwrModCtl_Type Power Mode Control Registers -+ \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). -+ */ -+typedef struct -+{ -+ __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ -+ __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ -+} PwrModCtl_Type; -+ -+/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ -+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ -+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ -+ -+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ -+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ -+ -+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ -+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ -+ -+/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ -+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ -+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ -+ -+/*@}*/ /* end of group PwrModCtl_Type */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup EWIC_Type External Wakeup Interrupt Controller Registers -+ \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). -+ */ -+typedef struct -+{ -+ __IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */ -+ __IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */ -+ __OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */ -+ __IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */ -+ uint32_t RESERVED0[124U]; -+ __IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */ -+ __IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */ -+ uint32_t RESERVED1[112U]; -+ __IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */ -+ __IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */ -+ uint32_t RESERVED2[112U]; -+ __IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */ -+} EWIC_Type; -+ -+/* EWIC Control (EWIC_CR) Register Definitions */ -+#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */ -+#define EWIC_EWIC_CR_EN_Msk (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */ -+ -+/* EWIC Automatic Sequence Control (EWIC_ASCR) Register Definitions */ -+#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */ -+#define EWIC_EWIC_ASCR_ASPU_Msk (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */ -+ -+#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */ -+#define EWIC_EWIC_ASCR_ASPD_Msk (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */ -+ -+/* EWIC Event Number ID (EWIC_NUMID) Register Definitions */ -+#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */ -+#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */ -+ -+/* EWIC Mask A (EWIC_MASKA) Register Definitions */ -+#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */ -+#define EWIC_EWIC_MASKA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */ -+ -+#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */ -+#define EWIC_EWIC_MASKA_NMI_Msk (0x1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */ -+ -+#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */ -+#define EWIC_EWIC_MASKA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */ -+ -+/* EWIC Mask n (EWIC_MASKn) Register Definitions */ -+#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */ -+#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */ -+ -+/* EWIC Pend A (EWIC_PENDA) Register Definitions */ -+#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */ -+#define EWIC_EWIC_PENDA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */ -+ -+#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */ -+#define EWIC_EWIC_PENDA_NMI_Msk (0x1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */ -+ -+#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */ -+#define EWIC_EWIC_PENDA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */ -+ -+/* EWIC Pend n (EWIC_PENDn) Register Definitions */ -+#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */ -+#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */ -+ -+/* EWIC Pend Summary (EWIC_PSR) Register Definitions */ -+#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */ -+#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */ -+ -+#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */ -+#define EWIC_EWIC_PSR_NZA_Msk (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */ -+ -+/*@}*/ /* end of group EWIC_Type */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup EWIC_ISA_Type External Wakeup Interrupt Controller (EWIC) interrupt status access registers -+ \brief Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA). -+ */ -+typedef struct -+{ -+ __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ -+ uint32_t RESERVED0[31U]; -+ __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/ ) Event Mask A Register */ -+ __IM uint32_t EVENTMASKn[15]; /*!< Offset: 0x084 (R/ ) Event Mask Register */ -+} EWIC_ISA_Type; -+ -+/* EWIC_ISA Event Set Pending (EVENTSPR) Register Definitions */ -+#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */ -+#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos) /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */ -+ -+#define EWIC_ISA_EVENTSPR_NMI_Pos 1U /*!< EWIC_ISA EVENTSPR: NMI Position */ -+#define EWIC_ISA_EVENTSPR_NMI_Msk (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos) /*!< EWIC_ISA EVENTSPR: NMI Mask */ -+ -+#define EWIC_ISA_EVENTSPR_EVENT_Pos 0U /*!< EWIC_ISA EVENTSPR: EVENT Position */ -+#define EWIC_ISA_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/) /*!< EWIC_ISA EVENTSPR: EVENT Mask */ -+ -+/* EWIC_ISA Event Mask A (EVENTMASKA) Register Definitions */ -+#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */ -+#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */ -+ -+#define EWIC_ISA_EVENTMASKA_NMI_Pos 1U /*!< EWIC_ISA EVENTMASKA: NMI Position */ -+#define EWIC_ISA_EVENTMASKA_NMI_Msk (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos) /*!< EWIC_ISA EVENTMASKA: NMI Mask */ -+ -+#define EWIC_ISA_EVENTMASKA_EVENT_Pos 0U /*!< EWIC_ISA EVENTMASKA: EVENT Position */ -+#define EWIC_ISA_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/) /*!< EWIC_ISA EVENTMASKA: EVENT Mask */ -+ -+/* EWIC_ISA Event Mask n (EVENTMASKn) Register Definitions */ -+#define EWIC_ISA_EVENTMASKn_IRQ_Pos 0U /*!< EWIC_ISA EVENTMASKn: IRQ Position */ -+#define EWIC_ISA_EVENTMASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */ -+ -+/*@}*/ /* end of group EWIC_ISA_Type */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) -+ \brief Type definitions for the Error Banking Registers (ERRBNK) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Error Banking Registers (ERRBNK). -+ */ -+typedef struct -+{ -+ __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ -+ __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ -+ uint32_t RESERVED0[2U]; -+ __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ -+ __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ -+ uint32_t RESERVED1[2U]; -+ __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ -+ uint32_t RESERVED2[1U]; -+ __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ -+} ErrBnk_Type; -+ -+/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ -+#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ -+#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ -+ -+#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ -+#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ -+ -+#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ -+#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ -+ -+#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ -+#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ -+ -+#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ -+#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ -+ -+/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ -+#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ -+#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ -+ -+#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ -+#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ -+ -+#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ -+#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ -+ -+#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ -+#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ -+ -+#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ -+#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ -+ -+/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ -+#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ -+#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ -+ -+#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ -+#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ -+ -+#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ -+#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ -+ -+#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ -+#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ -+ -+#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ -+#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ -+ -+#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ -+#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ -+ -+/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ -+#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ -+#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ -+ -+#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ -+#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ -+ -+#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ -+#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ -+ -+#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ -+#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ -+ -+#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ -+#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ -+ -+#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ -+#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ -+ -+/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ -+#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ -+#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ -+ -+#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ -+#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ -+ -+#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ -+#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ -+ -+#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ -+#define ERRBNK_TEBR0_BANK_Msk (0x7UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ -+ -+#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ -+#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ -+ -+#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ -+#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ -+ -+#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ -+#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ -+ -+/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ -+#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ -+#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ -+ -+#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ -+#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ -+ -+#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ -+#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ -+ -+#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ -+#define ERRBNK_TEBR1_BANK_Msk (0x7UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ -+ -+#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ -+#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ -+ -+#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ -+#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ -+ -+#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ -+#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ -+ -+/*@}*/ /* end of group ErrBnk_Type */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) -+ \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). -+ */ -+typedef struct -+{ -+ __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ -+ __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ -+} PrcCfgInf_Type; -+ -+/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ -+ -+/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ -+ -+/*@}*/ /* end of group PrcCfgInf_Type */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup STL_Type Software Test Library Observation Registers -+ \brief Type definitions for the Software Test Library Observation Registerss (STL) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Software Test Library Observation Registerss (STL). -+ */ -+typedef struct -+{ -+ __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ -+ __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ -+ uint32_t RESERVED0[2U]; -+ __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sample Register */ -+ __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ -+ __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ -+ __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ -+ -+} STL_Type; -+ -+/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ -+#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ -+#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ -+ -+#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ -+#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ -+ -+#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ -+#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ -+ -+#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ -+#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ -+ -+/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ -+#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ -+#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ -+ -+#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ -+#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ -+ -+#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ -+#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ -+ -+#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ -+#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ -+ -+/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ -+#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ -+#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ -+ -+#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ -+#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ -+ -+#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ -+#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ -+ -+/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ -+#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ -+#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ -+ -+#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ -+#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ -+ -+/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ -+#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ -+#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ -+ -+#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ -+#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ -+ -+/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ -+#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ -+#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ -+ -+#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ -+#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ -+ -+/*@}*/ /* end of group STL_Type */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_TPI Trace Port Interface (TPI) -+ \brief Type definitions for the Trace Port Interface (TPI) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Trace Port Interface Register (TPI). -+ */ -+typedef struct -+{ -+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ -+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ -+ uint32_t RESERVED0[2U]; -+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ -+ uint32_t RESERVED1[55U]; -+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ -+ uint32_t RESERVED2[131U]; -+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ -+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ -+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ -+ uint32_t RESERVED3[809U]; -+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ -+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ -+ uint32_t RESERVED4[4U]; -+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ -+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -+} TPI_Type; -+ -+/* TPI Asynchronous Clock Prescaler Register Definitions */ -+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ -+ -+/* TPI Selected Pin Protocol Register Definitions */ -+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ -+ -+/* TPI Formatter and Flush Status Register Definitions */ -+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -+ -+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -+ -+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -+ -+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ -+ -+/* TPI Formatter and Flush Control Register Definitions */ -+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -+ -+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ -+ -+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ -+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ -+ -+/* TPI Periodic Synchronization Control Register Definitions */ -+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ -+ -+/* TPI Software Lock Status Register Definitions */ -+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ -+ -+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ -+ -+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ -+ -+/* TPI DEVID Register Definitions */ -+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -+ -+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -+ -+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -+ -+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ -+ -+/* TPI DEVTYPE Register Definitions */ -+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ -+ -+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ -+ -+/*@}*/ /* end of group CMSIS_TPI */ -+ -+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) -+ \brief Type definitions for the Performance Monitoring Unit (PMU) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Performance Monitoring Unit (PMU). -+ */ -+typedef struct -+{ -+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ -+#if __PMU_NUM_EVENTCNT<31 -+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; -+#endif -+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ -+ uint32_t RESERVED1[224]; -+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ -+#if __PMU_NUM_EVENTCNT<31 -+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; -+#endif -+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ -+ uint32_t RESERVED3[480]; -+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ -+ uint32_t RESERVED4[7]; -+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ -+ uint32_t RESERVED5[7]; -+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ -+ uint32_t RESERVED6[7]; -+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ -+ uint32_t RESERVED7[7]; -+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ -+ uint32_t RESERVED8[7]; -+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ -+ uint32_t RESERVED9[7]; -+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ -+ uint32_t RESERVED10[79]; -+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ -+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ -+ uint32_t RESERVED11[108]; -+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ -+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ -+ uint32_t RESERVED12[3]; -+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ -+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ -+ uint32_t RESERVED13[3]; -+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ -+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ -+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ -+ __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ -+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ -+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ -+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ -+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ -+} PMU_Type; -+ -+/** \brief PMU Event Counter Registers (0-30) Definitions */ -+ -+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ -+#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ -+ -+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ -+ -+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ -+#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ -+ -+/** \brief PMU Count Enable Set Register Definitions */ -+ -+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ -+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ -+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ -+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ -+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ -+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ -+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ -+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ -+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ -+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ -+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ -+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ -+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ -+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ -+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ -+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ -+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ -+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ -+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ -+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ -+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ -+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ -+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ -+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ -+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ -+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ -+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ -+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ -+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ -+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ -+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ -+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ -+ -+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ -+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ -+ -+/** \brief PMU Count Enable Clear Register Definitions */ -+ -+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ -+ -+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ -+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ -+ -+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ -+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ -+ -+/** \brief PMU Interrupt Enable Set Register Definitions */ -+ -+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ -+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ -+ -+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ -+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ -+ -+/** \brief PMU Interrupt Enable Clear Register Definitions */ -+ -+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ -+ -+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ -+ -+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ -+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ -+ -+/** \brief PMU Overflow Flag Status Set Register Definitions */ -+ -+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ -+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ -+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ -+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ -+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ -+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ -+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ -+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ -+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ -+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ -+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ -+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ -+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ -+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ -+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ -+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ -+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ -+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ -+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ -+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ -+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ -+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ -+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ -+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ -+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ -+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ -+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ -+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ -+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ -+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ -+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ -+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ -+ -+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ -+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ -+ -+/** \brief PMU Overflow Flag Status Clear Register Definitions */ -+ -+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ -+ -+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ -+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ -+ -+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ -+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ -+ -+/** \brief PMU Software Increment Counter */ -+ -+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ -+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ -+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ -+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ -+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ -+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ -+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ -+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ -+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ -+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ -+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ -+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ -+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ -+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ -+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ -+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ -+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ -+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ -+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ -+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ -+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ -+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ -+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ -+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ -+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ -+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ -+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ -+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ -+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ -+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ -+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ -+ -+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ -+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ -+ -+/** \brief PMU Control Register Definitions */ -+ -+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ -+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ -+ -+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ -+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ -+ -+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ -+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ -+ -+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ -+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ -+ -+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ -+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ -+ -+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ -+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ -+ -+/** \brief PMU Type Register Definitions */ -+ -+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ -+#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ -+ -+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ -+#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ -+ -+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ -+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ -+ -+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ -+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ -+ -+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ -+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ -+ -+/** \brief PMU Authentication Status Register Definitions */ -+ -+#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ -+#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ -+ -+#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ -+#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ -+ -+#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ -+#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ -+ -+#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ -+#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ -+ -+#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ -+#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ -+ -+#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ -+#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ -+ -+#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ -+#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ -+ -+#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ -+#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ -+ -+ -+/*@} end of group CMSIS_PMU */ -+#endif -+ -+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_MPU Memory Protection Unit (MPU) -+ \brief Type definitions for the Memory Protection Unit (MPU) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Memory Protection Unit (MPU). -+ */ -+typedef struct -+{ -+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ -+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ -+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ -+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ -+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ -+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ -+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ -+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ -+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ -+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ -+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ -+ uint32_t RESERVED0[1]; -+ union { -+ __IOM uint32_t MAIR[2]; -+ struct { -+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ -+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ -+ }; -+ }; -+} MPU_Type; -+ -+#define MPU_TYPE_RALIASES 4U -+ -+/* MPU Type Register Definitions */ -+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -+ -+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -+ -+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ -+ -+/* MPU Control Register Definitions */ -+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -+ -+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -+ -+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ -+ -+/* MPU Region Number Register Definitions */ -+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ -+ -+/* MPU Region Base Address Register Definitions */ -+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ -+ -+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ -+ -+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ -+ -+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ -+ -+/* MPU Region Limit Address Register Definitions */ -+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ -+ -+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ -+ -+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ -+ -+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ -+ -+/* MPU Memory Attribute Indirection Register 0 Definitions */ -+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ -+ -+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ -+ -+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ -+ -+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ -+ -+/* MPU Memory Attribute Indirection Register 1 Definitions */ -+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ -+ -+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ -+ -+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ -+ -+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ -+ -+/*@} end of group CMSIS_MPU */ -+#endif -+ -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_SAU Security Attribution Unit (SAU) -+ \brief Type definitions for the Security Attribution Unit (SAU) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Security Attribution Unit (SAU). -+ */ -+typedef struct -+{ -+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ -+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ -+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ -+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -+#else -+ uint32_t RESERVED0[3]; -+#endif -+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ -+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -+} SAU_Type; -+ -+/* SAU Control Register Definitions */ -+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ -+ -+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ -+ -+/* SAU Type Register Definitions */ -+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ -+ -+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -+/* SAU Region Number Register Definitions */ -+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ -+ -+/* SAU Region Base Address Register Definitions */ -+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ -+ -+/* SAU Region Limit Address Register Definitions */ -+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ -+ -+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ -+ -+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ -+ -+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ -+ -+/* Secure Fault Status Register Definitions */ -+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ -+ -+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ -+ -+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ -+ -+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ -+ -+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ -+ -+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ -+ -+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ -+ -+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ -+ -+/*@} end of group CMSIS_SAU */ -+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_FPU Floating Point Unit (FPU) -+ \brief Type definitions for the Floating Point Unit (FPU) -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Floating Point Unit (FPU). -+ */ -+typedef struct -+{ -+ uint32_t RESERVED0[1U]; -+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ -+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ -+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ -+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ -+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ -+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -+} FPU_Type; -+ -+/* Floating-Point Context Control Register Definitions */ -+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ -+ -+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ -+ -+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ -+ -+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ -+ -+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ -+ -+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ -+ -+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ -+ -+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ -+ -+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ -+ -+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ -+ -+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ -+ -+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ -+ -+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ -+ -+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ -+ -+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ -+ -+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ -+ -+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ -+ -+/* Floating-Point Context Address Register Definitions */ -+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ -+ -+/* Floating-Point Default Status Control Register Definitions */ -+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ -+ -+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ -+ -+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ -+ -+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ -+ -+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ -+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ -+ -+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ -+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ -+ -+/* Media and VFP Feature Register 0 Definitions */ -+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ -+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ -+ -+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ -+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ -+ -+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ -+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ -+ -+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ -+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ -+ -+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ -+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ -+ -+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ -+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ -+ -+/* Media and VFP Feature Register 1 Definitions */ -+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ -+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ -+ -+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ -+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ -+ -+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ -+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ -+ -+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ -+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ -+ -+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ -+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ -+ -+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ -+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ -+ -+/* Media and VFP Feature Register 2 Definitions */ -+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ -+ -+/*@} end of group CMSIS_FPU */ -+ -+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) -+ \brief Type definitions for the Core Debug Registers -+ @{ -+ */ -+ -+/** -+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). -+ */ -+typedef struct -+{ -+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ -+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ -+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ -+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ -+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ -+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -+} CoreDebug_Type; -+ -+/* Debug Halting Control and Status Register Definitions */ -+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -+ -+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -+ -+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -+ -+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -+ -+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ -+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ -+ -+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ -+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ -+ -+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ -+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ -+ -+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ -+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ -+ -+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -+ -+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -+ -+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -+ -+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -+ -+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ -+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ -+ -+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ -+ -+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -+ -+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -+ -+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -+ -+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ -+ -+/* Debug Core Register Selector Register Definitions */ -+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -+ -+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ -+ -+/* Debug Exception and Monitor Control Register Definitions */ -+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ -+ -+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ -+ -+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ -+ -+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ -+ -+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ -+ -+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -+ -+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ -+ -+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ -+ -+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ -+ -+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ -+ -+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ -+ -+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ -+ -+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ -+ -+/* Debug Set Clear Exception and Monitor Control Register Definitions */ -+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ -+ -+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ -+ -+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ -+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ -+ -+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ -+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ -+ -+/* Debug Authentication Control Register Definitions */ -+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ -+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ -+ -+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ -+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ -+ -+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ -+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ -+ -+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -+ -+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -+ -+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -+ -+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ -+ -+/* Debug Security Control and Status Register Definitions */ -+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -+ -+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -+ -+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ -+ -+/*@} end of group CMSIS_CoreDebug */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_DCB Debug Control Block -+ \brief Type definitions for the Debug Control Block Registers -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Debug Control Block Registers (DCB). -+ */ -+typedef struct -+{ -+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ -+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ -+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ -+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ -+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ -+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -+} DCB_Type; -+ -+/* DHCSR, Debug Halting Control and Status Register Definitions */ -+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ -+ -+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ -+ -+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ -+ -+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ -+ -+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ -+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ -+ -+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ -+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ -+ -+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ -+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ -+ -+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ -+ -+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ -+ -+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ -+ -+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ -+ -+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ -+ -+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ -+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ -+ -+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ -+ -+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ -+ -+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ -+ -+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ -+ -+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ -+ -+/* DCRSR, Debug Core Register Select Register Definitions */ -+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ -+ -+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ -+ -+/* DCRDR, Debug Core Register Data Register Definitions */ -+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ -+ -+/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ -+ -+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ -+ -+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ -+ -+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ -+ -+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ -+ -+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ -+ -+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ -+ -+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ -+ -+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ -+ -+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ -+ -+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ -+ -+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ -+ -+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ -+ -+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ -+ -+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ -+ -+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ -+ -+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ -+ -+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ -+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ -+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ -+ -+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ -+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ -+ -+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ -+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ -+ -+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ -+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ -+ -+/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ -+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ -+ -+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ -+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ -+ -+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ -+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ -+ -+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ -+ -+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ -+ -+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ -+ -+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ -+ -+/* DSCSR, Debug Security Control and Status Register Definitions */ -+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ -+ -+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ -+ -+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ -+ -+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ -+ -+/*@} end of group CMSIS_DCB */ -+ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_DIB Debug Identification Block -+ \brief Type definitions for the Debug Identification Block Registers -+ @{ -+ */ -+ -+/** -+ \brief Structure type to access the Debug Identification Block Registers (DIB). -+ */ -+typedef struct -+{ -+ uint32_t RESERVED0[2U]; -+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ -+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ -+ uint32_t RESERVED1[3U]; -+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ -+} DIB_Type; -+ -+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ -+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ -+ -+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ -+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ -+ -+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ -+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ -+ -+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ -+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ -+ -+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ -+ -+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ -+ -+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ -+ -+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ -+ -+/* DDEVARCH, SCS Device Architecture Register Definitions */ -+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ -+ -+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ -+ -+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ -+ -+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ -+ -+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ -+ -+/* DDEVTYPE, SCS Device Type Register Definitions */ -+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ -+ -+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ -+ -+ -+/*@} end of group CMSIS_DIB */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_core_bitfield Core register bit field macros -+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). -+ @{ -+ */ -+ -+/** -+ \brief Mask and shift a bit field value for use in a register bit range. -+ \param[in] field Name of the register bit field. -+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. -+ \return Masked and shifted value. -+*/ -+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) -+ -+/** -+ \brief Mask and shift a register value to extract a bit filed value. -+ \param[in] field Name of the register bit field. -+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type. -+ \return Masked and shifted bit field value. -+*/ -+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) -+ -+/*@} end of group CMSIS_core_bitfield */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_core_base Core Definitions -+ \brief Definitions for base addresses, unions, and structures. -+ @{ -+ */ -+ -+/* Memory mapping of Core Hardware */ -+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -+ #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ -+ #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ -+ #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ -+ #define EWIC_ISA_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller interrupt status access Base Address */ -+ #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ -+ #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ -+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -+ #define EWIC_BASE (0xE0047000UL) /*!< External Wakeup Interrupt Controller Base Address */ -+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ -+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ -+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ -+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ -+ -+ #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -+ #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ -+ #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ -+ #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ -+ #define EWIC_ISA ((EWIC_ISA_Type *) EWIC_ISA_BASE ) /*!< EWIC interrupt status access struct */ -+ #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ -+ #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ -+ #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ -+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ -+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ -+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ -+ -+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -+ #endif -+ -+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ -+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ -+ #endif -+ -+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ -+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ -+ #endif -+ -+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ -+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ -+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ -+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ -+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ -+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ -+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ -+ -+ #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ -+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ -+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ -+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ -+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ -+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ -+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ -+ -+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ -+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ -+ #endif -+ -+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ -+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ -+ -+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -+/*@} */ -+ -+ -+/** -+ \ingroup CMSIS_core_register -+ \defgroup CMSIS_register_aliases Backwards Compatibility Aliases -+ \brief Register alias definitions for backwards compatibility. -+ @{ -+ */ -+#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -+ -+/* 'SCnSCB' is deprecated and replaced by 'ICB' */ -+typedef ICB_Type SCnSCB_Type; -+ -+/* Auxiliary Control Register Definitions */ -+#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) -+#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) -+ -+#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) -+#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) -+ -+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) -+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) -+ -+#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) -+#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) -+ -+#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) -+#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) -+ -+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) -+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) -+ -+#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) -+#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) -+ -+#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) -+#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) -+ -+#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) -+#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) -+ -+#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) -+#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) -+ -+#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) -+#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) -+ -+#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) -+#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) -+ -+#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) -+#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) -+ -+#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) -+#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) -+ -+/* Interrupt Controller Type Register Definitions */ -+#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) -+#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) -+ -+#define SCnSCB (ICB) -+#define SCnSCB_NS (ICB_NS) -+ -+/*@} */ -+ -+ -+/******************************************************************************* -+ * Hardware Abstraction Layer -+ Core Function Interface contains: -+ - Core NVIC Functions -+ - Core SysTick Functions -+ - Core Debug Functions -+ - Core Register Access Functions -+ ******************************************************************************/ -+/** -+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -+*/ -+ -+ -+ -+/* ########################## NVIC functions #################################### */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions -+ \brief Functions that manage interrupts and exceptions via the NVIC. -+ @{ -+ */ -+ -+#ifdef CMSIS_NVIC_VIRTUAL -+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE -+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" -+ #endif -+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -+#else -+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping -+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping -+ #define NVIC_EnableIRQ __NVIC_EnableIRQ -+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ -+ #define NVIC_DisableIRQ __NVIC_DisableIRQ -+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ -+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ -+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -+ #define NVIC_GetActive __NVIC_GetActive -+ #define NVIC_SetPriority __NVIC_SetPriority -+ #define NVIC_GetPriority __NVIC_GetPriority -+ #define NVIC_SystemReset __NVIC_SystemReset -+#endif /* CMSIS_NVIC_VIRTUAL */ -+ -+#ifdef CMSIS_VECTAB_VIRTUAL -+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE -+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" -+ #endif -+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -+#else -+ #define NVIC_SetVector __NVIC_SetVector -+ #define NVIC_GetVector __NVIC_GetVector -+#endif /* (CMSIS_VECTAB_VIRTUAL) */ -+ -+#define NVIC_USER_IRQ_OFFSET 16 -+ -+ -+/* Special LR values for Secure/Non-Secure call handling and exception handling */ -+ -+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ -+ -+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ -+ -+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -+#else -+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -+#endif -+ -+ -+/** -+ \brief Set Priority Grouping -+ \details Sets the priority grouping field using the required unlock sequence. -+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. -+ Only values from 0..7 are used. -+ In case of a conflict between priority grouping and available -+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. -+ \param [in] PriorityGroup Priority grouping field. -+ */ -+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -+{ -+ uint32_t reg_value; -+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ -+ -+ reg_value = SCB->AIRCR; /* read old register configuration */ -+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ -+ reg_value = (reg_value | -+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | -+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ -+ SCB->AIRCR = reg_value; -+} -+ -+ -+/** -+ \brief Get Priority Grouping -+ \details Reads the priority grouping field from the NVIC Interrupt Controller. -+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). -+ */ -+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -+{ -+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -+} -+ -+ -+/** -+ \brief Enable Interrupt -+ \details Enables a device specific interrupt in the NVIC interrupt controller. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ __COMPILER_BARRIER(); -+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ __COMPILER_BARRIER(); -+ } -+} -+ -+ -+/** -+ \brief Get Interrupt Enable status -+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 Interrupt is not enabled. -+ \return 1 Interrupt is enabled. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+/** -+ \brief Disable Interrupt -+ \details Disables a device specific interrupt in the NVIC interrupt controller. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ __DSB(); -+ __ISB(); -+ } -+} -+ -+ -+/** -+ \brief Get Pending Interrupt -+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 Interrupt status is not pending. -+ \return 1 Interrupt status is pending. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+/** -+ \brief Set Pending Interrupt -+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ } -+} -+ -+ -+/** -+ \brief Clear Pending Interrupt -+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ } -+} -+ -+ -+/** -+ \brief Get Active Interrupt -+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 Interrupt status is not active. -+ \return 1 Interrupt status is active. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+/** -+ \brief Get Interrupt Target State -+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 if interrupt is assigned to Secure -+ \return 1 if interrupt is assigned to Non Secure -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+/** -+ \brief Set Interrupt Target State -+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 if interrupt is assigned to Secure -+ 1 if interrupt is assigned to Non Secure -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); -+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+/** -+ \brief Clear Interrupt Target State -+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 if interrupt is assigned to Secure -+ 1 if interrupt is assigned to Non Secure -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); -+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -+ -+ -+/** -+ \brief Set Interrupt Priority -+ \details Sets the priority of a device specific interrupt or a processor exception. -+ The interrupt number can be positive to specify a device specific interrupt, -+ or negative to specify a processor exception. -+ \param [in] IRQn Interrupt number. -+ \param [in] priority Priority to set. -+ \note The priority cannot be set for every processor exception. -+ */ -+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); -+ } -+ else -+ { -+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); -+ } -+} -+ -+ -+/** -+ \brief Get Interrupt Priority -+ \details Reads the priority of a device specific interrupt or a processor exception. -+ The interrupt number can be positive to specify a device specific interrupt, -+ or negative to specify a processor exception. -+ \param [in] IRQn Interrupt number. -+ \return Interrupt Priority. -+ Value is aligned automatically to the implemented priority bits of the microcontroller. -+ */ -+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -+{ -+ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); -+ } -+ else -+ { -+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); -+ } -+} -+ -+ -+/** -+ \brief Encode Priority -+ \details Encodes the priority for an interrupt with the given priority group, -+ preemptive priority value, and subpriority value. -+ In case of a conflict between priority grouping and available -+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. -+ \param [in] PriorityGroup Used priority group. -+ \param [in] PreemptPriority Preemptive priority value (starting from 0). -+ \param [in] SubPriority Subpriority value (starting from 0). -+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). -+ */ -+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -+{ -+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ -+ uint32_t PreemptPriorityBits; -+ uint32_t SubPriorityBits; -+ -+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); -+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); -+ -+ return ( -+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | -+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) -+ ); -+} -+ -+ -+/** -+ \brief Decode Priority -+ \details Decodes an interrupt priority value with a given priority group to -+ preemptive priority value and subpriority value. -+ In case of a conflict between priority grouping and available -+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. -+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). -+ \param [in] PriorityGroup Used priority group. -+ \param [out] pPreemptPriority Preemptive priority value (starting from 0). -+ \param [out] pSubPriority Subpriority value (starting from 0). -+ */ -+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -+{ -+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ -+ uint32_t PreemptPriorityBits; -+ uint32_t SubPriorityBits; -+ -+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); -+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); -+ -+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); -+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -+} -+ -+ -+/** -+ \brief Set Interrupt Vector -+ \details Sets an interrupt vector in SRAM based interrupt vector table. -+ The interrupt number can be positive to specify a device specific interrupt, -+ or negative to specify a processor exception. -+ VTOR must been relocated to SRAM before. -+ \param [in] IRQn Interrupt number -+ \param [in] vector Address of interrupt handler function -+ */ -+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -+{ -+ uint32_t *vectors = (uint32_t *)SCB->VTOR; -+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -+ __DSB(); -+} -+ -+ -+/** -+ \brief Get Interrupt Vector -+ \details Reads an interrupt vector from interrupt vector table. -+ The interrupt number can be positive to specify a device specific interrupt, -+ or negative to specify a processor exception. -+ \param [in] IRQn Interrupt number. -+ \return Address of interrupt handler function -+ */ -+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -+{ -+ uint32_t *vectors = (uint32_t *)SCB->VTOR; -+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -+} -+ -+ -+/** -+ \brief System Reset -+ \details Initiates a system reset request to reset the MCU. -+ */ -+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -+{ -+ __DSB(); /* Ensure all outstanding memory accesses included -+ buffered write are completed before reset */ -+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | -+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | -+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ -+ __DSB(); /* Ensure completion of memory access */ -+ -+ for(;;) /* wait until reset */ -+ { -+ __NOP(); -+ } -+} -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+/** -+ \brief Set Priority Grouping (non-secure) -+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. -+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. -+ Only values from 0..7 are used. -+ In case of a conflict between priority grouping and available -+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. -+ \param [in] PriorityGroup Priority grouping field. -+ */ -+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -+{ -+ uint32_t reg_value; -+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ -+ -+ reg_value = SCB_NS->AIRCR; /* read old register configuration */ -+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ -+ reg_value = (reg_value | -+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | -+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ -+ SCB_NS->AIRCR = reg_value; -+} -+ -+ -+/** -+ \brief Get Priority Grouping (non-secure) -+ \details Reads the priority grouping field from the non-secure NVIC when in secure state. -+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). -+ */ -+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -+{ -+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -+} -+ -+ -+/** -+ \brief Enable Interrupt (non-secure) -+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ } -+} -+ -+ -+/** -+ \brief Get Interrupt Enable status (non-secure) -+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 Interrupt is not enabled. -+ \return 1 Interrupt is enabled. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+/** -+ \brief Disable Interrupt (non-secure) -+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ } -+} -+ -+ -+/** -+ \brief Get Pending Interrupt (non-secure) -+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 Interrupt status is not pending. -+ \return 1 Interrupt status is pending. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+/** -+ \brief Set Pending Interrupt (non-secure) -+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ } -+} -+ -+ -+/** -+ \brief Clear Pending Interrupt (non-secure) -+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. -+ \param [in] IRQn Device specific interrupt number. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); -+ } -+} -+ -+ -+/** -+ \brief Get Active Interrupt (non-secure) -+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. -+ \param [in] IRQn Device specific interrupt number. -+ \return 0 Interrupt status is not active. -+ \return 1 Interrupt status is active. -+ \note IRQn must not be negative. -+ */ -+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -+ } -+ else -+ { -+ return(0U); -+ } -+} -+ -+ -+/** -+ \brief Set Interrupt Priority (non-secure) -+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. -+ The interrupt number can be positive to specify a device specific interrupt, -+ or negative to specify a processor exception. -+ \param [in] IRQn Interrupt number. -+ \param [in] priority Priority to set. -+ \note The priority cannot be set for every non-secure processor exception. -+ */ -+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -+{ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); -+ } -+ else -+ { -+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); -+ } -+} -+ -+ -+/** -+ \brief Get Interrupt Priority (non-secure) -+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. -+ The interrupt number can be positive to specify a device specific interrupt, -+ or negative to specify a processor exception. -+ \param [in] IRQn Interrupt number. -+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. -+ */ -+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -+{ -+ -+ if ((int32_t)(IRQn) >= 0) -+ { -+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); -+ } -+ else -+ { -+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); -+ } -+} -+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ -+ -+/*@} end of CMSIS_Core_NVICFunctions */ -+ -+/* ########################## MPU functions #################################### */ -+ -+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -+ -+#include "mpu_armv8.h" -+ -+#endif -+ -+/* ########################## PMU functions and events #################################### */ -+ -+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -+ -+#include "pmu_armv8.h" -+ -+/** -+ \brief Cortex-M55 PMU events -+ \note Architectural PMU events can be found in pmu_armv8.h -+*/ -+ -+#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ -+#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ -+#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ -+#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ -+#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ -+#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ -+#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ -+#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ -+#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ -+#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ -+#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ -+#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ -+#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ -+#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ -+#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ -+#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ -+#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ -+#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ -+#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ -+#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ -+#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ -+#define ARMCM55_PMU_CDE_INST_RETIRED 0xC402 /*!< CDE instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_CX1_INST_RETIRED 0xC404 /*!< CDE CX1 instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_CX2_INST_RETIRED 0xC406 /*!< CDE CX2 instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_CX3_INST_RETIRED 0xC408 /*!< CDE CX3 instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_VCX1_INST_RETIRED 0xC40A /*!< CDE VCX1 instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_VCX2_INST_RETIRED 0xC40C /*!< CDE VCX2 instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_VCX3_INST_RETIRED 0xC40E /*!< CDE VCX3 instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_VCX1_VEC_INST_RETIRED 0xC410 /*!< CDE VCX1 Vector instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_VCX2_VEC_INST_RETIRED 0xC412 /*!< CDE VCX2 Vector instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_VCX3_VEC_INST_RETIRED 0xC414 /*!< CDE VCX3 Vector instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_PRED 0xC416 /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */ -+#define ARMCM55_PMU_CDE_STALL 0xC417 /*!< Stall cycles caused by a CDE instruction. */ -+#define ARMCM55_PMU_CDE_STALL_RESOURCE 0xC418 /*!< Stall cycles caused by a CDE instruction because of resource conflicts */ -+#define ARMCM55_PMU_CDE_STALL_DEPENDENCY 0xC419 /*!< Stall cycles caused by a CDE register dependency. */ -+#define ARMCM55_PMU_CDE_STALL_CUSTOM 0xC41A /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */ -+#define ARMCM55_PMU_CDE_STALL_OTHER 0xC41B /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */ -+#define ARMCM55_PMU_PF_LF_LA_1 0xC41C /*!< A data prefetcher line-fill request is made while the lookahead distance is 1. */ -+#define ARMCM55_PMU_PF_LF_LA_2 0xC41D /*!< A data prefetcher line-fill request is made while the lookahead distance is 2. */ -+#define ARMCM55_PMU_PF_LF_LA_3 0xC41E /*!< A data prefetcher line-fill request is made while the lookahead distance is 3. */ -+#define ARMCM55_PMU_PF_LF_LA_4 0xC41F /*!< A data prefetcher line-fill request is made while the lookahead distance is 4. */ -+#define ARMCM55_PMU_PF_LF_LA_5 0xC420 /*!< A data prefetcher line-fill request is made while the lookahead distance is 5. */ -+#define ARMCM55_PMU_PF_LF_LA_6 0xC421 /*!< A data prefetcher line-fill request is made while the lookahead distance is 6. */ -+#define ARMCM55_PMU_PF_BUFFER_FULL 0xC422 /*!< A data prefetcher request is made while the buffer is full. */ -+#define ARMCM55_PMU_PF_BUFFER_MISS 0xC423 /*!< A load requires a line-fill which misses in the data prefetcher buffer. */ -+#define ARMCM55_PMU_PF_BUFFER_HIT 0xC424 /*!< A load access hits in the data prefetcher buffer. */ -+ -+#endif -+ -+/* ########################## FPU functions #################################### */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_FpuFunctions FPU Functions -+ \brief Function that provides FPU type. -+ @{ -+ */ -+ -+/** -+ \brief get FPU type -+ \details returns the FPU type -+ \returns -+ - \b 0: No FPU -+ - \b 1: Single precision FPU -+ - \b 2: Double + Single precision FPU -+ */ -+__STATIC_INLINE uint32_t SCB_GetFPUType(void) -+{ -+ uint32_t mvfr0; -+ -+ mvfr0 = FPU->MVFR0; -+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) -+ { -+ return 2U; /* Double + Single precision FPU */ -+ } -+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) -+ { -+ return 1U; /* Single precision FPU */ -+ } -+ else -+ { -+ return 0U; /* No FPU */ -+ } -+} -+ -+ -+/*@} end of CMSIS_Core_FpuFunctions */ -+ -+/* ########################## MVE functions #################################### */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_MveFunctions MVE Functions -+ \brief Function that provides MVE type. -+ @{ -+ */ -+ -+/** -+ \brief get MVE type -+ \details returns the MVE type -+ \returns -+ - \b 0: No Vector Extension (MVE) -+ - \b 1: Integer Vector Extension (MVE-I) -+ - \b 2: Floating-point Vector Extension (MVE-F) -+ */ -+__STATIC_INLINE uint32_t SCB_GetMVEType(void) -+{ -+ const uint32_t mvfr1 = FPU->MVFR1; -+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) -+ { -+ return 2U; -+ } -+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) -+ { -+ return 1U; -+ } -+ else -+ { -+ return 0U; -+ } -+} -+ -+ -+/*@} end of CMSIS_Core_MveFunctions */ -+ -+ -+/* ########################## Cache functions #################################### */ -+ -+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ -+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -+#include "cachel1_armv7.h" -+#endif -+ -+ -+/* ########################## SAU functions #################################### */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_SAUFunctions SAU Functions -+ \brief Functions that configure the SAU. -+ @{ -+ */ -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+ -+/** -+ \brief Enable SAU -+ \details Enables the Security Attribution Unit (SAU). -+ */ -+__STATIC_INLINE void TZ_SAU_Enable(void) -+{ -+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -+} -+ -+ -+ -+/** -+ \brief Disable SAU -+ \details Disables the Security Attribution Unit (SAU). -+ */ -+__STATIC_INLINE void TZ_SAU_Disable(void) -+{ -+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -+} -+ -+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -+ -+/*@} end of CMSIS_Core_SAUFunctions */ -+ -+ -+ -+ -+/* ################################## Debug Control function ############################################ */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions -+ \brief Functions that access the Debug Control Block. -+ @{ -+ */ -+ -+ -+/** -+ \brief Set Debug Authentication Control Register -+ \details writes to Debug Authentication Control register. -+ \param [in] value value to be writen. -+ */ -+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -+{ -+ __DSB(); -+ __ISB(); -+ DCB->DAUTHCTRL = value; -+ __DSB(); -+ __ISB(); -+} -+ -+ -+/** -+ \brief Get Debug Authentication Control Register -+ \details Reads Debug Authentication Control register. -+ \return Debug Authentication Control Register. -+ */ -+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -+{ -+ return (DCB->DAUTHCTRL); -+} -+ -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+/** -+ \brief Set Debug Authentication Control Register (non-secure) -+ \details writes to non-secure Debug Authentication Control register when in secure state. -+ \param [in] value value to be writen -+ */ -+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -+{ -+ __DSB(); -+ __ISB(); -+ DCB_NS->DAUTHCTRL = value; -+ __DSB(); -+ __ISB(); -+} -+ -+ -+/** -+ \brief Get Debug Authentication Control Register (non-secure) -+ \details Reads non-secure Debug Authentication Control register when in secure state. -+ \return Debug Authentication Control Register. -+ */ -+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -+{ -+ return (DCB_NS->DAUTHCTRL); -+} -+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -+ -+/*@} end of CMSIS_Core_DCBFunctions */ -+ -+ -+ -+ -+/* ################################## Debug Identification function ############################################ */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions -+ \brief Functions that access the Debug Identification Block. -+ @{ -+ */ -+ -+ -+/** -+ \brief Get Debug Authentication Status Register -+ \details Reads Debug Authentication Status register. -+ \return Debug Authentication Status Register. -+ */ -+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -+{ -+ return (DIB->DAUTHSTATUS); -+} -+ -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+/** -+ \brief Get Debug Authentication Status Register (non-secure) -+ \details Reads non-secure Debug Authentication Status register when in secure state. -+ \return Debug Authentication Status Register. -+ */ -+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -+{ -+ return (DIB_NS->DAUTHSTATUS); -+} -+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -+ -+/*@} end of CMSIS_Core_DCBFunctions */ -+ -+ -+ -+ -+/* ################################## SysTick function ############################################ */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions -+ \brief Functions that configure the System. -+ @{ -+ */ -+ -+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) -+ -+/** -+ \brief System Tick Configuration -+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. -+ Counter is in free running mode to generate periodic interrupts. -+ \param [in] ticks Number of ticks between two interrupts. -+ \return 0 Function succeeded. -+ \return 1 Function failed. -+ \note When the variable __Vendor_SysTickConfig is set to 1, then the -+ function SysTick_Config is not included. In this case, the file device.h -+ must contain a vendor-specific implementation of this function. -+ */ -+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -+{ -+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) -+ { -+ return (1UL); /* Reload value impossible */ -+ } -+ -+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ -+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ -+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ -+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | -+ SysTick_CTRL_TICKINT_Msk | -+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ -+ return (0UL); /* Function successful */ -+} -+ -+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -+/** -+ \brief System Tick Configuration (non-secure) -+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. -+ Counter is in free running mode to generate periodic interrupts. -+ \param [in] ticks Number of ticks between two interrupts. -+ \return 0 Function succeeded. -+ \return 1 Function failed. -+ \note When the variable __Vendor_SysTickConfig is set to 1, then the -+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h -+ must contain a vendor-specific implementation of this function. -+ -+ */ -+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -+{ -+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) -+ { -+ return (1UL); /* Reload value impossible */ -+ } -+ -+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ -+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ -+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ -+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | -+ SysTick_CTRL_TICKINT_Msk | -+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ -+ return (0UL); /* Function successful */ -+} -+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -+ -+#endif -+ -+/*@} end of CMSIS_Core_SysTickFunctions */ -+ -+ -+ -+/* ##################################### Debug In/Output function ########################################### */ -+/** -+ \ingroup CMSIS_Core_FunctionInterface -+ \defgroup CMSIS_core_DebugFunctions ITM Functions -+ \brief Functions that access the ITM debug interface. -+ @{ -+ */ -+ -+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ -+ -+ -+/** -+ \brief ITM Send Character -+ \details Transmits a character via the ITM channel 0, and -+ \li Just returns when no debugger is connected that has booked the output. -+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. -+ \param [in] ch Character to transmit. -+ \returns Character to transmit. -+ */ -+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -+{ -+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ -+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ -+ { -+ while (ITM->PORT[0U].u32 == 0UL) -+ { -+ __NOP(); -+ } -+ ITM->PORT[0U].u8 = (uint8_t)ch; -+ } -+ return (ch); -+} -+ -+ -+/** -+ \brief ITM Receive Character -+ \details Inputs a character via the external variable \ref ITM_RxBuffer. -+ \return Received character. -+ \return -1 No character pending. -+ */ -+__STATIC_INLINE int32_t ITM_ReceiveChar (void) -+{ -+ int32_t ch = -1; /* no character available */ -+ -+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) -+ { -+ ch = ITM_RxBuffer; -+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ -+ } -+ -+ return (ch); -+} -+ -+ -+/** -+ \brief ITM Check Character -+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. -+ \return 0 No character available. -+ \return 1 Character available. -+ */ -+__STATIC_INLINE int32_t ITM_CheckChar (void) -+{ -+ -+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) -+ { -+ return (0); /* no character available */ -+ } -+ else -+ { -+ return (1); /* character available */ -+ } -+} -+ -+/*@} end of CMSIS_core_DebugFunctions */ -+ -+ -+ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __CORE_CM55_H_DEPENDANT */ -+ -+#endif /* __CMSIS_GENERIC */ -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/mpu_armv8.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/mpu_armv8.h -new file mode 100644 -index 0000000..8328621 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/mpu_armv8.h -@@ -0,0 +1,430 @@ -+/* *INDENT-OFF* */ -+ -+/****************************************************************************** -+ * @file mpu_armv8.h -+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU -+ * @version V5.9.0 -+ * @date 11. April 2023 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/mpu_armv8.h -+*/ -+ -+#if defined ( __ICCARM__ ) -+ #pragma system_include /* treat file as system include file for MISRA check */ -+#elif defined (__clang__) -+ #pragma clang system_header /* treat file as system include file */ -+#endif -+ -+#ifndef ARM_MPU_ARMV8_H -+#define ARM_MPU_ARMV8_H -+ -+/** \brief Attribute for device memory (outer only) */ -+#define ARM_MPU_ATTR_DEVICE ( 0U ) -+ -+/** \brief Attribute for non-cacheable, normal memory */ -+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) -+ -+/** \brief Attribute for Normal memory, Outer and Inner cacheability. -+* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. -+* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. -+* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. -+* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. -+*/ -+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ -+ ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) -+ -+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) -+ -+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) -+ -+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -+#define ARM_MPU_ATTR_DEVICE_nGRE (2U) -+ -+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -+#define ARM_MPU_ATTR_DEVICE_GRE (3U) -+ -+/** \brief Normal memory outer-cacheable and inner-cacheable attributes -+* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate -+*/ -+#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) -+#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) -+#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) -+#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) -+#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) -+#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) -+#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) -+#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) -+#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) -+#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) -+#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) -+#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) -+#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) -+#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) -+#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) -+#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) -+#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) -+#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) -+#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) -+#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) -+#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) -+#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) -+#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) -+#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) -+#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) -+#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) -+ -+/** \brief Memory Attribute -+* \param O Outer memory attributes -+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -+*/ -+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) -+ -+/* \brief Specifies MAIR_ATTR number */ -+#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) -+ -+/** -+ * Shareability -+ */ -+/** \brief Normal memory, non-shareable */ -+#define ARM_MPU_SH_NON (0U) -+ -+/** \brief Normal memory, outer shareable */ -+#define ARM_MPU_SH_OUTER (2U) -+ -+/** \brief Normal memory, inner shareable */ -+#define ARM_MPU_SH_INNER (3U) -+ -+/** -+ * Access permissions -+ * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only -+ */ -+/** \brief Normal memory, read/write */ -+#define ARM_MPU_AP_RW (0U) -+ -+/** \brief Normal memory, read-only */ -+#define ARM_MPU_AP_RO (1U) -+ -+/** \brief Normal memory, any privilege level */ -+#define ARM_MPU_AP_NP (1U) -+ -+/** \brief Normal memory, privileged access only */ -+#define ARM_MPU_AP_PO (0U) -+ -+/* -+ * Execute-never -+ * XN = Execute-never, EX = Executable -+ */ -+/** \brief Normal memory, Execution only permitted if read permitted */ -+#define ARM_MPU_XN (1U) -+ -+/** \brief Normal memory, Execution only permitted if read permitted */ -+#define ARM_MPU_EX (0U) -+ -+/** \brief Memory access permissions -+* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. -+* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. -+*/ -+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) -+ -+/** \brief Region Base Address Register value -+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -+* \param SH Defines the Shareability domain for this memory region. -+* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. -+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. -+* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. -+*/ -+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ -+ (((BASE) & MPU_RBAR_BASE_Msk) | \ -+ (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ -+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ -+ (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) -+ -+/** \brief Region Limit Address Register value -+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -+* \param IDX The attribute index to be associated with this memory region. -+*/ -+#define ARM_MPU_RLAR(LIMIT, IDX) \ -+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ -+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ -+ (MPU_RLAR_EN_Msk)) -+ -+#if defined(MPU_RLAR_PXN_Pos) -+ -+/** \brief Region Limit Address Register with PXN value -+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -+* \param IDX The attribute index to be associated with this memory region. -+*/ -+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ -+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ -+ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ -+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ -+ (MPU_RLAR_EN_Msk)) -+ -+#endif -+ -+/** -+* Struct for a single MPU Region -+*/ -+typedef struct { -+ uint32_t RBAR; /*!< Region Base Address Register value */ -+ uint32_t RLAR; /*!< Region Limit Address Register value */ -+} ARM_MPU_Region_t; -+ -+/** -+ \brief Read MPU Type Register -+ \return Number of MPU regions -+*/ -+__STATIC_INLINE uint32_t ARM_MPU_TYPE() -+{ -+ return ((MPU->TYPE) >> 8); -+} -+ -+/** Enable the MPU. -+* \param MPU_Control Default access permissions for unconfigured regions. -+*/ -+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -+{ -+ __DMB(); -+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -+#ifdef SCB_SHCSR_MEMFAULTENA_Msk -+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -+#endif -+ __DSB(); -+ __ISB(); -+} -+ -+/** Disable the MPU. -+*/ -+__STATIC_INLINE void ARM_MPU_Disable(void) -+{ -+ __DMB(); -+#ifdef SCB_SHCSR_MEMFAULTENA_Msk -+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -+#endif -+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -+ __DSB(); -+ __ISB(); -+} -+ -+#ifdef MPU_NS -+/** Enable the Non-secure MPU. -+* \param MPU_Control Default access permissions for unconfigured regions. -+*/ -+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -+{ -+ __DMB(); -+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -+#ifdef SCB_SHCSR_MEMFAULTENA_Msk -+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -+#endif -+ __DSB(); -+ __ISB(); -+} -+ -+/** Disable the Non-secure MPU. -+*/ -+__STATIC_INLINE void ARM_MPU_Disable_NS(void) -+{ -+ __DMB(); -+#ifdef SCB_SHCSR_MEMFAULTENA_Msk -+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -+#endif -+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; -+ __DSB(); -+ __ISB(); -+} -+#endif -+ -+/** Set the memory attribute encoding to the given MPU. -+* \param mpu Pointer to the MPU to be configured. -+* \param idx The attribute index to be set [0-7] -+* \param attr The attribute value to be set. -+*/ -+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -+{ -+ const uint8_t reg = idx / 4U; -+ const uint32_t pos = ((idx % 4U) * 8U); -+ const uint32_t mask = 0xFFU << pos; -+ -+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { -+ return; // invalid index -+ } -+ -+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -+} -+ -+/** Set the memory attribute encoding. -+* \param idx The attribute index to be set [0-7] -+* \param attr The attribute value to be set. -+*/ -+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -+{ -+ ARM_MPU_SetMemAttrEx(MPU, idx, attr); -+} -+ -+#ifdef MPU_NS -+/** Set the memory attribute encoding to the Non-secure MPU. -+* \param idx The attribute index to be set [0-7] -+* \param attr The attribute value to be set. -+*/ -+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -+{ -+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -+} -+#endif -+ -+/** Clear and disable the given MPU region of the given MPU. -+* \param mpu Pointer to MPU to be used. -+* \param rnr Region number to be cleared. -+*/ -+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -+{ -+ mpu->RNR = rnr; -+ mpu->RLAR = 0U; -+} -+ -+/** Clear and disable the given MPU region. -+* \param rnr Region number to be cleared. -+*/ -+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -+{ -+ ARM_MPU_ClrRegionEx(MPU, rnr); -+} -+ -+#ifdef MPU_NS -+/** Clear and disable the given Non-secure MPU region. -+* \param rnr Region number to be cleared. -+*/ -+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -+{ -+ ARM_MPU_ClrRegionEx(MPU_NS, rnr); -+} -+#endif -+ -+/** Configure the given MPU region of the given MPU. -+* \param mpu Pointer to MPU to be used. -+* \param rnr Region number to be configured. -+* \param rbar Value for RBAR register. -+* \param rlar Value for RLAR register. -+*/ -+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -+{ -+ mpu->RNR = rnr; -+ mpu->RBAR = rbar; -+ mpu->RLAR = rlar; -+} -+ -+/** Configure the given MPU region. -+* \param rnr Region number to be configured. -+* \param rbar Value for RBAR register. -+* \param rlar Value for RLAR register. -+*/ -+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -+{ -+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -+} -+ -+#ifdef MPU_NS -+/** Configure the given Non-secure MPU region. -+* \param rnr Region number to be configured. -+* \param rbar Value for RBAR register. -+* \param rlar Value for RLAR register. -+*/ -+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -+{ -+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -+} -+#endif -+ -+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -+* \param dst Destination data is copied to. -+* \param src Source data is copied from. -+* \param len Amount of data words to be copied. -+*/ -+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -+{ -+ uint32_t i; -+ for (i = 0U; i < len; ++i) -+ { -+ dst[i] = src[i]; -+ } -+} -+ -+/** Load the given number of MPU regions from a table to the given MPU. -+* \param mpu Pointer to the MPU registers to be used. -+* \param rnr First region number to be configured. -+* \param table Pointer to the MPU configuration table. -+* \param cnt Amount of regions to be configured. -+*/ -+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -+{ -+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; -+ if (cnt == 1U) { -+ mpu->RNR = rnr; -+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); -+ } else { -+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); -+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; -+ -+ mpu->RNR = rnrBase; -+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { -+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset; -+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); -+ table += c; -+ cnt -= c; -+ rnrOffset = 0U; -+ rnrBase += MPU_TYPE_RALIASES; -+ mpu->RNR = rnrBase; -+ } -+ -+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); -+ } -+} -+ -+/** Load the given number of MPU regions from a table. -+* \param rnr First region number to be configured. -+* \param table Pointer to the MPU configuration table. -+* \param cnt Amount of regions to be configured. -+*/ -+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -+{ -+ ARM_MPU_LoadEx(MPU, rnr, table, cnt); -+} -+ -+#ifdef MPU_NS -+/** Load the given number of MPU regions from a table to the Non-secure MPU. -+* \param rnr First region number to be configured. -+* \param table Pointer to the MPU configuration table. -+* \param cnt Amount of regions to be configured. -+*/ -+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -+{ -+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -+} -+#endif -+ -+#endif -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_base_address.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_base_address.h -new file mode 100644 -index 0000000..750f4c4 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_base_address.h -@@ -0,0 +1,303 @@ -+/* -+ * Copyright (c) 2024 Arm Limited -+ * -+ * Licensed under the Apache License Version 2.0 (the "License"); -+ * you may not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * http://www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing software -+ * distributed under the License is distributed on an "AS IS" BASIS -+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/** -+ * \file platform_base_address.h -+ * \brief This file defines all the peripheral base addresses for Corstone-315. -+ */ -+ -+#ifndef __PLATFORM_BASE_ADDRESS_H__ -+#define __PLATFORM_BASE_ADDRESS_H__ -+ -+/* ======= Defines peripherals memory map addresses ======= */ -+/* Non-secure memory map addresses */ -+#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ -+#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ -+#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ -+#define DTCM1_BASE_NS 0x20002000 /* Data TCM block 1 Non-Secure base address */ -+#define DTCM2_BASE_NS 0x20004000 /* Data TCM block 2 Non-Secure base address */ -+#define DTCM3_BASE_NS 0x20006000 /* Data TCM block 3 Non-Secure base address */ -+#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -+#define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */ -+#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ -+/* Non-Secure Subsystem peripheral region */ -+#define DMA_350_BASE_NS 0x40002000 /* DMA350 register block Non-Secure base address */ -+ -+#define NPU0_APB_BASE_NS 0x40004000 /* NPU0 APB Non-Secure base address */ -+#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ -+#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ -+#define CORSTONE315_NSACFG_BASE_NS 0x40080000 /* Corstone-315 Non-Secure Access Configuration Register Block Non-Secure base address */ -+/* Non-Secure MSTEXPPILL Peripheral region */ -+#define GPIO0_CMSDK_BASE_NS 0x40100000 /* GPIO 0 Non-Secure base address */ -+#define GPIO1_CMSDK_BASE_NS 0x40101000 /* GPIO 1 Non-Secure base address */ -+#define GPIO2_CMSDK_BASE_NS 0x40102000 /* GPIO 2 Non-Secure base address */ -+#define GPIO3_CMSDK_BASE_NS 0x40103000 /* GPIO 3 Non-Secure base address */ -+#define AHB_USER_0_BASE_NS 0x40104000 /* AHB USER 0 Non-Secure base address */ -+#define AHB_USER_1_BASE_NS 0x40105000 /* AHB USER 1 Non-Secure base address */ -+#define AHB_USER_2_BASE_NS 0x40106000 /* AHB USER 2 Non-Secure base address */ -+#define AHB_USER_3_BASE_NS 0x40107000 /* AHB USER 3 Non-Secure base address */ -+#define HDLCD_BASE_NS 0x40310000 /* HDLCD Non-Secure base address */ -+#define ETHERNET_BASE_NS 0x40400000 /* Ethernet Non-Secure base address */ -+#define USB_BASE_NS 0x40500000 /* USB Non-Secure base address */ -+#define USER_APB0_BASE_NS 0x40700000 /* User APB 0 Non-Secure base address */ -+#define USER_APB1_BASE_NS 0x40701000 /* User APB 1 Non-Secure base address */ -+#define USER_APB2_BASE_NS 0x40702000 /* User APB 2 Non-Secure base address */ -+#define USER_APB3_BASE_NS 0x40703000 /* User APB 3 Non-Secure base address */ -+#define QSPI_CONFIG_BASE_NS 0x40800000 /* QSPI Config Non-Secure base address */ -+#define QSPI_WRITE_BASE_NS 0x40801000 /* QSPI Write Non-Secure base address */ -+/* Non-Secure Subsystem peripheral region */ -+#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ -+#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ -+#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ -+#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ -+#define CORSTONE315_SYSINFO_BASE_NS 0x48020000 /* Corstone-315 System info Block Non-Secure base address */ -+#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ -+#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ -+#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ -+#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ -+/* Non-Secure MSTEXPPIHL Peripheral region */ -+#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x48100000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ -+#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x48101000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ -+#define FPGA_SPI_ADC_BASE_NS 0x48102000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ -+#define FPGA_SPI_SHIELD0_BASE_NS 0x48103000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ -+#define FPGA_SPI_SHIELD1_BASE_NS 0x48104000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ -+#define SBCon_I2C_SHIELD0_BASE_NS 0x48105000 /* SBCon (I2C - Shield0) Non-Secure base address */ -+#define SBCon_I2C_SHIELD1_BASE_NS 0x48106000 /* SBCon (I2C – Shield1) Non-Secure base address */ -+#define USER_APB_BASE_NS 0x48107000 /* USER APB Non-Secure base address */ -+#define FPGA_DDR4_EEPROM_BASE_NS 0x48108000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ -+#define FPGA_SCC_BASE_NS 0x48200000 /* FPGA - SCC registers Non-Secure base address */ -+#define FPGA_I2S_BASE_NS 0x48201000 /* FPGA - I2S (Audio) Non-Secure base address */ -+#define FPGA_IO_BASE_NS 0x48202000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ -+#define UART0_BASE_NS 0x48203000 /* UART 0 Non-Secure base address */ -+#define UART1_BASE_NS 0x48204000 /* UART 1 Non-Secure base address */ -+#define UART2_BASE_NS 0x48205000 /* UART 2 Non-Secure base address */ -+#define UART3_BASE_NS 0x48206000 /* UART 3 Non-Secure base address */ -+#define UART4_BASE_NS 0x48207000 /* UART 4 Non-Secure base address */ -+#define UART5_BASE_NS 0x48208000 /* UART 5 Non-Secure base address */ -+#define RTC_BASE_NS 0x4820B000 /* RTC Non-Secure base address */ -+#define ISP_BASE_NS 0x48300000 /* ISP SOC base address */ -+#define ISP_VIRTUAL_CAMERA_BASE_NS 0x48400000 /* ISP Virtual Camera base address */ -+ -+#define VSOCKET_BASE_NS 0x4FEE0000 /*!< VSOCKET Non-Secure base address */ -+#define VIO_BASE_NS 0x4FEF0000 /*!< VIO Non-Secure base address */ -+#define VSI0_BASE_NS 0x4FF00000 /*!< VSI 0 Non-Secure base address */ -+#define VSI1_BASE_NS 0x4FF10000 /*!< VSI 1 Non-Secure base address */ -+#define VSI2_BASE_NS 0x4FF20000 /*!< VSI 2 Non-Secure base address */ -+#define VSI3_BASE_NS 0x4FF30000 /*!< VSI 3 Non-Secure base address */ -+#define VSI4_BASE_NS 0x4FF40000 /*!< VSI 4 Non-Secure base address */ -+#define VSI5_BASE_NS 0x4FF50000 /*!< VSI 5 Non-Secure base address */ -+#define VSI6_BASE_NS 0x4FF60000 /*!< VSI 6 Non-Secure base address */ -+#define VSI7_BASE_NS 0x4FF70000 /*!< VSI 7 Non-Secure base address */ -+ -+#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ -+#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ -+#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ -+#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ -+ -+/* Secure memory map addresses */ -+#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ -+#define BOOT_ROM_BASE_S 0x11000000 /* Boot ROM Secure base address */ -+#define SRAM_BASE_S 0x12000000 /* CODE SRAM Secure base address */ -+#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ -+#define DTCM1_BASE_S 0x30002000 /* Data TCM block 1 Secure base address */ -+#define DTCM2_BASE_S 0x30004000 /* Data TCM block 2 Secure base address */ -+#define DTCM3_BASE_S 0x30006000 /* Data TCM block 3 Secure base address */ -+#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -+#define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */ -+#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ -+/* Secure Subsystem peripheral region */ -+#define DMA_350_BASE_S 0x50002000 /* DMA350 register block Secure base address */ -+#define NPU0_APB_BASE_S 0x50004000 /* NPU0 APB Secure base address */ -+#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ -+#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ -+#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ -+#define CORSTONE315_SACFG_BASE_S 0x50080000 /* Corstone-315 Secure Access Configuration Register Secure base address */ -+#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ -+#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ -+#define CC3XX_BASE_S 0x50094000 /* CryptoCell CC3XX Secure base address */ -+#define KMU_BASE_S 0x5009E000 /* KMU Secure base address */ -+#define LCM_BASE_S 0x500A0000 /* LCM Secure base address */ -+ -+/* Secure MSTEXPPILL Peripheral region */ -+#define GPIO0_CMSDK_BASE_S 0x50100000 /* GPIO 0 Secure base address */ -+#define GPIO1_CMSDK_BASE_S 0x50101000 /* GPIO 1 Secure base address */ -+#define GPIO2_CMSDK_BASE_S 0x50102000 /* GPIO 2 Secure base address */ -+#define GPIO3_CMSDK_BASE_S 0x50103000 /* GPIO 3 Secure base address */ -+#define AHB_USER_0_BASE_S 0x50104000 /* AHB USER 0 Secure base address */ -+#define AHB_USER_1_BASE_S 0x50105000 /* AHB USER 1 Secure base address */ -+#define AHB_USER_2_BASE_S 0x50106000 /* AHB USER 2 Secure base address */ -+#define AHB_USER_3_BASE_S 0x50107000 /* AHB USER 3 Secure base address */ -+#define HDLCD_BASE_S 0x50310000 /* HDLCD Secure base address */ -+#define ETHERNET_BASE_S 0x50400000 /* Ethernet Secure base address */ -+#define USB_BASE_S 0x50500000 /* USB Secure base address */ -+#define USER_APB0_BASE_S 0x50700000 /* User APB 0 Secure base address */ -+#define USER_APB1_BASE_S 0x50701000 /* User APB 1 Secure base address */ -+#define USER_APB2_BASE_S 0x50702000 /* User APB 2 Secure base address */ -+#define USER_APB3_BASE_S 0x50703000 /* User APB 3 Secure base address */ -+#define QSPI_CONFIG_BASE_S 0x50800000 /* QSPI Config Secure base address */ -+#define QSPI_WRITE_BASE_S 0x50801000 /* QSPI Write Secure base address */ -+#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ -+#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ -+#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ -+ -+/* Secure Subsystem peripheral region */ -+#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ -+#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ -+#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ -+#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ -+#define CORSTONE315_SYSINFO_BASE_S 0x58020000 /* Corstone-315 System info Block Secure base address */ -+#define CORSTONE315_SYSCTRL_BASE_S 0x58021000 /* Corstone-315 System control Block Secure base address */ -+#define CORSTONE315_SYSPPU_BASE_S 0x58022000 /* Corstone-315 System Power Policy Unit Secure base address */ -+#define CORSTONE315_CPU0PPU_BASE_S 0x58023000 /* Corstone-315 CPU 0 Power Policy Unit Secure base address */ -+#define CORSTONE315_MGMTPPU_BASE_S 0x58028000 /* Corstone-315 Management Power Policy Unit Secure base address */ -+#define CORSTONE315_DBGPPU_BASE_S 0x58029000 /* Corstone-315 Debug Power Policy Unit Secure base address */ -+#define CORSTONE315_NPU0PPU_BASE_S 0x5802A000 /* Corstone-315 NPU 0 Power Policy Unit Secure base address */ -+#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ -+#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ -+#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ -+#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ -+#define SAM_BASE_S 0x58042000 /* SAM Secure base address */ -+#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ -+#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ -+/* Secure MSTEXPPIHL Peripheral region */ -+#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x58100000 /* FPGA - SBCon I2C (Touch) Secure base address */ -+#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x58101000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ -+#define FPGA_SPI_ADC_BASE_S 0x58102000 /* FPGA - PL022 (SPI ADC) Secure base address */ -+#define FPGA_SPI_SHIELD0_BASE_S 0x58103000 /* FPGA - PL022 (SPI Shield0) Secure base address */ -+#define FPGA_SPI_SHIELD1_BASE_S 0x58104000 /* FPGA - PL022 (SPI Shield1) Secure base address */ -+#define SBCon_I2C_SHIELD0_BASE_S 0x58105000 /* SBCon (I2C - Shield0) Secure base address */ -+#define SBCon_I2C_SHIELD1_BASE_S 0x58106000 /* SBCon (I2C – Shield1) Secure base address */ -+#define USER_APB_BASE_S 0x58107000 /* USER APB Secure base address */ -+#define FPGA_DDR4_EEPROM_BASE_S 0x58108000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ -+#define FPGA_SCC_BASE_S 0x58200000 /* FPGA - SCC registers Secure base address */ -+#define FPGA_I2S_BASE_S 0x58201000 /* FPGA - I2S (Audio) Secure base address */ -+#define FPGA_IO_BASE_S 0x58202000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ -+#define UART0_BASE_S 0x58203000 /* UART 0 Secure base address */ -+#define UART1_BASE_S 0x58204000 /* UART 1 Secure base address */ -+#define UART2_BASE_S 0x58205000 /* UART 2 Secure base address */ -+#define UART3_BASE_S 0x58206000 /* UART 3 Secure base address */ -+#define UART4_BASE_S 0x58207000 /* UART 4 Secure base address */ -+#define UART5_BASE_S 0x58208000 /* UART 5 Secure base address */ -+#define RTC_BASE_S 0x5820B000 /* RTC Secure base address */ -+ -+#define VSOCKET_BASE_S 0x5FEE0000 /*!< VSOCKET Secure base address */ -+#define VIO_BASE_S 0x5FEF0000 /*!< VIO Secure base address */ -+#define VSI0_BASE_S 0x5FF00000 /*!< VSI 0 Secure base address */ -+#define VSI1_BASE_S 0x5FF10000 /*!< VSI 1 Secure base address */ -+#define VSI2_BASE_S 0x5FF20000 /*!< VSI 2 Secure base address */ -+#define VSI3_BASE_S 0x5FF30000 /*!< VSI 3 Secure base address */ -+#define VSI4_BASE_S 0x5FF40000 /*!< VSI 4 Secure base address */ -+#define VSI5_BASE_S 0x5FF50000 /*!< VSI 5 Secure base address */ -+#define VSI6_BASE_S 0x5FF60000 /*!< VSI 6 Secure base address */ -+#define VSI7_BASE_S 0x5FF70000 /*!< VSI 7 Secure base address */ -+ -+#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ -+#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ -+#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ -+#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ -+ -+/* TCM Security Gate register addresses */ -+#define ITGU_CTRL_BASE 0xE001E500 /* TGU control register for ITCM */ -+#define ITGU_CFG_BASE 0xE001E504 /* TGU configuration register for ITCM */ -+#define ITGU_LUTn_BASE 0xE001E510 /* TGU Look Up Table register for ITCM */ -+#define DTGU_CTRL_BASE 0xE001E600 /* TGU control register for DTCM */ -+#define DTGU_CFG_BASE 0xE001E604 /* TGU configuration register for DTCM */ -+#define DTGU_LUTn_BASE 0xE001E610 /* TGU Look Up Table register for DTCM */ -+ -+/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ -+#define CORSTONE315_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller -+ * Access from Non-secure software is only allowed -+ * if AIRCR.BFHFNMINS is set to 1 */ -+ -+/* Memory size definitions */ -+#define ITCM_SIZE (0x00008000) /* 32 kB */ -+#define DTCM_BLK_SIZE (0x00002000) /* 8 kB */ -+#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -+#define DTCM_SIZE (DTCM_BLK_SIZE*DTCM_BLK_NUM) -+#define BOOT_ROM_SIZE (0x20000) /* 128 kB */ -+#define SRAM_SIZE (0x00200000) /* 2 MB */ -+#define ISRAM0_SIZE (0x00200000) /* 2 MB */ -+#define ISRAM1_SIZE (0x00200000) /* 2 MB */ -+#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ -+#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ -+#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ -+#define OTP_TOTAL_SIZE (0x4000) -+ -+/* All VMs use the same MPC block size as defined by VMMPCBLKSIZE. */ -+#define SRAM_MPC_BLK_SIZE (0x4000) /* 16 kB */ -+#define QSPI_MPC_BLK_SIZE (0x40000) /* 256 kB */ -+#define DDR4_MPC_BLK_SIZE (0x100000) /* 1 MB */ -+ -+/* Defines for Driver MPC's */ -+/* SRAM -- 2 MB */ -+#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) -+#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) -+#define MPC_SRAM_RANGE_OFFSET_NS (0x0) -+#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) -+#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) -+#define MPC_SRAM_RANGE_OFFSET_S (0x0) -+ -+/* QSPI -- 8 MB */ -+#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) -+#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) -+#define MPC_QSPI_RANGE_OFFSET_NS (0x0) -+#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) -+#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) -+#define MPC_QSPI_RANGE_OFFSET_S (0x0) -+ -+/* ISRAM0 -- 2 MB*/ -+#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) -+#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) -+#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) -+#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) -+#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) -+#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) -+ -+/* ISRAM1 -- 2 MB */ -+#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) -+#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) -+#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) -+#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) -+#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) -+#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) -+ -+/* DDR4 -- 2GB (8 * 256 MB) */ -+#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) -+#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) -+#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) -+#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) -+#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) -+#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) -+#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) -+#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) -+#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) -+#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) -+#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) -+#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) -+#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) -+#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) -+#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) -+#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) -+#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) -+ -+#endif /* __PLATFORM_BASE_ADDRESS_H__ */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_irq.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_irq.h -new file mode 100644 -index 0000000..8bb95a5 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_irq.h -@@ -0,0 +1,119 @@ -+/* -+ * Copyright (c) 2024 Arm Limited. All rights reserved. -+ * -+ * Licensed under the Apache License Version 2.0 (the "License"); -+ * you may not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * http://www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing software -+ * distributed under the License is distributed on an "AS IS" BASIS -+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+#ifndef __PLATFORM_IRQ_H__ -+#define __PLATFORM_IRQ_H__ -+ -+typedef enum _IRQn_Type { -+ NonMaskableInt_IRQn = -14, /* Non Maskable Interrupt */ -+ HardFault_IRQn = -13, /* HardFault Interrupt */ -+ MemoryManagement_IRQn = -12, /* Memory Management Interrupt */ -+ BusFault_IRQn = -11, /* Bus Fault Interrupt */ -+ UsageFault_IRQn = -10, /* Usage Fault Interrupt */ -+ SecureFault_IRQn = -9, /* Secure Fault Interrupt */ -+ SVCall_IRQn = -5, /* SV Call Interrupt */ -+ DebugMonitor_IRQn = -4, /* Debug Monitor Interrupt */ -+ PendSV_IRQn = -2, /* Pend SV Interrupt */ -+ SysTick_IRQn = -1, /* System Tick Interrupt */ -+ NONSEC_WATCHDOG_RESET_REQ_IRQn = 0, /* Non-Secure Watchdog Reset -+ * Request Interrupt -+ */ -+ NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */ -+ SLOWCLK_TIMER_IRQn = 2, /* SLOWCLK Timer Interrupt */ -+ TIMER0_IRQn = 3, /* TIMER 0 Interrupt */ -+ TIMER1_IRQn = 4, /* TIMER 1 Interrupt */ -+ TIMER2_IRQn = 5, /* TIMER 2 Interrupt */ -+ /* Reserved = 6, Reserved */ -+ /* Reserved = 7, Reserved */ -+ /* Reserved = 8, Reserved */ -+ MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */ -+ PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */ -+ MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */ -+ BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined -+ * (Secure) Interrupt -+ */ -+ /* Reserved = 13, Reserved */ -+ Combined_PPU_IRQn = 14, /* Combined PPU */ -+ SDC_IRQn = 15, /* Secure Debug channel Interrupt */ -+ NPU0_IRQn = 16, /* NPU0 */ -+ /* Reserved = 17, Reserved */ -+ /* Reserved = 18, Reserved */ -+ /* Reserved = 19, Reserved */ -+ KMU_IRQn = 20, /* KMU Interrupt */ -+ /* Reserved = 21, Reserved */ -+ /* Reserved = 22, Reserved */ -+ /* Reserved = 23, Reserved */ -+ DMA_SEC_Combined_IRQn = 24, /* DMA Secure Combined Interrupt */ -+ DMA_NONSEC_Combined_IRQn = 25, /* DMA Non-Secure Combined Interrupt */ -+ DMA_SECURITY_VIOLATION_IRQn = 26, /* DMA Security Violation Interrupt */ -+ TIMER3_AON_IRQn = 27, /* TIMER 3 AON Interrupt */ -+ CPU0_CTI_0_IRQn = 28, /* CPU0 CTI IRQ 0 */ -+ CPU0_CTI_1_IRQn = 29, /* CPU0 CTI IRQ 1 */ -+ SAM_CRITICAL_SEVERITY_FAULT_IRQn = 30, /* SAM Critical Severity Fault Interrupt */ -+ SAM_SEVERITY_FAULT_HANDLER_IRQn = 31, /* SAM Severity Fault Handler Interrupt */ -+ /* Reserved = 32, Reserved */ -+ UARTRX0_IRQn = 33, /* UART 0 RX Interrupt */ -+ UARTTX0_IRQn = 34, /* UART 0 TX Interrupt */ -+ UARTRX1_IRQn = 35, /* UART 1 RX Interrupt */ -+ UARTTX1_IRQn = 36, /* UART 1 TX Interrupt */ -+ UARTRX2_IRQn = 37, /* UART 2 RX Interrupt */ -+ UARTTX2_IRQn = 38, /* UART 2 TX Interrupt */ -+ UARTRX3_IRQn = 39, /* UART 3 RX Interrupt */ -+ UARTTX3_IRQn = 40, /* UART 3 TX Interrupt */ -+ UARTRX4_IRQn = 41, /* UART 4 RX Interrupt */ -+ UARTTX4_IRQn = 42, /* UART 4 TX Interrupt */ -+ UART0_Combined_IRQn = 43, /* UART 0 Combined Interrupt */ -+ UART1_Combined_IRQn = 44, /* UART 1 Combined Interrupt */ -+ UART2_Combined_IRQn = 45, /* UART 2 Combined Interrupt */ -+ UART3_Combined_IRQn = 46, /* UART 3 Combined Interrupt */ -+ UART4_Combined_IRQn = 47, /* UART 4 Combined Interrupt */ -+ UARTOVF_IRQn = 48, /* UART 0, 1, 2, 3, 4 & 5 Overflow Interrupt */ -+ ETHERNET_IRQn = 49, /* Ethernet Interrupt */ -+ I2S_IRQn = 50, /* Audio I2S Interrupt */ -+ /* Reserved = 51, Reserved */ -+ /* Reserved = 52, Reserved */ -+ /* Reserved = 53, Reserved */ -+ /* Reserved = 54, Reserved */ -+ /* Reserved = 55, Reserved */ -+ /* Reserved = 56, Reserved */ -+ DMA_CHANNEL_0_IRQn = 57, /* DMA Channel 0 Interrupt */ -+ DMA_CHANNEL_1_IRQn = 58, /* DMA Channel 1 Interrupt */ -+ /* Reserved = 59:68 Reserved */ -+ GPIO0_Combined_IRQn = 69, /* GPIO 0 Combined Interrupt */ -+ GPIO1_Combined_IRQn = 70, /* GPIO 1 Combined Interrupt */ -+ GPIO2_Combined_IRQn = 71, /* GPIO 2 Combined Interrupt */ -+ GPIO3_Combined_IRQn = 72, /* GPIO 3 Combined Interrupt */ -+ /* Reserved = 73:124 Reserved */ -+ UARTRX5_IRQn = 125, /* UART 5 RX Interrupt */ -+ UARTTX5_IRQn = 126, /* UART 5 TX Interrupt */ -+ /* Reserved = 127 Reserved */ -+ RTC_IRQn = 128, /* RTC Interrupt */ -+ /* Reserved = 129:131 Reserved */ -+ ISP_IRQn = 132, /* ISP C55 Interrupt */ -+ HDLCD_IRQn = 133, /* HDLCD Interrupt */ -+ /* Reserved = 134:223 Reserved */ -+ ARM_VSI0_IRQn = 224, /* VSI 0 Interrupt */ -+ ARM_VSI1_IRQn = 225, /* VSI 1 Interrupt */ -+ ARM_VSI2_IRQn = 226, /* VSI 2 Interrupt */ -+ ARM_VSI3_IRQn = 227, /* VSI 3 Interrupt */ -+ ARM_VSI4_IRQn = 228, /* VSI 4 Interrupt */ -+ ARM_VSI5_IRQn = 229, /* VSI 5 Interrupt */ -+ ARM_VSI6_IRQn = 230, /* VSI 6 Interrupt */ -+ ARM_VSI7_IRQn = 231, /* VSI 7 Interrupt */ -+ -+} IRQn_Type; -+ -+#endif /* __PLATFORM_IRQ_H__ */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_pins.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_pins.h -new file mode 100644 -index 0000000..b5a063a ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_pins.h -@@ -0,0 +1,114 @@ -+/* -+ * Copyright (c) 2019-2024 Arm Limited. All rights reserved. -+ * -+ * Licensed under the Apache License, Version 2.0 (the "License"); -+ * you may not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * http://www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing software -+ * distributed under the License is distributed on an "AS IS" BASIS -+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/** -+ * \file platform_pins.h -+ * \brief This file defines all the pins for this platform. -+ */ -+ -+#ifndef __PLATFORM_PINS_H__ -+#define __PLATFORM_PINS_H__ -+ -+/* AHB GPIO pin names */ -+enum arm_gpio_pin_name_t { -+ AHB_GPIO0_0 = 0U, -+ AHB_GPIO0_1 = 1U, -+ AHB_GPIO0_2 = 2U, -+ AHB_GPIO0_3 = 3U, -+ AHB_GPIO0_4 = 4U, -+ AHB_GPIO0_5 = 5U, -+ AHB_GPIO0_6 = 6U, -+ AHB_GPIO0_7 = 7U, -+ AHB_GPIO0_8 = 8U, -+ AHB_GPIO0_9 = 9U, -+ AHB_GPIO0_10 = 10U, -+ AHB_GPIO0_11 = 11U, -+ AHB_GPIO0_12 = 12U, -+ AHB_GPIO0_13 = 13U, -+ AHB_GPIO0_14 = 14U, -+ AHB_GPIO0_15 = 15U, -+ AHB_GPIO1_0 = 0U, -+ AHB_GPIO1_1 = 1U, -+ AHB_GPIO1_2 = 2U, -+ AHB_GPIO1_3 = 3U, -+ AHB_GPIO1_4 = 4U, -+ AHB_GPIO1_5 = 5U, -+ AHB_GPIO1_6 = 6U, -+ AHB_GPIO1_7 = 7U, -+ AHB_GPIO1_8 = 8U, -+ AHB_GPIO1_9 = 9U, -+ AHB_GPIO1_10 = 10U, -+ AHB_GPIO1_11 = 11U, -+ AHB_GPIO1_12 = 12U, -+ AHB_GPIO1_13 = 13U, -+ AHB_GPIO1_14 = 14U, -+ AHB_GPIO1_15 = 15U, -+ AHB_GPIO2_0 = 0U, -+ AHB_GPIO2_1 = 1U, -+ AHB_GPIO2_2 = 2U, -+ AHB_GPIO2_3 = 3U, -+ AHB_GPIO2_4 = 4U, -+ AHB_GPIO2_5 = 5U, -+ AHB_GPIO2_6 = 6U, -+ AHB_GPIO2_7 = 7U, -+ AHB_GPIO2_8 = 8U, -+ AHB_GPIO2_9 = 9U, -+ AHB_GPIO2_10 = 10U, -+ AHB_GPIO2_11 = 11U, -+ AHB_GPIO2_12 = 12U, -+ AHB_GPIO2_13 = 13U, -+ AHB_GPIO2_14 = 14U, -+ AHB_GPIO2_15 = 15U, -+ AHB_GPIO3_0 = 0U, -+ AHB_GPIO3_1 = 1U, -+ AHB_GPIO3_2 = 2U, -+ AHB_GPIO3_3 = 3U, -+ AHB_GPIO3_4 = 4U, -+ AHB_GPIO3_5 = 5U, -+ AHB_GPIO3_6 = 6U, -+ AHB_GPIO3_7 = 7U, -+ AHB_GPIO3_8 = 8U, -+ AHB_GPIO3_9 = 9U, -+ AHB_GPIO3_10 = 10U, -+ AHB_GPIO3_11 = 11U, -+ AHB_GPIO3_12 = 12U, -+ AHB_GPIO3_13 = 13U, -+ AHB_GPIO3_14 = 14U, -+ AHB_GPIO3_15 = 15U, -+}; -+ -+/* GPIO shield 0 definition */ -+#define SH0_UART_RX AHB_GPIO0_0 -+#define SH0_UART_TX AHB_GPIO0_1 -+#define SH0_SPI_SS AHB_GPIO0_10 -+#define SH0_SPI_MOSI AHB_GPIO0_11 -+#define SH0_SPI_MISO AHB_GPIO0_12 -+#define SH0_SPI_SCK AHB_GPIO0_13 -+#define SH0_I2C_SDA AHB_GPIO0_14 -+#define SH0_I2C_SCL AHB_GPIO0_15 -+ -+/* GPIO shield 1 definition */ -+#define SH1_UART_RX AHB_GPIO1_0 -+#define SH1_UART_TX AHB_GPIO1_1 -+ -+#define SH1_SPI_SS AHB_GPIO1_10 -+#define SH1_SPI_MOSI AHB_GPIO1_11 -+#define SH1_SPI_MISO AHB_GPIO1_12 -+#define SH1_SPI_SCK AHB_GPIO1_13 -+#define SH1_I2C_SDA AHB_GPIO1_14 -+#define SH1_I2C_SCL AHB_GPIO1_15 -+ -+#endif /* __PLATFORM_PINS_H__ */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_regs.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_regs.h -new file mode 100644 -index 0000000..62edc68 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/platform_regs.h -@@ -0,0 +1,510 @@ -+/* -+ * Copyright (c) 2024 Arm Limited -+ * -+ * Licensed under the Apache License, Version 2.0 (the "License"); -+ * you may not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * http://www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an "AS IS" BASIS, -+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+#ifndef __PLATFORM_REGS_H__ -+#define __PLATFORM_REGS_H__ -+ -+#include -+ -+/* Secure Access Configuration Register Block */ -+struct corstone315_sacfg_t { -+ volatile uint32_t spcsecctrl; /* 0x000 (R/W) Secure Privilege Controller -+ Secure Configuration Control -+ register */ -+ volatile uint32_t buswait; /* 0x004 (R/W) Bus Access wait control */ -+ volatile uint32_t reserved0[2]; -+ volatile uint32_t secrespcfg; /* 0x010 (R/W) Security Violation Response -+ * Configuration register */ -+ volatile uint32_t nsccfg; /* 0x014 (R/W) Non Secure Callable -+ * Configuration for IDAU */ -+ volatile uint32_t reserved1; -+ volatile uint32_t secmpcintstat; /* 0x01C (R/ ) Secure MPC IRQ Status */ -+ volatile uint32_t secppcintstat; /* 0x020 (R/ ) Secure PPC IRQ Status */ -+ volatile uint32_t secppcintclr; /* 0x024 (R/W) Secure PPC IRQ Clear */ -+ volatile uint32_t secppcinten; /* 0x028 (R/W) Secure PPC IRQ Enable */ -+ volatile uint32_t reserved2; -+ volatile uint32_t secmscintstat; /* 0x030 (R/ ) Secure MSC IRQ Status */ -+ volatile uint32_t secmscintclr; /* 0x034 (R/W) Secure MSC IRQ Clear */ -+ volatile uint32_t secmscinten; /* 0x038 (R/W) Secure MSC IRQ Enable */ -+ volatile uint32_t reserved3; -+ volatile uint32_t brgintstat; /* 0x040 (R/ ) Bridge Buffer Error IRQ -+ * Status */ -+ volatile uint32_t brgintclr; /* 0x044 (R/W) Bridge Buffer Error IRQ -+ * Clear */ -+ volatile uint32_t brginten; /* 0x048 (R/W) Bridge Buffer Error IRQ -+ * Enable */ -+ volatile uint32_t reserved4; -+ volatile uint32_t mainnsppc0; /* 0x050 (R/W) Non-secure Access -+ * Peripheral Protection -+ * Control 0 on the Main -+ * Interconnect */ -+ volatile uint32_t reserved5[3]; -+ volatile uint32_t mainnsppcexp0; /* 0x060 (R/W) Expansion 0 Non-secure -+ * Access Peripheral -+ * Protection Control on the -+ * Main Interconnect */ -+ volatile uint32_t mainnsppcexp1; /* 0x064 (R/W) Expansion 1 Non-secure -+ * Access Peripheral -+ * Protection Control on the -+ * Main Interconnect */ -+ volatile uint32_t mainnsppcexp2; /* 0x068 (R/W) Expansion 2 Non-secure -+ * Access Peripheral -+ * Protection Control on the -+ * Main Interconnect */ -+ volatile uint32_t mainnsppcexp3; /* 0x06C (R/W) Expansion 3 Non-secure -+ * Access Peripheral -+ * Protection Control on the -+ * Main Interconnect */ -+ volatile uint32_t periphnsppc0; /* 0x070 (R/W) Non-secure Access -+ * Peripheral Protection -+ * Control 0 on the Peripheral -+ * Interconnect */ -+ volatile uint32_t periphnsppc1; /* 0x074 (R/W) Non-secure Access -+ * Peripheral Protection -+ * Control 1 on the Peripheral -+ * Interconnect */ -+ volatile uint32_t reserved6[2]; -+ volatile uint32_t periphnsppcexp0;/* 0x080 (R/W) Expansion 0 Non-secure -+ * Access Peripheral -+ * Protection Control on -+ * Peripheral Bus */ -+ volatile uint32_t periphnsppcexp1;/* 0x084 (R/W) Expansion 1 Non-secure -+ * Access Peripheral -+ * Protection Control on -+ * Peripheral Bus */ -+ volatile uint32_t periphnsppcexp2;/* 0x088 (R/W) Expansion 2 Non-secure -+ * Access Peripheral -+ * Protection Control on -+ * Peripheral Bus */ -+ volatile uint32_t periphnsppcexp3;/* 0x08C (R/W) Expansion 3 Non-secure -+ * Access Peripheral -+ * Protection Control on -+ * Peripheral Bus */ -+ volatile uint32_t mainspppc0; /* 0x090 (R/W) Secure Unprivileged Access -+ * Peripheral Protection -+ * Control 0 on Main -+ * Interconnect */ -+ volatile uint32_t reserved7[3]; -+ volatile uint32_t mainspppcexp0; /* 0x0A0 (R/W) Expansion 0 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t mainspppcexp1; /* 0x0A4 (R/W) Expansion 1 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t mainspppcexp2; /* 0x0A8 (R/W) Expansion 2 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t mainspppcexp3; /* 0x0AC (R/W) Expansion 3 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t periphspppc0; /* 0x0B0 (R/W) Secure Unprivileged Access -+ * Peripheral Protection -+ * Control 0 on -+ * Peripheral Interconnect */ -+ volatile uint32_t periphspppc1; /* 0x0B4 (R/W) Secure Unprivileged Access -+ * Peripheral Protection -+ * Control 1 on -+ * Peripheral Interconnect */ -+ volatile uint32_t npuspporpl; /* 0x0B8 (R/W) Secure Access NPU privilege -+ * level reset state -+ * control */ -+ volatile uint32_t reserved8[1]; -+ volatile uint32_t periphspppcexp0;/* 0x0C0 (R/W) Expansion 0 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t periphspppcexp1;/* 0x0C4 (R/W) Expansion 1 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t periphspppcexp2;/* 0x0C8 (R/W) Expansion 2 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t periphspppcexp3;/* 0x0CC (R/W) Expansion 3 Secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t nsmscexp; /* 0x0D0 (R/W) Expansion MSC Non-Secure -+ * Configuration */ -+ volatile uint32_t reserved9[959]; -+ volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */ -+ volatile uint32_t reserved10[3]; -+ volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */ -+ volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */ -+ volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */ -+ volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */ -+ volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */ -+ volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */ -+ volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */ -+ volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */ -+}; -+ -+/* PPC interrupt position mask */ -+#define PERIPH_PPC0_INT_POS_MASK (1UL << 0) -+#define PERIPH_PPC1_INT_POS_MASK (1UL << 1) -+#define PERIPH_PPCEXP0_INT_POS_MASK (1UL << 4) -+#define PERIPH_PPCEXP1_INT_POS_MASK (1UL << 5) -+#define PERIPH_PPCEXP2_INT_POS_MASK (1UL << 6) -+#define PERIPH_PPCEXP3_INT_POS_MASK (1UL << 7) -+#define MAIN_PPC0_INT_POS_MASK (1UL << 16) -+#define MAIN_PPCEXP0_INT_POS_MASK (1UL << 20) -+#define MAIN_PPCEXP1_INT_POS_MASK (1UL << 21) -+#define MAIN_PPCEXP2_INT_POS_MASK (1UL << 22) -+#define MAIN_PPCEXP3_INT_POS_MASK (1UL << 23) -+ -+/* Non-secure Access Configuration Register Block */ -+struct corstone315_nsacfg_t { -+ volatile uint32_t reserved0[36]; -+ volatile uint32_t mainnspppc0; /* 0x090 (R/W) Non-secure Unprivileged -+ * Access Peripheral -+ * Protection Control 0 on -+ * Main Interconnect */ -+ volatile uint32_t reserved1[3]; -+ -+ volatile uint32_t mainnspppcexp0; /* 0x0A0 (R/W) Expansion 0 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t mainnspppcexp1; /* 0x0A4 (R/W) Expansion 1 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t mainnspppcexp2; /* 0x0A8 (R/W) Expansion 2 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t mainnspppcexp3; /* 0x0AC (R/W) Expansion 3 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Main -+ * Interconnect */ -+ volatile uint32_t periphnspppc0; /* 0x0B0 (R/W) Non-secure Unprivileged -+ * Access Peripheral -+ * Protection Control 0 on -+ * Peripheral Interconnect */ -+ volatile uint32_t periphnspppc1; /* 0x0B4 (R/W) Non-secure Unprivileged -+ * Access Peripheral -+ * Protection Control 1 on -+ * Peripheral Interconnect */ -+ volatile uint32_t npuspporpl; /* 0x0B8 (R/W) Non-Secure Access NPU -+ * privilege level reset -+ * state control */ -+ volatile uint32_t reserved2[1]; -+ volatile uint32_t periphnspppcexp0;/* 0x0C0 (R/W) Expansion 0 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t periphnspppcexp1;/* 0x0C4 (R/W) Expansion 1 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t periphnspppcexp2;/* 0x0C8 (R/W) Expansion 2 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t periphnspppcexp3;/* 0x0CC (R/W) Expansion 3 Non-secure -+ * Unprivileged Access -+ * Peripheral Protection -+ * Control on Peripheral -+ * Interconnect */ -+ volatile uint32_t reserved3[960]; -+ volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */ -+ volatile uint32_t reserved4[3]; -+ volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */ -+ volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */ -+ volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */ -+ volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */ -+ volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */ -+ volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */ -+ volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */ -+ volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */ -+}; -+ -+/* MAIN PPC0 peripherals definition */ -+/* End MAIN PPC0 peripherals definition */ -+ -+/* MAIN PPCEXP0 peripherals definition */ -+#define GPIO0_MAIN_PPCEXP0_POS_MASK (1UL << 0) -+#define GPIO1_MAIN_PPCEXP0_POS_MASK (1UL << 1) -+#define GPIO2_MAIN_PPCEXP0_POS_MASK (1UL << 2) -+#define GPIO3_MAIN_PPCEXP0_POS_MASK (1UL << 3) -+#define USB_AND_ETHERNET_MAIN_PPCEXP0_POS_MASK (1UL << 8) -+/* End MAIN PPCEXP0 peripherals definition */ -+ -+/* MAIN PPCEXP1 peripherals definition */ -+ -+/* End MAIN PPCEXP1 peripherals definition */ -+ -+/* MAIN PPCEXP2 peripherals definition */ -+/* End MAIN PPCEXP2 peripherals definition */ -+ -+/* MAIN PPCEXP3 peripherals definition */ -+/* End MAIN PPCEXP3 peripherals definition */ -+ -+/* PERIPH PPC0 peripherals definition */ -+#define SYSTEM_TIMER0_PERIPH_PPC0_POS_MASK (1UL << 0) -+#define SYSTEM_TIMER1_PERIPH_PPC0_POS_MASK (1UL << 1) -+#define SYSTEM_TIMER2_PERIPH_PPC0_POS_MASK (1UL << 2) -+#define SYSTEM_TIMER3_PERIPH_PPC0_POS_MASK (1UL << 5) -+#define WATCHDOG_PERIPH_PPC0_POS_MASK (1UL << 6) -+/* There are separate secure and non-secure watchdog peripherals, so this bit -+ * can only be used in the unprivileged access registers. */ -+/* End PERIPH PPC0 peripherals definition */ -+ -+/* PERIPH PPC1 peripherals definition */ -+#define SLOWCLK_TIMER_PERIPH_PPC1_POS_MASK (1UL << 0) -+/* End PERIPH PPC1 peripherals definition */ -+ -+/* PERIPH PPCEXP0 peripherals definition */ -+#define TIMING_ADAPTERS_PERIPH_PPCEXP0_POS_MASK (1UL << 5) -+/* End PERIPH PPCEXP0 peripherals definition */ -+ -+/* PERIPH PPCEXP1 peripherals definition */ -+#define FPGA_I2C_TOUCH_PERIPH_PPCEXP1_POS_MASK (1UL << 0) -+#define FPGA_I2C_AUDIO_PERIPH_PPCEXP1_POS_MASK (1UL << 1) -+#define FPGA_SPI_ADC_PERIPH_PPCEXP1_POS_MASK (1UL << 2) -+#define FPGA_SPI_SHIELD0_PERIPH_PPCEXP1_POS_MASK (1UL << 3) -+#define FPGA_SPI_SHIELD1_PERIPH_PPCEXP1_POS_MASK (1UL << 4) -+#define SBCon_I2C_SHIELD0_PERIPH_PPCEXP1_POS_MASK (1UL << 5) -+#define SBCon_I2C_SHIELD1_PERIPH_PPCEXP1_POS_MASK (1UL << 6) -+#define FPGA_SBCon_I2C_PERIPH_PPCEXP1_POS_MASK (1UL << 8) -+/* End PERIPH PPCEXP1 peripherals definition */ -+ -+/* PERIPH PPCEXP2 peripherals definition */ -+#define FPGA_SCC_PERIPH_PPCEXP2_POS_MASK (1UL << 0) -+#define FPGA_I2S_PERIPH_PPCEXP2_POS_MASK (1UL << 1) -+#define FPGA_IO_PERIPH_PPCEXP2_POS_MASK (1UL << 2) -+#define UART0_PERIPH_PPCEXP2_POS_MASK (1UL << 3) -+#define UART1_PERIPH_PPCEXP2_POS_MASK (1UL << 4) -+#define UART2_PERIPH_PPCEXP2_POS_MASK (1UL << 5) -+#define UART3_PERIPH_PPCEXP2_POS_MASK (1UL << 6) -+#define UART4_PERIPH_PPCEXP2_POS_MASK (1UL << 7) -+#define UART5_PERIPH_PPCEXP2_POS_MASK (1UL << 8) -+#define RTC_PERIPH_PPCEXP2_POS_MASK (1UL << 11) -+ -+#define VSI_PERIPH_PPCEXP2_POS_MASK (1UL << 12) -+#define VIO_PERIPH_PPCEXP2_POS_MASK (1UL << 13) -+#define VSOCKET_PERIPH_PPCEXP2_POS_MASK (1UL << 14) -+/* End PERIPH PPCEXP2 peripherals definition */ -+ -+/* PERIPH PPCEXP3 peripherals definition */ -+/* End PERIPH PPCEXP3 peripherals definition */ -+ -+struct cpu0_pwrctrl_t { -+ volatile uint32_t cpupwrcfg; /* 0x000 (R/W) CPU 0 Local Power -+ * Configuration */ -+ volatile uint32_t reserved0[1011]; -+ volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */ -+ volatile uint32_t reserved1[3]; -+ volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */ -+ volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */ -+ volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */ -+ volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */ -+ volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */ -+ volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */ -+ volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */ -+ volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */ -+}; -+ -+struct cpu0_secctrl_t { -+ volatile uint32_t cpuseccfg; /* 0x000 (R/W) CPU Local Security -+ * Configuration */ -+ volatile uint32_t reserved0[1011]; -+ volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */ -+ volatile uint32_t reserved1[3]; -+ volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */ -+ volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */ -+ volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */ -+ volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */ -+ volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */ -+ volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */ -+ volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */ -+ volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */ -+}; -+ -+struct corstone315_sysinfo_t { -+ volatile uint32_t soc_identity; /* 0x000 (R/ ) SoC Identity Register */ -+ volatile uint32_t sys_config0; /* 0x004 (R/ ) System Hardware -+ * Configuration 0 */ -+ volatile uint32_t sys_config1; /* 0x008 (R/ ) System Hardware -+ * Configuration 1 */ -+ volatile uint32_t reserved0[1006]; -+ volatile uint32_t iidr; /* 0xFC8 (R/ ) Subsystem Implementation -+ * Identity */ -+ volatile uint32_t reserved1; -+ volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */ -+ volatile uint32_t reserved2[3]; -+ volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */ -+ volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */ -+ volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */ -+ volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */ -+ volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */ -+ volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */ -+ volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */ -+ volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */ -+}; -+ -+struct corstone315_sysctrl_t { -+ volatile uint32_t secdbgstat; /* 0x000 (R/ ) Secure Debug -+ * Configuration Status */ -+ volatile uint32_t secdbgset; /* 0x004 (R/W) Secure Debug -+ * Configuration Set */ -+ volatile uint32_t secdbgclr; /* 0x008 ( /W) Secure Debug -+ * Configuration Clear */ -+ volatile uint32_t scsecctrl; /* 0x00C (R/W) System Control Security -+ * Controls */ -+ volatile uint32_t clk_cfg0; /* 0x010 (R/W) Clock Configuration 0 */ -+ volatile uint32_t clk_cfg1; /* 0x014 (R/W) Clock Configuration 1 */ -+ volatile uint32_t clock_force; /* 0x018 (R/W) Clock Forces */ -+ volatile uint32_t reserved0[57]; -+ volatile uint32_t reset_syndrome; /* 0x100 (R/W) Reset syndrome */ -+ volatile uint32_t reset_mask; /* 0x104 (R/W) Reset mask */ -+ volatile uint32_t swreset; /* 0x108 ( /W) Software Reset */ -+ volatile uint32_t gretreg; /* 0x10C (R/W) General Purpose -+ * Retention */ -+ volatile uint32_t initsvtor0; /* 0x110 (R/W) CPU 0 Initial Secure -+ * Reset Vector Register */ -+ volatile uint32_t reserved1[3]; -+ volatile uint32_t cpuwait; /* 0x120 (R/W) CPU Boot Wait Control */ -+ volatile uint32_t nmi_enable; /* 0x124 (R/W) Non Maskable Interrupts -+ * Enable */ -+ volatile uint32_t reserved2[53]; -+ volatile uint32_t pwrctrl; /* 0x1FC (R/W) Power Configuration and -+ * Control */ -+ volatile uint32_t pdcm_pd_sys_sense; /* 0x200 (R/W) PDCM PD_SYS -+ * Sensitivity */ -+ volatile uint32_t pdcm_pd_cpu0_sense;/* 0x204 (R/ ) PDCM PD_CPU0 -+ * Sensitivity */ -+ volatile uint32_t reserved3[3]; -+ volatile uint32_t pdcm_pd_vmr0_sense;/* 0x214 (R/W) PDCM PD_VMR0 -+ * Sensitivity */ -+ volatile uint32_t pdcm_pd_vmr1_sense;/* 0x218 (R/W) PDCM PD_VMR1 -+ * Sensitivity */ -+ volatile uint32_t pdcm_pd_vmr2_sense; /* 0x21C (R/W) PDCM PD_VMR2 -+ * Sensitivity */ -+ volatile uint32_t pdcm_pd_vmr3_sense; /* 0x220 (R/W) PDCM PD_VMR3 -+ * Sensitivity */ -+ volatile uint32_t reserved4[10]; /* 0x224-0x248 Reserved */ -+ volatile uint32_t pdcm_pd_mgmt_sense; /* 0x24C (R/W) PDCM PD_MGMT -+ * Sensitivity */ -+ volatile uint32_t reserved5[3]; /* 0x250-0x258 Reserved */ -+ volatile uint32_t lcm_dcu_force_dis; /* 0x25C DCU Force disable */ -+ volatile uint32_t reserved6[860]; -+ volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */ -+ volatile uint32_t reserved7[3]; -+ volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */ -+ volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */ -+ volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */ -+ volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */ -+ volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */ -+ volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */ -+ volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */ -+ volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */ -+}; -+ -+#define SYSCTRL_RESET_SYNDROME_POR_MASK (1UL << 0) -+#define SYSCTRL_RESET_SYNDROME_NSWDRSTREQ_MASK (1UL << 1) -+#define SYSCTRL_RESET_SYNDROME_SWDRSTREQ_MASK (1UL << 2) -+#define SYSCTRL_RESET_SYNDROME_SLOWCLKWDRSTREQ_MASK (1UL << 3) -+#define SYSCTRL_RESET_SYNDROME_RESETREQ_MASK (1UL << 4) -+#define SYSCTRL_RESET_SYNDROME_SWRESETREQ_MASK (1UL << 5) -+#define SYSCTRL_RESET_SYNDROME_HOSTRESETREQ_MASK (1UL << 7) -+#define SYSCTRL_RESET_SYNDROME_CPU0RSTREQ_MASK (1UL << 8) -+#define SYSCTRL_RESET_SYNDROME_CPU0LOCKUP_MASK (1UL << 12) -+ -+#define SYSCTRL_SWRESET_SWRESETREQ_MASK (1UL << 9) -+ -+#define SYSCTRL_RESET_MASK_NSWDRSTREQEN_MASK (1UL << 1) -+#define SYSCTRL_RESET_MASK_CPU0RSTREQEN_MASK (1UL << 8) -+ -+struct corstone315_ewic_t { -+ volatile uint32_t ewic_cr; /* 0x000 (R/W) EWIC Control */ -+ volatile uint32_t ewic_ascr; /* 0x004 (R/W) Automatic Sequence -+ * Control */ -+ volatile uint32_t ewic_clrmask; /* 0x008 ( /W) Clear All Mask */ -+ volatile uint32_t ewic_numid; /* 0x00C (R/ ) ID Register for the number -+ * of events supported */ -+ volatile uint32_t reserved0[124]; -+ volatile uint32_t ewic_maska; /* 0x200 (R/W) Set which internal events -+ * cause wakeup */ -+ volatile uint32_t ewic_mask[15]; /* 0x204 (R/W) Set which external -+ * interrupts cause wakeup -+ * Only the first (total -+ * system IRQ number)/32 -+ * registers are implemented -+ * in array */ -+ volatile uint32_t reserved1[112]; -+ volatile uint32_t ewic_penda; /* 0x400 (R/ ) Shows which internal -+ * interrupts were pended -+ * while the EWIC was -+ * enabled */ -+ -+ volatile uint32_t ewic_pend[15]; /* 0x404 (R/W) Shows which external -+ * interrupts were pended -+ * while the EWIC was -+ * enabled -+ * Only the first (total -+ * system IRQ number)/32 -+ * registers are implemented -+ * in array */ -+ volatile uint32_t reserved2[112]; -+ volatile uint32_t ewic_psr; /* 0x600 (R/ ) Pending Summary */ -+ volatile uint32_t reserved3[575]; -+ volatile uint32_t itctrl; /* 0xF00 (R/ ) Integration Mode Control */ -+ volatile uint32_t reserved4[39]; -+ volatile uint32_t claimset; /* 0xFA0 (R/W) Claim Tag Set */ -+ volatile uint32_t claimclr; /* 0xFA4 (R/W) Claim Tag Clear */ -+ volatile uint32_t devaff0; /* 0xFA8 (R/ ) Device Affinity 0 */ -+ volatile uint32_t devaff1; /* 0xFAC (R/ ) Device Affinity 1 */ -+ volatile uint32_t lar; /* 0xFB0 ( /W) Lock Access */ -+ volatile uint32_t lsr; /* 0xFB4 (R/ ) Lock Status */ -+ volatile uint32_t authstatus; /* 0xFB8 (R/ ) Authentication Status */ -+ volatile uint32_t devarch; /* 0xFBC (R/ ) Device Architecture */ -+ volatile uint32_t devid2; /* 0xFC0 (R/ ) Device Configuration 2 */ -+ volatile uint32_t devid1; /* 0xFC4 (R/ ) Device Configuration 1 */ -+ volatile uint32_t devid; /* 0xFC8 (R/ ) Device Configuration */ -+ volatile uint32_t devtype; /* 0xFCC (R/ ) Device Type */ -+ volatile uint32_t pidr4; /* 0xFD0 (R/ ) Peripheral ID 4 */ -+ volatile uint32_t reserved5[3]; -+ volatile uint32_t pidr0; /* 0xFE0 (R/ ) Peripheral ID 0 */ -+ volatile uint32_t pidr1; /* 0xFE4 (R/ ) Peripheral ID 1 */ -+ volatile uint32_t pidr2; /* 0xFE8 (R/ ) Peripheral ID 2 */ -+ volatile uint32_t pidr3; /* 0xFEC (R/ ) Peripheral ID 3 */ -+ volatile uint32_t cidr0; /* 0xFF0 (R/ ) Component ID 0 */ -+ volatile uint32_t cidr1; /* 0xFF4 (R/ ) Component ID 1 */ -+ volatile uint32_t cidr2; /* 0xFF8 (R/ ) Component ID 2 */ -+ volatile uint32_t cidr3; /* 0xFFC (R/ ) Component ID 3 */ -+}; -+#endif /* __PLATFORM_REGS_H__ */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/pmu_armv8.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/pmu_armv8.h -new file mode 100644 -index 0000000..e11cbb8 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/pmu_armv8.h -@@ -0,0 +1,345 @@ -+/* *INDENT-OFF* */ -+ -+/****************************************************************************** -+ * @file pmu_armv8.h -+ * @brief CMSIS PMU API for Armv8.1-M PMU -+ * @version V1.0.1 -+ * @date 15. April 2020 -+ ******************************************************************************/ -+/* -+ * Copyright (c) 2020 Arm Limited. All rights reserved. -+ * -+ * SPDX-License-Identifier: Apache-2.0 -+ * -+ * Licensed under the Apache License, Version 2.0 (the License); you may -+ * not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT -+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* This file is a copy of -+ * https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/pmu_armv8.h -+*/ -+ -+#if defined ( __ICCARM__ ) -+ #pragma system_include /* treat file as system include file for MISRA check */ -+#elif defined (__clang__) -+ #pragma clang system_header /* treat file as system include file */ -+#endif -+ -+#ifndef ARM_PMU_ARMV8_H -+#define ARM_PMU_ARMV8_H -+ -+/** -+ * \brief PMU Events -+ * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. -+ * */ -+ -+#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ -+#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ -+#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ -+#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ -+#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ -+#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ -+#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ -+#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ -+#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ -+#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ -+#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ -+#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ -+#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ -+#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ -+#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ -+#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ -+#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ -+#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ -+#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ -+#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ -+#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ -+#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ -+#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ -+#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ -+#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ -+#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ -+#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ -+#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ -+#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ -+#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ -+#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ -+#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ -+#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ -+#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ -+#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ -+#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ -+#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ -+#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ -+#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ -+#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ -+#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ -+#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ -+#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ -+#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ -+#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ -+#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ -+#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ -+#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ -+#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ -+#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ -+#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ -+#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ -+#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ -+#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ -+#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ -+#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ -+#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ -+#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ -+#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ -+#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ -+#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ -+#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ -+#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ -+#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ -+#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ -+#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ -+#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ -+#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ -+#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ -+#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ -+#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ -+#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ -+#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ -+#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ -+#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ -+#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ -+#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ -+#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ -+#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ -+#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ -+#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ -+#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ -+#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ -+#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ -+#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ -+#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ -+#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ -+#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ -+#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ -+#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ -+#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ -+#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ -+#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ -+#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ -+#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ -+#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ -+#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ -+#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ -+#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ -+#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ -+#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ -+#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ -+#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ -+#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ -+#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ -+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ -+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ -+#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ -+#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ -+#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ -+#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ -+#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ -+#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ -+#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ -+#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ -+#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ -+#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ -+#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ -+#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ -+#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ -+#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ -+#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ -+#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ -+#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ -+#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ -+#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ -+#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ -+#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ -+#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ -+#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ -+#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ -+ -+/** \brief PMU Functions */ -+ -+__STATIC_INLINE void ARM_PMU_Enable(void); -+__STATIC_INLINE void ARM_PMU_Disable(void); -+ -+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); -+ -+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); -+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); -+ -+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); -+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); -+ -+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); -+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); -+ -+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); -+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); -+ -+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); -+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); -+ -+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); -+ -+/** -+ \brief Enable the PMU -+*/ -+__STATIC_INLINE void ARM_PMU_Enable(void) -+{ -+ PMU->CTRL |= PMU_CTRL_ENABLE_Msk; -+} -+ -+/** -+ \brief Disable the PMU -+*/ -+__STATIC_INLINE void ARM_PMU_Disable(void) -+{ -+ PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; -+} -+ -+/** -+ \brief Set event to count for PMU eventer counter -+ \param [in] num Event counter (0-30) to configure -+ \param [in] type Event to count -+*/ -+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) -+{ -+ PMU->EVTYPER[num] = type; -+} -+ -+/** -+ \brief Reset cycle counter -+*/ -+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) -+{ -+ PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; -+} -+ -+/** -+ \brief Reset all event counters -+*/ -+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) -+{ -+ PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; -+} -+ -+/** -+ \brief Enable counters -+ \param [in] mask Counters to enable -+ \note Enables one or more of the following: -+ - event counters (0-30) -+ - cycle counter -+*/ -+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) -+{ -+ PMU->CNTENSET = mask; -+} -+ -+/** -+ \brief Disable counters -+ \param [in] mask Counters to enable -+ \note Disables one or more of the following: -+ - event counters (0-30) -+ - cycle counter -+*/ -+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) -+{ -+ PMU->CNTENCLR = mask; -+} -+ -+/** -+ \brief Read cycle counter -+ \return Cycle count -+*/ -+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) -+{ -+ return PMU->CCNTR; -+} -+ -+/** -+ \brief Read event counter -+ \param [in] num Event counter (0-30) to read -+ \return Event count -+*/ -+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) -+{ -+ return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; -+} -+ -+/** -+ \brief Read counter overflow status -+ \return Counter overflow status bits for the following: -+ - event counters (0-30) -+ - cycle counter -+*/ -+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) -+{ -+ return PMU->OVSSET; -+} -+ -+/** -+ \brief Clear counter overflow status -+ \param [in] mask Counter overflow status bits to clear -+ \note Clears overflow status bits for one or more of the following: -+ - event counters (0-30) -+ - cycle counter -+*/ -+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) -+{ -+ PMU->OVSCLR = mask; -+} -+ -+/** -+ \brief Enable counter overflow interrupt request -+ \param [in] mask Counter overflow interrupt request bits to set -+ \note Sets overflow interrupt request bits for one or more of the following: -+ - event counters (0-30) -+ - cycle counter -+*/ -+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) -+{ -+ PMU->INTENSET = mask; -+} -+ -+/** -+ \brief Disable counter overflow interrupt request -+ \param [in] mask Counter overflow interrupt request bits to clear -+ \note Clears overflow interrupt request bits for one or more of the following: -+ - event counters (0-30) -+ - cycle counter -+*/ -+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) -+{ -+ PMU->INTENCLR = mask; -+} -+ -+/** -+ \brief Software increment event counter -+ \param [in] mask Counters to increment -+ \note Software increment bits for one or more event counters (0-30) -+*/ -+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) -+{ -+ PMU->SWINC = mask; -+} -+ -+#endif -+ -+/* *INDENT-ON* */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/Device/Include/system_SSE315.h b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/system_SSE315.h -new file mode 100644 -index 0000000..7750f53 ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/Device/Include/system_SSE315.h -@@ -0,0 +1,53 @@ -+/* -+ * Copyright (c) 2009-2024 Arm Limited -+ * -+ * Licensed under the Apache License, Version 2.0 (the "License"); -+ * you may not use this file except in compliance with the License. -+ * You may obtain a copy of the License at -+ * -+ * http://www.apache.org/licenses/LICENSE-2.0 -+ * -+ * Unless required by applicable law or agreed to in writing, software -+ * distributed under the License is distributed on an "AS IS" BASIS, -+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -+ * See the License for the specific language governing permissions and -+ * limitations under the License. -+ */ -+ -+/* -+ * This file is derivative of CMSIS V5.9.0 system_ARMCM85.h -+ * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c -+ */ -+ -+#ifndef __SYSTEM_CORE_INIT_H__ -+#define __SYSTEM_CORE_INIT_H__ -+ -+#include -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ -+ -+/** -+ \brief Exception / Interrupt Handler Function Prototype -+*/ -+typedef void(*VECTOR_TABLE_Type)(void); -+ -+/** -+ * \brief Initializes the system -+ */ -+extern void SystemInit(void); -+ -+/** -+ * \brief Restores system core clock -+ */ -+extern void SystemCoreClockUpdate(void); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __SYSTEM_CORE_INIT_H__ */ -diff --git a/source/portable/NetworkInterface/MPS4_CS315/NetworkInterface.c b/source/portable/NetworkInterface/MPS4_CS315/NetworkInterface.c -new file mode 100644 -index 0000000..9fc319f ---- /dev/null -+++ b/source/portable/NetworkInterface/MPS4_CS315/NetworkInterface.c -@@ -0,0 +1,548 @@ -+/* -+ * FreeRTOS+TCP -+ * Copyright (C) 2022 Amazon.com, Inc. or its affiliates. All Rights Reserved. -+ * Copyright 2023 Arm Limited and/or its affiliates -+ * -+ * SPDX-License-Identifier: MIT -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a copy of -+ * this software and associated documentation files (the "Software"), to deal in -+ * the Software without restriction, including without limitation the rights to -+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -+ * the Software, and to permit persons to whom the Software is furnished to do so, -+ * subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be included in all -+ * copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * https://github.com/FreeRTOS -+ * https://www.FreeRTOS.org -+ */ -+ -+/* FreeRTOS includes. */ -+#include "FreeRTOS.h" -+#include "list.h" -+#include "task.h" -+#include "semphr.h" -+ -+/* Standard library definitions */ -+#include -+#include -+ -+/* FreeRTOS+TCP includes. */ -+#include -+#include -+#include -+#include -+ -+/* Ethernet driver includes. */ -+#include "Driver_ETH_MAC.h" -+#include "Driver_ETH_PHY.h" -+ -+/* ETH_LAN91C111 driver (ETH_LAN91C111.c) maintains it's own TX buffer to which -+* ethenet packet is copied into during transmission and during reception, the -+* driver expects a buffer into which the received ethernet packet is copied. */ -+#if ( ipconfigZERO_COPY_TX_DRIVER != 0 ) || ( ipconfigZERO_COPY_RX_DRIVER != 0 ) -+ #error ETH_LAN91C111 driver (ETH_LAN91C111.c) does not support zero copy. -+#endif -+ -+/* Ethernet interface */ -+typedef struct xEthernetInterface -+{ -+ ARM_DRIVER_ETH_MAC * pxEthernetMACDriver; -+ ARM_DRIVER_ETH_PHY * pxEthernetPHYDriver; -+ ARM_ETH_LINK_STATE eEthernetLinkState; -+} -+xEthernetInterface_t; -+ -+/* Ethernet MAC & PHY Driver */ -+extern ARM_DRIVER_ETH_MAC ARM_Driver_ETH_MAC_( 0 ); -+extern ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_( 0 ); -+ -+/* Initialise Ethernet interface */ -+static xEthernetInterface_t xEthernetInterface0 = -+{ -+ .pxEthernetMACDriver = &ARM_Driver_ETH_MAC_( 0 ), -+ .pxEthernetPHYDriver = &ARM_Driver_ETH_PHY_( 0 ), -+ .eEthernetLinkState = ARM_ETH_LINK_DOWN -+}; -+ -+/* The function xLAN91C111_NetworkInterfaceInitialise() will be called as -+ * long as it returns the value pdFAIL. -+ * It will go through several stages as described in 'eEMACState'. -+ */ -+typedef enum xEMAC_STATE -+{ -+ xEMAC_Init, -+ xEMAC_WaitPHY, -+ xEMAC_Ready, -+ xEMAC_Fatal, -+} EMACState_t; -+ -+static EMACState_t eEMACState = xEMAC_Init; -+ -+/* Sets the size of the stack (in words, not bytes) of the task that reads bytes -+ * from the network. */ -+#ifndef nwRX_TASK_STACK_SIZE -+ #define nwRX_TASK_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2 ) -+#endif -+ -+#ifndef nwETHERNET_RX_HANDLER_TASK_PRIORITY -+ /* #define nwETHERNET_RX_HANDLER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) */ -+ #define nwETHERNET_RX_HANDLER_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) -+#endif -+ -+/* Maximum size of ethernet frame that can transmitted using ETH_LAN91C111 -+ * driver (ETH_LAN91C111.c). The value of this macro is based on ETH_BUF_SIZE -+ * macro defined in ETH_LAN91C111.c. */ -+#define ETHERNET_FRAME_MAX_SIZE 1536 -+ -+/*-----------------------------------------------------------*/ -+ -+/* -+ * The task that processes incoming Ethernet packets. It is unblocked by the -+ * Ethernet Rx interrupt. -+ */ -+static void prvRxTask( void * pvParameters ); -+ -+/* -+ * Performs low level reads to obtain data from the Ethernet hardware. -+ */ -+static uint32_t prvLowLevelInput( NetworkBufferDescriptor_t ** pxNetworkBuffer ); -+ -+/* Check Ethernet link status */ -+static void prvLAN91C111_CheckEthertnetLinkStatus(); -+ -+/*-----------------------------------------------------------*/ -+ -+/* -+ * A pointer to the network interface is needed later when receiving packets. -+ */ -+static NetworkInterface_t * pxMyInterface; -+ -+static void prvEthernetDriverNotifications( uint32_t event ); -+static BaseType_t xLAN91C111_NetworkInterfaceInitialise( NetworkInterface_t * pxInterface ); -+static BaseType_t xLAN91C111_NetworkInterfaceOutput( NetworkInterface_t * pxInterface, -+ NetworkBufferDescriptor_t * const pxNetworkBuffer, -+ BaseType_t bReleaseAfterSend ); -+static BaseType_t xLAN91C111_GetPhyLinkStatus( NetworkInterface_t * pxInterface ); -+ -+NetworkInterface_t * pxLAN91C111_FillInterfaceDescriptor( BaseType_t xEMACIndex, -+ NetworkInterface_t * pxInterface ); -+ -+/*-----------------------------------------------------------*/ -+ -+static TaskHandle_t xRxTaskHandle = NULL; -+ -+/*-----------------------------------------------------------*/ -+ -+static void prvLAN91C111_CheckEthertnetLinkStatus() -+{ -+ ARM_ETH_LINK_STATE eEthernetLinkState; -+ IPStackEvent_t xRxEvent; -+ -+ eEthernetLinkState = xEthernetInterface0.pxEthernetPHYDriver->GetLinkState(); -+ -+ /* If the ethernet link status has not changed, then return without taking -+ * any actions */ -+ if( eEthernetLinkState != xEthernetInterface0.eEthernetLinkState ) -+ { -+ xEthernetInterface0.eEthernetLinkState = eEthernetLinkState; -+ -+ /* The ethernet link is down, notify the IP stack and set driver -+ * initialisation state machine to xEMAC_Init. The IP stack calls -+ * xLAN91C111_NetworkInterfaceInitialise when it receives -+ * eNetworkDownEvent event. */ -+ if( eEthernetLinkState == ARM_ETH_LINK_DOWN ) -+ { -+ FreeRTOS_printf( ( "NetworkInterface: Ethernet link is down" ) ); -+ eEMACState = xEMAC_Init; -+ xRxEvent.eEventType = eNetworkDownEvent; -+ xRxEvent.pvData = ( void * ) pxMyInterface; -+ xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 0 ); -+ } -+ } -+} -+ -+/*-----------------------------------------------------------*/ -+ -+static void prvRxTask( void * pvParameters ) -+{ -+ const TickType_t xBlockTime = pdMS_TO_TICKS( 100UL ); -+ IPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL }; -+ NetworkBufferDescriptor_t * pxNetworkBuffer = NULL; -+ uint32_t ulDataRead; -+ BaseType_t xReleaseNetworkBuffer = pdFALSE; -+ -+ ( void ) pvParameters; -+ -+ for( ; ; ) -+ { -+ /* Wait for the Ethernet ISR to receive a packet or a timeout (100ms). */ -+ ulTaskNotifyTake( pdFALSE, xBlockTime ); -+ -+ ulDataRead = prvLowLevelInput( &pxNetworkBuffer ); -+ -+ if( ulDataRead > 0 ) -+ { -+ xRxEvent.pvData = ( void * ) pxNetworkBuffer; -+ -+ pxNetworkBuffer->pxInterface = pxMyInterface; -+ pxNetworkBuffer->pxEndPoint = FreeRTOS_MatchingEndpoint( pxMyInterface, pxNetworkBuffer->pucEthernetBuffer ); -+ -+ if( pxNetworkBuffer->pxEndPoint == NULL ) -+ { -+ FreeRTOS_printf( ( "NetworkInterface: can not find a proper endpoint\n" ) ); -+ xReleaseNetworkBuffer = pdTRUE; -+ } -+ else -+ { -+ if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 0 ) == pdFAIL ) -+ { -+ xReleaseNetworkBuffer = pdTRUE; -+ } -+ } -+ -+ if( xReleaseNetworkBuffer == pdTRUE ) -+ { -+ vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); -+ } -+ } -+ -+ prvLAN91C111_CheckEthertnetLinkStatus(); -+ } -+} -+/*-----------------------------------------------------------*/ -+ -+static uint32_t prvLowLevelInput( NetworkBufferDescriptor_t ** pxNetworkBuffer ) -+{ -+ const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 0 ); -+ uint32_t ulMessageLength = 0; -+ int32_t lReceivedBytes = 0; -+ -+ ulMessageLength = xEthernetInterface0.pxEthernetMACDriver->GetRxFrameSize(); -+ -+ if( ulMessageLength != 0 ) -+ { -+ *pxNetworkBuffer = pxGetNetworkBufferWithDescriptor( ulMessageLength, -+ xDescriptorWaitTime ); -+ -+ if( *pxNetworkBuffer != NULL ) -+ { -+ lReceivedBytes = xEthernetInterface0.pxEthernetMACDriver->ReadFrame( -+ ( ( *pxNetworkBuffer )->pucEthernetBuffer ), -+ ulMessageLength ); -+ -+ if( lReceivedBytes >= 0 ) -+ { -+ ( *pxNetworkBuffer )->xDataLength = lReceivedBytes; -+ } -+ else -+ { -+ FreeRTOS_debug_printf( ( "NetworkInterface: Ethernet driver ReadFrame returned %d \n", lReceivedBytes ) ); -+ lReceivedBytes = 0; -+ } -+ } -+ else -+ { -+ FreeRTOS_printf( ( "NetworkInterface: pxNetworkBuffer = NULL\n" ) ); -+ /* No memory available for NetworkBuffer, drop the frame */ -+ xEthernetInterface0.pxEthernetMACDriver->ReadFrame( -+ NULL, -+ 0 ); -+ } -+ } -+ -+ return lReceivedBytes; -+} -+/*-----------------------------------------------------------*/ -+ -+static BaseType_t xLAN91C111_NetworkInterfaceInitialise( NetworkInterface_t * pxInterface ) -+{ -+ BaseType_t xReturn = pdFAIL; -+ BaseType_t xDriverReturn = ARM_DRIVER_ERROR; -+ const TickType_t xEthernetLinkStateTimeOut = pdMS_TO_TICKS( 1000 ); -+ ARM_ETH_MAC_CAPABILITIES xEthernetMACCapabilities; -+ ARM_ETH_LINK_INFO xEthernetLinkInfo; -+ uint32_t ulMACControlArg; -+ -+ ( void ) pxInterface; -+ -+ switch( eEMACState ) -+ { -+ case xEMAC_Init: -+ -+ /* Initialise Ethernet Driver */ -+ xDriverReturn = xEthernetInterface0.pxEthernetMACDriver->Initialize( prvEthernetDriverNotifications ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to initialise MAC Driver: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ xDriverReturn = xEthernetInterface0.pxEthernetMACDriver->PowerControl( ARM_POWER_FULL ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to set power to ethernet MAC device: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ xDriverReturn = xEthernetInterface0.pxEthernetMACDriver->SetMacAddress( ( ARM_ETH_MAC_ADDR * ) &pxInterface->pxEndPoint->xMACAddress ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to set MAC address: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ /* Initialise PHY Driver */ -+ xDriverReturn = xEthernetInterface0.pxEthernetPHYDriver->Initialize( -+ xEthernetInterface0.pxEthernetMACDriver->PHY_Read, -+ xEthernetInterface0.pxEthernetMACDriver->PHY_Write ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to initialise PHY Driver: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ xDriverReturn = xEthernetInterface0.pxEthernetPHYDriver->PowerControl( ARM_POWER_FULL ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to set power to PHY device: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ xDriverReturn = xEthernetInterface0.pxEthernetPHYDriver->SetInterface( xEthernetMACCapabilities.media_interface ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to set ethernet media interface: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ xDriverReturn = xEthernetInterface0.pxEthernetPHYDriver->SetMode( ARM_ETH_PHY_AUTO_NEGOTIATE ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to set ethernet PHY device operation mode: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ eEMACState = xEMAC_WaitPHY; -+ -+ case xEMAC_WaitPHY: -+ -+ /* Wait for the Ethernet link to be up */ -+ vTaskDelay( xEthernetLinkStateTimeOut ); -+ xEthernetInterface0.eEthernetLinkState = xEthernetInterface0.pxEthernetPHYDriver->GetLinkState(); -+ -+ if( xEthernetInterface0.eEthernetLinkState == ARM_ETH_LINK_DOWN ) -+ { -+ break; -+ } -+ -+ xEthernetLinkInfo = xEthernetInterface0.pxEthernetPHYDriver->GetLinkInfo(); -+ ulMACControlArg = xEthernetLinkInfo.speed << ARM_ETH_MAC_SPEED_Pos | -+ xEthernetLinkInfo.duplex << ARM_ETH_MAC_DUPLEX_Pos | -+ ARM_ETH_MAC_ADDRESS_BROADCAST; -+ /* Configure Ethernet MAC based on PHY status */ -+ xDriverReturn = xEthernetInterface0.pxEthernetMACDriver->Control( ARM_ETH_MAC_CONFIGURE, ulMACControlArg ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to configure ethernet MAC device: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ /* Enable RX */ -+ xDriverReturn = xEthernetInterface0.pxEthernetMACDriver->Control( ARM_ETH_MAC_CONTROL_RX, 1 ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to enable ethernet MAC reception: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ /* Enable TX */ -+ xDriverReturn = xEthernetInterface0.pxEthernetMACDriver->Control( ARM_ETH_MAC_CONTROL_TX, 1 ); -+ -+ if( xDriverReturn != ARM_DRIVER_OK ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Failed to enable ethernet MAC transmission: %d\n", xDriverReturn ) ); -+ break; -+ } -+ -+ if( xRxTaskHandle == NULL ) -+ { -+ /* Task that reads incoming Ethernet frames and sends it FreeRTOS -+ * TCP/IP stack. */ -+ xDriverReturn = xTaskCreate( prvRxTask, -+ "EMAC ", -+ nwRX_TASK_STACK_SIZE, -+ NULL, -+ nwETHERNET_RX_HANDLER_TASK_PRIORITY, -+ &xRxTaskHandle ); -+ -+ if( xDriverReturn != pdPASS ) -+ { -+ eEMACState = xEMAC_Fatal; -+ FreeRTOS_printf( ( "NetworkInterface: Unable to create prvRxTask: %d\n", xDriverReturn ) ); -+ break; -+ } -+ } -+ -+ eEMACState = xEMAC_Ready; -+ -+ case xEMAC_Ready: -+ -+ /* Ethernet driver is ready. */ -+ xReturn = pdPASS; -+ break; -+ -+ case xEMAC_Fatal: -+ -+ /* A fatal error has occurred, and the ethernet driver -+ * can not start. */ -+ break; -+ } -+ -+ return xReturn; -+} -+ -+static void prvEthernetDriverNotifications( uint32_t event ) -+{ -+ BaseType_t xHigherPriorityTaskWoken = pdFALSE; -+ -+ configASSERT( xRxTaskHandle ); -+ -+ if( event == ARM_ETH_MAC_EVENT_RX_FRAME ) -+ { -+ /* Ethernet frame received. Send notification to Receive task. */ -+ vTaskNotifyGiveFromISR( xRxTaskHandle, &xHigherPriorityTaskWoken ); -+ } -+ -+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); -+} -+/*-----------------------------------------------------------*/ -+ -+static BaseType_t xLAN91C111_NetworkInterfaceOutput( NetworkInterface_t * pxInterface, -+ NetworkBufferDescriptor_t * const pxNetworkBuffer, -+ BaseType_t xReleaseAfterSend ) -+{ -+ BaseType_t xReturn = pdPASS; -+ -+ ( void ) pxInterface; -+ -+ if( xEthernetInterface0.eEthernetLinkState == ARM_ETH_LINK_UP ) -+ { -+ if( pxNetworkBuffer->xDataLength > ETHERNET_FRAME_MAX_SIZE ) -+ { -+ FreeRTOS_debug_printf( ( "NetworkInterface: Too big Ethernet frame, Size:", pxNetworkBuffer->xDataLength ) ); -+ xReturn = pdFAIL; -+ } -+ -+ if( xReturn == pdPASS ) -+ { -+ xReturn = xEthernetInterface0.pxEthernetMACDriver->SendFrame( -+ pxNetworkBuffer->pucEthernetBuffer, -+ pxNetworkBuffer->xDataLength, -+ 0 ); -+ -+ if( xReturn < 0 ) -+ { -+ FreeRTOS_debug_printf( ( "NetworkInterface: Ethernet driver SendFrame returned %d ", xReturn ) ); -+ } -+ } -+ } -+ -+ if( xReleaseAfterSend == pdTRUE ) -+ { -+ vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ); -+ } -+ -+ return xReturn; -+} -+/*-----------------------------------------------------------*/ -+ -+void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] ) -+{ -+ /* FIX ME if you want to use BufferAllocation_1.c, which uses statically -+ * allocated network buffers. */ -+ -+ /* Hard force an assert as this driver cannot be used with BufferAllocation_1.c -+ * without implementing this function. */ -+ configASSERT( 0 ); -+ ( void ) pxNetworkBuffers; -+} -+/*-----------------------------------------------------------*/ -+ -+ -+static BaseType_t xLAN91C111_GetPhyLinkStatus( NetworkInterface_t * pxInterface ) -+{ -+ ( void ) pxInterface; -+ -+ return ( BaseType_t ) xEthernetInterface0.pxEthernetPHYDriver->GetLinkState(); -+} -+ -+/*-----------------------------------------------------------*/ -+ -+#if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) -+ -+/* Do not call the following function directly. It is there for downward compatibility. -+ * The function FreeRTOS_IPInit() will call it to initialise the interface and end-point -+ * objects. See the description in FreeRTOS_Routing.h. */ -+ NetworkInterface_t * pxFillInterfaceDescriptor( BaseType_t xEMACIndex, -+ NetworkInterface_t * pxInterface ) -+ { -+ pxLAN91C111_FillInterfaceDescriptor( xEMACIndex, pxInterface ); -+ } -+ -+#endif -+/*-----------------------------------------------------------*/ -+ -+NetworkInterface_t * pxLAN91C111_FillInterfaceDescriptor( BaseType_t xEMACIndex, -+ NetworkInterface_t * pxInterface ) -+{ -+ static char pcName[ 17 ]; -+ -+ /* This function adds a network-interface. -+ * Make sure that the object pointed to by 'pxInterface' -+ * is declared static or global, and that it will remain to exist. */ -+ -+ pxMyInterface = pxInterface; -+ -+ snprintf( pcName, sizeof( pcName ), "eth % ld ", xEMACIndex ); -+ -+ memset( pxInterface, '\0', sizeof( *pxInterface ) ); -+ pxInterface->pcName = pcName; /* Just for logging, debugging. */ -+ pxInterface->pvArgument = ( void * ) xEMACIndex; /* Has only meaning for the driver functions. */ -+ pxInterface->pfInitialise = xLAN91C111_NetworkInterfaceInitialise; -+ pxInterface->pfOutput = xLAN91C111_NetworkInterfaceOutput; -+ pxInterface->pfGetPhyLinkStatus = xLAN91C111_GetPhyLinkStatus; -+ -+ FreeRTOS_AddNetworkInterface( pxInterface ); -+ -+ return pxInterface; -+} -+/*-----------------------------------------------------------*/ -diff --git a/source/portable/NetworkInterface/CMakeLists.txt b/source/portable/NetworkInterface/CMakeLists.txt -index 46a21ea..519729e 100644 ---- a/source/portable/NetworkInterface/CMakeLists.txt -+++ b/source/portable/NetworkInterface/CMakeLists.txt -@@ -42,6 +42,7 @@ add_subdirectory(LPC54018) - add_subdirectory(M487) - add_subdirectory(MPS2_AN385) - add_subdirectory(MPS3_AN552) -+add_subdirectory(MPS4_CS315) - add_subdirectory(mw300_rd) - add_subdirectory(pic32mzef) - add_subdirectory(RX) --- -2.40.1 - diff --git a/manifest.yml b/manifest.yml index 987c9524..2039edd1 100644 --- a/manifest.yml +++ b/manifest.yml @@ -138,7 +138,7 @@ dependencies: path: "components/tools/unity/library" - name: "FreeRTOS-Plus-TCP" license: "MIT" - version: "3d5ee0e821cab38cb6e6265fcf1ce7552a54519d" + version: "7b68a91f0870f9bcff444bb14e441d6a08658377" repository: type: "git" url: "https://github.com/FreeRTOS/FreeRTOS-Plus-TCP.git" diff --git a/release_changes/202404111359.change b/release_changes/202404111359.change new file mode 100644 index 00000000..c8229e82 --- /dev/null +++ b/release_changes/202404111359.change @@ -0,0 +1 @@ +build: Bump FreeRTOS-Plus-TCP commit hash