diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 587c6975a709f..e6606b1e4de80 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1106,6 +1106,16 @@ local_eliminate_vsetvl_insn (const vector_insn_info &dem)
 	      if (!new_info.skip_avl_compatible_p (dem))
 		return;
 
+	      /* Be more conservative here since we don't really get full
+		 demand info for following instructions, also that instruction
+		 isn't exist in RTL-SSA yet so we need parse that by low level
+		 API rather than vector_insn_info::parse_insn, see PR114747.  */
+	      unsigned last_vsetvli_sew = ::get_sew (PREV_INSN (i->rtl ()));
+	      unsigned last_vsetvli_lmul = ::get_vlmul (PREV_INSN (i->rtl ()));
+	      if (new_info.get_sew() != last_vsetvli_sew ||
+		  new_info.get_vlmul() != last_vsetvli_lmul)
+		return;
+
 	      new_info.set_avl_info (dem.get_avl_info ());
 	      new_info = dem.merge (new_info, LOCAL_MERGE);
 	      change_vsetvl_insn (insn, new_info);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
new file mode 100644
index 0000000000000..c478405e8d674
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+typedef unsigned short char16_t;
+
+size_t convert_latin1_to_utf16le(const char *src, size_t len, char16_t *dst) {
+  char16_t *beg = dst;
+  for (size_t vl; len > 0; len -= vl, src += vl, dst += vl) {
+    vl = __riscv_vsetvl_e8m4(len);
+    vuint8m4_t v = __riscv_vle8_v_u8m4((uint8_t*)src, vl);
+    __riscv_vse16_v_u16m8((uint16_t*)dst, __riscv_vzext_vf2_u16m8(v, vl), vl);
+  }
+  return dst - beg;
+}
+
+/* { dg-final { scan-assembler {vsetvli\s+[a-z0-9]+,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} } } */