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Common options:
"options": { "ghdl_analysis": [ "--ieee=synopsys" ] },
Converting from lsp to json (for writing tests):
python3 -m vhdl_langserver.lsptools lsp2json < vhdl-ls.trace.in > cmds.json
Creating a project from HDLMake:
hdl-prj.json: Makefile
echo "{ \"files\": [" > $@
comma=false; for f in $(SOURCES_VerilogFile); do \
if [ $$comma == "true" ]; then echo "," >> $@; else comma=true; fi; \
echo -n " { \"file\": \"$$f\", \"language\": \"verilog\"}" >> $@; \
done; \
for f in $(SOURCES_VHDLFile); do \
if [ $$comma == "true" ]; then echo "," >> $@; else comma=true; fi; \
echo -n " { \"file\": \"$$f\", \"language\": \"vhdl\"}" >> $@; \
done
echo >> $@
echo "]}" >> $@