forked from Xiaoyang-Lu/ChampSim_CAMAT
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy path4dis.txt
1083 lines (1017 loc) · 29.1 KB
/
4dis.txt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
*************************************************
ChampSim Multicore Out-of-Order Simulator
Last compiled: Mar 20 2022 18:18:42
*************************************************
DRAM access latency: 170
Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s
DRAM_DBUS_RETURN_TIME: 13
trace_0 ./traces/437.leslie3d-265B.champsimtrace.xz
trace_1 ./traces/429.mcf-22B.champsimtrace.xz
trace_2 ./traces/436.cactusADM-1804B.champsimtrace.xz
trace_3 ./traces/403.gcc-17B.champsimtrace.xz
warmup_instructions 1000
simulation_instructions 100000
champsim_seed 830
num_cpus 4
cpu_freq 4000
dram_io_freq 2400
page_size 4096
block_size 64
max_read_per_cycle 20
max_fill_per_cycle 20
dram_channels 1
dram_ranks 1
dram_banks 8
dram_rows 65536
dram_columns 128
dram_row_size 8
dram_size 4096
dram_pages 1048576
fetch_width 20
decode_width 20
exec_width 20
lq_width 20
sq_width 20
retire_width 20
scheduler_size 128
branch_mispredict_penalty 20
rob_size 256
lq_size 72
sq_size 56
num_instr_destinations_sparc 4
num_instr_destinations 2
num_instr_sources 4
itlb_set 16
itlb_way 8
itlb_rq_size 16
itlb_wq_size 16
itlb_pq_size 0
itlb_mshr_size 8
itlb_latency 1
dtlb_set 16
dtlb_way 4
dtlb_rq_size 16
dtlb_wq_size 16
dtlb_pq_size 0
dtlb_mshr_size 8
dtlb_latency 1
stlb_set 128
stlb_way 12
stlb_rq_size 32
stlb_wq_size 32
stlb_pq_size 0
stlb_mshr_size 16
stlb_latency 8
l1i_size 32
l1i_set 64
l1i_way 8
l1i_rq_size 64
l1i_wq_size 64
l1i_pq_size 8
l1i_mshr_size 8
l1i_latency 1
l1d_size 32
l1d_set 64
l1d_way 8
l1d_rq_size 64
l1d_wq_size 64
l1d_pq_size 32
l1d_mshr_size 16
l1d_latency 4
l2c_size 256
l2c_set 512
l2c_way 8
l2c_rq_size 32
l2c_wq_size 32
l2c_pq_size 16
l2c_mshr_size 32
l2c_latency 10
llc_size 8192
llc_set 8192
llc_way 16
llc_rq_size 128
llc_wq_size 128
llc_pq_size 128
llc_mshr_size 256
llc_latency 20
dram_channel_width 8
dram_wq_size 64
dram_rq_size 64
tRP 15
tRCD 15
tCAS 12.5
dram_dbus_turn_around_time 30
dram_write_high_wm 56
dram_write_low_wm 48
min_dram_writes_per_switch 16
dram_mtps 2400
dram_dbus_return_time 13
Warmup complete CPU 0 instructions: 6672 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec)
Warmup complete CPU 1 instructions: 5025 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec)
Warmup complete CPU 2 instructions: 4894 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec)
Warmup complete CPU 3 instructions: 1001 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec)
Finished CPU 0 instructions: 100015 cycles: 187720 cumulative IPC: 0.532788 (Simulation time: 0 hr 0 min 5 sec)
Finished CPU 1 instructions: 100017 cycles: 242354 cumulative IPC: 0.41269 (Simulation time: 0 hr 0 min 7 sec)
Finished CPU 2 instructions: 100006 cycles: 261955 cumulative IPC: 0.381768 (Simulation time: 0 hr 0 min 7 sec)
Finished CPU 3 instructions: 100000 cycles: 424579 cumulative IPC: 0.235527 (Simulation time: 0 hr 0 min 10 sec)
ChampSim completed all CPUs
Total Simulation Statistics (not including warmup)
CPU 0 cumulative IPC: 0.663516 instructions: 281715 cycles: 424579
Core_0_L1D_total_access 74885
Core_0_L1D_total_hit 71502
Core_0_L1D_total_miss 3383
Core_0_L1D_loads 65502
Core_0_L1D_load_hit 62902
Core_0_L1D_load_miss 2600
Core_0_L1D_RFOs 9383
Core_0_L1D_RFO_hit 8600
Core_0_L1D_RFO_miss 783
Core_0_L1D_prefetches 0
Core_0_L1D_prefetch_hit 0
Core_0_L1D_prefetch_miss 0
Core_0_L1D_writebacks 0
Core_0_L1D_writeback_hit 0
Core_0_L1D_writeback_miss 0
Core_0_L1I_total_access 48572
Core_0_L1I_total_hit 48528
Core_0_L1I_total_miss 44
Core_0_L1I_loads 48572
Core_0_L1I_load_hit 48528
Core_0_L1I_load_miss 44
Core_0_L1I_RFOs 0
Core_0_L1I_RFO_hit 0
Core_0_L1I_RFO_miss 0
Core_0_L1I_prefetches 0
Core_0_L1I_prefetch_hit 0
Core_0_L1I_prefetch_miss 0
Core_0_L1I_writebacks 0
Core_0_L1I_writeback_hit 0
Core_0_L1I_writeback_miss 0
Core_0_L2C_total_access 4354
Core_0_L2C_total_hit 2205
Core_0_L2C_total_miss 2149
Core_0_L2C_loads 2644
Core_0_L2C_load_hit 835
Core_0_L2C_load_miss 1809
Core_0_L2C_RFOs 783
Core_0_L2C_RFO_hit 443
Core_0_L2C_RFO_miss 340
Core_0_L2C_prefetches 0
Core_0_L2C_prefetch_hit 0
Core_0_L2C_prefetch_miss 0
Core_0_L2C_writebacks 927
Core_0_L2C_writeback_hit 927
Core_0_L2C_writeback_miss 0
Core_0_LLC_total_access 2149
Core_0_LLC_total_hit 0
Core_0_LLC_total_miss 2149
Core_0_LLC_loads 1809
Core_0_LLC_load_hit 0
Core_0_LLC_load_miss 1809
Core_0_LLC_RFOs 340
Core_0_LLC_RFO_hit 0
Core_0_LLC_RFO_miss 340
Core_0_LLC_prefetches 0
Core_0_LLC_prefetch_hit 0
Core_0_LLC_prefetch_miss 0
Core_0_LLC_writebacks 0
Core_0_LLC_writeback_hit 0
Core_0_LLC_writeback_miss 0
CPU 1 cumulative IPC: 0.392554 instructions: 166670 cycles: 424579
Core_1_L1D_total_access 56227
Core_1_L1D_total_hit 52972
Core_1_L1D_total_miss 3255
Core_1_L1D_loads 20728
Core_1_L1D_load_hit 17492
Core_1_L1D_load_miss 3236
Core_1_L1D_RFOs 35499
Core_1_L1D_RFO_hit 35480
Core_1_L1D_RFO_miss 19
Core_1_L1D_prefetches 0
Core_1_L1D_prefetch_hit 0
Core_1_L1D_prefetch_miss 0
Core_1_L1D_writebacks 0
Core_1_L1D_writeback_hit 0
Core_1_L1D_writeback_miss 0
Core_1_L1I_total_access 28964
Core_1_L1I_total_hit 28964
Core_1_L1I_total_miss 0
Core_1_L1I_loads 28964
Core_1_L1I_load_hit 28964
Core_1_L1I_load_miss 0
Core_1_L1I_RFOs 0
Core_1_L1I_RFO_hit 0
Core_1_L1I_RFO_miss 0
Core_1_L1I_prefetches 0
Core_1_L1I_prefetch_hit 0
Core_1_L1I_prefetch_miss 0
Core_1_L1I_writebacks 0
Core_1_L1I_writeback_hit 0
Core_1_L1I_writeback_miss 0
Core_1_L2C_total_access 3939
Core_1_L2C_total_hit 1269
Core_1_L2C_total_miss 2670
Core_1_L2C_loads 3187
Core_1_L2C_load_hit 518
Core_1_L2C_load_miss 2669
Core_1_L2C_RFOs 19
Core_1_L2C_RFO_hit 19
Core_1_L2C_RFO_miss 0
Core_1_L2C_prefetches 0
Core_1_L2C_prefetch_hit 0
Core_1_L2C_prefetch_miss 0
Core_1_L2C_writebacks 733
Core_1_L2C_writeback_hit 732
Core_1_L2C_writeback_miss 1
Core_1_LLC_total_access 2675
Core_1_LLC_total_hit 6
Core_1_LLC_total_miss 2669
Core_1_LLC_loads 2669
Core_1_LLC_load_hit 0
Core_1_LLC_load_miss 2669
Core_1_LLC_RFOs 0
Core_1_LLC_RFO_hit 0
Core_1_LLC_RFO_miss 0
Core_1_LLC_prefetches 0
Core_1_LLC_prefetch_hit 0
Core_1_LLC_prefetch_miss 0
Core_1_LLC_writebacks 6
Core_1_LLC_writeback_hit 6
Core_1_LLC_writeback_miss 0
CPU 2 cumulative IPC: 0.396725 instructions: 168441 cycles: 424579
Core_2_L1D_total_access 81023
Core_2_L1D_total_hit 79980
Core_2_L1D_total_miss 1043
Core_2_L1D_loads 54503
Core_2_L1D_load_hit 53544
Core_2_L1D_load_miss 959
Core_2_L1D_RFOs 26520
Core_2_L1D_RFO_hit 26436
Core_2_L1D_RFO_miss 84
Core_2_L1D_prefetches 0
Core_2_L1D_prefetch_hit 0
Core_2_L1D_prefetch_miss 0
Core_2_L1D_writebacks 0
Core_2_L1D_writeback_hit 0
Core_2_L1D_writeback_miss 0
Core_2_L1I_total_access 38872
Core_2_L1I_total_hit 38819
Core_2_L1I_total_miss 53
Core_2_L1I_loads 38872
Core_2_L1I_load_hit 38819
Core_2_L1I_load_miss 53
Core_2_L1I_RFOs 0
Core_2_L1I_RFO_hit 0
Core_2_L1I_RFO_miss 0
Core_2_L1I_prefetches 0
Core_2_L1I_prefetch_hit 0
Core_2_L1I_prefetch_miss 0
Core_2_L1I_writebacks 0
Core_2_L1I_writeback_hit 0
Core_2_L1I_writeback_miss 0
Core_2_L2C_total_access 1168
Core_2_L2C_total_hit 89
Core_2_L2C_total_miss 1079
Core_2_L2C_loads 1012
Core_2_L2C_load_hit 17
Core_2_L2C_load_miss 995
Core_2_L2C_RFOs 84
Core_2_L2C_RFO_hit 0
Core_2_L2C_RFO_miss 84
Core_2_L2C_prefetches 0
Core_2_L2C_prefetch_hit 0
Core_2_L2C_prefetch_miss 0
Core_2_L2C_writebacks 72
Core_2_L2C_writeback_hit 72
Core_2_L2C_writeback_miss 0
Core_2_LLC_total_access 1079
Core_2_LLC_total_hit 0
Core_2_LLC_total_miss 1079
Core_2_LLC_loads 995
Core_2_LLC_load_hit 0
Core_2_LLC_load_miss 995
Core_2_LLC_RFOs 84
Core_2_LLC_RFO_hit 0
Core_2_LLC_RFO_miss 84
Core_2_LLC_prefetches 0
Core_2_LLC_prefetch_hit 0
Core_2_LLC_prefetch_miss 0
Core_2_LLC_writebacks 0
Core_2_LLC_writeback_hit 0
Core_2_LLC_writeback_miss 0
CPU 3 cumulative IPC: 0.235527 instructions: 100000 cycles: 424579
Core_3_L1D_total_access 33528
Core_3_L1D_total_hit 32612
Core_3_L1D_total_miss 916
Core_3_L1D_loads 19879
Core_3_L1D_load_hit 18976
Core_3_L1D_load_miss 903
Core_3_L1D_RFOs 13649
Core_3_L1D_RFO_hit 13636
Core_3_L1D_RFO_miss 13
Core_3_L1D_prefetches 0
Core_3_L1D_prefetch_hit 0
Core_3_L1D_prefetch_miss 0
Core_3_L1D_writebacks 0
Core_3_L1D_writeback_hit 0
Core_3_L1D_writeback_miss 0
Core_3_L1I_total_access 18572
Core_3_L1I_total_hit 18382
Core_3_L1I_total_miss 190
Core_3_L1I_loads 18572
Core_3_L1I_load_hit 18382
Core_3_L1I_load_miss 190
Core_3_L1I_RFOs 0
Core_3_L1I_RFO_hit 0
Core_3_L1I_RFO_miss 0
Core_3_L1I_prefetches 0
Core_3_L1I_prefetch_hit 0
Core_3_L1I_prefetch_miss 0
Core_3_L1I_writebacks 0
Core_3_L1I_writeback_hit 0
Core_3_L1I_writeback_miss 0
Core_3_L2C_total_access 1124
Core_3_L2C_total_hit 35
Core_3_L2C_total_miss 1089
Core_3_L2C_loads 1093
Core_3_L2C_load_hit 16
Core_3_L2C_load_miss 1077
Core_3_L2C_RFOs 13
Core_3_L2C_RFO_hit 1
Core_3_L2C_RFO_miss 12
Core_3_L2C_prefetches 0
Core_3_L2C_prefetch_hit 0
Core_3_L2C_prefetch_miss 0
Core_3_L2C_writebacks 18
Core_3_L2C_writeback_hit 18
Core_3_L2C_writeback_miss 0
Core_3_LLC_total_access 1089
Core_3_LLC_total_hit 0
Core_3_LLC_total_miss 1089
Core_3_LLC_loads 1077
Core_3_LLC_load_hit 0
Core_3_LLC_load_miss 1077
Core_3_LLC_RFOs 12
Core_3_LLC_RFO_hit 0
Core_3_LLC_RFO_miss 12
Core_3_LLC_prefetches 0
Core_3_LLC_prefetch_hit 0
Core_3_LLC_prefetch_miss 0
Core_3_LLC_writebacks 0
Core_3_LLC_writeback_hit 0
Core_3_LLC_writeback_miss 0
[ROI Statistics]
Core_0_instructions 100015
Core_0_cycles 187720
Core_0_IPC 0.532788
Core_0_branch_prediction_accuracy 98.9952
Core_0_branch_MPKI 0.257493
Core_0_average_ROB_occupancy_at_mispredict 212.203
Core_0_L1D_total_access 26646
Core_0_L1D_total_hit 25319
Core_0_L1D_total_miss 1327
Core_0_L1D_total_overlap_miss 1327
Core_0_L1D_loads 23455
Core_0_L1D_load_hit 22424
Core_0_L1D_load_miss 1031
Core_0_L1D_RFOs 3191
Core_0_L1D_RFO_hit 2895
Core_0_L1D_RFO_miss 296
Core_0_L1D_prefetches 0
Core_0_L1D_prefetch_hit 0
Core_0_L1D_prefetch_miss 0
Core_0_L1D_writebacks 0
Core_0_L1D_writeback_hit 0
Core_0_L1D_writeback_miss 0
Core_0_L1D_miss_rate 0.0498011
Core_0_L1D_MPKI 13.27
Core_0_L1D_demand_miss 1327
Core_0_L1D_prefetch_requested 0
Core_0_L1D_prefetch_issued 0
Core_0_L1D_prefetch_useful 0
Core_0_L1D_prefetch_useless 0
Core_0_L1D_prefetch_late 0
Core_0_L1D_average_miss_latency 398.213
Core_0_L1D_active_cycles 386812
Core_0_L1D_active_hit_cycles 164407
Core_0_L1D_active_miss_cycles 294735
Core_0_L1D_active_pure_miss_cycles 222405
Core_0_L1D_active_hit_miss_overlap_cycles 72330
Core_0_L1D_total_pure_miss 1291
Core_0_L1D_pure_miss_rate 0.04845
Core_0_L1D_active_cycles_per_core 386812
Core_0_L1D_active_hit_cycles_per_core 164407
Core_0_L1D_active_miss_cycles_per_core 294735
Core_0_L1D_active_pure_miss_cycles_per_core 222405
Core_0_L1D_hit_miss_overlap_cycles_per_core 72330
Core_0_L1D_camat_per_core 14.5167
Core_0_L1I_total_access 17216
Core_0_L1I_total_hit 17172
Core_0_L1I_total_miss 44
Core_0_L1I_total_overlap_miss 44
Core_0_L1I_loads 17216
Core_0_L1I_load_hit 17172
Core_0_L1I_load_miss 44
Core_0_L1I_RFOs 0
Core_0_L1I_RFO_hit 0
Core_0_L1I_RFO_miss 0
Core_0_L1I_prefetches 0
Core_0_L1I_prefetch_hit 0
Core_0_L1I_prefetch_miss 0
Core_0_L1I_writebacks 0
Core_0_L1I_writeback_hit 0
Core_0_L1I_writeback_miss 0
Core_0_L1I_miss_rate 0.00255576
Core_0_L1I_MPKI 0.44
Core_0_L1I_demand_miss 44
Core_0_L1I_prefetch_requested 0
Core_0_L1I_prefetch_issued 0
Core_0_L1I_prefetch_useful 0
Core_0_L1I_prefetch_useless 0
Core_0_L1I_prefetch_late 0
Core_0_L1I_average_miss_latency 255.886
Core_0_L1I_active_cycles 70696
Core_0_L1I_active_hit_cycles 67317
Core_0_L1I_active_miss_cycles 3904
Core_0_L1I_active_pure_miss_cycles 3379
Core_0_L1I_active_hit_miss_overlap_cycles 525
Core_0_L1I_total_pure_miss 39
Core_0_L1I_pure_miss_rate 0.00226533
Core_0_L1I_active_cycles_per_core 70696
Core_0_L1I_active_hit_cycles_per_core 67317
Core_0_L1I_active_miss_cycles_per_core 3904
Core_0_L1I_active_pure_miss_cycles_per_core 3379
Core_0_L1I_hit_miss_overlap_cycles_per_core 525
Core_0_L1I_camat_per_core 4.10641
Core_0_L2C_total_access 1656
Core_0_L2C_total_hit 499
Core_0_L2C_total_miss 1157
Core_0_L2C_total_overlap_miss 1157
Core_0_L2C_loads 1075
Core_0_L2C_load_hit 98
Core_0_L2C_load_miss 977
Core_0_L2C_RFOs 296
Core_0_L2C_RFO_hit 116
Core_0_L2C_RFO_miss 180
Core_0_L2C_prefetches 0
Core_0_L2C_prefetch_hit 0
Core_0_L2C_prefetch_miss 0
Core_0_L2C_writebacks 285
Core_0_L2C_writeback_hit 285
Core_0_L2C_writeback_miss 0
Core_0_L2C_miss_rate 0.698671
Core_0_L2C_MPKI 11.57
Core_0_L2C_demand_miss 1157
Core_0_L2C_prefetch_requested 0
Core_0_L2C_prefetch_issued 0
Core_0_L2C_prefetch_useful 0
Core_0_L2C_prefetch_useless 0
Core_0_L2C_prefetch_late 0
Core_0_L2C_average_miss_latency 423.759
Core_0_L2C_active_cycles 294414
Core_0_L2C_active_hit_cycles 41974
Core_0_L2C_active_miss_cycles 270734
Core_0_L2C_active_pure_miss_cycles 252440
Core_0_L2C_active_hit_miss_overlap_cycles 18294
Core_0_L2C_total_pure_miss 1157
Core_0_L2C_pure_miss_rate 0.698671
Core_0_L2C_active_cycles_per_core 294414
Core_0_L2C_active_hit_cycles_per_core 41974
Core_0_L2C_active_miss_cycles_per_core 270734
Core_0_L2C_active_pure_miss_cycles_per_core 252440
Core_0_L2C_hit_miss_overlap_cycles_per_core 18294
Core_0_L2C_camat_per_core 177.786
Core_0_LLC_total_access 1157
Core_0_LLC_total_hit 0
Core_0_LLC_total_miss 1157
Core_0_LLC_total_overlap_miss 1157
Core_0_LLC_loads 977
Core_0_LLC_load_hit 0
Core_0_LLC_load_miss 977
Core_0_LLC_RFOs 180
Core_0_LLC_RFO_hit 0
Core_0_LLC_RFO_miss 180
Core_0_LLC_prefetches 0
Core_0_LLC_prefetch_hit 0
Core_0_LLC_prefetch_miss 0
Core_0_LLC_writebacks 0
Core_0_LLC_writeback_hit 0
Core_0_LLC_writeback_miss 0
Core_0_LLC_miss_rate 1
Core_0_LLC_MPKI 11.57
Core_0_LLC_demand_miss 1157
Core_0_LLC_prefetch_requested 0
Core_0_LLC_prefetch_issued 0
Core_0_LLC_prefetch_useful 0
Core_0_LLC_prefetch_useless 0
Core_0_LLC_prefetch_late 0
Core_0_LLC_average_miss_latency 1089.05
Core_0_LLC_active_cycles 400479
Core_0_LLC_active_hit_cycles 105011
Core_0_LLC_active_miss_cycles 390570
Core_0_LLC_active_pure_miss_cycles 295468
Core_0_LLC_active_hit_miss_overlap_cycles 95102
Core_0_LLC_total_pure_miss 1157
Core_0_LLC_pure_miss_rate 1
Core_0_LLC_active_cycles_per_core 261954
Core_0_LLC_active_hit_cycles_per_core 37595
Core_0_LLC_active_miss_cycles_per_core 244613
Core_0_LLC_active_pure_miss_cycles_per_core 224359
Core_0_LLC_hit_miss_overlap_cycles_per_core 20254
Core_0_LLC_camat_per_core 226.408
Core_0_major_page_fault 0
Core_0_minor_page_fault 72
Core_1_instructions 100017
Core_1_cycles 242354
Core_1_IPC 0.41269
Core_1_branch_prediction_accuracy 96.2138
Core_1_branch_MPKI 3.22798
Core_1_average_ROB_occupancy_at_mispredict 93.755
Core_1_L1D_total_access 33726
Core_1_L1D_total_hit 32022
Core_1_L1D_total_miss 1704
Core_1_L1D_total_overlap_miss 1704
Core_1_L1D_loads 12345
Core_1_L1D_load_hit 10643
Core_1_L1D_load_miss 1702
Core_1_L1D_RFOs 21381
Core_1_L1D_RFO_hit 21379
Core_1_L1D_RFO_miss 2
Core_1_L1D_prefetches 0
Core_1_L1D_prefetch_hit 0
Core_1_L1D_prefetch_miss 0
Core_1_L1D_writebacks 0
Core_1_L1D_writeback_hit 0
Core_1_L1D_writeback_miss 0
Core_1_L1D_miss_rate 0.0505248
Core_1_L1D_MPKI 17.04
Core_1_L1D_demand_miss 1704
Core_1_L1D_prefetch_requested 0
Core_1_L1D_prefetch_issued 0
Core_1_L1D_prefetch_useful 0
Core_1_L1D_prefetch_useless 0
Core_1_L1D_prefetch_late 0
Core_1_L1D_average_miss_latency 335.523
Core_1_L1D_active_cycles 383920
Core_1_L1D_active_hit_cycles 84626
Core_1_L1D_active_miss_cycles 319897
Core_1_L1D_active_pure_miss_cycles 299294
Core_1_L1D_active_hit_miss_overlap_cycles 20603
Core_1_L1D_total_pure_miss 1676
Core_1_L1D_pure_miss_rate 0.0496946
Core_1_L1D_active_cycles_per_core 383920
Core_1_L1D_active_hit_cycles_per_core 84626
Core_1_L1D_active_miss_cycles_per_core 319897
Core_1_L1D_active_pure_miss_cycles_per_core 299294
Core_1_L1D_hit_miss_overlap_cycles_per_core 20603
Core_1_L1D_camat_per_core 11.3835
Core_1_L1I_total_access 17470
Core_1_L1I_total_hit 17470
Core_1_L1I_total_miss 0
Core_1_L1I_total_overlap_miss 0
Core_1_L1I_loads 17470
Core_1_L1I_load_hit 17470
Core_1_L1I_load_miss 0
Core_1_L1I_RFOs 0
Core_1_L1I_RFO_hit 0
Core_1_L1I_RFO_miss 0
Core_1_L1I_prefetches 0
Core_1_L1I_prefetch_hit 0
Core_1_L1I_prefetch_miss 0
Core_1_L1I_writebacks 0
Core_1_L1I_writeback_hit 0
Core_1_L1I_writeback_miss 0
Core_1_L1I_miss_rate 0
Core_1_L1I_MPKI 0
Core_1_L1I_demand_miss 0
Core_1_L1I_prefetch_requested 0
Core_1_L1I_prefetch_issued 0
Core_1_L1I_prefetch_useful 0
Core_1_L1I_prefetch_useless 0
Core_1_L1I_prefetch_late 0
Core_1_L1I_average_miss_latency -nan
Core_1_L1I_active_cycles 29251
Core_1_L1I_active_hit_cycles 29251
Core_1_L1I_active_miss_cycles 0
Core_1_L1I_active_pure_miss_cycles 0
Core_1_L1I_active_hit_miss_overlap_cycles 0
Core_1_L1I_total_pure_miss 0
Core_1_L1I_pure_miss_rate 0
Core_1_L1I_active_cycles_per_core 29251
Core_1_L1I_active_hit_cycles_per_core 29251
Core_1_L1I_active_miss_cycles_per_core 0
Core_1_L1I_active_pure_miss_cycles_per_core 0
Core_1_L1I_hit_miss_overlap_cycles_per_core 0
Core_1_L1I_camat_per_core 1.67436
Core_1_L2C_total_access 1922
Core_1_L2C_total_hit 347
Core_1_L2C_total_miss 1575
Core_1_L2C_total_overlap_miss 1575
Core_1_L2C_loads 1691
Core_1_L2C_load_hit 116
Core_1_L2C_load_miss 1575
Core_1_L2C_RFOs 2
Core_1_L2C_RFO_hit 2
Core_1_L2C_RFO_miss 0
Core_1_L2C_prefetches 0
Core_1_L2C_prefetch_hit 0
Core_1_L2C_prefetch_miss 0
Core_1_L2C_writebacks 229
Core_1_L2C_writeback_hit 229
Core_1_L2C_writeback_miss 0
Core_1_L2C_miss_rate 0.819459
Core_1_L2C_MPKI 15.75
Core_1_L2C_demand_miss 1575
Core_1_L2C_prefetch_requested 0
Core_1_L2C_prefetch_issued 0
Core_1_L2C_prefetch_useful 0
Core_1_L2C_prefetch_useless 0
Core_1_L2C_prefetch_late 0
Core_1_L2C_average_miss_latency 331.961
Core_1_L2C_active_cycles 318032
Core_1_L2C_active_hit_cycles 37713
Core_1_L2C_active_miss_cycles 295526
Core_1_L2C_active_pure_miss_cycles 280319
Core_1_L2C_active_hit_miss_overlap_cycles 15207
Core_1_L2C_total_pure_miss 1575
Core_1_L2C_pure_miss_rate 0.819459
Core_1_L2C_active_cycles_per_core 318032
Core_1_L2C_active_hit_cycles_per_core 37713
Core_1_L2C_active_miss_cycles_per_core 295526
Core_1_L2C_active_pure_miss_cycles_per_core 280319
Core_1_L2C_hit_miss_overlap_cycles_per_core 15207
Core_1_L2C_camat_per_core 165.469
Core_1_LLC_total_access 1576
Core_1_LLC_total_hit 0
Core_1_LLC_total_miss 1576
Core_1_LLC_total_overlap_miss 1576
Core_1_LLC_loads 1576
Core_1_LLC_load_hit 0
Core_1_LLC_load_miss 1576
Core_1_LLC_RFOs 0
Core_1_LLC_RFO_hit 0
Core_1_LLC_RFO_miss 0
Core_1_LLC_prefetches 0
Core_1_LLC_prefetch_hit 0
Core_1_LLC_prefetch_miss 0
Core_1_LLC_writebacks 0
Core_1_LLC_writeback_hit 0
Core_1_LLC_writeback_miss 0
Core_1_LLC_miss_rate 1
Core_1_LLC_MPKI 15.76
Core_1_LLC_demand_miss 1576
Core_1_LLC_prefetch_requested 0
Core_1_LLC_prefetch_issued 0
Core_1_LLC_prefetch_useful 0
Core_1_LLC_prefetch_useless 0
Core_1_LLC_prefetch_late 0
Core_1_LLC_average_miss_latency 799.515
Core_1_LLC_active_cycles 400479
Core_1_LLC_active_hit_cycles 105011
Core_1_LLC_active_miss_cycles 390570
Core_1_LLC_active_pure_miss_cycles 295468
Core_1_LLC_active_hit_miss_overlap_cycles 95102
Core_1_LLC_total_pure_miss 1576
Core_1_LLC_pure_miss_rate 1
Core_1_LLC_active_cycles_per_core 282890
Core_1_LLC_active_hit_cycles_per_core 39891
Core_1_LLC_active_miss_cycles_per_core 257488
Core_1_LLC_active_pure_miss_cycles_per_core 242999
Core_1_LLC_hit_miss_overlap_cycles_per_core 14489
Core_1_LLC_camat_per_core 179.499
Core_1_major_page_fault 0
Core_1_minor_page_fault 105
Core_2_instructions 100006
Core_2_cycles 261955
Core_2_IPC 0.381768
Core_2_branch_prediction_accuracy 97.3451
Core_2_branch_MPKI 0.017408
Core_2_average_ROB_occupancy_at_mispredict 197
Core_2_L1D_total_access 48168
Core_2_L1D_total_hit 47540
Core_2_L1D_total_miss 628
Core_2_L1D_total_overlap_miss 628
Core_2_L1D_loads 32413
Core_2_L1D_load_hit 31833
Core_2_L1D_load_miss 580
Core_2_L1D_RFOs 15755
Core_2_L1D_RFO_hit 15707
Core_2_L1D_RFO_miss 48
Core_2_L1D_prefetches 0
Core_2_L1D_prefetch_hit 0
Core_2_L1D_prefetch_miss 0
Core_2_L1D_writebacks 0
Core_2_L1D_writeback_hit 0
Core_2_L1D_writeback_miss 0
Core_2_L1D_miss_rate 0.0130377
Core_2_L1D_MPKI 6.28
Core_2_L1D_demand_miss 628
Core_2_L1D_prefetch_requested 0
Core_2_L1D_prefetch_issued 0
Core_2_L1D_prefetch_useful 0
Core_2_L1D_prefetch_useless 0
Core_2_L1D_prefetch_late 0
Core_2_L1D_average_miss_latency 430.674
Core_2_L1D_active_cycles 332017
Core_2_L1D_active_hit_cycles 221304
Core_2_L1D_active_miss_cycles 154078
Core_2_L1D_active_pure_miss_cycles 110713
Core_2_L1D_active_hit_miss_overlap_cycles 43365
Core_2_L1D_total_pure_miss 588
Core_2_L1D_pure_miss_rate 0.0122073
Core_2_L1D_active_cycles_per_core 332017
Core_2_L1D_active_hit_cycles_per_core 221304
Core_2_L1D_active_miss_cycles_per_core 154078
Core_2_L1D_active_pure_miss_cycles_per_core 110713
Core_2_L1D_hit_miss_overlap_cycles_per_core 43365
Core_2_L1D_camat_per_core 6.8929
Core_2_L1I_total_access 22987
Core_2_L1I_total_hit 22934
Core_2_L1I_total_miss 53
Core_2_L1I_total_overlap_miss 53
Core_2_L1I_loads 22987
Core_2_L1I_load_hit 22934
Core_2_L1I_load_miss 53
Core_2_L1I_RFOs 0
Core_2_L1I_RFO_hit 0
Core_2_L1I_RFO_miss 0
Core_2_L1I_prefetches 0
Core_2_L1I_prefetch_hit 0
Core_2_L1I_prefetch_miss 0
Core_2_L1I_writebacks 0
Core_2_L1I_writeback_hit 0
Core_2_L1I_writeback_miss 0
Core_2_L1I_miss_rate 0.00230565
Core_2_L1I_MPKI 0.53
Core_2_L1I_demand_miss 53
Core_2_L1I_prefetch_requested 0
Core_2_L1I_prefetch_issued 0
Core_2_L1I_prefetch_useful 0
Core_2_L1I_prefetch_useless 0
Core_2_L1I_prefetch_late 0
Core_2_L1I_average_miss_latency 242.604
Core_2_L1I_active_cycles 57290
Core_2_L1I_active_hit_cycles 56514
Core_2_L1I_active_miss_cycles 2013
Core_2_L1I_active_pure_miss_cycles 776
Core_2_L1I_active_hit_miss_overlap_cycles 1237
Core_2_L1I_total_pure_miss 23
Core_2_L1I_pure_miss_rate 0.00100057
Core_2_L1I_active_cycles_per_core 57290
Core_2_L1I_active_hit_cycles_per_core 56514
Core_2_L1I_active_miss_cycles_per_core 2013
Core_2_L1I_active_pure_miss_cycles_per_core 776
Core_2_L1I_hit_miss_overlap_cycles_per_core 1237
Core_2_L1I_camat_per_core 2.49228
Core_2_L2C_total_access 720
Core_2_L2C_total_hit 39
Core_2_L2C_total_miss 681
Core_2_L2C_total_overlap_miss 681
Core_2_L2C_loads 633
Core_2_L2C_load_hit 0
Core_2_L2C_load_miss 633
Core_2_L2C_RFOs 48
Core_2_L2C_RFO_hit 0
Core_2_L2C_RFO_miss 48
Core_2_L2C_prefetches 0
Core_2_L2C_prefetch_hit 0
Core_2_L2C_prefetch_miss 0
Core_2_L2C_writebacks 39
Core_2_L2C_writeback_hit 39
Core_2_L2C_writeback_miss 0
Core_2_L2C_miss_rate 0.945833
Core_2_L2C_MPKI 6.81
Core_2_L2C_demand_miss 681
Core_2_L2C_prefetch_requested 0
Core_2_L2C_prefetch_issued 0
Core_2_L2C_prefetch_useful 0
Core_2_L2C_prefetch_useless 0
Core_2_L2C_prefetch_late 0
Core_2_L2C_average_miss_latency 373.184
Core_2_L2C_active_cycles 151313
Core_2_L2C_active_hit_cycles 15979
Core_2_L2C_active_miss_cycles 144124
Core_2_L2C_active_pure_miss_cycles 135334
Core_2_L2C_active_hit_miss_overlap_cycles 8790
Core_2_L2C_total_pure_miss 678
Core_2_L2C_pure_miss_rate 0.941667
Core_2_L2C_active_cycles_per_core 151313
Core_2_L2C_active_hit_cycles_per_core 15979
Core_2_L2C_active_miss_cycles_per_core 144124
Core_2_L2C_active_pure_miss_cycles_per_core 135334
Core_2_L2C_hit_miss_overlap_cycles_per_core 8790
Core_2_L2C_camat_per_core 210.157
Core_2_LLC_total_access 681
Core_2_LLC_total_hit 0
Core_2_LLC_total_miss 681
Core_2_LLC_total_overlap_miss 681
Core_2_LLC_loads 633
Core_2_LLC_load_hit 0
Core_2_LLC_load_miss 633
Core_2_LLC_RFOs 48
Core_2_LLC_RFO_hit 0
Core_2_LLC_RFO_miss 48
Core_2_LLC_prefetches 0
Core_2_LLC_prefetch_hit 0
Core_2_LLC_prefetch_miss 0
Core_2_LLC_writebacks 0
Core_2_LLC_writeback_hit 0
Core_2_LLC_writeback_miss 0
Core_2_LLC_miss_rate 1
Core_2_LLC_MPKI 6.81
Core_2_LLC_demand_miss 681
Core_2_LLC_prefetch_requested 0
Core_2_LLC_prefetch_issued 0
Core_2_LLC_prefetch_useful 0
Core_2_LLC_prefetch_useless 0
Core_2_LLC_prefetch_late 0
Core_2_LLC_average_miss_latency 1850.27
Core_2_LLC_active_cycles 400479
Core_2_LLC_active_hit_cycles 105011
Core_2_LLC_active_miss_cycles 390570
Core_2_LLC_active_pure_miss_cycles 295468
Core_2_LLC_active_hit_miss_overlap_cycles 95102
Core_2_LLC_total_pure_miss 681
Core_2_LLC_pure_miss_rate 1
Core_2_LLC_active_cycles_per_core 136351
Core_2_LLC_active_hit_cycles_per_core 16986
Core_2_LLC_active_miss_cycles_per_core 125108
Core_2_LLC_active_pure_miss_cycles_per_core 119365
Core_2_LLC_hit_miss_overlap_cycles_per_core 5743
Core_2_LLC_camat_per_core 200.222
Core_2_major_page_fault 0
Core_2_minor_page_fault 67
Core_3_instructions 100000
Core_3_cycles 424579
Core_3_IPC 0.235527
Core_3_branch_prediction_accuracy 90.9586
Core_3_branch_MPKI 16.4398
Core_3_average_ROB_occupancy_at_mispredict 57.2555
Core_3_L1D_total_access 33528
Core_3_L1D_total_hit 32612
Core_3_L1D_total_miss 916
Core_3_L1D_total_overlap_miss 916
Core_3_L1D_loads 19879
Core_3_L1D_load_hit 18976
Core_3_L1D_load_miss 903
Core_3_L1D_RFOs 13649
Core_3_L1D_RFO_hit 13636
Core_3_L1D_RFO_miss 13
Core_3_L1D_prefetches 0
Core_3_L1D_prefetch_hit 0
Core_3_L1D_prefetch_miss 0
Core_3_L1D_writebacks 0
Core_3_L1D_writeback_hit 0
Core_3_L1D_writeback_miss 0
Core_3_L1D_miss_rate 0.0273204
Core_3_L1D_MPKI 9.16
Core_3_L1D_demand_miss 916
Core_3_L1D_prefetch_requested 0
Core_3_L1D_prefetch_issued 0
Core_3_L1D_prefetch_useful 0
Core_3_L1D_prefetch_useless 0
Core_3_L1D_prefetch_late 0
Core_3_L1D_average_miss_latency 208.928
Core_3_L1D_active_cycles 281197
Core_3_L1D_active_hit_cycles 114300
Core_3_L1D_active_miss_cycles 182836
Core_3_L1D_active_pure_miss_cycles 166897
Core_3_L1D_active_hit_miss_overlap_cycles 15939
Core_3_L1D_total_pure_miss 916
Core_3_L1D_pure_miss_rate 0.0273204
Core_3_L1D_active_cycles_per_core 281197
Core_3_L1D_active_hit_cycles_per_core 114300
Core_3_L1D_active_miss_cycles_per_core 182836
Core_3_L1D_active_pure_miss_cycles_per_core 166897
Core_3_L1D_hit_miss_overlap_cycles_per_core 15939
Core_3_L1D_camat_per_core 8.38693
Core_3_L1I_total_access 18572
Core_3_L1I_total_hit 18382
Core_3_L1I_total_miss 190
Core_3_L1I_total_overlap_miss 190
Core_3_L1I_loads 18572
Core_3_L1I_load_hit 18382
Core_3_L1I_load_miss 190
Core_3_L1I_RFOs 0
Core_3_L1I_RFO_hit 0
Core_3_L1I_RFO_miss 0
Core_3_L1I_prefetches 0
Core_3_L1I_prefetch_hit 0
Core_3_L1I_prefetch_miss 0
Core_3_L1I_writebacks 0
Core_3_L1I_writeback_hit 0
Core_3_L1I_writeback_miss 0
Core_3_L1I_miss_rate 0.0102305
Core_3_L1I_MPKI 1.9
Core_3_L1I_demand_miss 190
Core_3_L1I_prefetch_requested 0
Core_3_L1I_prefetch_issued 0
Core_3_L1I_prefetch_useful 0
Core_3_L1I_prefetch_useless 0
Core_3_L1I_prefetch_late 0
Core_3_L1I_average_miss_latency 217.289
Core_3_L1I_active_cycles 44392
Core_3_L1I_active_hit_cycles 18431
Core_3_L1I_active_miss_cycles 26170
Core_3_L1I_active_pure_miss_cycles 25961
Core_3_L1I_active_hit_miss_overlap_cycles 209
Core_3_L1I_total_pure_miss 190
Core_3_L1I_pure_miss_rate 0.0102305
Core_3_L1I_active_cycles_per_core 44392
Core_3_L1I_active_hit_cycles_per_core 18431
Core_3_L1I_active_miss_cycles_per_core 26170
Core_3_L1I_active_pure_miss_cycles_per_core 25961
Core_3_L1I_hit_miss_overlap_cycles_per_core 209
Core_3_L1I_camat_per_core 2.39026
Core_3_L2C_total_access 1124
Core_3_L2C_total_hit 35
Core_3_L2C_total_miss 1089
Core_3_L2C_total_overlap_miss 1089
Core_3_L2C_loads 1093
Core_3_L2C_load_hit 16
Core_3_L2C_load_miss 1077
Core_3_L2C_RFOs 13
Core_3_L2C_RFO_hit 1
Core_3_L2C_RFO_miss 12
Core_3_L2C_prefetches 0
Core_3_L2C_prefetch_hit 0