diff --git a/4dis.txt b/4dis.txt new file mode 100644 index 0000000..17e61f5 --- /dev/null +++ b/4dis.txt @@ -0,0 +1,1083 @@ +************************************************* + ChampSim Multicore Out-of-Order Simulator + Last compiled: Mar 20 2022 18:18:42 +************************************************* + DRAM access latency: 170 +Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s + DRAM_DBUS_RETURN_TIME: 13 + +trace_0 ./traces/437.leslie3d-265B.champsimtrace.xz +trace_1 ./traces/429.mcf-22B.champsimtrace.xz +trace_2 ./traces/436.cactusADM-1804B.champsimtrace.xz +trace_3 ./traces/403.gcc-17B.champsimtrace.xz +warmup_instructions 1000 +simulation_instructions 100000 +champsim_seed 830 + +num_cpus 4 +cpu_freq 4000 +dram_io_freq 2400 +page_size 4096 +block_size 64 +max_read_per_cycle 20 +max_fill_per_cycle 20 +dram_channels 1 +dram_ranks 1 +dram_banks 8 +dram_rows 65536 +dram_columns 128 +dram_row_size 8 +dram_size 4096 +dram_pages 1048576 + +fetch_width 20 +decode_width 20 +exec_width 20 +lq_width 20 +sq_width 20 +retire_width 20 +scheduler_size 128 +branch_mispredict_penalty 20 +rob_size 256 +lq_size 72 +sq_size 56 +num_instr_destinations_sparc 4 +num_instr_destinations 2 +num_instr_sources 4 + +itlb_set 16 +itlb_way 8 +itlb_rq_size 16 +itlb_wq_size 16 +itlb_pq_size 0 +itlb_mshr_size 8 +itlb_latency 1 + +dtlb_set 16 +dtlb_way 4 +dtlb_rq_size 16 +dtlb_wq_size 16 +dtlb_pq_size 0 +dtlb_mshr_size 8 +dtlb_latency 1 + +stlb_set 128 +stlb_way 12 +stlb_rq_size 32 +stlb_wq_size 32 +stlb_pq_size 0 +stlb_mshr_size 16 +stlb_latency 8 + +l1i_size 32 +l1i_set 64 +l1i_way 8 +l1i_rq_size 64 +l1i_wq_size 64 +l1i_pq_size 8 +l1i_mshr_size 8 +l1i_latency 1 + +l1d_size 32 +l1d_set 64 +l1d_way 8 +l1d_rq_size 64 +l1d_wq_size 64 +l1d_pq_size 32 +l1d_mshr_size 16 +l1d_latency 4 + +l2c_size 256 +l2c_set 512 +l2c_way 8 +l2c_rq_size 32 +l2c_wq_size 32 +l2c_pq_size 16 +l2c_mshr_size 32 +l2c_latency 10 + +llc_size 8192 +llc_set 8192 +llc_way 16 +llc_rq_size 128 +llc_wq_size 128 +llc_pq_size 128 +llc_mshr_size 256 +llc_latency 20 + +dram_channel_width 8 +dram_wq_size 64 +dram_rq_size 64 +tRP 15 +tRCD 15 +tCAS 12.5 +dram_dbus_turn_around_time 30 +dram_write_high_wm 56 +dram_write_low_wm 48 +min_dram_writes_per_switch 16 +dram_mtps 2400 +dram_dbus_return_time 13 + + + +Warmup complete CPU 0 instructions: 6672 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 1 instructions: 5025 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 2 instructions: 4894 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 3 instructions: 1001 cycles: 2305 (Simulation time: 0 hr 0 min 0 sec) + +Finished CPU 0 instructions: 100015 cycles: 187720 cumulative IPC: 0.532788 (Simulation time: 0 hr 0 min 5 sec) +Finished CPU 1 instructions: 100017 cycles: 242354 cumulative IPC: 0.41269 (Simulation time: 0 hr 0 min 7 sec) +Finished CPU 2 instructions: 100006 cycles: 261955 cumulative IPC: 0.381768 (Simulation time: 0 hr 0 min 7 sec) +Finished CPU 3 instructions: 100000 cycles: 424579 cumulative IPC: 0.235527 (Simulation time: 0 hr 0 min 10 sec) + +ChampSim completed all CPUs + +Total Simulation Statistics (not including warmup) + +CPU 0 cumulative IPC: 0.663516 instructions: 281715 cycles: 424579 +Core_0_L1D_total_access 74885 +Core_0_L1D_total_hit 71502 +Core_0_L1D_total_miss 3383 +Core_0_L1D_loads 65502 +Core_0_L1D_load_hit 62902 +Core_0_L1D_load_miss 2600 +Core_0_L1D_RFOs 9383 +Core_0_L1D_RFO_hit 8600 +Core_0_L1D_RFO_miss 783 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 + +Core_0_L1I_total_access 48572 +Core_0_L1I_total_hit 48528 +Core_0_L1I_total_miss 44 +Core_0_L1I_loads 48572 +Core_0_L1I_load_hit 48528 +Core_0_L1I_load_miss 44 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 + +Core_0_L2C_total_access 4354 +Core_0_L2C_total_hit 2205 +Core_0_L2C_total_miss 2149 +Core_0_L2C_loads 2644 +Core_0_L2C_load_hit 835 +Core_0_L2C_load_miss 1809 +Core_0_L2C_RFOs 783 +Core_0_L2C_RFO_hit 443 +Core_0_L2C_RFO_miss 340 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 927 +Core_0_L2C_writeback_hit 927 +Core_0_L2C_writeback_miss 0 + +Core_0_LLC_total_access 2149 +Core_0_LLC_total_hit 0 +Core_0_LLC_total_miss 2149 +Core_0_LLC_loads 1809 +Core_0_LLC_load_hit 0 +Core_0_LLC_load_miss 1809 +Core_0_LLC_RFOs 340 +Core_0_LLC_RFO_hit 0 +Core_0_LLC_RFO_miss 340 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 0 +Core_0_LLC_writeback_hit 0 +Core_0_LLC_writeback_miss 0 + + +CPU 1 cumulative IPC: 0.392554 instructions: 166670 cycles: 424579 +Core_1_L1D_total_access 56227 +Core_1_L1D_total_hit 52972 +Core_1_L1D_total_miss 3255 +Core_1_L1D_loads 20728 +Core_1_L1D_load_hit 17492 +Core_1_L1D_load_miss 3236 +Core_1_L1D_RFOs 35499 +Core_1_L1D_RFO_hit 35480 +Core_1_L1D_RFO_miss 19 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 + +Core_1_L1I_total_access 28964 +Core_1_L1I_total_hit 28964 +Core_1_L1I_total_miss 0 +Core_1_L1I_loads 28964 +Core_1_L1I_load_hit 28964 +Core_1_L1I_load_miss 0 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 + +Core_1_L2C_total_access 3939 +Core_1_L2C_total_hit 1269 +Core_1_L2C_total_miss 2670 +Core_1_L2C_loads 3187 +Core_1_L2C_load_hit 518 +Core_1_L2C_load_miss 2669 +Core_1_L2C_RFOs 19 +Core_1_L2C_RFO_hit 19 +Core_1_L2C_RFO_miss 0 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 733 +Core_1_L2C_writeback_hit 732 +Core_1_L2C_writeback_miss 1 + +Core_1_LLC_total_access 2675 +Core_1_LLC_total_hit 6 +Core_1_LLC_total_miss 2669 +Core_1_LLC_loads 2669 +Core_1_LLC_load_hit 0 +Core_1_LLC_load_miss 2669 +Core_1_LLC_RFOs 0 +Core_1_LLC_RFO_hit 0 +Core_1_LLC_RFO_miss 0 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 6 +Core_1_LLC_writeback_hit 6 +Core_1_LLC_writeback_miss 0 + + +CPU 2 cumulative IPC: 0.396725 instructions: 168441 cycles: 424579 +Core_2_L1D_total_access 81023 +Core_2_L1D_total_hit 79980 +Core_2_L1D_total_miss 1043 +Core_2_L1D_loads 54503 +Core_2_L1D_load_hit 53544 +Core_2_L1D_load_miss 959 +Core_2_L1D_RFOs 26520 +Core_2_L1D_RFO_hit 26436 +Core_2_L1D_RFO_miss 84 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 + +Core_2_L1I_total_access 38872 +Core_2_L1I_total_hit 38819 +Core_2_L1I_total_miss 53 +Core_2_L1I_loads 38872 +Core_2_L1I_load_hit 38819 +Core_2_L1I_load_miss 53 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 + +Core_2_L2C_total_access 1168 +Core_2_L2C_total_hit 89 +Core_2_L2C_total_miss 1079 +Core_2_L2C_loads 1012 +Core_2_L2C_load_hit 17 +Core_2_L2C_load_miss 995 +Core_2_L2C_RFOs 84 +Core_2_L2C_RFO_hit 0 +Core_2_L2C_RFO_miss 84 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 72 +Core_2_L2C_writeback_hit 72 +Core_2_L2C_writeback_miss 0 + +Core_2_LLC_total_access 1079 +Core_2_LLC_total_hit 0 +Core_2_LLC_total_miss 1079 +Core_2_LLC_loads 995 +Core_2_LLC_load_hit 0 +Core_2_LLC_load_miss 995 +Core_2_LLC_RFOs 84 +Core_2_LLC_RFO_hit 0 +Core_2_LLC_RFO_miss 84 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 0 +Core_2_LLC_writeback_hit 0 +Core_2_LLC_writeback_miss 0 + + +CPU 3 cumulative IPC: 0.235527 instructions: 100000 cycles: 424579 +Core_3_L1D_total_access 33528 +Core_3_L1D_total_hit 32612 +Core_3_L1D_total_miss 916 +Core_3_L1D_loads 19879 +Core_3_L1D_load_hit 18976 +Core_3_L1D_load_miss 903 +Core_3_L1D_RFOs 13649 +Core_3_L1D_RFO_hit 13636 +Core_3_L1D_RFO_miss 13 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 + +Core_3_L1I_total_access 18572 +Core_3_L1I_total_hit 18382 +Core_3_L1I_total_miss 190 +Core_3_L1I_loads 18572 +Core_3_L1I_load_hit 18382 +Core_3_L1I_load_miss 190 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 + +Core_3_L2C_total_access 1124 +Core_3_L2C_total_hit 35 +Core_3_L2C_total_miss 1089 +Core_3_L2C_loads 1093 +Core_3_L2C_load_hit 16 +Core_3_L2C_load_miss 1077 +Core_3_L2C_RFOs 13 +Core_3_L2C_RFO_hit 1 +Core_3_L2C_RFO_miss 12 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 18 +Core_3_L2C_writeback_hit 18 +Core_3_L2C_writeback_miss 0 + +Core_3_LLC_total_access 1089 +Core_3_LLC_total_hit 0 +Core_3_LLC_total_miss 1089 +Core_3_LLC_loads 1077 +Core_3_LLC_load_hit 0 +Core_3_LLC_load_miss 1077 +Core_3_LLC_RFOs 12 +Core_3_LLC_RFO_hit 0 +Core_3_LLC_RFO_miss 12 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 0 +Core_3_LLC_writeback_hit 0 +Core_3_LLC_writeback_miss 0 + + +[ROI Statistics] +Core_0_instructions 100015 +Core_0_cycles 187720 +Core_0_IPC 0.532788 + +Core_0_branch_prediction_accuracy 98.9952 +Core_0_branch_MPKI 0.257493 +Core_0_average_ROB_occupancy_at_mispredict 212.203 + +Core_0_L1D_total_access 26646 +Core_0_L1D_total_hit 25319 +Core_0_L1D_total_miss 1327 +Core_0_L1D_total_overlap_miss 1327 +Core_0_L1D_loads 23455 +Core_0_L1D_load_hit 22424 +Core_0_L1D_load_miss 1031 +Core_0_L1D_RFOs 3191 +Core_0_L1D_RFO_hit 2895 +Core_0_L1D_RFO_miss 296 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 +Core_0_L1D_miss_rate 0.0498011 +Core_0_L1D_MPKI 13.27 +Core_0_L1D_demand_miss 1327 +Core_0_L1D_prefetch_requested 0 +Core_0_L1D_prefetch_issued 0 +Core_0_L1D_prefetch_useful 0 +Core_0_L1D_prefetch_useless 0 +Core_0_L1D_prefetch_late 0 +Core_0_L1D_average_miss_latency 398.213 +Core_0_L1D_active_cycles 386812 +Core_0_L1D_active_hit_cycles 164407 +Core_0_L1D_active_miss_cycles 294735 +Core_0_L1D_active_pure_miss_cycles 222405 +Core_0_L1D_active_hit_miss_overlap_cycles 72330 +Core_0_L1D_total_pure_miss 1291 +Core_0_L1D_pure_miss_rate 0.04845 +Core_0_L1D_active_cycles_per_core 386812 +Core_0_L1D_active_hit_cycles_per_core 164407 +Core_0_L1D_active_miss_cycles_per_core 294735 +Core_0_L1D_active_pure_miss_cycles_per_core 222405 +Core_0_L1D_hit_miss_overlap_cycles_per_core 72330 +Core_0_L1D_camat_per_core 14.5167 + +Core_0_L1I_total_access 17216 +Core_0_L1I_total_hit 17172 +Core_0_L1I_total_miss 44 +Core_0_L1I_total_overlap_miss 44 +Core_0_L1I_loads 17216 +Core_0_L1I_load_hit 17172 +Core_0_L1I_load_miss 44 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 +Core_0_L1I_miss_rate 0.00255576 +Core_0_L1I_MPKI 0.44 +Core_0_L1I_demand_miss 44 +Core_0_L1I_prefetch_requested 0 +Core_0_L1I_prefetch_issued 0 +Core_0_L1I_prefetch_useful 0 +Core_0_L1I_prefetch_useless 0 +Core_0_L1I_prefetch_late 0 +Core_0_L1I_average_miss_latency 255.886 +Core_0_L1I_active_cycles 70696 +Core_0_L1I_active_hit_cycles 67317 +Core_0_L1I_active_miss_cycles 3904 +Core_0_L1I_active_pure_miss_cycles 3379 +Core_0_L1I_active_hit_miss_overlap_cycles 525 +Core_0_L1I_total_pure_miss 39 +Core_0_L1I_pure_miss_rate 0.00226533 +Core_0_L1I_active_cycles_per_core 70696 +Core_0_L1I_active_hit_cycles_per_core 67317 +Core_0_L1I_active_miss_cycles_per_core 3904 +Core_0_L1I_active_pure_miss_cycles_per_core 3379 +Core_0_L1I_hit_miss_overlap_cycles_per_core 525 +Core_0_L1I_camat_per_core 4.10641 + +Core_0_L2C_total_access 1656 +Core_0_L2C_total_hit 499 +Core_0_L2C_total_miss 1157 +Core_0_L2C_total_overlap_miss 1157 +Core_0_L2C_loads 1075 +Core_0_L2C_load_hit 98 +Core_0_L2C_load_miss 977 +Core_0_L2C_RFOs 296 +Core_0_L2C_RFO_hit 116 +Core_0_L2C_RFO_miss 180 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 285 +Core_0_L2C_writeback_hit 285 +Core_0_L2C_writeback_miss 0 +Core_0_L2C_miss_rate 0.698671 +Core_0_L2C_MPKI 11.57 +Core_0_L2C_demand_miss 1157 +Core_0_L2C_prefetch_requested 0 +Core_0_L2C_prefetch_issued 0 +Core_0_L2C_prefetch_useful 0 +Core_0_L2C_prefetch_useless 0 +Core_0_L2C_prefetch_late 0 +Core_0_L2C_average_miss_latency 423.759 +Core_0_L2C_active_cycles 294414 +Core_0_L2C_active_hit_cycles 41974 +Core_0_L2C_active_miss_cycles 270734 +Core_0_L2C_active_pure_miss_cycles 252440 +Core_0_L2C_active_hit_miss_overlap_cycles 18294 +Core_0_L2C_total_pure_miss 1157 +Core_0_L2C_pure_miss_rate 0.698671 +Core_0_L2C_active_cycles_per_core 294414 +Core_0_L2C_active_hit_cycles_per_core 41974 +Core_0_L2C_active_miss_cycles_per_core 270734 +Core_0_L2C_active_pure_miss_cycles_per_core 252440 +Core_0_L2C_hit_miss_overlap_cycles_per_core 18294 +Core_0_L2C_camat_per_core 177.786 + +Core_0_LLC_total_access 1157 +Core_0_LLC_total_hit 0 +Core_0_LLC_total_miss 1157 +Core_0_LLC_total_overlap_miss 1157 +Core_0_LLC_loads 977 +Core_0_LLC_load_hit 0 +Core_0_LLC_load_miss 977 +Core_0_LLC_RFOs 180 +Core_0_LLC_RFO_hit 0 +Core_0_LLC_RFO_miss 180 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 0 +Core_0_LLC_writeback_hit 0 +Core_0_LLC_writeback_miss 0 +Core_0_LLC_miss_rate 1 +Core_0_LLC_MPKI 11.57 +Core_0_LLC_demand_miss 1157 +Core_0_LLC_prefetch_requested 0 +Core_0_LLC_prefetch_issued 0 +Core_0_LLC_prefetch_useful 0 +Core_0_LLC_prefetch_useless 0 +Core_0_LLC_prefetch_late 0 +Core_0_LLC_average_miss_latency 1089.05 +Core_0_LLC_active_cycles 400479 +Core_0_LLC_active_hit_cycles 105011 +Core_0_LLC_active_miss_cycles 390570 +Core_0_LLC_active_pure_miss_cycles 295468 +Core_0_LLC_active_hit_miss_overlap_cycles 95102 +Core_0_LLC_total_pure_miss 1157 +Core_0_LLC_pure_miss_rate 1 +Core_0_LLC_active_cycles_per_core 261954 +Core_0_LLC_active_hit_cycles_per_core 37595 +Core_0_LLC_active_miss_cycles_per_core 244613 +Core_0_LLC_active_pure_miss_cycles_per_core 224359 +Core_0_LLC_hit_miss_overlap_cycles_per_core 20254 +Core_0_LLC_camat_per_core 226.408 + +Core_0_major_page_fault 0 +Core_0_minor_page_fault 72 + +Core_1_instructions 100017 +Core_1_cycles 242354 +Core_1_IPC 0.41269 + +Core_1_branch_prediction_accuracy 96.2138 +Core_1_branch_MPKI 3.22798 +Core_1_average_ROB_occupancy_at_mispredict 93.755 + +Core_1_L1D_total_access 33726 +Core_1_L1D_total_hit 32022 +Core_1_L1D_total_miss 1704 +Core_1_L1D_total_overlap_miss 1704 +Core_1_L1D_loads 12345 +Core_1_L1D_load_hit 10643 +Core_1_L1D_load_miss 1702 +Core_1_L1D_RFOs 21381 +Core_1_L1D_RFO_hit 21379 +Core_1_L1D_RFO_miss 2 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 +Core_1_L1D_miss_rate 0.0505248 +Core_1_L1D_MPKI 17.04 +Core_1_L1D_demand_miss 1704 +Core_1_L1D_prefetch_requested 0 +Core_1_L1D_prefetch_issued 0 +Core_1_L1D_prefetch_useful 0 +Core_1_L1D_prefetch_useless 0 +Core_1_L1D_prefetch_late 0 +Core_1_L1D_average_miss_latency 335.523 +Core_1_L1D_active_cycles 383920 +Core_1_L1D_active_hit_cycles 84626 +Core_1_L1D_active_miss_cycles 319897 +Core_1_L1D_active_pure_miss_cycles 299294 +Core_1_L1D_active_hit_miss_overlap_cycles 20603 +Core_1_L1D_total_pure_miss 1676 +Core_1_L1D_pure_miss_rate 0.0496946 +Core_1_L1D_active_cycles_per_core 383920 +Core_1_L1D_active_hit_cycles_per_core 84626 +Core_1_L1D_active_miss_cycles_per_core 319897 +Core_1_L1D_active_pure_miss_cycles_per_core 299294 +Core_1_L1D_hit_miss_overlap_cycles_per_core 20603 +Core_1_L1D_camat_per_core 11.3835 + +Core_1_L1I_total_access 17470 +Core_1_L1I_total_hit 17470 +Core_1_L1I_total_miss 0 +Core_1_L1I_total_overlap_miss 0 +Core_1_L1I_loads 17470 +Core_1_L1I_load_hit 17470 +Core_1_L1I_load_miss 0 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 +Core_1_L1I_miss_rate 0 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+Core_3_LLC_prefetch_requested 0 +Core_3_LLC_prefetch_issued 0 +Core_3_LLC_prefetch_useful 0 +Core_3_LLC_prefetch_useless 0 +Core_3_LLC_prefetch_late 0 +Core_3_LLC_average_miss_latency 1157.06 +Core_3_LLC_active_cycles 400479 +Core_3_LLC_active_hit_cycles 105011 +Core_3_LLC_active_miss_cycles 390570 +Core_3_LLC_active_pure_miss_cycles 295468 +Core_3_LLC_active_hit_miss_overlap_cycles 95102 +Core_3_LLC_total_pure_miss 1089 +Core_3_LLC_pure_miss_rate 1 +Core_3_LLC_active_cycles_per_core 181314 +Core_3_LLC_active_hit_cycles_per_core 20786 +Core_3_LLC_active_miss_cycles_per_core 163009 +Core_3_LLC_active_pure_miss_cycles_per_core 160528 +Core_3_LLC_hit_miss_overlap_cycles_per_core 2481 +Core_3_LLC_camat_per_core 166.496 + +Core_3_major_page_fault 0 +Core_3_minor_page_fault 156 + +Channel_0_RQ_row_buffer_hit 1907 +Channel_0_RQ_row_buffer_miss 2911 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 815 +Channel_0_RQ_row_buffer_hit 494 +Channel_0_RQ_row_buffer_miss 1674 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 301 +avg_congested_cycle 0 8 +avg_congested_cycle 19 diff --git a/bin/perceptron-no-no-no-lru-4core b/bin/perceptron-no-no-no-lru-4core index 676751d..11c3dab 100755 Binary files a/bin/perceptron-no-no-no-lru-4core and b/bin/perceptron-no-no-no-lru-4core differ diff --git a/dram-nvram-2blsize.txt b/dram-nvram-2blsize.txt new file mode 100644 index 0000000..95c2437 --- /dev/null +++ b/dram-nvram-2blsize.txt @@ -0,0 +1,1150 @@ +************************************************* + ChampSim Multicore Out-of-Order Simulator + Last compiled: Mar 27 2022 21:13:30 +************************************************* + DRAM access latency: 170 + NVRAM access latency: 236 +Off-chip DRAM Size: 16384 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s +Off-chip NVRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 1600 MT/s + DRAM_DBUS_RETURN_TIME: 13 + NVRAM_DBUS_RETURN_TIME: 20 + +trace_0 ./traces/403.gcc-17B.champsimtrace.xz +trace_1 ./traces/403.gcc-17B.champsimtrace.xz +trace_2 ./traces/403.gcc-17B.champsimtrace.xz +trace_3 ./traces/403.gcc-17B.champsimtrace.xz +warmup_instructions 100000 +simulation_instructions 10000000 +champsim_seed 680 + +num_cpus 4 +cpu_freq 4000 +dram_io_freq 2400 +nvram_io_freq 2400 +page_size 4096 +block_size 64 +max_read_per_cycle 20 +max_fill_per_cycle 20 +dram_channels 1 +dram_ranks 4 +dram_banks 8 +dram_rows 65536 +dram_columns 128 +dram_row_size 8 +dram_size 16384 +dram_pages 4194304 +NVram_channels 1 +NVram_ranks 1 +NVram_banks 8 +NVram_rows 65536 +NVram_columns 128 +NVram_row_size 8 +NVram_size 4096 +NVram_pages 1048576 + +fetch_width 20 +decode_width 20 +exec_width 20 +lq_width 20 +sq_width 20 +retire_width 20 +scheduler_size 128 +branch_mispredict_penalty 20 +rob_size 256 +lq_size 72 +sq_size 56 +num_instr_destinations_sparc 4 +num_instr_destinations 2 +num_instr_sources 4 + +itlb_set 16 +itlb_way 8 +itlb_rq_size 16 +itlb_wq_size 16 +itlb_pq_size 0 +itlb_mshr_size 8 +itlb_latency 1 + +dtlb_set 16 +dtlb_way 4 +dtlb_rq_size 16 +dtlb_wq_size 16 +dtlb_pq_size 0 +dtlb_mshr_size 8 +dtlb_latency 1 + +stlb_set 128 +stlb_way 12 +stlb_rq_size 32 +stlb_wq_size 32 +stlb_pq_size 0 +stlb_mshr_size 16 +stlb_latency 8 + +l1i_size 32 +l1i_set 64 +l1i_way 8 +l1i_rq_size 64 +l1i_wq_size 64 +l1i_pq_size 8 +l1i_mshr_size 8 +l1i_latency 1 + +l1d_size 32 +l1d_set 64 +l1d_way 8 +l1d_rq_size 64 +l1d_wq_size 64 +l1d_pq_size 32 +l1d_mshr_size 16 +l1d_latency 4 + +l2c_size 256 +l2c_set 512 +l2c_way 8 +l2c_rq_size 32 +l2c_wq_size 32 +l2c_pq_size 16 +l2c_mshr_size 32 +l2c_latency 10 + +llc_size 8192 +llc_set 8192 +llc_way 16 +llc_rq_size 128 +llc_wq_size 128 +llc_pq_size 128 +llc_mshr_size 256 +llc_latency 20 + +dram_channel_width 8 +dram_wq_size 64 +dram_rq_size 64 +tRP 15 +tRCD 15 +tCAS 12.5 +dram_dbus_turn_around_time 30 +dram_write_high_wm 56 +dram_write_low_wm 48 +min_dram_writes_per_switch 16 +dram_mtps 2400 +dram_dbus_return_time 13 + +NVram_channel_width 8 +NVram_wq_size 128 +NVram_rq_size 128 +NV_tRP 22 +NV_tRCD 22 +NV_tCAS 15 +NVram_dbus_turn_around_time 36 +NVram_write_high_wm 112 +NVram_write_low_wm 96 +min_NVram_writes_per_switch 16 +NVram_mtps 1600 +NVram_dbus_return_time 20 + + + +Warmup complete CPU 0 instructions: 100093 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 1 instructions: 100058 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 2 instructions: 100034 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 3 instructions: 100001 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) + +Heartbeat CPU 1 instructions: 1000002 cycles: 2822358 heartbeat IPC: 0.35431 cumulative IPC: 0.32907 (Simulation time: 0 hr 0 min 38 sec) +Heartbeat CPU 0 instructions: 1000002 cycles: 2822409 heartbeat IPC: 0.35431 cumulative IPC: 0.32905 (Simulation time: 0 hr 0 min 38 sec) +Heartbeat CPU 3 instructions: 1000002 cycles: 3366711 heartbeat IPC: 0.29703 cumulative IPC: 0.27446 (Simulation time: 0 hr 0 min 46 sec) +Heartbeat CPU 2 instructions: 1000002 cycles: 3366772 heartbeat IPC: 0.29702 cumulative IPC: 0.27444 (Simulation time: 0 hr 0 min 46 sec) +Heartbeat CPU 0 instructions: 2000002 cycles: 5783210 heartbeat IPC: 0.33775 cumulative IPC: 0.33357 (Simulation time: 0 hr 1 min 25 sec) +Heartbeat CPU 1 instructions: 2000002 cycles: 5783261 heartbeat IPC: 0.33773 cumulative IPC: 0.33357 (Simulation time: 0 hr 1 min 25 sec) +Heartbeat CPU 2 instructions: 2000002 cycles: 6926570 heartbeat IPC: 0.28091 cumulative IPC: 0.27781 (Simulation time: 0 hr 1 min 44 sec) +Heartbeat CPU 3 instructions: 2000002 cycles: 6926631 heartbeat IPC: 0.28091 cumulative IPC: 0.27781 (Simulation time: 0 hr 1 min 44 sec) +Heartbeat CPU 0 instructions: 3000013 cycles: 8743635 heartbeat IPC: 0.33779 cumulative IPC: 0.33501 (Simulation time: 0 hr 2 min 16 sec) +Heartbeat CPU 1 instructions: 3000013 cycles: 8743686 heartbeat IPC: 0.33779 cumulative IPC: 0.33502 (Simulation time: 0 hr 2 min 16 sec) +Heartbeat CPU 2 instructions: 3000013 cycles: 10469880 heartbeat IPC: 0.28223 cumulative IPC: 0.27932 (Simulation time: 0 hr 2 min 46 sec) +Heartbeat CPU 3 instructions: 3000013 cycles: 10469941 heartbeat IPC: 0.28223 cumulative IPC: 0.27932 (Simulation time: 0 hr 2 min 46 sec) +Heartbeat CPU 1 instructions: 4000000 cycles: 11712428 heartbeat IPC: 0.33684 cumulative IPC: 0.33548 (Simulation time: 0 hr 3 min 10 sec) +Heartbeat CPU 0 instructions: 4000000 cycles: 11712479 heartbeat IPC: 0.33683 cumulative IPC: 0.33548 (Simulation time: 0 hr 3 min 10 sec) +Heartbeat CPU 2 instructions: 4000000 cycles: 14045388 heartbeat IPC: 0.27968 cumulative IPC: 0.27941 (Simulation time: 0 hr 3 min 56 sec) +Heartbeat CPU 3 instructions: 4000000 cycles: 14045449 heartbeat IPC: 0.27968 cumulative IPC: 0.27941 (Simulation time: 0 hr 3 min 56 sec) +Heartbeat CPU 0 instructions: 5000000 cycles: 14746593 heartbeat IPC: 0.32959 cumulative IPC: 0.33426 (Simulation time: 0 hr 4 min 10 sec) +Heartbeat CPU 1 instructions: 5000000 cycles: 14746644 heartbeat IPC: 0.32957 cumulative IPC: 0.33426 (Simulation time: 0 hr 4 min 10 sec) +Heartbeat CPU 1 instructions: 6000004 cycles: 17689749 heartbeat IPC: 0.33978 cumulative IPC: 0.33518 (Simulation time: 0 hr 5 min 12 sec) +Heartbeat CPU 0 instructions: 6000004 cycles: 17689800 heartbeat IPC: 0.33977 cumulative IPC: 0.33518 (Simulation time: 0 hr 5 min 12 sec) +Heartbeat CPU 2 instructions: 5000000 cycles: 17771431 heartbeat IPC: 0.26838 cumulative IPC: 0.27709 (Simulation time: 0 hr 5 min 14 sec) +Heartbeat CPU 3 instructions: 5000000 cycles: 17771492 heartbeat IPC: 0.26838 cumulative IPC: 0.27709 (Simulation time: 0 hr 5 min 14 sec) +Heartbeat CPU 0 instructions: 7000002 cycles: 20640536 heartbeat IPC: 0.33890 cumulative IPC: 0.33571 (Simulation time: 0 hr 6 min 16 sec) +Heartbeat CPU 1 instructions: 7000002 cycles: 20640587 heartbeat IPC: 0.33889 cumulative IPC: 0.33571 (Simulation time: 0 hr 6 min 16 sec) +Heartbeat CPU 3 instructions: 6000004 cycles: 21365698 heartbeat IPC: 0.27823 cumulative IPC: 0.27728 (Simulation time: 0 hr 6 min 32 sec) +Heartbeat CPU 2 instructions: 6000004 cycles: 21365759 heartbeat IPC: 0.27822 cumulative IPC: 0.27728 (Simulation time: 0 hr 6 min 32 sec) +Heartbeat CPU 1 instructions: 8000000 cycles: 23580832 heartbeat IPC: 0.34011 cumulative IPC: 0.33626 (Simulation time: 0 hr 7 min 21 sec) +Heartbeat CPU 0 instructions: 8000000 cycles: 23580883 heartbeat IPC: 0.34010 cumulative IPC: 0.33626 (Simulation time: 0 hr 7 min 21 sec) +Heartbeat CPU 3 instructions: 7000002 cycles: 24915251 heartbeat IPC: 0.28173 cumulative IPC: 0.27792 (Simulation time: 0 hr 7 min 51 sec) +Heartbeat CPU 2 instructions: 7000002 cycles: 24915312 heartbeat IPC: 0.28173 cumulative IPC: 0.27791 (Simulation time: 0 hr 7 min 51 sec) +Heartbeat CPU 1 instructions: 9000000 cycles: 26548580 heartbeat IPC: 0.33696 cumulative IPC: 0.33634 (Simulation time: 0 hr 8 min 27 sec) +Heartbeat CPU 0 instructions: 9000000 cycles: 26548653 heartbeat IPC: 0.33695 cumulative IPC: 0.33634 (Simulation time: 0 hr 8 min 27 sec) +Heartbeat CPU 3 instructions: 8000000 cycles: 28498682 heartbeat IPC: 0.27906 cumulative IPC: 0.27806 (Simulation time: 0 hr 9 min 8 sec) +Heartbeat CPU 2 instructions: 8000000 cycles: 28498743 heartbeat IPC: 0.27906 cumulative IPC: 0.27806 (Simulation time: 0 hr 9 min 8 sec) +Heartbeat CPU 1 instructions: 10000014 cycles: 29549435 heartbeat IPC: 0.33324 cumulative IPC: 0.33603 (Simulation time: 0 hr 9 min 31 sec) +Heartbeat CPU 0 instructions: 10000014 cycles: 29549675 heartbeat IPC: 0.33322 cumulative IPC: 0.33602 (Simulation time: 0 hr 9 min 31 sec) +Finished CPU 1 instructions: 10000016 cycles: 29785354 cumulative IPC: 0.33574 (Simulation time: 0 hr 9 min 39 sec) +Finished CPU 0 instructions: 10000013 cycles: 29785441 cumulative IPC: 0.33573 (Simulation time: 0 hr 9 min 39 sec) +Heartbeat CPU 2 instructions: 9000000 cycles: 32088145 heartbeat IPC: 0.27860 cumulative IPC: 0.27812 (Simulation time: 0 hr 10 min 27 sec) +Heartbeat CPU 3 instructions: 9000000 cycles: 32088206 heartbeat IPC: 0.27859 cumulative IPC: 0.27812 (Simulation time: 0 hr 10 min 27 sec) +Heartbeat CPU 1 instructions: 11000011 cycles: 34410732 heartbeat IPC: 0.20571 cumulative IPC: 0.31757 (Simulation time: 0 hr 11 min 16 sec) +Heartbeat CPU 0 instructions: 11000011 cycles: 34410783 heartbeat IPC: 0.20571 cumulative IPC: 0.31757 (Simulation time: 0 hr 11 min 16 sec) +Heartbeat CPU 3 instructions: 10000013 cycles: 35676633 heartbeat IPC: 0.27868 cumulative IPC: 0.27818 (Simulation time: 0 hr 11 min 43 sec) +Heartbeat CPU 2 instructions: 10000013 cycles: 35676694 heartbeat IPC: 0.27867 cumulative IPC: 0.27817 (Simulation time: 0 hr 11 min 43 sec) +Finished CPU 3 instructions: 10000001 cycles: 35977452 cumulative IPC: 0.27795 (Simulation time: 0 hr 11 min 51 sec) +Finished CPU 2 instructions: 10000000 cycles: 35978583 cumulative IPC: 0.27794 (Simulation time: 0 hr 11 min 51 sec) + +ChampSim completed all CPUs + +Total Simulation Statistics (not including warmup) + +CPU 0 cumulative IPC: 0.31329 instructions: 11271859 cycles: 35978583 +Core_0_L1D_total_access 3679191 +Core_0_L1D_total_hit 3578029 +Core_0_L1D_total_miss 101162 +Core_0_L1D_loads 2154095 +Core_0_L1D_load_hit 2053821 +Core_0_L1D_load_miss 100274 +Core_0_L1D_RFOs 1525096 +Core_0_L1D_RFO_hit 1524208 +Core_0_L1D_RFO_miss 888 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 + +Core_0_L1I_total_access 2472822 +Core_0_L1I_total_hit 2471819 +Core_0_L1I_total_miss 1003 +Core_0_L1I_loads 2472822 +Core_0_L1I_load_hit 2471819 +Core_0_L1I_load_miss 1003 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 + +Core_0_L2C_total_access 106341 +Core_0_L2C_total_hit 8552 +Core_0_L2C_total_miss 97789 +Core_0_L2C_loads 101277 +Core_0_L2C_load_hit 4138 +Core_0_L2C_load_miss 97139 +Core_0_L2C_RFOs 888 +Core_0_L2C_RFO_hit 348 +Core_0_L2C_RFO_miss 540 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 4176 +Core_0_L2C_writeback_hit 4066 +Core_0_L2C_writeback_miss 110 + +Core_0_LLC_total_access 100930 +Core_0_LLC_total_hit 5339 +Core_0_LLC_total_miss 95591 +Core_0_LLC_loads 97139 +Core_0_LLC_load_hit 2049 +Core_0_LLC_load_miss 95090 +Core_0_LLC_RFOs 540 +Core_0_LLC_RFO_hit 68 +Core_0_LLC_RFO_miss 472 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 3251 +Core_0_LLC_writeback_hit 3222 +Core_0_LLC_writeback_miss 29 + + +CPU 1 cumulative IPC: 0.31329 instructions: 11271894 cycles: 35978583 +Core_1_L1D_total_access 3679433 +Core_1_L1D_total_hit 3578270 +Core_1_L1D_total_miss 101163 +Core_1_L1D_loads 2154198 +Core_1_L1D_load_hit 2053923 +Core_1_L1D_load_miss 100275 +Core_1_L1D_RFOs 1525235 +Core_1_L1D_RFO_hit 1524347 +Core_1_L1D_RFO_miss 888 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 + +Core_1_L1I_total_access 2473082 +Core_1_L1I_total_hit 2472079 +Core_1_L1I_total_miss 1003 +Core_1_L1I_loads 2473082 +Core_1_L1I_load_hit 2472079 +Core_1_L1I_load_miss 1003 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 + +Core_1_L2C_total_access 106343 +Core_1_L2C_total_hit 8570 +Core_1_L2C_total_miss 97773 +Core_1_L2C_loads 101278 +Core_1_L2C_load_hit 4156 +Core_1_L2C_load_miss 97122 +Core_1_L2C_RFOs 888 +Core_1_L2C_RFO_hit 345 +Core_1_L2C_RFO_miss 543 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 4177 +Core_1_L2C_writeback_hit 4069 +Core_1_L2C_writeback_miss 108 + +Core_1_LLC_total_access 100900 +Core_1_LLC_total_hit 5328 +Core_1_LLC_total_miss 95572 +Core_1_LLC_loads 97122 +Core_1_LLC_load_hit 2051 +Core_1_LLC_load_miss 95071 +Core_1_LLC_RFOs 543 +Core_1_LLC_RFO_hit 70 +Core_1_LLC_RFO_miss 473 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 3235 +Core_1_LLC_writeback_hit 3207 +Core_1_LLC_writeback_miss 28 + + +CPU 2 cumulative IPC: 0.27794 instructions: 10000000 cycles: 35978583 +Core_2_L1D_total_access 3228616 +Core_2_L1D_total_hit 3150461 +Core_2_L1D_total_miss 78155 +Core_2_L1D_loads 1875030 +Core_2_L1D_load_hit 1797511 +Core_2_L1D_load_miss 77519 +Core_2_L1D_RFOs 1353586 +Core_2_L1D_RFO_hit 1352950 +Core_2_L1D_RFO_miss 636 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 + +Core_2_L1I_total_access 2218606 +Core_2_L1I_total_hit 2217745 +Core_2_L1I_total_miss 861 +Core_2_L1I_loads 2218606 +Core_2_L1I_load_hit 2217745 +Core_2_L1I_load_miss 861 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 + +Core_2_L2C_total_access 81988 +Core_2_L2C_total_hit 6499 +Core_2_L2C_total_miss 75489 +Core_2_L2C_loads 78380 +Core_2_L2C_load_hit 3273 +Core_2_L2C_load_miss 75107 +Core_2_L2C_RFOs 636 +Core_2_L2C_RFO_hit 323 +Core_2_L2C_RFO_miss 313 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 2972 +Core_2_L2C_writeback_hit 2903 +Core_2_L2C_writeback_miss 69 + +Core_2_LLC_total_access 77441 +Core_2_LLC_total_hit 2659 +Core_2_LLC_total_miss 74782 +Core_2_LLC_loads 75107 +Core_2_LLC_load_hit 612 +Core_2_LLC_load_miss 74495 +Core_2_LLC_RFOs 313 +Core_2_LLC_RFO_hit 42 +Core_2_LLC_RFO_miss 271 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 2021 +Core_2_LLC_writeback_hit 2005 +Core_2_LLC_writeback_miss 16 + + +CPU 3 cumulative IPC: 0.27794 instructions: 10000032 cycles: 35978583 +Core_3_L1D_total_access 3228704 +Core_3_L1D_total_hit 3150546 +Core_3_L1D_total_miss 78158 +Core_3_L1D_loads 1875108 +Core_3_L1D_load_hit 1797586 +Core_3_L1D_load_miss 77522 +Core_3_L1D_RFOs 1353596 +Core_3_L1D_RFO_hit 1352960 +Core_3_L1D_RFO_miss 636 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 + +Core_3_L1I_total_access 2218664 +Core_3_L1I_total_hit 2217803 +Core_3_L1I_total_miss 861 +Core_3_L1I_loads 2218664 +Core_3_L1I_load_hit 2217803 +Core_3_L1I_load_miss 861 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 + +Core_3_L2C_total_access 81990 +Core_3_L2C_total_hit 6462 +Core_3_L2C_total_miss 75528 +Core_3_L2C_loads 78383 +Core_3_L2C_load_hit 3237 +Core_3_L2C_load_miss 75146 +Core_3_L2C_RFOs 636 +Core_3_L2C_RFO_hit 315 +Core_3_L2C_RFO_miss 321 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 2971 +Core_3_L2C_writeback_hit 2910 +Core_3_L2C_writeback_miss 61 + +Core_3_LLC_total_access 77495 +Core_3_LLC_total_hit 2692 +Core_3_LLC_total_miss 74803 +Core_3_LLC_loads 75145 +Core_3_LLC_load_hit 628 +Core_3_LLC_load_miss 74517 +Core_3_LLC_RFOs 321 +Core_3_LLC_RFO_hit 47 +Core_3_LLC_RFO_miss 274 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 2029 +Core_3_LLC_writeback_hit 2017 +Core_3_LLC_writeback_miss 12 + + +[ROI Statistics] +Core_0_instructions 10000013 +Core_0_cycles 29785441 +Core_0_IPC 0.33573 + +Core_0_branch_prediction_accuracy 96.60997 +Core_0_branch_MPKI 6.21179 +Core_0_average_ROB_occupancy_at_mispredict 113.69815 + +Core_0_L1D_total_access 3238214 +Core_0_L1D_total_hit 3160058 +Core_0_L1D_total_miss 78156 +Core_0_L1D_total_overlap_miss 78156 +Core_0_L1D_loads 1881951 +Core_0_L1D_load_hit 1804431 +Core_0_L1D_load_miss 77520 +Core_0_L1D_RFOs 1356263 +Core_0_L1D_RFO_hit 1355627 +Core_0_L1D_RFO_miss 636 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 +Core_0_L1D_miss_rate 0.02414 +Core_0_L1D_MPKI 7.81560 +Core_0_L1D_demand_miss 78156 +Core_0_L1D_prefetch_requested 0 +Core_0_L1D_prefetch_issued 0 +Core_0_L1D_prefetch_useful 0 +Core_0_L1D_prefetch_useless 0 +Core_0_L1D_prefetch_late 0 +Core_0_L1D_average_miss_latency 196.42406 +Core_0_L1D_active_cycles 25165210 +Core_0_L1D_active_hit_cycles 12158039 +Core_0_L1D_active_miss_cycles 14628236 +Core_0_L1D_active_pure_miss_cycles 13007171 +Core_0_L1D_active_hit_miss_overlap_cycles 1621065 +Core_0_L1D_total_pure_miss 78138 +Core_0_L1D_pure_miss_rate 0.02413 +Core_0_L1D_active_cycles_per_core 25165210 +Core_0_L1D_active_hit_cycles_per_core 12158039 +Core_0_L1D_active_miss_cycles_per_core 14628236 +Core_0_L1D_active_pure_miss_cycles_per_core 13007171 +Core_0_L1D_hit_miss_overlap_cycles_per_core 1621065 +Core_0_L1D_camat_per_core 7.77132 + +Core_0_L1I_total_access 2223797 +Core_0_L1I_total_hit 2222936 +Core_0_L1I_total_miss 861 +Core_0_L1I_total_overlap_miss 861 +Core_0_L1I_loads 2223797 +Core_0_L1I_load_hit 2222936 +Core_0_L1I_load_miss 861 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 +Core_0_L1I_miss_rate 0.00039 +Core_0_L1I_MPKI 0.08610 +Core_0_L1I_demand_miss 861 +Core_0_L1I_prefetch_requested 0 +Core_0_L1I_prefetch_issued 0 +Core_0_L1I_prefetch_useful 0 +Core_0_L1I_prefetch_useless 0 +Core_0_L1I_prefetch_late 0 +Core_0_L1I_average_miss_latency 103.02904 +Core_0_L1I_active_cycles 2971338 +Core_0_L1I_active_hit_cycles 2906603 +Core_0_L1I_active_miss_cycles 68408 +Core_0_L1I_active_pure_miss_cycles 64735 +Core_0_L1I_active_hit_miss_overlap_cycles 3673 +Core_0_L1I_total_pure_miss 824 +Core_0_L1I_pure_miss_rate 0.00037 +Core_0_L1I_active_cycles_per_core 2971338 +Core_0_L1I_active_hit_cycles_per_core 2906603 +Core_0_L1I_active_miss_cycles_per_core 68408 +Core_0_L1I_active_pure_miss_cycles_per_core 64735 +Core_0_L1I_hit_miss_overlap_cycles_per_core 3673 +Core_0_L1I_camat_per_core 1.33616 + +Core_0_L2C_total_access 81988 +Core_0_L2C_total_hit 6435 +Core_0_L2C_total_miss 75553 +Core_0_L2C_total_overlap_miss 75473 +Core_0_L2C_loads 78381 +Core_0_L2C_load_hit 3232 +Core_0_L2C_load_miss 75149 +Core_0_L2C_RFOs 636 +Core_0_L2C_RFO_hit 312 +Core_0_L2C_RFO_miss 324 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 2971 +Core_0_L2C_writeback_hit 2891 +Core_0_L2C_writeback_miss 80 +Core_0_L2C_miss_rate 0.92151 +Core_0_L2C_MPKI 7.55530 +Core_0_L2C_demand_miss 75553 +Core_0_L2C_prefetch_requested 0 +Core_0_L2C_prefetch_issued 0 +Core_0_L2C_prefetch_useful 0 +Core_0_L2C_prefetch_useless 0 +Core_0_L2C_prefetch_late 0 +Core_0_L2C_average_miss_latency 184.87916 +Core_0_L2C_active_cycles 14357381 +Core_0_L2C_active_hit_cycles 1180466 +Core_0_L2C_active_miss_cycles 13321875 +Core_0_L2C_active_pure_miss_cycles 13176915 +Core_0_L2C_active_hit_miss_overlap_cycles 144960 +Core_0_L2C_total_pure_miss 75473 +Core_0_L2C_pure_miss_rate 0.92054 +Core_0_L2C_active_cycles_per_core 14357381 +Core_0_L2C_active_hit_cycles_per_core 1180466 +Core_0_L2C_active_miss_cycles_per_core 13321875 +Core_0_L2C_active_pure_miss_cycles_per_core 13176915 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+Core_2_LLC_total_access 77441 +Core_2_LLC_total_hit 2659 +Core_2_LLC_total_miss 74782 +Core_2_LLC_total_overlap_miss 74766 +Core_2_LLC_loads 75107 +Core_2_LLC_load_hit 612 +Core_2_LLC_load_miss 74495 +Core_2_LLC_RFOs 313 +Core_2_LLC_RFO_hit 42 +Core_2_LLC_RFO_miss 271 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 2021 +Core_2_LLC_writeback_hit 2005 +Core_2_LLC_writeback_miss 16 +Core_2_LLC_miss_rate 0.96566 +Core_2_LLC_MPKI 7.47820 +Core_2_LLC_demand_miss 74782 +Core_2_LLC_prefetch_requested 0 +Core_2_LLC_prefetch_issued 0 +Core_2_LLC_prefetch_useful 0 +Core_2_LLC_prefetch_useless 0 +Core_2_LLC_prefetch_late 0 +Core_2_LLC_average_miss_latency 708.06939 +Core_2_LLC_active_cycles 27583584 +Core_2_LLC_active_hit_cycles 6849283 +Core_2_LLC_active_miss_cycles 26452269 +Core_2_LLC_active_pure_miss_cycles 20734301 +Core_2_LLC_active_hit_miss_overlap_cycles 5717968 +Core_2_LLC_total_pure_miss 74766 +Core_2_LLC_pure_miss_rate 0.96546 +Core_2_LLC_active_cycles_per_core 16133222 +Core_2_LLC_active_hit_cycles_per_core 1573202 +Core_2_LLC_active_miss_cycles_per_core 14681285 +Core_2_LLC_active_pure_miss_cycles_per_core 14560020 +Core_2_LLC_hit_miss_overlap_cycles_per_core 121265 +Core_2_LLC_camat_per_core 208.32921 + +Core_2_major_page_fault 0 +Core_2_minor_page_fault 3636 + +Core_3_instructions 10000001 +Core_3_cycles 35977452 +Core_3_IPC 0.27795 + +Core_3_branch_prediction_accuracy 96.77959 +Core_3_branch_MPKI 5.89828 +Core_3_average_ROB_occupancy_at_mispredict 118.17130 + +Core_3_L1D_total_access 3228681 +Core_3_L1D_total_hit 3150525 +Core_3_L1D_total_miss 78156 +Core_3_L1D_total_overlap_miss 78156 +Core_3_L1D_loads 1875094 +Core_3_L1D_load_hit 1797574 +Core_3_L1D_load_miss 77520 +Core_3_L1D_RFOs 1353587 +Core_3_L1D_RFO_hit 1352951 +Core_3_L1D_RFO_miss 636 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 +Core_3_L1D_miss_rate 0.02421 +Core_3_L1D_MPKI 7.81560 +Core_3_L1D_demand_miss 78156 +Core_3_L1D_prefetch_requested 0 +Core_3_L1D_prefetch_issued 0 +Core_3_L1D_prefetch_useful 0 +Core_3_L1D_prefetch_useless 0 +Core_3_L1D_prefetch_late 0 +Core_3_L1D_average_miss_latency 239.97598 +Core_3_L1D_active_cycles 26938996 +Core_3_L1D_active_hit_cycles 10543881 +Core_3_L1D_active_miss_cycles 17800731 +Core_3_L1D_active_pure_miss_cycles 16395115 +Core_3_L1D_active_hit_miss_overlap_cycles 1405616 +Core_3_L1D_total_pure_miss 78139 +Core_3_L1D_pure_miss_rate 0.02420 +Core_3_L1D_active_cycles_per_core 26938996 +Core_3_L1D_active_hit_cycles_per_core 10543881 +Core_3_L1D_active_miss_cycles_per_core 17800731 +Core_3_L1D_active_pure_miss_cycles_per_core 16395115 +Core_3_L1D_hit_miss_overlap_cycles_per_core 1405616 +Core_3_L1D_camat_per_core 8.34365 + +Core_3_L1I_total_access 2218652 +Core_3_L1I_total_hit 2217791 +Core_3_L1I_total_miss 861 +Core_3_L1I_total_overlap_miss 861 +Core_3_L1I_loads 2218652 +Core_3_L1I_load_hit 2217791 +Core_3_L1I_load_miss 861 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 +Core_3_L1I_miss_rate 0.00039 +Core_3_L1I_MPKI 0.08610 +Core_3_L1I_demand_miss 861 +Core_3_L1I_prefetch_requested 0 +Core_3_L1I_prefetch_issued 0 +Core_3_L1I_prefetch_useful 0 +Core_3_L1I_prefetch_useless 0 +Core_3_L1I_prefetch_late 0 +Core_3_L1I_average_miss_latency 106.81301 +Core_3_L1I_active_cycles 2661409 +Core_3_L1I_active_hit_cycles 2594659 +Core_3_L1I_active_miss_cycles 70204 +Core_3_L1I_active_pure_miss_cycles 66750 +Core_3_L1I_active_hit_miss_overlap_cycles 3454 +Core_3_L1I_total_pure_miss 833 +Core_3_L1I_pure_miss_rate 0.00038 +Core_3_L1I_active_cycles_per_core 2661409 +Core_3_L1I_active_hit_cycles_per_core 2594659 +Core_3_L1I_active_miss_cycles_per_core 70204 +Core_3_L1I_active_pure_miss_cycles_per_core 66750 +Core_3_L1I_hit_miss_overlap_cycles_per_core 3454 +Core_3_L1I_camat_per_core 1.19956 + +Core_3_L2C_total_access 81988 +Core_3_L2C_total_hit 6462 +Core_3_L2C_total_miss 75526 +Core_3_L2C_total_overlap_miss 75465 +Core_3_L2C_loads 78381 +Core_3_L2C_load_hit 3237 +Core_3_L2C_load_miss 75144 +Core_3_L2C_RFOs 636 +Core_3_L2C_RFO_hit 315 +Core_3_L2C_RFO_miss 321 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 2971 +Core_3_L2C_writeback_hit 2910 +Core_3_L2C_writeback_miss 61 +Core_3_L2C_miss_rate 0.92118 +Core_3_L2C_MPKI 7.55260 +Core_3_L2C_demand_miss 75526 +Core_3_L2C_prefetch_requested 0 +Core_3_L2C_prefetch_issued 0 +Core_3_L2C_prefetch_useful 0 +Core_3_L2C_prefetch_useless 0 +Core_3_L2C_prefetch_late 0 +Core_3_L2C_average_miss_latency 234.44684 +Core_3_L2C_active_cycles 17600161 +Core_3_L2C_active_hit_cycles 909193 +Core_3_L2C_active_miss_cycles 16800357 +Core_3_L2C_active_pure_miss_cycles 16690968 +Core_3_L2C_active_hit_miss_overlap_cycles 109389 +Core_3_L2C_total_pure_miss 75465 +Core_3_L2C_pure_miss_rate 0.92044 +Core_3_L2C_active_cycles_per_core 17600161 +Core_3_L2C_active_hit_cycles_per_core 909193 +Core_3_L2C_active_miss_cycles_per_core 16800357 +Core_3_L2C_active_pure_miss_cycles_per_core 16690968 +Core_3_L2C_hit_miss_overlap_cycles_per_core 109389 +Core_3_L2C_camat_per_core 214.66752 + +Core_3_LLC_total_access 77493 +Core_3_LLC_total_hit 2692 +Core_3_LLC_total_miss 74801 +Core_3_LLC_total_overlap_miss 74789 +Core_3_LLC_loads 75143 +Core_3_LLC_load_hit 628 +Core_3_LLC_load_miss 74515 +Core_3_LLC_RFOs 321 +Core_3_LLC_RFO_hit 47 +Core_3_LLC_RFO_miss 274 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 2029 +Core_3_LLC_writeback_hit 2017 +Core_3_LLC_writeback_miss 12 +Core_3_LLC_miss_rate 0.96526 +Core_3_LLC_MPKI 7.48010 +Core_3_LLC_demand_miss 74801 +Core_3_LLC_prefetch_requested 0 +Core_3_LLC_prefetch_issued 0 +Core_3_LLC_prefetch_useful 0 +Core_3_LLC_prefetch_useless 0 +Core_3_LLC_prefetch_late 0 +Core_3_LLC_average_miss_latency 707.88953 +Core_3_LLC_active_cycles 27583584 +Core_3_LLC_active_hit_cycles 6849283 +Core_3_LLC_active_miss_cycles 26452269 +Core_3_LLC_active_pure_miss_cycles 20734301 +Core_3_LLC_active_hit_miss_overlap_cycles 5717968 +Core_3_LLC_total_pure_miss 74789 +Core_3_LLC_pure_miss_rate 0.96511 +Core_3_LLC_active_cycles_per_core 16134138 +Core_3_LLC_active_hit_cycles_per_core 1574176 +Core_3_LLC_active_miss_cycles_per_core 14681168 +Core_3_LLC_active_pure_miss_cycles_per_core 14559962 +Core_3_LLC_hit_miss_overlap_cycles_per_core 121206 +Core_3_LLC_camat_per_core 208.20123 + +Core_3_major_page_fault 0 +Core_3_minor_page_fault 3636 + +Channel_0_RQ_row_buffer_hit 149372 +Channel_0_RQ_row_buffer_miss 41735 +Channel_0_WQ_row_buffer_hit 670 +Channel_0_WQ_row_buffer_miss 2983 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 4631 +Channel_0_RQ_row_buffer_hit 90690 +Channel_0_RQ_row_buffer_miss 58867 +Channel_0_WQ_row_buffer_hit 460 +Channel_0_WQ_row_buffer_miss 2317 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 3569 +avg_congested_cycle 0 9 +avg_congested_cycle 1 14 diff --git a/dram-nvram-equal.txt b/dram-nvram-equal.txt new file mode 100644 index 0000000..69b4059 --- /dev/null +++ b/dram-nvram-equal.txt @@ -0,0 +1,1099 @@ +************************************************* + ChampSim Multicore Out-of-Order Simulator + Last compiled: Mar 24 2022 20:50:50 +************************************************* + DRAM access latency: 170 + NVRAM access latency: 170 +Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s + DRAM_DBUS_RETURN_TIME: 13 + NVRAM_DBUS_RETURN_TIME: 13 + +trace_0 ./traces/403.gcc-17B.champsimtrace.xz +trace_1 ./traces/403.gcc-17B.champsimtrace.xz +trace_2 ./traces/403.gcc-17B.champsimtrace.xz +trace_3 ./traces/403.gcc-17B.champsimtrace.xz +warmup_instructions 1000 +simulation_instructions 100000 +champsim_seed 680 + +num_cpus 4 +cpu_freq 4000 +dram_io_freq 2400 +nvram_io_freq 2400 +page_size 4096 +block_size 64 +max_read_per_cycle 20 +max_fill_per_cycle 20 +dram_channels 1 +dram_ranks 1 +dram_banks 8 +dram_rows 65536 +dram_columns 128 +dram_row_size 8 +dram_size 4096 +dram_pages 1048576 + +fetch_width 20 +decode_width 20 +exec_width 20 +lq_width 20 +sq_width 20 +retire_width 20 +scheduler_size 128 +branch_mispredict_penalty 20 +rob_size 256 +lq_size 72 +sq_size 56 +num_instr_destinations_sparc 4 +num_instr_destinations 2 +num_instr_sources 4 + +itlb_set 16 +itlb_way 8 +itlb_rq_size 16 +itlb_wq_size 16 +itlb_pq_size 0 +itlb_mshr_size 8 +itlb_latency 1 + +dtlb_set 16 +dtlb_way 4 +dtlb_rq_size 16 +dtlb_wq_size 16 +dtlb_pq_size 0 +dtlb_mshr_size 8 +dtlb_latency 1 + +stlb_set 128 +stlb_way 12 +stlb_rq_size 32 +stlb_wq_size 32 +stlb_pq_size 0 +stlb_mshr_size 16 +stlb_latency 8 + +l1i_size 32 +l1i_set 64 +l1i_way 8 +l1i_rq_size 64 +l1i_wq_size 64 +l1i_pq_size 8 +l1i_mshr_size 8 +l1i_latency 1 + +l1d_size 32 +l1d_set 64 +l1d_way 8 +l1d_rq_size 64 +l1d_wq_size 64 +l1d_pq_size 32 +l1d_mshr_size 16 +l1d_latency 4 + +l2c_size 256 +l2c_set 512 +l2c_way 8 +l2c_rq_size 32 +l2c_wq_size 32 +l2c_pq_size 16 +l2c_mshr_size 32 +l2c_latency 10 + +llc_size 8192 +llc_set 8192 +llc_way 16 +llc_rq_size 128 +llc_wq_size 128 +llc_pq_size 128 +llc_mshr_size 256 +llc_latency 20 + +dram_channel_width 8 +dram_wq_size 64 +dram_rq_size 64 +tRP 15 +tRCD 15 +tCAS 12.5 +dram_dbus_turn_around_time 30 +dram_write_high_wm 56 +dram_write_low_wm 48 +min_dram_writes_per_switch 16 +dram_mtps 2400 +dram_dbus_return_time 13 + +NVram_channel_width 8 +NVram_wq_size 64 +NVram_rq_size 64 +NV_tRP 15 +NV_tRCD 15 +NV_tCAS 12.5 +NVram_dbus_turn_around_time 30 +NVram_write_high_wm 56 +NVram_write_low_wm 48 +min_NVram_writes_per_switch 16 +NVram_mtps 2400 +NVram_dbus_return_time 13 + + + +Warmup complete CPU 0 instructions: 1026 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 1 instructions: 1026 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 2 instructions: 1019 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 3 instructions: 1001 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) + +Finished CPU 2 instructions: 100001 cycles: 416751 cumulative IPC: 0.239954 (Simulation time: 0 hr 0 min 4 sec) +Finished CPU 3 instructions: 100000 cycles: 416781 cumulative IPC: 0.239934 (Simulation time: 0 hr 0 min 4 sec) +Finished CPU 0 instructions: 100006 cycles: 416796 cumulative IPC: 0.23994 (Simulation time: 0 hr 0 min 4 sec) +Finished CPU 1 instructions: 100006 cycles: 416847 cumulative IPC: 0.239911 (Simulation time: 0 hr 0 min 4 sec) + +ChampSim completed all CPUs + +Total Simulation Statistics (not including warmup) + +CPU 0 cumulative IPC: 0.239925 instructions: 100012 cycles: 416847 +Core_0_L1D_total_access 33589 +Core_0_L1D_total_hit 32673 +Core_0_L1D_total_miss 916 +Core_0_L1D_loads 19918 +Core_0_L1D_load_hit 19015 +Core_0_L1D_load_miss 903 +Core_0_L1D_RFOs 13671 +Core_0_L1D_RFO_hit 13658 +Core_0_L1D_RFO_miss 13 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 + +Core_0_L1I_total_access 18579 +Core_0_L1I_total_hit 18389 +Core_0_L1I_total_miss 190 +Core_0_L1I_loads 18579 +Core_0_L1I_load_hit 18389 +Core_0_L1I_load_miss 190 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 + +Core_0_L2C_total_access 1124 +Core_0_L2C_total_hit 35 +Core_0_L2C_total_miss 1089 +Core_0_L2C_loads 1093 +Core_0_L2C_load_hit 16 +Core_0_L2C_load_miss 1077 +Core_0_L2C_RFOs 13 +Core_0_L2C_RFO_hit 1 +Core_0_L2C_RFO_miss 12 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 18 +Core_0_L2C_writeback_hit 18 +Core_0_L2C_writeback_miss 0 + +Core_0_LLC_total_access 1089 +Core_0_LLC_total_hit 0 +Core_0_LLC_total_miss 1089 +Core_0_LLC_loads 1077 +Core_0_LLC_load_hit 0 +Core_0_LLC_load_miss 1077 +Core_0_LLC_RFOs 12 +Core_0_LLC_RFO_hit 0 +Core_0_LLC_RFO_miss 12 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 0 +Core_0_LLC_writeback_hit 0 +Core_0_LLC_writeback_miss 0 + + +CPU 1 cumulative IPC: 0.239911 instructions: 100006 cycles: 416847 +Core_1_L1D_total_access 33573 +Core_1_L1D_total_hit 32657 +Core_1_L1D_total_miss 916 +Core_1_L1D_loads 19911 +Core_1_L1D_load_hit 19008 +Core_1_L1D_load_miss 903 +Core_1_L1D_RFOs 13662 +Core_1_L1D_RFO_hit 13649 +Core_1_L1D_RFO_miss 13 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 + +Core_1_L1I_total_access 18579 +Core_1_L1I_total_hit 18389 +Core_1_L1I_total_miss 190 +Core_1_L1I_loads 18579 +Core_1_L1I_load_hit 18389 +Core_1_L1I_load_miss 190 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 + +Core_1_L2C_total_access 1124 +Core_1_L2C_total_hit 35 +Core_1_L2C_total_miss 1089 +Core_1_L2C_loads 1093 +Core_1_L2C_load_hit 16 +Core_1_L2C_load_miss 1077 +Core_1_L2C_RFOs 13 +Core_1_L2C_RFO_hit 1 +Core_1_L2C_RFO_miss 12 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 18 +Core_1_L2C_writeback_hit 18 +Core_1_L2C_writeback_miss 0 + +Core_1_LLC_total_access 1089 +Core_1_LLC_total_hit 0 +Core_1_LLC_total_miss 1089 +Core_1_LLC_loads 1077 +Core_1_LLC_load_hit 0 +Core_1_LLC_load_miss 1077 +Core_1_LLC_RFOs 12 +Core_1_LLC_RFO_hit 0 +Core_1_LLC_RFO_miss 12 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 0 +Core_1_LLC_writeback_hit 0 +Core_1_LLC_writeback_miss 0 + + +CPU 2 cumulative IPC: 0.239999 instructions: 100043 cycles: 416847 +Core_2_L1D_total_access 33603 +Core_2_L1D_total_hit 32687 +Core_2_L1D_total_miss 916 +Core_2_L1D_loads 19918 +Core_2_L1D_load_hit 19015 +Core_2_L1D_load_miss 903 +Core_2_L1D_RFOs 13685 +Core_2_L1D_RFO_hit 13672 +Core_2_L1D_RFO_miss 13 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 + +Core_2_L1I_total_access 18579 +Core_2_L1I_total_hit 18389 +Core_2_L1I_total_miss 190 +Core_2_L1I_loads 18579 +Core_2_L1I_load_hit 18389 +Core_2_L1I_load_miss 190 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 + +Core_2_L2C_total_access 1124 +Core_2_L2C_total_hit 35 +Core_2_L2C_total_miss 1089 +Core_2_L2C_loads 1093 +Core_2_L2C_load_hit 16 +Core_2_L2C_load_miss 1077 +Core_2_L2C_RFOs 13 +Core_2_L2C_RFO_hit 1 +Core_2_L2C_RFO_miss 12 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 18 +Core_2_L2C_writeback_hit 18 +Core_2_L2C_writeback_miss 0 + +Core_2_LLC_total_access 1089 +Core_2_LLC_total_hit 0 +Core_2_LLC_total_miss 1089 +Core_2_LLC_loads 1077 +Core_2_LLC_load_hit 0 +Core_2_LLC_load_miss 1077 +Core_2_LLC_RFOs 12 +Core_2_LLC_RFO_hit 0 +Core_2_LLC_RFO_miss 12 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 0 +Core_2_LLC_writeback_hit 0 +Core_2_LLC_writeback_miss 0 + + +CPU 3 cumulative IPC: 0.239983 instructions: 100036 cycles: 416847 +Core_3_L1D_total_access 33594 +Core_3_L1D_total_hit 32678 +Core_3_L1D_total_miss 916 +Core_3_L1D_loads 19920 +Core_3_L1D_load_hit 19017 +Core_3_L1D_load_miss 903 +Core_3_L1D_RFOs 13674 +Core_3_L1D_RFO_hit 13661 +Core_3_L1D_RFO_miss 13 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 + +Core_3_L1I_total_access 18579 +Core_3_L1I_total_hit 18389 +Core_3_L1I_total_miss 190 +Core_3_L1I_loads 18579 +Core_3_L1I_load_hit 18389 +Core_3_L1I_load_miss 190 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 + +Core_3_L2C_total_access 1124 +Core_3_L2C_total_hit 35 +Core_3_L2C_total_miss 1089 +Core_3_L2C_loads 1093 +Core_3_L2C_load_hit 16 +Core_3_L2C_load_miss 1077 +Core_3_L2C_RFOs 13 +Core_3_L2C_RFO_hit 1 +Core_3_L2C_RFO_miss 12 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 18 +Core_3_L2C_writeback_hit 18 +Core_3_L2C_writeback_miss 0 + +Core_3_LLC_total_access 1089 +Core_3_LLC_total_hit 0 +Core_3_LLC_total_miss 1089 +Core_3_LLC_loads 1077 +Core_3_LLC_load_hit 0 +Core_3_LLC_load_miss 1077 +Core_3_LLC_RFOs 12 +Core_3_LLC_RFO_hit 0 +Core_3_LLC_RFO_miss 12 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 0 +Core_3_LLC_writeback_hit 0 +Core_3_LLC_writeback_miss 0 + + +[ROI Statistics] +Core_0_instructions 100006 +Core_0_cycles 416796 +Core_0_IPC 0.23994 + +Core_0_branch_prediction_accuracy 90.9586 +Core_0_branch_MPKI 16.4338 +Core_0_average_ROB_occupancy_at_mispredict 57.0998 + +Core_0_L1D_total_access 33579 +Core_0_L1D_total_hit 32663 +Core_0_L1D_total_miss 916 +Core_0_L1D_total_overlap_miss 916 +Core_0_L1D_loads 19914 +Core_0_L1D_load_hit 19011 +Core_0_L1D_load_miss 903 +Core_0_L1D_RFOs 13665 +Core_0_L1D_RFO_hit 13652 +Core_0_L1D_RFO_miss 13 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 +Core_0_L1D_miss_rate 0.027279 +Core_0_L1D_MPKI 9.16 +Core_0_L1D_demand_miss 916 +Core_0_L1D_prefetch_requested 0 +Core_0_L1D_prefetch_issued 0 +Core_0_L1D_prefetch_useful 0 +Core_0_L1D_prefetch_useless 0 +Core_0_L1D_prefetch_late 0 +Core_0_L1D_average_miss_latency 198.864 +Core_0_L1D_active_cycles 272565 +Core_0_L1D_active_hit_cycles 114580 +Core_0_L1D_active_miss_cycles 173650 +Core_0_L1D_active_pure_miss_cycles 157985 +Core_0_L1D_active_hit_miss_overlap_cycles 15665 +Core_0_L1D_total_pure_miss 916 +Core_0_L1D_pure_miss_rate 0.027279 +Core_0_L1D_active_cycles_per_core 272565 +Core_0_L1D_active_hit_cycles_per_core 114580 +Core_0_L1D_active_miss_cycles_per_core 173650 +Core_0_L1D_active_pure_miss_cycles_per_core 157985 +Core_0_L1D_hit_miss_overlap_cycles_per_core 15665 +Core_0_L1D_camat_per_core 8.11713 + +Core_0_L1I_total_access 18579 +Core_0_L1I_total_hit 18389 +Core_0_L1I_total_miss 190 +Core_0_L1I_total_overlap_miss 190 +Core_0_L1I_loads 18579 +Core_0_L1I_load_hit 18389 +Core_0_L1I_load_miss 190 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 +Core_0_L1I_miss_rate 0.0102266 +Core_0_L1I_MPKI 1.9 +Core_0_L1I_demand_miss 190 +Core_0_L1I_prefetch_requested 0 +Core_0_L1I_prefetch_issued 0 +Core_0_L1I_prefetch_useful 0 +Core_0_L1I_prefetch_useless 0 +Core_0_L1I_prefetch_late 0 +Core_0_L1I_average_miss_latency 227.247 +Core_0_L1I_active_cycles 44782 +Core_0_L1I_active_hit_cycles 18441 +Core_0_L1I_active_miss_cycles 26550 +Core_0_L1I_active_pure_miss_cycles 26341 +Core_0_L1I_active_hit_miss_overlap_cycles 209 +Core_0_L1I_total_pure_miss 190 +Core_0_L1I_pure_miss_rate 0.0102266 +Core_0_L1I_active_cycles_per_core 44782 +Core_0_L1I_active_hit_cycles_per_core 18441 +Core_0_L1I_active_miss_cycles_per_core 26550 +Core_0_L1I_active_pure_miss_cycles_per_core 26341 +Core_0_L1I_hit_miss_overlap_cycles_per_core 209 +Core_0_L1I_camat_per_core 2.41036 + +Core_0_L2C_total_access 1124 +Core_0_L2C_total_hit 35 +Core_0_L2C_total_miss 1089 +Core_0_L2C_total_overlap_miss 1089 +Core_0_L2C_loads 1093 +Core_0_L2C_load_hit 16 +Core_0_L2C_load_miss 1077 +Core_0_L2C_RFOs 13 +Core_0_L2C_RFO_hit 1 +Core_0_L2C_RFO_miss 12 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 18 +Core_0_L2C_writeback_hit 18 +Core_0_L2C_writeback_miss 0 +Core_0_L2C_miss_rate 0.968861 +Core_0_L2C_MPKI 10.89 +Core_0_L2C_demand_miss 1089 +Core_0_L2C_prefetch_requested 0 +Core_0_L2C_prefetch_issued 0 +Core_0_L2C_prefetch_useful 0 +Core_0_L2C_prefetch_useless 0 +Core_0_L2C_prefetch_late 0 +Core_0_L2C_average_miss_latency 190.749 +Core_0_L2C_active_cycles 192987 +Core_0_L2C_active_hit_cycles 13201 +Core_0_L2C_active_miss_cycles 181763 +Core_0_L2C_active_pure_miss_cycles 179786 +Core_0_L2C_active_hit_miss_overlap_cycles 1977 +Core_0_L2C_total_pure_miss 1089 +Core_0_L2C_pure_miss_rate 0.968861 +Core_0_L2C_active_cycles_per_core 192987 +Core_0_L2C_active_hit_cycles_per_core 13201 +Core_0_L2C_active_miss_cycles_per_core 181763 +Core_0_L2C_active_pure_miss_cycles_per_core 179786 +Core_0_L2C_hit_miss_overlap_cycles_per_core 1977 +Core_0_L2C_camat_per_core 171.697 + +Core_0_LLC_total_access 1089 +Core_0_LLC_total_hit 0 +Core_0_LLC_total_miss 1089 +Core_0_LLC_total_overlap_miss 1089 +Core_0_LLC_loads 1077 +Core_0_LLC_load_hit 0 +Core_0_LLC_load_miss 1077 +Core_0_LLC_RFOs 12 +Core_0_LLC_RFO_hit 0 +Core_0_LLC_RFO_miss 12 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 0 +Core_0_LLC_writeback_hit 0 +Core_0_LLC_writeback_miss 0 +Core_0_LLC_miss_rate 1 +Core_0_LLC_MPKI 10.89 +Core_0_LLC_demand_miss 1089 +Core_0_LLC_prefetch_requested 0 +Core_0_LLC_prefetch_issued 0 +Core_0_LLC_prefetch_useful 0 +Core_0_LLC_prefetch_useless 0 +Core_0_LLC_prefetch_late 0 +Core_0_LLC_average_miss_latency 644.858 +Core_0_LLC_active_cycles 246090 +Core_0_LLC_active_hit_cycles 73716 +Core_0_LLC_active_miss_cycles 236922 +Core_0_LLC_active_pure_miss_cycles 172374 +Core_0_LLC_active_hit_miss_overlap_cycles 64548 +Core_0_LLC_total_pure_miss 1089 +Core_0_LLC_pure_miss_rate 1 +Core_0_LLC_active_cycles_per_core 172453 +Core_0_LLC_active_hit_cycles_per_core 20787 +Core_0_LLC_active_miss_cycles_per_core 154014 +Core_0_LLC_active_pure_miss_cycles_per_core 151666 +Core_0_LLC_hit_miss_overlap_cycles_per_core 2348 +Core_0_LLC_camat_per_core 158.359 + +Core_0_major_page_fault 0 +Core_0_minor_page_fault 156 + +Core_1_instructions 100006 +Core_1_cycles 416847 +Core_1_IPC 0.239911 + +Core_1_branch_prediction_accuracy 90.9586 +Core_1_branch_MPKI 16.4347 +Core_1_average_ROB_occupancy_at_mispredict 57.1186 + +Core_1_L1D_total_access 33573 +Core_1_L1D_total_hit 32657 +Core_1_L1D_total_miss 916 +Core_1_L1D_total_overlap_miss 916 +Core_1_L1D_loads 19911 +Core_1_L1D_load_hit 19008 +Core_1_L1D_load_miss 903 +Core_1_L1D_RFOs 13662 +Core_1_L1D_RFO_hit 13649 +Core_1_L1D_RFO_miss 13 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 +Core_1_L1D_miss_rate 0.0272838 +Core_1_L1D_MPKI 9.16 +Core_1_L1D_demand_miss 916 +Core_1_L1D_prefetch_requested 0 +Core_1_L1D_prefetch_issued 0 +Core_1_L1D_prefetch_useful 0 +Core_1_L1D_prefetch_useless 0 +Core_1_L1D_prefetch_late 0 +Core_1_L1D_average_miss_latency 197.931 +Core_1_L1D_active_cycles 271271 +Core_1_L1D_active_hit_cycles 114408 +Core_1_L1D_active_miss_cycles 172514 +Core_1_L1D_active_pure_miss_cycles 156863 +Core_1_L1D_active_hit_miss_overlap_cycles 15651 +Core_1_L1D_total_pure_miss 916 +Core_1_L1D_pure_miss_rate 0.0272838 +Core_1_L1D_active_cycles_per_core 271271 +Core_1_L1D_active_hit_cycles_per_core 114408 +Core_1_L1D_active_miss_cycles_per_core 172514 +Core_1_L1D_active_pure_miss_cycles_per_core 156863 +Core_1_L1D_hit_miss_overlap_cycles_per_core 15651 +Core_1_L1D_camat_per_core 8.08003 + +Core_1_L1I_total_access 18579 +Core_1_L1I_total_hit 18389 +Core_1_L1I_total_miss 190 +Core_1_L1I_total_overlap_miss 190 +Core_1_L1I_loads 18579 +Core_1_L1I_load_hit 18389 +Core_1_L1I_load_miss 190 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 +Core_1_L1I_miss_rate 0.0102266 +Core_1_L1I_MPKI 1.9 +Core_1_L1I_demand_miss 190 +Core_1_L1I_prefetch_requested 0 +Core_1_L1I_prefetch_issued 0 +Core_1_L1I_prefetch_useful 0 +Core_1_L1I_prefetch_useless 0 +Core_1_L1I_prefetch_late 0 +Core_1_L1I_average_miss_latency 240.742 +Core_1_L1I_active_cycles 45919 +Core_1_L1I_active_hit_cycles 18441 +Core_1_L1I_active_miss_cycles 27687 +Core_1_L1I_active_pure_miss_cycles 27478 +Core_1_L1I_active_hit_miss_overlap_cycles 209 +Core_1_L1I_total_pure_miss 190 +Core_1_L1I_pure_miss_rate 0.0102266 +Core_1_L1I_active_cycles_per_core 45919 +Core_1_L1I_active_hit_cycles_per_core 18441 +Core_1_L1I_active_miss_cycles_per_core 27687 +Core_1_L1I_active_pure_miss_cycles_per_core 27478 +Core_1_L1I_hit_miss_overlap_cycles_per_core 209 +Core_1_L1I_camat_per_core 2.47155 + +Core_1_L2C_total_access 1124 +Core_1_L2C_total_hit 35 +Core_1_L2C_total_miss 1089 +Core_1_L2C_total_overlap_miss 1089 +Core_1_L2C_loads 1093 +Core_1_L2C_load_hit 16 +Core_1_L2C_load_miss 1077 +Core_1_L2C_RFOs 13 +Core_1_L2C_RFO_hit 1 +Core_1_L2C_RFO_miss 12 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 18 +Core_1_L2C_writeback_hit 18 +Core_1_L2C_writeback_miss 0 +Core_1_L2C_miss_rate 0.968861 +Core_1_L2C_MPKI 10.89 +Core_1_L2C_demand_miss 1089 +Core_1_L2C_prefetch_requested 0 +Core_1_L2C_prefetch_issued 0 +Core_1_L2C_prefetch_useful 0 +Core_1_L2C_prefetch_useless 0 +Core_1_L2C_prefetch_late 0 +Core_1_L2C_average_miss_latency 192.32 +Core_1_L2C_active_cycles 193079 +Core_1_L2C_active_hit_cycles 13192 +Core_1_L2C_active_miss_cycles 181845 +Core_1_L2C_active_pure_miss_cycles 179887 +Core_1_L2C_active_hit_miss_overlap_cycles 1958 +Core_1_L2C_total_pure_miss 1089 +Core_1_L2C_pure_miss_rate 0.968861 +Core_1_L2C_active_cycles_per_core 193079 +Core_1_L2C_active_hit_cycles_per_core 13192 +Core_1_L2C_active_miss_cycles_per_core 181845 +Core_1_L2C_active_pure_miss_cycles_per_core 179887 +Core_1_L2C_hit_miss_overlap_cycles_per_core 1958 +Core_1_L2C_camat_per_core 171.778 + +Core_1_LLC_total_access 1089 +Core_1_LLC_total_hit 0 +Core_1_LLC_total_miss 1089 +Core_1_LLC_total_overlap_miss 1089 +Core_1_LLC_loads 1077 +Core_1_LLC_load_hit 0 +Core_1_LLC_load_miss 1077 +Core_1_LLC_RFOs 12 +Core_1_LLC_RFO_hit 0 +Core_1_LLC_RFO_miss 12 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 0 +Core_1_LLC_writeback_hit 0 +Core_1_LLC_writeback_miss 0 +Core_1_LLC_miss_rate 1 +Core_1_LLC_MPKI 10.89 +Core_1_LLC_demand_miss 1089 +Core_1_LLC_prefetch_requested 0 +Core_1_LLC_prefetch_issued 0 +Core_1_LLC_prefetch_useful 0 +Core_1_LLC_prefetch_useless 0 +Core_1_LLC_prefetch_late 0 +Core_1_LLC_average_miss_latency 644.858 +Core_1_LLC_active_cycles 246090 +Core_1_LLC_active_hit_cycles 73716 +Core_1_LLC_active_miss_cycles 236922 +Core_1_LLC_active_pure_miss_cycles 172374 +Core_1_LLC_active_hit_miss_overlap_cycles 64548 +Core_1_LLC_total_pure_miss 1089 +Core_1_LLC_pure_miss_rate 1 +Core_1_LLC_active_cycles_per_core 172564 +Core_1_LLC_active_hit_cycles_per_core 20768 +Core_1_LLC_active_miss_cycles_per_core 154106 +Core_1_LLC_active_pure_miss_cycles_per_core 151796 +Core_1_LLC_hit_miss_overlap_cycles_per_core 2310 +Core_1_LLC_camat_per_core 158.461 + +Core_1_major_page_fault 0 +Core_1_minor_page_fault 156 + +Core_2_instructions 100001 +Core_2_cycles 416751 +Core_2_IPC 0.239954 + +Core_2_branch_prediction_accuracy 90.9586 +Core_2_branch_MPKI 16.4298 +Core_2_average_ROB_occupancy_at_mispredict 57.0998 + +Core_2_L1D_total_access 33580 +Core_2_L1D_total_hit 32664 +Core_2_L1D_total_miss 916 +Core_2_L1D_total_overlap_miss 916 +Core_2_L1D_loads 19913 +Core_2_L1D_load_hit 19010 +Core_2_L1D_load_miss 903 +Core_2_L1D_RFOs 13667 +Core_2_L1D_RFO_hit 13654 +Core_2_L1D_RFO_miss 13 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 +Core_2_L1D_miss_rate 0.0272781 +Core_2_L1D_MPKI 9.16 +Core_2_L1D_demand_miss 916 +Core_2_L1D_prefetch_requested 0 +Core_2_L1D_prefetch_issued 0 +Core_2_L1D_prefetch_useful 0 +Core_2_L1D_prefetch_useless 0 +Core_2_L1D_prefetch_late 0 +Core_2_L1D_average_miss_latency 198.837 +Core_2_L1D_active_cycles 272646 +Core_2_L1D_active_hit_cycles 114617 +Core_2_L1D_active_miss_cycles 173689 +Core_2_L1D_active_pure_miss_cycles 158029 +Core_2_L1D_active_hit_miss_overlap_cycles 15660 +Core_2_L1D_total_pure_miss 916 +Core_2_L1D_pure_miss_rate 0.0272781 +Core_2_L1D_active_cycles_per_core 272646 +Core_2_L1D_active_hit_cycles_per_core 114617 +Core_2_L1D_active_miss_cycles_per_core 173689 +Core_2_L1D_active_pure_miss_cycles_per_core 158029 +Core_2_L1D_hit_miss_overlap_cycles_per_core 15660 +Core_2_L1D_camat_per_core 8.1193 + +Core_2_L1I_total_access 18579 +Core_2_L1I_total_hit 18389 +Core_2_L1I_total_miss 190 +Core_2_L1I_total_overlap_miss 190 +Core_2_L1I_loads 18579 +Core_2_L1I_load_hit 18389 +Core_2_L1I_load_miss 190 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 +Core_2_L1I_miss_rate 0.0102266 +Core_2_L1I_MPKI 1.9 +Core_2_L1I_demand_miss 190 +Core_2_L1I_prefetch_requested 0 +Core_2_L1I_prefetch_issued 0 +Core_2_L1I_prefetch_useful 0 +Core_2_L1I_prefetch_useless 0 +Core_2_L1I_prefetch_late 0 +Core_2_L1I_average_miss_latency 224.4 +Core_2_L1I_active_cycles 44572 +Core_2_L1I_active_hit_cycles 18441 +Core_2_L1I_active_miss_cycles 26340 +Core_2_L1I_active_pure_miss_cycles 26131 +Core_2_L1I_active_hit_miss_overlap_cycles 209 +Core_2_L1I_total_pure_miss 190 +Core_2_L1I_pure_miss_rate 0.0102266 +Core_2_L1I_active_cycles_per_core 44572 +Core_2_L1I_active_hit_cycles_per_core 18441 +Core_2_L1I_active_miss_cycles_per_core 26340 +Core_2_L1I_active_pure_miss_cycles_per_core 26131 +Core_2_L1I_hit_miss_overlap_cycles_per_core 209 +Core_2_L1I_camat_per_core 2.39905 + +Core_2_L2C_total_access 1124 +Core_2_L2C_total_hit 35 +Core_2_L2C_total_miss 1089 +Core_2_L2C_total_overlap_miss 1089 +Core_2_L2C_loads 1093 +Core_2_L2C_load_hit 16 +Core_2_L2C_load_miss 1077 +Core_2_L2C_RFOs 13 +Core_2_L2C_RFO_hit 1 +Core_2_L2C_RFO_miss 12 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 18 +Core_2_L2C_writeback_hit 18 +Core_2_L2C_writeback_miss 0 +Core_2_L2C_miss_rate 0.968861 +Core_2_L2C_MPKI 10.89 +Core_2_L2C_demand_miss 1089 +Core_2_L2C_prefetch_requested 0 +Core_2_L2C_prefetch_issued 0 +Core_2_L2C_prefetch_useful 0 +Core_2_L2C_prefetch_useless 0 +Core_2_L2C_prefetch_late 0 +Core_2_L2C_average_miss_latency 190.23 +Core_2_L2C_active_cycles 192886 +Core_2_L2C_active_hit_cycles 13201 +Core_2_L2C_active_miss_cycles 181642 +Core_2_L2C_active_pure_miss_cycles 179685 +Core_2_L2C_active_hit_miss_overlap_cycles 1957 +Core_2_L2C_total_pure_miss 1089 +Core_2_L2C_pure_miss_rate 0.968861 +Core_2_L2C_active_cycles_per_core 192886 +Core_2_L2C_active_hit_cycles_per_core 13201 +Core_2_L2C_active_miss_cycles_per_core 181642 +Core_2_L2C_active_pure_miss_cycles_per_core 179685 +Core_2_L2C_hit_miss_overlap_cycles_per_core 1957 +Core_2_L2C_camat_per_core 171.607 + +Core_2_LLC_total_access 1089 +Core_2_LLC_total_hit 0 +Core_2_LLC_total_miss 1089 +Core_2_LLC_total_overlap_miss 1089 +Core_2_LLC_loads 1077 +Core_2_LLC_load_hit 0 +Core_2_LLC_load_miss 1077 +Core_2_LLC_RFOs 12 +Core_2_LLC_RFO_hit 0 +Core_2_LLC_RFO_miss 12 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 0 +Core_2_LLC_writeback_hit 0 +Core_2_LLC_writeback_miss 0 +Core_2_LLC_miss_rate 1 +Core_2_LLC_MPKI 10.89 +Core_2_LLC_demand_miss 1089 +Core_2_LLC_prefetch_requested 0 +Core_2_LLC_prefetch_issued 0 +Core_2_LLC_prefetch_useful 0 +Core_2_LLC_prefetch_useless 0 +Core_2_LLC_prefetch_late 0 +Core_2_LLC_average_miss_latency 644.858 +Core_2_LLC_active_cycles 246090 +Core_2_LLC_active_hit_cycles 73716 +Core_2_LLC_active_miss_cycles 236922 +Core_2_LLC_active_pure_miss_cycles 172374 +Core_2_LLC_active_hit_miss_overlap_cycles 64548 +Core_2_LLC_total_pure_miss 1089 +Core_2_LLC_pure_miss_rate 1 +Core_2_LLC_active_cycles_per_core 172283 +Core_2_LLC_active_hit_cycles_per_core 20787 +Core_2_LLC_active_miss_cycles_per_core 153804 +Core_2_LLC_active_pure_miss_cycles_per_core 151496 +Core_2_LLC_hit_miss_overlap_cycles_per_core 2308 +Core_2_LLC_camat_per_core 158.203 + +Core_2_major_page_fault 0 +Core_2_minor_page_fault 156 + +Core_3_instructions 100000 +Core_3_cycles 416781 +Core_3_IPC 0.239934 + +Core_3_branch_prediction_accuracy 90.9586 +Core_3_branch_MPKI 16.4339 +Core_3_average_ROB_occupancy_at_mispredict 57.0529 + +Core_3_L1D_total_access 33577 +Core_3_L1D_total_hit 32661 +Core_3_L1D_total_miss 916 +Core_3_L1D_total_overlap_miss 916 +Core_3_L1D_loads 19909 +Core_3_L1D_load_hit 19006 +Core_3_L1D_load_miss 903 +Core_3_L1D_RFOs 13668 +Core_3_L1D_RFO_hit 13655 +Core_3_L1D_RFO_miss 13 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 +Core_3_L1D_miss_rate 0.0272806 +Core_3_L1D_MPKI 9.16 +Core_3_L1D_demand_miss 916 +Core_3_L1D_prefetch_requested 0 +Core_3_L1D_prefetch_issued 0 +Core_3_L1D_prefetch_useful 0 +Core_3_L1D_prefetch_useless 0 +Core_3_L1D_prefetch_late 0 +Core_3_L1D_average_miss_latency 198.222 +Core_3_L1D_active_cycles 271615 +Core_3_L1D_active_hit_cycles 114504 +Core_3_L1D_active_miss_cycles 172718 +Core_3_L1D_active_pure_miss_cycles 157111 +Core_3_L1D_active_hit_miss_overlap_cycles 15607 +Core_3_L1D_total_pure_miss 916 +Core_3_L1D_pure_miss_rate 0.0272806 +Core_3_L1D_active_cycles_per_core 271615 +Core_3_L1D_active_hit_cycles_per_core 114504 +Core_3_L1D_active_miss_cycles_per_core 172718 +Core_3_L1D_active_pure_miss_cycles_per_core 157111 +Core_3_L1D_hit_miss_overlap_cycles_per_core 15607 +Core_3_L1D_camat_per_core 8.08932 + +Core_3_L1I_total_access 18579 +Core_3_L1I_total_hit 18389 +Core_3_L1I_total_miss 190 +Core_3_L1I_total_overlap_miss 190 +Core_3_L1I_loads 18579 +Core_3_L1I_load_hit 18389 +Core_3_L1I_load_miss 190 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 +Core_3_L1I_miss_rate 0.0102266 +Core_3_L1I_MPKI 1.9 +Core_3_L1I_demand_miss 190 +Core_3_L1I_prefetch_requested 0 +Core_3_L1I_prefetch_issued 0 +Core_3_L1I_prefetch_useful 0 +Core_3_L1I_prefetch_useless 0 +Core_3_L1I_prefetch_late 0 +Core_3_L1I_average_miss_latency 238.363 +Core_3_L1I_active_cycles 45384 +Core_3_L1I_active_hit_cycles 18441 +Core_3_L1I_active_miss_cycles 27152 +Core_3_L1I_active_pure_miss_cycles 26943 +Core_3_L1I_active_hit_miss_overlap_cycles 209 +Core_3_L1I_total_pure_miss 190 +Core_3_L1I_pure_miss_rate 0.0102266 +Core_3_L1I_active_cycles_per_core 45384 +Core_3_L1I_active_hit_cycles_per_core 18441 +Core_3_L1I_active_miss_cycles_per_core 27152 +Core_3_L1I_active_pure_miss_cycles_per_core 26943 +Core_3_L1I_hit_miss_overlap_cycles_per_core 209 +Core_3_L1I_camat_per_core 2.44276 + +Core_3_L2C_total_access 1124 +Core_3_L2C_total_hit 35 +Core_3_L2C_total_miss 1089 +Core_3_L2C_total_overlap_miss 1089 +Core_3_L2C_loads 1093 +Core_3_L2C_load_hit 16 +Core_3_L2C_load_miss 1077 +Core_3_L2C_RFOs 13 +Core_3_L2C_RFO_hit 1 +Core_3_L2C_RFO_miss 12 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 18 +Core_3_L2C_writeback_hit 18 +Core_3_L2C_writeback_miss 0 +Core_3_L2C_miss_rate 0.968861 +Core_3_L2C_MPKI 10.89 +Core_3_L2C_demand_miss 1089 +Core_3_L2C_prefetch_requested 0 +Core_3_L2C_prefetch_issued 0 +Core_3_L2C_prefetch_useful 0 +Core_3_L2C_prefetch_useless 0 +Core_3_L2C_prefetch_late 0 +Core_3_L2C_average_miss_latency 192.149 +Core_3_L2C_active_cycles 192788 +Core_3_L2C_active_hit_cycles 13192 +Core_3_L2C_active_miss_cycles 181554 +Core_3_L2C_active_pure_miss_cycles 179596 +Core_3_L2C_active_hit_miss_overlap_cycles 1958 +Core_3_L2C_total_pure_miss 1089 +Core_3_L2C_pure_miss_rate 0.968861 +Core_3_L2C_active_cycles_per_core 192788 +Core_3_L2C_active_hit_cycles_per_core 13192 +Core_3_L2C_active_miss_cycles_per_core 181554 +Core_3_L2C_active_pure_miss_cycles_per_core 179596 +Core_3_L2C_hit_miss_overlap_cycles_per_core 1958 +Core_3_L2C_camat_per_core 171.52 + +Core_3_LLC_total_access 1089 +Core_3_LLC_total_hit 0 +Core_3_LLC_total_miss 1089 +Core_3_LLC_total_overlap_miss 1089 +Core_3_LLC_loads 1077 +Core_3_LLC_load_hit 0 +Core_3_LLC_load_miss 1077 +Core_3_LLC_RFOs 12 +Core_3_LLC_RFO_hit 0 +Core_3_LLC_RFO_miss 12 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 0 +Core_3_LLC_writeback_hit 0 +Core_3_LLC_writeback_miss 0 +Core_3_LLC_miss_rate 1 +Core_3_LLC_MPKI 10.89 +Core_3_LLC_demand_miss 1089 +Core_3_LLC_prefetch_requested 0 +Core_3_LLC_prefetch_issued 0 +Core_3_LLC_prefetch_useful 0 +Core_3_LLC_prefetch_useless 0 +Core_3_LLC_prefetch_late 0 +Core_3_LLC_average_miss_latency 644.858 +Core_3_LLC_active_cycles 246090 +Core_3_LLC_active_hit_cycles 73716 +Core_3_LLC_active_miss_cycles 236922 +Core_3_LLC_active_pure_miss_cycles 172374 +Core_3_LLC_active_hit_miss_overlap_cycles 64548 +Core_3_LLC_total_pure_miss 1089 +Core_3_LLC_pure_miss_rate 1 +Core_3_LLC_active_cycles_per_core 172344 +Core_3_LLC_active_hit_cycles_per_core 20768 +Core_3_LLC_active_miss_cycles_per_core 153906 +Core_3_LLC_active_pure_miss_cycles_per_core 151576 +Core_3_LLC_hit_miss_overlap_cycles_per_core 2330 +Core_3_LLC_camat_per_core 158.259 + +Core_3_major_page_fault 0 +Core_3_minor_page_fault 156 + +Channel_0_RQ_row_buffer_hit 1255 +Channel_0_RQ_row_buffer_miss 923 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 97 +Channel_0_RQ_row_buffer_hit 1254 +Channel_0_RQ_row_buffer_miss 924 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 98 +avg_congested_cycle 0 10 +avg_congested_cycle 1 10 diff --git a/dram-nvram-equalsize.txt b/dram-nvram-equalsize.txt new file mode 100644 index 0000000..e51d2d9 --- /dev/null +++ b/dram-nvram-equalsize.txt @@ -0,0 +1,1148 @@ +************************************************* + ChampSim Multicore Out-of-Order Simulator + Last compiled: Mar 24 2022 22:40:10 +************************************************* + DRAM access latency: 170 + NVRAM access latency: 236 +Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s +Off-chip NVRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s + DRAM_DBUS_RETURN_TIME: 13 + NVRAM_DBUS_RETURN_TIME: 13 + +trace_0 ./traces/403.gcc-17B.champsimtrace.xz +trace_1 ./traces/403.gcc-17B.champsimtrace.xz +trace_2 ./traces/403.gcc-17B.champsimtrace.xz +trace_3 ./traces/403.gcc-17B.champsimtrace.xz +warmup_instructions 100000 +simulation_instructions 10000000 +champsim_seed 680 + +num_cpus 4 +cpu_freq 4000 +dram_io_freq 2400 +nvram_io_freq 2400 +page_size 4096 +block_size 64 +max_read_per_cycle 20 +max_fill_per_cycle 20 +dram_channels 1 +dram_ranks 1 +dram_banks 8 +dram_rows 65536 +dram_columns 128 +dram_row_size 8 +dram_size 4096 +dram_pages 1048576 +NVram_channels 1 +NVram_ranks 1 +NVram_banks 8 +NVram_rows 65536 +NVram_columns 128 +NVram_row_size 8 +NVram_size 4096 +NVram_pages 1048576 + +fetch_width 20 +decode_width 20 +exec_width 20 +lq_width 20 +sq_width 20 +retire_width 20 +scheduler_size 128 +branch_mispredict_penalty 20 +rob_size 256 +lq_size 72 +sq_size 56 +num_instr_destinations_sparc 4 +num_instr_destinations 2 +num_instr_sources 4 + +itlb_set 16 +itlb_way 8 +itlb_rq_size 16 +itlb_wq_size 16 +itlb_pq_size 0 +itlb_mshr_size 8 +itlb_latency 1 + +dtlb_set 16 +dtlb_way 4 +dtlb_rq_size 16 +dtlb_wq_size 16 +dtlb_pq_size 0 +dtlb_mshr_size 8 +dtlb_latency 1 + +stlb_set 128 +stlb_way 12 +stlb_rq_size 32 +stlb_wq_size 32 +stlb_pq_size 0 +stlb_mshr_size 16 +stlb_latency 8 + +l1i_size 32 +l1i_set 64 +l1i_way 8 +l1i_rq_size 64 +l1i_wq_size 64 +l1i_pq_size 8 +l1i_mshr_size 8 +l1i_latency 1 + +l1d_size 32 +l1d_set 64 +l1d_way 8 +l1d_rq_size 64 +l1d_wq_size 64 +l1d_pq_size 32 +l1d_mshr_size 16 +l1d_latency 4 + +l2c_size 256 +l2c_set 512 +l2c_way 8 +l2c_rq_size 32 +l2c_wq_size 32 +l2c_pq_size 16 +l2c_mshr_size 32 +l2c_latency 10 + +llc_size 8192 +llc_set 8192 +llc_way 16 +llc_rq_size 128 +llc_wq_size 128 +llc_pq_size 128 +llc_mshr_size 256 +llc_latency 20 + +dram_channel_width 8 +dram_wq_size 64 +dram_rq_size 64 +tRP 15 +tRCD 15 +tCAS 12.5 +dram_dbus_turn_around_time 30 +dram_write_high_wm 56 +dram_write_low_wm 48 +min_dram_writes_per_switch 16 +dram_mtps 2400 +dram_dbus_return_time 13 + +NVram_channel_width 8 +NVram_wq_size 128 +NVram_rq_size 128 +NV_tRP 22 +NV_tRCD 22 +NV_tCAS 15 +NVram_dbus_turn_around_time 30 +NVram_write_high_wm 112 +NVram_write_low_wm 96 +min_NVram_writes_per_switch 16 +NVram_mtps 2400 +NVram_dbus_return_time 13 + + + +Warmup complete CPU 0 instructions: 100093 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 1 instructions: 100058 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 2 instructions: 100034 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 3 instructions: 100001 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) + +Heartbeat CPU 1 instructions: 1000002 cycles: 3060933 heartbeat IPC: 0.32670 cumulative IPC: 0.30267 (Simulation time: 0 hr 0 min 40 sec) +Heartbeat CPU 0 instructions: 1000002 cycles: 3060984 heartbeat IPC: 0.32669 cumulative IPC: 0.30265 (Simulation time: 0 hr 0 min 40 sec) +Heartbeat CPU 3 instructions: 1000002 cycles: 3344230 heartbeat IPC: 0.29902 cumulative IPC: 0.27635 (Simulation time: 0 hr 0 min 45 sec) +Heartbeat CPU 2 instructions: 1000002 cycles: 3344291 heartbeat IPC: 0.29902 cumulative IPC: 0.27634 (Simulation time: 0 hr 0 min 45 sec) +Heartbeat CPU 0 instructions: 2000002 cycles: 6293640 heartbeat IPC: 0.30934 cumulative IPC: 0.30614 (Simulation time: 0 hr 1 min 34 sec) +Heartbeat CPU 1 instructions: 2000002 cycles: 6293691 heartbeat IPC: 0.30933 cumulative IPC: 0.30614 (Simulation time: 0 hr 1 min 34 sec) +Heartbeat CPU 3 instructions: 2000002 cycles: 6885330 heartbeat IPC: 0.28240 cumulative IPC: 0.27950 (Simulation time: 0 hr 1 min 45 sec) +Heartbeat CPU 2 instructions: 2000002 cycles: 6885391 heartbeat IPC: 0.28240 cumulative IPC: 0.27950 (Simulation time: 0 hr 1 min 45 sec) +Heartbeat CPU 1 instructions: 3000013 cycles: 9479796 heartbeat IPC: 0.31387 cumulative IPC: 0.30876 (Simulation time: 0 hr 2 min 32 sec) +Heartbeat CPU 0 instructions: 3000013 cycles: 9479847 heartbeat IPC: 0.31386 cumulative IPC: 0.30875 (Simulation time: 0 hr 2 min 32 sec) +Heartbeat CPU 2 instructions: 3000013 cycles: 10408762 heartbeat IPC: 0.28382 cumulative IPC: 0.28097 (Simulation time: 0 hr 2 min 50 sec) +Heartbeat CPU 3 instructions: 3000013 cycles: 10408823 heartbeat IPC: 0.28381 cumulative IPC: 0.28097 (Simulation time: 0 hr 2 min 50 sec) +Heartbeat CPU 0 instructions: 4000000 cycles: 12711135 heartbeat IPC: 0.30947 cumulative IPC: 0.30894 (Simulation time: 0 hr 3 min 34 sec) +Heartbeat CPU 1 instructions: 4000000 cycles: 12711186 heartbeat IPC: 0.30946 cumulative IPC: 0.30894 (Simulation time: 0 hr 3 min 34 sec) +Heartbeat CPU 3 instructions: 4000000 cycles: 13983217 heartbeat IPC: 0.27976 cumulative IPC: 0.28066 (Simulation time: 0 hr 3 min 59 sec) +Heartbeat CPU 2 instructions: 4000000 cycles: 13983278 heartbeat IPC: 0.27975 cumulative IPC: 0.28066 (Simulation time: 0 hr 3 min 59 sec) +Heartbeat CPU 1 instructions: 5000000 cycles: 16041667 heartbeat IPC: 0.30026 cumulative IPC: 0.30713 (Simulation time: 0 hr 4 min 41 sec) +Heartbeat CPU 0 instructions: 5000000 cycles: 16041718 heartbeat IPC: 0.30025 cumulative IPC: 0.30712 (Simulation time: 0 hr 4 min 41 sec) +Heartbeat CPU 2 instructions: 5000000 cycles: 17685232 heartbeat IPC: 0.27013 cumulative IPC: 0.27844 (Simulation time: 0 hr 5 min 16 sec) +Heartbeat CPU 3 instructions: 5000000 cycles: 17685293 heartbeat IPC: 0.27012 cumulative IPC: 0.27844 (Simulation time: 0 hr 5 min 16 sec) +Heartbeat CPU 0 instructions: 6000004 cycles: 19237416 heartbeat IPC: 0.31292 cumulative IPC: 0.30809 (Simulation time: 0 hr 5 min 49 sec) +Heartbeat CPU 1 instructions: 6000004 cycles: 19237467 heartbeat IPC: 0.31291 cumulative IPC: 0.30809 (Simulation time: 0 hr 5 min 49 sec) +Heartbeat CPU 3 instructions: 6000004 cycles: 21245046 heartbeat IPC: 0.28092 cumulative IPC: 0.27886 (Simulation time: 0 hr 6 min 34 sec) +Heartbeat CPU 2 instructions: 6000004 cycles: 21245107 heartbeat IPC: 0.28091 cumulative IPC: 0.27886 (Simulation time: 0 hr 6 min 34 sec) +Heartbeat CPU 0 instructions: 7000002 cycles: 22446316 heartbeat IPC: 0.31163 cumulative IPC: 0.30860 (Simulation time: 0 hr 7 min 0 sec) +Heartbeat CPU 1 instructions: 7000002 cycles: 22446367 heartbeat IPC: 0.31163 cumulative IPC: 0.30860 (Simulation time: 0 hr 7 min 0 sec) +Heartbeat CPU 3 instructions: 7000002 cycles: 24806304 heartbeat IPC: 0.28080 cumulative IPC: 0.27914 (Simulation time: 0 hr 7 min 52 sec) +Heartbeat CPU 2 instructions: 7000002 cycles: 24806541 heartbeat IPC: 0.28079 cumulative IPC: 0.27914 (Simulation time: 0 hr 7 min 52 sec) +Heartbeat CPU 1 instructions: 8000000 cycles: 25652313 heartbeat IPC: 0.31192 cumulative IPC: 0.30902 (Simulation time: 0 hr 8 min 11 sec) +Heartbeat CPU 0 instructions: 8000000 cycles: 25652604 heartbeat IPC: 0.31189 cumulative IPC: 0.30901 (Simulation time: 0 hr 8 min 11 sec) +Heartbeat CPU 3 instructions: 8000000 cycles: 28387017 heartbeat IPC: 0.27927 cumulative IPC: 0.27916 (Simulation time: 0 hr 9 min 13 sec) +Heartbeat CPU 2 instructions: 8000000 cycles: 28387078 heartbeat IPC: 0.27929 cumulative IPC: 0.27916 (Simulation time: 0 hr 9 min 13 sec) +Heartbeat CPU 0 instructions: 9000000 cycles: 28870611 heartbeat IPC: 0.31075 cumulative IPC: 0.30921 (Simulation time: 0 hr 9 min 24 sec) +Heartbeat CPU 1 instructions: 9000000 cycles: 28870662 heartbeat IPC: 0.31072 cumulative IPC: 0.30921 (Simulation time: 0 hr 9 min 24 sec) +Heartbeat CPU 3 instructions: 9000000 cycles: 31971369 heartbeat IPC: 0.27899 cumulative IPC: 0.27914 (Simulation time: 0 hr 10 min 32 sec) +Heartbeat CPU 2 instructions: 9000000 cycles: 31971430 heartbeat IPC: 0.27899 cumulative IPC: 0.27914 (Simulation time: 0 hr 10 min 32 sec) +Heartbeat CPU 0 instructions: 10000013 cycles: 32108554 heartbeat IPC: 0.30884 cumulative IPC: 0.30917 (Simulation time: 0 hr 10 min 34 sec) +Heartbeat CPU 1 instructions: 10000013 cycles: 32108605 heartbeat IPC: 0.30884 cumulative IPC: 0.30917 (Simulation time: 0 hr 10 min 34 sec) +Finished CPU 1 instructions: 10000016 cycles: 32365872 cumulative IPC: 0.30897 (Simulation time: 0 hr 10 min 41 sec) +Finished CPU 0 instructions: 10000013 cycles: 32366257 cumulative IPC: 0.30896 (Simulation time: 0 hr 10 min 41 sec) +Heartbeat CPU 3 instructions: 10000014 cycles: 35547415 heartbeat IPC: 0.27964 cumulative IPC: 0.27919 (Simulation time: 0 hr 11 min 44 sec) +Heartbeat CPU 2 instructions: 10000014 cycles: 35547476 heartbeat IPC: 0.27964 cumulative IPC: 0.27919 (Simulation time: 0 hr 11 min 44 sec) +Finished CPU 3 instructions: 10000001 cycles: 35838785 cumulative IPC: 0.27903 (Simulation time: 0 hr 11 min 51 sec) +Finished CPU 2 instructions: 10000000 cycles: 35839755 cumulative IPC: 0.27902 (Simulation time: 0 hr 11 min 51 sec) + +ChampSim completed all CPUs + +Total Simulation Statistics (not including warmup) + +CPU 0 cumulative IPC: 0.29646 instructions: 10625176 cycles: 35839755 +Core_0_L1D_total_access 3438879 +Core_0_L1D_total_hit 3350462 +Core_0_L1D_total_miss 88417 +Core_0_L1D_loads 2003043 +Core_0_L1D_load_hit 1915404 +Core_0_L1D_load_miss 87639 +Core_0_L1D_RFOs 1435836 +Core_0_L1D_RFO_hit 1435058 +Core_0_L1D_RFO_miss 778 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 + +Core_0_L1I_total_access 2362993 +Core_0_L1I_total_hit 2362022 +Core_0_L1I_total_miss 971 +Core_0_L1I_loads 2362993 +Core_0_L1I_load_hit 2362022 +Core_0_L1I_load_miss 971 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 + +Core_0_L2C_total_access 93001 +Core_0_L2C_total_hit 7273 +Core_0_L2C_total_miss 85728 +Core_0_L2C_loads 88610 +Core_0_L2C_load_hit 3469 +Core_0_L2C_load_miss 85141 +Core_0_L2C_RFOs 778 +Core_0_L2C_RFO_hit 315 +Core_0_L2C_RFO_miss 463 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 3613 +Core_0_L2C_writeback_hit 3489 +Core_0_L2C_writeback_miss 124 + +Core_0_LLC_total_access 88262 +Core_0_LLC_total_hit 3543 +Core_0_LLC_total_miss 84719 +Core_0_LLC_loads 85141 +Core_0_LLC_load_hit 825 +Core_0_LLC_load_miss 84316 +Core_0_LLC_RFOs 463 +Core_0_LLC_RFO_hit 85 +Core_0_LLC_RFO_miss 378 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 2658 +Core_0_LLC_writeback_hit 2633 +Core_0_LLC_writeback_miss 25 + + +CPU 1 cumulative IPC: 0.29646 instructions: 10625227 cycles: 35839755 +Core_1_L1D_total_access 3438848 +Core_1_L1D_total_hit 3350427 +Core_1_L1D_total_miss 88421 +Core_1_L1D_loads 2003024 +Core_1_L1D_load_hit 1915381 +Core_1_L1D_load_miss 87643 +Core_1_L1D_RFOs 1435824 +Core_1_L1D_RFO_hit 1435046 +Core_1_L1D_RFO_miss 778 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 + +Core_1_L1I_total_access 2362926 +Core_1_L1I_total_hit 2361955 +Core_1_L1I_total_miss 971 +Core_1_L1I_loads 2362926 +Core_1_L1I_load_hit 2361955 +Core_1_L1I_load_miss 971 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 + +Core_1_L2C_total_access 93006 +Core_1_L2C_total_hit 7312 +Core_1_L2C_total_miss 85694 +Core_1_L2C_loads 88614 +Core_1_L2C_load_hit 3480 +Core_1_L2C_load_miss 85134 +Core_1_L2C_RFOs 778 +Core_1_L2C_RFO_hit 325 +Core_1_L2C_RFO_miss 453 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 3614 +Core_1_L2C_writeback_hit 3507 +Core_1_L2C_writeback_miss 107 + +Core_1_LLC_total_access 88212 +Core_1_LLC_total_hit 3488 +Core_1_LLC_total_miss 84724 +Core_1_LLC_loads 85134 +Core_1_LLC_load_hit 822 +Core_1_LLC_load_miss 84312 +Core_1_LLC_RFOs 453 +Core_1_LLC_RFO_hit 73 +Core_1_LLC_RFO_miss 380 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 2625 +Core_1_LLC_writeback_hit 2593 +Core_1_LLC_writeback_miss 32 + + +CPU 2 cumulative IPC: 0.27902 instructions: 10000000 cycles: 35839755 +Core_2_L1D_total_access 3229035 +Core_2_L1D_total_hit 3150880 +Core_2_L1D_total_miss 78155 +Core_2_L1D_loads 1875287 +Core_2_L1D_load_hit 1797768 +Core_2_L1D_load_miss 77519 +Core_2_L1D_RFOs 1353748 +Core_2_L1D_RFO_hit 1353112 +Core_2_L1D_RFO_miss 636 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 + +Core_2_L1I_total_access 2218520 +Core_2_L1I_total_hit 2217659 +Core_2_L1I_total_miss 861 +Core_2_L1I_loads 2218520 +Core_2_L1I_load_hit 2217659 +Core_2_L1I_load_miss 861 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 + +Core_2_L2C_total_access 81988 +Core_2_L2C_total_hit 6487 +Core_2_L2C_total_miss 75501 +Core_2_L2C_loads 78380 +Core_2_L2C_load_hit 3275 +Core_2_L2C_load_miss 75105 +Core_2_L2C_RFOs 636 +Core_2_L2C_RFO_hit 318 +Core_2_L2C_RFO_miss 318 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 2972 +Core_2_L2C_writeback_hit 2894 +Core_2_L2C_writeback_miss 78 + +Core_2_LLC_total_access 77435 +Core_2_LLC_total_hit 2677 +Core_2_LLC_total_miss 74758 +Core_2_LLC_loads 75105 +Core_2_LLC_load_hit 631 +Core_2_LLC_load_miss 74474 +Core_2_LLC_RFOs 318 +Core_2_LLC_RFO_hit 51 +Core_2_LLC_RFO_miss 267 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 2012 +Core_2_LLC_writeback_hit 1995 +Core_2_LLC_writeback_miss 17 + + +CPU 3 cumulative IPC: 0.27902 instructions: 10000032 cycles: 35839755 +Core_3_L1D_total_access 3228931 +Core_3_L1D_total_hit 3150772 +Core_3_L1D_total_miss 78159 +Core_3_L1D_loads 1875307 +Core_3_L1D_load_hit 1797784 +Core_3_L1D_load_miss 77523 +Core_3_L1D_RFOs 1353624 +Core_3_L1D_RFO_hit 1352988 +Core_3_L1D_RFO_miss 636 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 + +Core_3_L1I_total_access 2218559 +Core_3_L1I_total_hit 2217698 +Core_3_L1I_total_miss 861 +Core_3_L1I_loads 2218559 +Core_3_L1I_load_hit 2217698 +Core_3_L1I_load_miss 861 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 + +Core_3_L2C_total_access 81992 +Core_3_L2C_total_hit 6482 +Core_3_L2C_total_miss 75510 +Core_3_L2C_loads 78384 +Core_3_L2C_load_hit 3285 +Core_3_L2C_load_miss 75099 +Core_3_L2C_RFOs 636 +Core_3_L2C_RFO_hit 306 +Core_3_L2C_RFO_miss 330 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 2972 +Core_3_L2C_writeback_hit 2891 +Core_3_L2C_writeback_miss 81 + +Core_3_LLC_total_access 77445 +Core_3_LLC_total_hit 2683 +Core_3_LLC_total_miss 74762 +Core_3_LLC_loads 75099 +Core_3_LLC_load_hit 618 +Core_3_LLC_load_miss 74481 +Core_3_LLC_RFOs 330 +Core_3_LLC_RFO_hit 64 +Core_3_LLC_RFO_miss 266 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 2016 +Core_3_LLC_writeback_hit 2001 +Core_3_LLC_writeback_miss 15 + + +[ROI Statistics] +Core_0_instructions 10000013 +Core_0_cycles 32366257 +Core_0_IPC 0.30896 + +Core_0_branch_prediction_accuracy 96.74369 +Core_0_branch_MPKI 5.97848 +Core_0_average_ROB_occupancy_at_mispredict 115.98840 + +Core_0_L1D_total_access 3232178 +Core_0_L1D_total_hit 3154022 +Core_0_L1D_total_miss 78156 +Core_0_L1D_total_overlap_miss 78156 +Core_0_L1D_loads 1877879 +Core_0_L1D_load_hit 1800359 +Core_0_L1D_load_miss 77520 +Core_0_L1D_RFOs 1354299 +Core_0_L1D_RFO_hit 1353663 +Core_0_L1D_RFO_miss 636 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 +Core_0_L1D_miss_rate 0.02418 +Core_0_L1D_MPKI 7.81560 +Core_0_L1D_demand_miss 78156 +Core_0_L1D_prefetch_requested 0 +Core_0_L1D_prefetch_issued 0 +Core_0_L1D_prefetch_useful 0 +Core_0_L1D_prefetch_useless 0 +Core_0_L1D_prefetch_late 0 +Core_0_L1D_average_miss_latency 217.27830 +Core_0_L1D_active_cycles 25989214 +Core_0_L1D_active_hit_cycles 11277505 +Core_0_L1D_active_miss_cycles 16190329 +Core_0_L1D_active_pure_miss_cycles 14711709 +Core_0_L1D_active_hit_miss_overlap_cycles 1478620 +Core_0_L1D_total_pure_miss 78138 +Core_0_L1D_pure_miss_rate 0.02418 +Core_0_L1D_active_cycles_per_core 25989214 +Core_0_L1D_active_hit_cycles_per_core 11277505 +Core_0_L1D_active_miss_cycles_per_core 16190329 +Core_0_L1D_active_pure_miss_cycles_per_core 14711709 +Core_0_L1D_hit_miss_overlap_cycles_per_core 1478620 +Core_0_L1D_camat_per_core 8.04077 + +Core_0_L1I_total_access 2220479 +Core_0_L1I_total_hit 2219618 +Core_0_L1I_total_miss 861 +Core_0_L1I_total_overlap_miss 861 +Core_0_L1I_loads 2220479 +Core_0_L1I_load_hit 2219618 +Core_0_L1I_load_miss 861 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 +Core_0_L1I_miss_rate 0.00039 +Core_0_L1I_MPKI 0.08610 +Core_0_L1I_demand_miss 861 +Core_0_L1I_prefetch_requested 0 +Core_0_L1I_prefetch_issued 0 +Core_0_L1I_prefetch_useful 0 +Core_0_L1I_prefetch_useless 0 +Core_0_L1I_prefetch_late 0 +Core_0_L1I_average_miss_latency 101.98026 +Core_0_L1I_active_cycles 2836195 +Core_0_L1I_active_hit_cycles 2772965 +Core_0_L1I_active_miss_cycles 66906 +Core_0_L1I_active_pure_miss_cycles 63230 +Core_0_L1I_active_hit_miss_overlap_cycles 3676 +Core_0_L1I_total_pure_miss 826 +Core_0_L1I_pure_miss_rate 0.00037 +Core_0_L1I_active_cycles_per_core 2836195 +Core_0_L1I_active_hit_cycles_per_core 2772965 +Core_0_L1I_active_miss_cycles_per_core 66906 +Core_0_L1I_active_pure_miss_cycles_per_core 63230 +Core_0_L1I_hit_miss_overlap_cycles_per_core 3676 +Core_0_L1I_camat_per_core 1.27729 + +Core_0_L2C_total_access 81988 +Core_0_L2C_total_hit 6350 +Core_0_L2C_total_miss 75638 +Core_0_L2C_total_overlap_miss 75544 +Core_0_L2C_loads 78381 +Core_0_L2C_load_hit 3185 +Core_0_L2C_load_miss 75196 +Core_0_L2C_RFOs 636 +Core_0_L2C_RFO_hit 288 +Core_0_L2C_RFO_miss 348 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 2971 +Core_0_L2C_writeback_hit 2877 +Core_0_L2C_writeback_miss 94 +Core_0_L2C_miss_rate 0.92255 +Core_0_L2C_MPKI 7.56380 +Core_0_L2C_demand_miss 75638 +Core_0_L2C_prefetch_requested 0 +Core_0_L2C_prefetch_issued 0 +Core_0_L2C_prefetch_useful 0 +Core_0_L2C_prefetch_useless 0 +Core_0_L2C_prefetch_late 0 +Core_0_L2C_average_miss_latency 208.67500 +Core_0_L2C_active_cycles 15958167 +Core_0_L2C_active_hit_cycles 1031152 +Core_0_L2C_active_miss_cycles 15049358 +Core_0_L2C_active_pure_miss_cycles 14927015 +Core_0_L2C_active_hit_miss_overlap_cycles 122343 +Core_0_L2C_total_pure_miss 75544 +Core_0_L2C_pure_miss_rate 0.92140 +Core_0_L2C_active_cycles_per_core 15958167 +Core_0_L2C_active_hit_cycles_per_core 1031152 +Core_0_L2C_active_miss_cycles_per_core 15049358 +Core_0_L2C_active_pure_miss_cycles_per_core 14927015 +Core_0_L2C_hit_miss_overlap_cycles_per_core 122343 +Core_0_L2C_camat_per_core 194.64028 + +Core_0_LLC_total_access 77605 +Core_0_LLC_total_hit 2885 +Core_0_LLC_total_miss 74720 +Core_0_LLC_total_overlap_miss 74708 +Core_0_LLC_loads 75196 +Core_0_LLC_load_hit 753 +Core_0_LLC_load_miss 74443 +Core_0_LLC_RFOs 348 +Core_0_LLC_RFO_hit 83 +Core_0_LLC_RFO_miss 265 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 2061 +Core_0_LLC_writeback_hit 2049 +Core_0_LLC_writeback_miss 12 +Core_0_LLC_miss_rate 0.96282 +Core_0_LLC_MPKI 7.47200 +Core_0_LLC_demand_miss 74720 +Core_0_LLC_prefetch_requested 0 +Core_0_LLC_prefetch_issued 0 +Core_0_LLC_prefetch_useful 0 +Core_0_LLC_prefetch_useless 0 +Core_0_LLC_prefetch_late 0 +Core_0_LLC_average_miss_latency 762.50830 +Core_0_LLC_active_cycles 28079859 +Core_0_LLC_active_hit_cycles 6392555 +Core_0_LLC_active_miss_cycles 27124682 +Core_0_LLC_active_pure_miss_cycles 21687304 +Core_0_LLC_active_hit_miss_overlap_cycles 5437378 +Core_0_LLC_total_pure_miss 74708 +Core_0_LLC_pure_miss_rate 0.96267 +Core_0_LLC_active_cycles_per_core 14298721 +Core_0_LLC_active_hit_cycles_per_core 1796036 +Core_0_LLC_active_miss_cycles_per_core 12640720 +Core_0_LLC_active_pure_miss_cycles_per_core 12502685 +Core_0_LLC_hit_miss_overlap_cycles_per_core 138035 +Core_0_LLC_camat_per_core 184.25000 + +Core_0_major_page_fault 0 +Core_0_minor_page_fault 4067 + +Core_1_instructions 10000016 +Core_1_cycles 32365872 +Core_1_IPC 0.30897 + +Core_1_branch_prediction_accuracy 96.74369 +Core_1_branch_MPKI 5.97847 +Core_1_average_ROB_occupancy_at_mispredict 115.99129 + +Core_1_L1D_total_access 3232107 +Core_1_L1D_total_hit 3153951 +Core_1_L1D_total_miss 78156 +Core_1_L1D_total_overlap_miss 78156 +Core_1_L1D_loads 1877810 +Core_1_L1D_load_hit 1800290 +Core_1_L1D_load_miss 77520 +Core_1_L1D_RFOs 1354297 +Core_1_L1D_RFO_hit 1353661 +Core_1_L1D_RFO_miss 636 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 +Core_1_L1D_miss_rate 0.02418 +Core_1_L1D_MPKI 7.81560 +Core_1_L1D_demand_miss 78156 +Core_1_L1D_prefetch_requested 0 +Core_1_L1D_prefetch_issued 0 +Core_1_L1D_prefetch_useful 0 +Core_1_L1D_prefetch_useless 0 +Core_1_L1D_prefetch_late 0 +Core_1_L1D_average_miss_latency 217.29075 +Core_1_L1D_active_cycles 25990674 +Core_1_L1D_active_hit_cycles 11277531 +Core_1_L1D_active_miss_cycles 16191494 +Core_1_L1D_active_pure_miss_cycles 14713143 +Core_1_L1D_active_hit_miss_overlap_cycles 1478351 +Core_1_L1D_total_pure_miss 78141 +Core_1_L1D_pure_miss_rate 0.02418 +Core_1_L1D_active_cycles_per_core 25990674 +Core_1_L1D_active_hit_cycles_per_core 11277531 +Core_1_L1D_active_miss_cycles_per_core 16191494 +Core_1_L1D_active_pure_miss_cycles_per_core 14713143 +Core_1_L1D_hit_miss_overlap_cycles_per_core 1478351 +Core_1_L1D_camat_per_core 8.04140 + +Core_1_L1I_total_access 2220415 +Core_1_L1I_total_hit 2219554 +Core_1_L1I_total_miss 861 +Core_1_L1I_total_overlap_miss 861 +Core_1_L1I_loads 2220415 +Core_1_L1I_load_hit 2219554 +Core_1_L1I_load_miss 861 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 +Core_1_L1I_miss_rate 0.00039 +Core_1_L1I_MPKI 0.08610 +Core_1_L1I_demand_miss 861 +Core_1_L1I_prefetch_requested 0 +Core_1_L1I_prefetch_issued 0 +Core_1_L1I_prefetch_useful 0 +Core_1_L1I_prefetch_useless 0 +Core_1_L1I_prefetch_late 0 +Core_1_L1I_average_miss_latency 103.78862 +Core_1_L1I_active_cycles 2836954 +Core_1_L1I_active_hit_cycles 2773089 +Core_1_L1I_active_miss_cycles 67557 +Core_1_L1I_active_pure_miss_cycles 63865 +Core_1_L1I_active_hit_miss_overlap_cycles 3692 +Core_1_L1I_total_pure_miss 830 +Core_1_L1I_pure_miss_rate 0.00037 +Core_1_L1I_active_cycles_per_core 2836954 +Core_1_L1I_active_hit_cycles_per_core 2773089 +Core_1_L1I_active_miss_cycles_per_core 67557 +Core_1_L1I_active_pure_miss_cycles_per_core 63865 +Core_1_L1I_hit_miss_overlap_cycles_per_core 3692 +Core_1_L1I_camat_per_core 1.27767 + +Core_1_L2C_total_access 81989 +Core_1_L2C_total_hit 6378 +Core_1_L2C_total_miss 75611 +Core_1_L2C_total_overlap_miss 75528 +Core_1_L2C_loads 78381 +Core_1_L2C_load_hit 3191 +Core_1_L2C_load_miss 75190 +Core_1_L2C_RFOs 636 +Core_1_L2C_RFO_hit 298 +Core_1_L2C_RFO_miss 338 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 2972 +Core_1_L2C_writeback_hit 2889 +Core_1_L2C_writeback_miss 83 +Core_1_L2C_miss_rate 0.92221 +Core_1_L2C_MPKI 7.56110 +Core_1_L2C_demand_miss 75611 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+Channel_0_RQ_row_buffer_hit 97690 +Channel_0_RQ_row_buffer_miss 71696 +Channel_0_WQ_row_buffer_hit 449 +Channel_0_WQ_row_buffer_miss 2703 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 3193 +Channel_0_RQ_row_buffer_hit 91931 +Channel_0_RQ_row_buffer_miss 57557 +Channel_0_WQ_row_buffer_hit 445 +Channel_0_WQ_row_buffer_miss 2511 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 2279 +avg_congested_cycle 0 9 +avg_congested_cycle 1 10 diff --git a/dram-nvram-noequal.txt b/dram-nvram-noequal.txt new file mode 100644 index 0000000..cfde8ae --- /dev/null +++ b/dram-nvram-noequal.txt @@ -0,0 +1,1148 @@ +************************************************* + ChampSim Multicore Out-of-Order Simulator + Last compiled: Mar 24 2022 21:12:50 +************************************************* + DRAM access latency: 170 + NVRAM access latency: 236 +Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s +Off-chip NVRAM Size: 8192 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s + DRAM_DBUS_RETURN_TIME: 13 + NVRAM_DBUS_RETURN_TIME: 13 + +trace_0 ./traces/403.gcc-17B.champsimtrace.xz +trace_1 ./traces/403.gcc-17B.champsimtrace.xz +trace_2 ./traces/403.gcc-17B.champsimtrace.xz +trace_3 ./traces/403.gcc-17B.champsimtrace.xz +warmup_instructions 100000 +simulation_instructions 10000000 +champsim_seed 680 + +num_cpus 4 +cpu_freq 4000 +dram_io_freq 2400 +nvram_io_freq 2400 +page_size 4096 +block_size 64 +max_read_per_cycle 20 +max_fill_per_cycle 20 +dram_channels 1 +dram_ranks 1 +dram_banks 8 +dram_rows 65536 +dram_columns 128 +dram_row_size 8 +dram_size 4096 +dram_pages 1048576 +NVram_channels 1 +NVram_ranks 2 +NVram_banks 8 +NVram_rows 65536 +NVram_columns 128 +NVram_row_size 8 +NVram_size 8192 +NVram_pages 2097152 + +fetch_width 20 +decode_width 20 +exec_width 20 +lq_width 20 +sq_width 20 +retire_width 20 +scheduler_size 128 +branch_mispredict_penalty 20 +rob_size 256 +lq_size 72 +sq_size 56 +num_instr_destinations_sparc 4 +num_instr_destinations 2 +num_instr_sources 4 + +itlb_set 16 +itlb_way 8 +itlb_rq_size 16 +itlb_wq_size 16 +itlb_pq_size 0 +itlb_mshr_size 8 +itlb_latency 1 + +dtlb_set 16 +dtlb_way 4 +dtlb_rq_size 16 +dtlb_wq_size 16 +dtlb_pq_size 0 +dtlb_mshr_size 8 +dtlb_latency 1 + +stlb_set 128 +stlb_way 12 +stlb_rq_size 32 +stlb_wq_size 32 +stlb_pq_size 0 +stlb_mshr_size 16 +stlb_latency 8 + +l1i_size 32 +l1i_set 64 +l1i_way 8 +l1i_rq_size 64 +l1i_wq_size 64 +l1i_pq_size 8 +l1i_mshr_size 8 +l1i_latency 1 + +l1d_size 32 +l1d_set 64 +l1d_way 8 +l1d_rq_size 64 +l1d_wq_size 64 +l1d_pq_size 32 +l1d_mshr_size 16 +l1d_latency 4 + +l2c_size 256 +l2c_set 512 +l2c_way 8 +l2c_rq_size 32 +l2c_wq_size 32 +l2c_pq_size 16 +l2c_mshr_size 32 +l2c_latency 10 + +llc_size 8192 +llc_set 8192 +llc_way 16 +llc_rq_size 128 +llc_wq_size 128 +llc_pq_size 128 +llc_mshr_size 256 +llc_latency 20 + +dram_channel_width 8 +dram_wq_size 64 +dram_rq_size 64 +tRP 15 +tRCD 15 +tCAS 12.5 +dram_dbus_turn_around_time 30 +dram_write_high_wm 56 +dram_write_low_wm 48 +min_dram_writes_per_switch 16 +dram_mtps 2400 +dram_dbus_return_time 13 + +NVram_channel_width 8 +NVram_wq_size 128 +NVram_rq_size 128 +NV_tRP 22 +NV_tRCD 22 +NV_tCAS 15 +NVram_dbus_turn_around_time 30 +NVram_write_high_wm 112 +NVram_write_low_wm 96 +min_NVram_writes_per_switch 16 +NVram_mtps 2400 +NVram_dbus_return_time 13 + + + +Warmup complete CPU 0 instructions: 100093 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 1 instructions: 100058 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 2 instructions: 100034 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) +Warmup complete CPU 3 instructions: 100001 cycles: 87538 (Simulation time: 0 hr 0 min 1 sec) + +Heartbeat CPU 1 instructions: 1000002 cycles: 3060933 heartbeat IPC: 0.32670 cumulative IPC: 0.30267 (Simulation time: 0 hr 0 min 41 sec) +Heartbeat CPU 0 instructions: 1000002 cycles: 3060984 heartbeat IPC: 0.32669 cumulative IPC: 0.30265 (Simulation time: 0 hr 0 min 41 sec) +Heartbeat CPU 3 instructions: 1000002 cycles: 3344230 heartbeat IPC: 0.29902 cumulative IPC: 0.27635 (Simulation time: 0 hr 0 min 46 sec) +Heartbeat CPU 2 instructions: 1000002 cycles: 3344291 heartbeat IPC: 0.29902 cumulative IPC: 0.27634 (Simulation time: 0 hr 0 min 46 sec) +Heartbeat CPU 0 instructions: 2000002 cycles: 6293640 heartbeat IPC: 0.30934 cumulative IPC: 0.30614 (Simulation time: 0 hr 1 min 36 sec) +Heartbeat CPU 1 instructions: 2000002 cycles: 6293691 heartbeat IPC: 0.30933 cumulative IPC: 0.30614 (Simulation time: 0 hr 1 min 36 sec) +Heartbeat CPU 3 instructions: 2000002 cycles: 6885330 heartbeat IPC: 0.28240 cumulative IPC: 0.27950 (Simulation time: 0 hr 1 min 46 sec) +Heartbeat CPU 2 instructions: 2000002 cycles: 6885391 heartbeat IPC: 0.28240 cumulative IPC: 0.27950 (Simulation time: 0 hr 1 min 46 sec) +Heartbeat CPU 1 instructions: 3000013 cycles: 9479796 heartbeat IPC: 0.31387 cumulative IPC: 0.30876 (Simulation time: 0 hr 2 min 33 sec) +Heartbeat CPU 0 instructions: 3000013 cycles: 9479847 heartbeat IPC: 0.31386 cumulative IPC: 0.30875 (Simulation time: 0 hr 2 min 33 sec) +Heartbeat CPU 2 instructions: 3000013 cycles: 10408762 heartbeat IPC: 0.28382 cumulative IPC: 0.28097 (Simulation time: 0 hr 2 min 51 sec) +Heartbeat CPU 3 instructions: 3000013 cycles: 10408823 heartbeat IPC: 0.28381 cumulative IPC: 0.28097 (Simulation time: 0 hr 2 min 51 sec) +Heartbeat CPU 0 instructions: 4000000 cycles: 12711135 heartbeat IPC: 0.30947 cumulative IPC: 0.30894 (Simulation time: 0 hr 3 min 35 sec) +Heartbeat CPU 1 instructions: 4000000 cycles: 12711186 heartbeat IPC: 0.30946 cumulative IPC: 0.30894 (Simulation time: 0 hr 3 min 35 sec) +Heartbeat CPU 3 instructions: 4000000 cycles: 13983217 heartbeat IPC: 0.27976 cumulative IPC: 0.28066 (Simulation time: 0 hr 4 min 1 sec) +Heartbeat CPU 2 instructions: 4000000 cycles: 13983278 heartbeat IPC: 0.27975 cumulative IPC: 0.28066 (Simulation time: 0 hr 4 min 1 sec) +Heartbeat CPU 1 instructions: 5000000 cycles: 16041667 heartbeat IPC: 0.30026 cumulative IPC: 0.30713 (Simulation time: 0 hr 4 min 44 sec) +Heartbeat CPU 0 instructions: 5000000 cycles: 16041718 heartbeat IPC: 0.30025 cumulative IPC: 0.30712 (Simulation time: 0 hr 4 min 44 sec) +Heartbeat CPU 2 instructions: 5000000 cycles: 17685232 heartbeat IPC: 0.27013 cumulative IPC: 0.27844 (Simulation time: 0 hr 5 min 19 sec) +Heartbeat CPU 3 instructions: 5000000 cycles: 17685293 heartbeat IPC: 0.27012 cumulative IPC: 0.27844 (Simulation time: 0 hr 5 min 19 sec) +Heartbeat CPU 0 instructions: 6000004 cycles: 19237416 heartbeat IPC: 0.31292 cumulative IPC: 0.30809 (Simulation time: 0 hr 5 min 52 sec) +Heartbeat CPU 1 instructions: 6000004 cycles: 19237467 heartbeat IPC: 0.31291 cumulative IPC: 0.30809 (Simulation time: 0 hr 5 min 52 sec) +Heartbeat CPU 3 instructions: 6000004 cycles: 21245046 heartbeat IPC: 0.28092 cumulative IPC: 0.27886 (Simulation time: 0 hr 6 min 36 sec) +Heartbeat CPU 2 instructions: 6000004 cycles: 21245107 heartbeat IPC: 0.28091 cumulative IPC: 0.27886 (Simulation time: 0 hr 6 min 36 sec) +Heartbeat CPU 0 instructions: 7000002 cycles: 22446316 heartbeat IPC: 0.31163 cumulative IPC: 0.30860 (Simulation time: 0 hr 7 min 2 sec) +Heartbeat CPU 1 instructions: 7000002 cycles: 22446367 heartbeat IPC: 0.31163 cumulative IPC: 0.30860 (Simulation time: 0 hr 7 min 2 sec) +Heartbeat CPU 3 instructions: 7000002 cycles: 24806304 heartbeat IPC: 0.28080 cumulative IPC: 0.27914 (Simulation time: 0 hr 7 min 56 sec) +Heartbeat CPU 2 instructions: 7000002 cycles: 24806541 heartbeat IPC: 0.28079 cumulative IPC: 0.27914 (Simulation time: 0 hr 7 min 56 sec) +Heartbeat CPU 1 instructions: 8000000 cycles: 25652313 heartbeat IPC: 0.31192 cumulative IPC: 0.30902 (Simulation time: 0 hr 8 min 15 sec) +Heartbeat CPU 0 instructions: 8000000 cycles: 25652604 heartbeat IPC: 0.31189 cumulative IPC: 0.30901 (Simulation time: 0 hr 8 min 15 sec) +Heartbeat CPU 3 instructions: 8000000 cycles: 28387017 heartbeat IPC: 0.27927 cumulative IPC: 0.27916 (Simulation time: 0 hr 9 min 17 sec) +Heartbeat CPU 2 instructions: 8000000 cycles: 28387078 heartbeat IPC: 0.27929 cumulative IPC: 0.27916 (Simulation time: 0 hr 9 min 17 sec) +Heartbeat CPU 0 instructions: 9000000 cycles: 28870611 heartbeat IPC: 0.31075 cumulative IPC: 0.30921 (Simulation time: 0 hr 9 min 27 sec) +Heartbeat CPU 1 instructions: 9000000 cycles: 28870662 heartbeat IPC: 0.31072 cumulative IPC: 0.30921 (Simulation time: 0 hr 9 min 27 sec) +Heartbeat CPU 3 instructions: 9000000 cycles: 31971369 heartbeat IPC: 0.27899 cumulative IPC: 0.27914 (Simulation time: 0 hr 10 min 36 sec) +Heartbeat CPU 2 instructions: 9000000 cycles: 31971430 heartbeat IPC: 0.27899 cumulative IPC: 0.27914 (Simulation time: 0 hr 10 min 36 sec) +Heartbeat CPU 0 instructions: 10000013 cycles: 32108554 heartbeat IPC: 0.30884 cumulative IPC: 0.30917 (Simulation time: 0 hr 10 min 39 sec) +Heartbeat CPU 1 instructions: 10000013 cycles: 32108605 heartbeat IPC: 0.30884 cumulative IPC: 0.30917 (Simulation time: 0 hr 10 min 39 sec) +Finished CPU 1 instructions: 10000016 cycles: 32365872 cumulative IPC: 0.30897 (Simulation time: 0 hr 10 min 46 sec) +Finished CPU 0 instructions: 10000013 cycles: 32366257 cumulative IPC: 0.30896 (Simulation time: 0 hr 10 min 46 sec) +Heartbeat CPU 3 instructions: 10000014 cycles: 35547415 heartbeat IPC: 0.27964 cumulative IPC: 0.27919 (Simulation time: 0 hr 11 min 52 sec) +Heartbeat CPU 2 instructions: 10000014 cycles: 35547476 heartbeat IPC: 0.27964 cumulative IPC: 0.27919 (Simulation time: 0 hr 11 min 52 sec) +Finished CPU 3 instructions: 10000001 cycles: 35838785 cumulative IPC: 0.27903 (Simulation time: 0 hr 11 min 59 sec) +Finished CPU 2 instructions: 10000000 cycles: 35839755 cumulative IPC: 0.27902 (Simulation time: 0 hr 11 min 59 sec) + +ChampSim completed all CPUs + +Total Simulation Statistics (not including warmup) + +CPU 0 cumulative IPC: 0.29646 instructions: 10625176 cycles: 35839755 +Core_0_L1D_total_access 3438879 +Core_0_L1D_total_hit 3350462 +Core_0_L1D_total_miss 88417 +Core_0_L1D_loads 2003043 +Core_0_L1D_load_hit 1915404 +Core_0_L1D_load_miss 87639 +Core_0_L1D_RFOs 1435836 +Core_0_L1D_RFO_hit 1435058 +Core_0_L1D_RFO_miss 778 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 + +Core_0_L1I_total_access 2362993 +Core_0_L1I_total_hit 2362022 +Core_0_L1I_total_miss 971 +Core_0_L1I_loads 2362993 +Core_0_L1I_load_hit 2362022 +Core_0_L1I_load_miss 971 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 + +Core_0_L2C_total_access 93001 +Core_0_L2C_total_hit 7273 +Core_0_L2C_total_miss 85728 +Core_0_L2C_loads 88610 +Core_0_L2C_load_hit 3469 +Core_0_L2C_load_miss 85141 +Core_0_L2C_RFOs 778 +Core_0_L2C_RFO_hit 315 +Core_0_L2C_RFO_miss 463 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 3613 +Core_0_L2C_writeback_hit 3489 +Core_0_L2C_writeback_miss 124 + +Core_0_LLC_total_access 88262 +Core_0_LLC_total_hit 3543 +Core_0_LLC_total_miss 84719 +Core_0_LLC_loads 85141 +Core_0_LLC_load_hit 825 +Core_0_LLC_load_miss 84316 +Core_0_LLC_RFOs 463 +Core_0_LLC_RFO_hit 85 +Core_0_LLC_RFO_miss 378 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 2658 +Core_0_LLC_writeback_hit 2633 +Core_0_LLC_writeback_miss 25 + + +CPU 1 cumulative IPC: 0.29646 instructions: 10625227 cycles: 35839755 +Core_1_L1D_total_access 3438848 +Core_1_L1D_total_hit 3350427 +Core_1_L1D_total_miss 88421 +Core_1_L1D_loads 2003024 +Core_1_L1D_load_hit 1915381 +Core_1_L1D_load_miss 87643 +Core_1_L1D_RFOs 1435824 +Core_1_L1D_RFO_hit 1435046 +Core_1_L1D_RFO_miss 778 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 + +Core_1_L1I_total_access 2362926 +Core_1_L1I_total_hit 2361955 +Core_1_L1I_total_miss 971 +Core_1_L1I_loads 2362926 +Core_1_L1I_load_hit 2361955 +Core_1_L1I_load_miss 971 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 + +Core_1_L2C_total_access 93006 +Core_1_L2C_total_hit 7312 +Core_1_L2C_total_miss 85694 +Core_1_L2C_loads 88614 +Core_1_L2C_load_hit 3480 +Core_1_L2C_load_miss 85134 +Core_1_L2C_RFOs 778 +Core_1_L2C_RFO_hit 325 +Core_1_L2C_RFO_miss 453 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 3614 +Core_1_L2C_writeback_hit 3507 +Core_1_L2C_writeback_miss 107 + +Core_1_LLC_total_access 88212 +Core_1_LLC_total_hit 3488 +Core_1_LLC_total_miss 84724 +Core_1_LLC_loads 85134 +Core_1_LLC_load_hit 822 +Core_1_LLC_load_miss 84312 +Core_1_LLC_RFOs 453 +Core_1_LLC_RFO_hit 73 +Core_1_LLC_RFO_miss 380 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 2625 +Core_1_LLC_writeback_hit 2593 +Core_1_LLC_writeback_miss 32 + + +CPU 2 cumulative IPC: 0.27902 instructions: 10000000 cycles: 35839755 +Core_2_L1D_total_access 3229035 +Core_2_L1D_total_hit 3150880 +Core_2_L1D_total_miss 78155 +Core_2_L1D_loads 1875287 +Core_2_L1D_load_hit 1797768 +Core_2_L1D_load_miss 77519 +Core_2_L1D_RFOs 1353748 +Core_2_L1D_RFO_hit 1353112 +Core_2_L1D_RFO_miss 636 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 + +Core_2_L1I_total_access 2218520 +Core_2_L1I_total_hit 2217659 +Core_2_L1I_total_miss 861 +Core_2_L1I_loads 2218520 +Core_2_L1I_load_hit 2217659 +Core_2_L1I_load_miss 861 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 + +Core_2_L2C_total_access 81988 +Core_2_L2C_total_hit 6487 +Core_2_L2C_total_miss 75501 +Core_2_L2C_loads 78380 +Core_2_L2C_load_hit 3275 +Core_2_L2C_load_miss 75105 +Core_2_L2C_RFOs 636 +Core_2_L2C_RFO_hit 318 +Core_2_L2C_RFO_miss 318 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 2972 +Core_2_L2C_writeback_hit 2894 +Core_2_L2C_writeback_miss 78 + +Core_2_LLC_total_access 77435 +Core_2_LLC_total_hit 2677 +Core_2_LLC_total_miss 74758 +Core_2_LLC_loads 75105 +Core_2_LLC_load_hit 631 +Core_2_LLC_load_miss 74474 +Core_2_LLC_RFOs 318 +Core_2_LLC_RFO_hit 51 +Core_2_LLC_RFO_miss 267 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 2012 +Core_2_LLC_writeback_hit 1995 +Core_2_LLC_writeback_miss 17 + + +CPU 3 cumulative IPC: 0.27902 instructions: 10000032 cycles: 35839755 +Core_3_L1D_total_access 3228931 +Core_3_L1D_total_hit 3150772 +Core_3_L1D_total_miss 78159 +Core_3_L1D_loads 1875307 +Core_3_L1D_load_hit 1797784 +Core_3_L1D_load_miss 77523 +Core_3_L1D_RFOs 1353624 +Core_3_L1D_RFO_hit 1352988 +Core_3_L1D_RFO_miss 636 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 + +Core_3_L1I_total_access 2218559 +Core_3_L1I_total_hit 2217698 +Core_3_L1I_total_miss 861 +Core_3_L1I_loads 2218559 +Core_3_L1I_load_hit 2217698 +Core_3_L1I_load_miss 861 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 + +Core_3_L2C_total_access 81992 +Core_3_L2C_total_hit 6482 +Core_3_L2C_total_miss 75510 +Core_3_L2C_loads 78384 +Core_3_L2C_load_hit 3285 +Core_3_L2C_load_miss 75099 +Core_3_L2C_RFOs 636 +Core_3_L2C_RFO_hit 306 +Core_3_L2C_RFO_miss 330 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 2972 +Core_3_L2C_writeback_hit 2891 +Core_3_L2C_writeback_miss 81 + +Core_3_LLC_total_access 77445 +Core_3_LLC_total_hit 2683 +Core_3_LLC_total_miss 74762 +Core_3_LLC_loads 75099 +Core_3_LLC_load_hit 618 +Core_3_LLC_load_miss 74481 +Core_3_LLC_RFOs 330 +Core_3_LLC_RFO_hit 64 +Core_3_LLC_RFO_miss 266 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 2016 +Core_3_LLC_writeback_hit 2001 +Core_3_LLC_writeback_miss 15 + + +[ROI Statistics] +Core_0_instructions 10000013 +Core_0_cycles 32366257 +Core_0_IPC 0.30896 + +Core_0_branch_prediction_accuracy 96.74369 +Core_0_branch_MPKI 5.97848 +Core_0_average_ROB_occupancy_at_mispredict 115.98840 + +Core_0_L1D_total_access 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+Core_3_L1D_active_cycles 26793834 +Core_3_L1D_active_hit_cycles 10546272 +Core_3_L1D_active_miss_cycles 17650816 +Core_3_L1D_active_pure_miss_cycles 16247562 +Core_3_L1D_active_hit_miss_overlap_cycles 1403254 +Core_3_L1D_total_pure_miss 78137 +Core_3_L1D_pure_miss_rate 0.02420 +Core_3_L1D_active_cycles_per_core 26793834 +Core_3_L1D_active_hit_cycles_per_core 10546272 +Core_3_L1D_active_miss_cycles_per_core 17650816 +Core_3_L1D_active_pure_miss_cycles_per_core 16247562 +Core_3_L1D_hit_miss_overlap_cycles_per_core 1403254 +Core_3_L1D_camat_per_core 8.29811 + +Core_3_L1I_total_access 2218547 +Core_3_L1I_total_hit 2217686 +Core_3_L1I_total_miss 861 +Core_3_L1I_total_overlap_miss 861 +Core_3_L1I_loads 2218547 +Core_3_L1I_load_hit 2217686 +Core_3_L1I_load_miss 861 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 +Core_3_L1I_miss_rate 0.00039 +Core_3_L1I_MPKI 0.08610 +Core_3_L1I_demand_miss 861 +Core_3_L1I_prefetch_requested 0 +Core_3_L1I_prefetch_issued 0 +Core_3_L1I_prefetch_useful 0 +Core_3_L1I_prefetch_useless 0 +Core_3_L1I_prefetch_late 0 +Core_3_L1I_average_miss_latency 102.82927 +Core_3_L1I_active_cycles 2658911 +Core_3_L1I_active_hit_cycles 2594518 +Core_3_L1I_active_miss_cycles 67851 +Core_3_L1I_active_pure_miss_cycles 64393 +Core_3_L1I_active_hit_miss_overlap_cycles 3458 +Core_3_L1I_total_pure_miss 829 +Core_3_L1I_pure_miss_rate 0.00037 +Core_3_L1I_active_cycles_per_core 2658911 +Core_3_L1I_active_hit_cycles_per_core 2594518 +Core_3_L1I_active_miss_cycles_per_core 67851 +Core_3_L1I_active_pure_miss_cycles_per_core 64393 +Core_3_L1I_hit_miss_overlap_cycles_per_core 3458 +Core_3_L1I_camat_per_core 1.19849 + +Core_3_L2C_total_access 81990 +Core_3_L2C_total_hit 6482 +Core_3_L2C_total_miss 75508 +Core_3_L2C_total_overlap_miss 75427 +Core_3_L2C_loads 78382 +Core_3_L2C_load_hit 3285 +Core_3_L2C_load_miss 75097 +Core_3_L2C_RFOs 636 +Core_3_L2C_RFO_hit 306 +Core_3_L2C_RFO_miss 330 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 2972 +Core_3_L2C_writeback_hit 2891 +Core_3_L2C_writeback_miss 81 +Core_3_L2C_miss_rate 0.92094 +Core_3_L2C_MPKI 7.55080 +Core_3_L2C_demand_miss 75508 +Core_3_L2C_prefetch_requested 0 +Core_3_L2C_prefetch_issued 0 +Core_3_L2C_prefetch_useful 0 +Core_3_L2C_prefetch_useless 0 +Core_3_L2C_prefetch_late 0 +Core_3_L2C_average_miss_latency 232.19528 +Core_3_L2C_active_cycles 17451446 +Core_3_L2C_active_hit_cycles 909492 +Core_3_L2C_active_miss_cycles 16650495 +Core_3_L2C_active_pure_miss_cycles 16541954 +Core_3_L2C_active_hit_miss_overlap_cycles 108541 +Core_3_L2C_total_pure_miss 75427 +Core_3_L2C_pure_miss_rate 0.91995 +Core_3_L2C_active_cycles_per_core 17451446 +Core_3_L2C_active_hit_cycles_per_core 909492 +Core_3_L2C_active_miss_cycles_per_core 16650495 +Core_3_L2C_active_pure_miss_cycles_per_core 16541954 +Core_3_L2C_hit_miss_overlap_cycles_per_core 108541 +Core_3_L2C_camat_per_core 212.84847 + +Core_3_LLC_total_access 77443 +Core_3_LLC_total_hit 2683 +Core_3_LLC_total_miss 74760 +Core_3_LLC_total_overlap_miss 74745 +Core_3_LLC_loads 75097 +Core_3_LLC_load_hit 618 +Core_3_LLC_load_miss 74479 +Core_3_LLC_RFOs 330 +Core_3_LLC_RFO_hit 64 +Core_3_LLC_RFO_miss 266 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 2016 +Core_3_LLC_writeback_hit 2001 +Core_3_LLC_writeback_miss 15 +Core_3_LLC_miss_rate 0.96536 +Core_3_LLC_MPKI 7.47600 +Core_3_LLC_demand_miss 74760 +Core_3_LLC_prefetch_requested 0 +Core_3_LLC_prefetch_issued 0 +Core_3_LLC_prefetch_useful 0 +Core_3_LLC_prefetch_useless 0 +Core_3_LLC_prefetch_late 0 +Core_3_LLC_average_miss_latency 762.10032 +Core_3_LLC_active_cycles 28079859 +Core_3_LLC_active_hit_cycles 6392555 +Core_3_LLC_active_miss_cycles 27124682 +Core_3_LLC_active_pure_miss_cycles 21687304 +Core_3_LLC_active_hit_miss_overlap_cycles 5437378 +Core_3_LLC_total_pure_miss 74745 +Core_3_LLC_pure_miss_rate 0.96516 +Core_3_LLC_active_cycles_per_core 15984775 +Core_3_LLC_active_hit_cycles_per_core 1573053 +Core_3_LLC_active_miss_cycles_per_core 14533321 +Core_3_LLC_active_pure_miss_cycles_per_core 14411722 +Core_3_LLC_hit_miss_overlap_cycles_per_core 121599 +Core_3_LLC_camat_per_core 206.40697 + +Core_3_major_page_fault 0 +Core_3_minor_page_fault 3636 + +Channel_0_RQ_row_buffer_hit 97690 +Channel_0_RQ_row_buffer_miss 71696 +Channel_0_WQ_row_buffer_hit 449 +Channel_0_WQ_row_buffer_miss 2703 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 3193 +Channel_0_RQ_row_buffer_hit 91931 +Channel_0_RQ_row_buffer_miss 57557 +Channel_0_WQ_row_buffer_hit 445 +Channel_0_WQ_row_buffer_miss 2511 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 2279 +avg_congested_cycle 0 9 +avg_congested_cycle 1 10 diff --git a/inc/cache.h b/inc/cache.h index b1af8f5..3ca415e 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -104,8 +104,16 @@ class CACHE : public MEMORY { pf_fill; // queues + // PACKET_QUEUE WQ0{NAME + "_WQ0", WQ_SIZE}, // write0 queue + // WQ1{NAME + "_WQ1", WQ_SIZE}, // write1 queue + + // RQ0{NAME + "_RQ0", RQ_SIZE}, // read0 queue + // RQ1{NAME + "_RQ1", RQ_SIZE}, // read1 queue + PACKET_QUEUE WQ{NAME + "_WQ", WQ_SIZE}, // write queue - RQ{NAME + "_RQ", RQ_SIZE}, // read queue + RQ{NAME + "_RQ", RQ_SIZE}, // read0 queue + + PQ{NAME + "_PQ", PQ_SIZE}, // prefetch queue MSHR{NAME + "_MSHR", MSHR_SIZE}, // MSHR PROCESSED{NAME + "_PROCESSED", ROB_SIZE}; // processed queue @@ -213,6 +221,10 @@ class CACHE : public MEMORY { }; // functions + // int CACHE::sub_add_rq(PACKET_QUEUE read_queue, PACKET_QUEUE write_queue, PACKET *packet); + // int CACHE::sub_add_wq(PACKET_QUEUE read_queue, PACKET_QUEUE write_queue, PACKET *packet); + // int CACHE::sub_add_pq(PACKET_QUEUE read_queue, PACKET_QUEUE write_queue, PACKET *packet); + int add_rq(PACKET *packet), add_wq(PACKET *packet), add_pq(PACKET *packet); diff --git a/inc/champsim.h b/inc/champsim.h index fd7c145..4020bff 100644 --- a/inc/champsim.h +++ b/inc/champsim.h @@ -36,6 +36,7 @@ #define NUM_CPUS 1 #define CPU_FREQ 4000 #define DRAM_IO_FREQ 2400 // DDR4-2400 +#define NVRAM_IO_FREQ 1600 // DDR4-2400 #define PAGE_SIZE 4096 #define LOG2_PAGE_SIZE 12 @@ -53,12 +54,12 @@ #define FILL_LLC 4 #define FILL_DRC 8 #define FILL_DRAM 16 - +#define FILL_NVRAM 16 // DRAM #define DRAM_CHANNELS 1 // default: assuming one DIMM per one channel 4GB * 1 => 4GB off-chip memory #define LOG2_DRAM_CHANNELS 0 -#define DRAM_RANKS 1 // 512MB * 8 ranks => 4GB per DIMM -#define LOG2_DRAM_RANKS 0 +#define DRAM_RANKS 4 // 512MB * 8 ranks => 4GB per DIMM +#define LOG2_DRAM_RANKS 2 #define DRAM_BANKS 8 // 64MB * 8 banks => 512MB per rank #define LOG2_DRAM_BANKS 3 #define DRAM_ROWS 65536 // 2KB * 32K rows => 64MB per bank @@ -69,6 +70,22 @@ #define DRAM_SIZE (DRAM_CHANNELS*DRAM_RANKS*DRAM_BANKS*DRAM_ROWS*DRAM_ROW_SIZE/1024) #define DRAM_PAGES ((DRAM_SIZE<<10)>>2) + +// NVRAM /////////////////////////////////////////////// +#define NVRAM_CHANNELS 1 // default: assuming one DIMM per one channel 4GB * 1 => 4GB off-chip memory +#define LOG2_NVRAM_CHANNELS 0 +#define NVRAM_RANKS 1 // 512MB * 8 ranks => 4GB per DIMM +#define LOG2_NVRAM_RANKS 0 +#define NVRAM_BANKS 8 // 64MB * 8 banks => 512MB per rank +#define LOG2_NVRAM_BANKS 3 +#define NVRAM_ROWS 65536 // 2KB * 32K rows => 64MB per bank +#define LOG2_NVRAM_ROWS 16 +#define NVRAM_COLUMNS 128 // 64B * 32 column chunks (Assuming 1B DRAM cell * 8 chips * 8 transactions = 64B size of column chunks) => 2KB per row +#define LOG2_NVRAM_COLUMNS 7 +#define NVRAM_ROW_SIZE (BLOCK_SIZE*NVRAM_COLUMNS/1024) + +#define NVRAM_SIZE (NVRAM_CHANNELS*NVRAM_RANKS*NVRAM_BANKS*NVRAM_ROWS*NVRAM_ROW_SIZE/1024) +#define NVRAM_PAGES ((NVRAM_SIZE<<10)>>2) //#define DRAM_PAGES 10 using namespace std; diff --git a/inc/champsim.h.bak b/inc/champsim.h.bak index 38ad34d..e38f8ea 100644 --- a/inc/champsim.h.bak +++ b/inc/champsim.h.bak @@ -36,6 +36,7 @@ #define NUM_CPUS 4 #define CPU_FREQ 4000 #define DRAM_IO_FREQ 2400 // DDR4-2400 +#define NVRAM_IO_FREQ 1600 // DDR4-2400 #define PAGE_SIZE 4096 #define LOG2_PAGE_SIZE 12 @@ -53,12 +54,12 @@ #define FILL_LLC 4 #define FILL_DRC 8 #define FILL_DRAM 16 - +#define FILL_NVRAM 16 // DRAM #define DRAM_CHANNELS 1 // default: assuming one DIMM per one channel 4GB * 1 => 4GB off-chip memory #define LOG2_DRAM_CHANNELS 0 -#define DRAM_RANKS 1 // 512MB * 8 ranks => 4GB per DIMM -#define LOG2_DRAM_RANKS 0 +#define DRAM_RANKS 4 // 512MB * 8 ranks => 4GB per DIMM +#define LOG2_DRAM_RANKS 2 #define DRAM_BANKS 8 // 64MB * 8 banks => 512MB per rank #define LOG2_DRAM_BANKS 3 #define DRAM_ROWS 65536 // 2KB * 32K rows => 64MB per bank @@ -69,6 +70,22 @@ #define DRAM_SIZE (DRAM_CHANNELS*DRAM_RANKS*DRAM_BANKS*DRAM_ROWS*DRAM_ROW_SIZE/1024) #define DRAM_PAGES ((DRAM_SIZE<<10)>>2) + +// NVRAM /////////////////////////////////////////////// +#define NVRAM_CHANNELS 1 // default: assuming one DIMM per one channel 4GB * 1 => 4GB off-chip memory +#define LOG2_NVRAM_CHANNELS 0 +#define NVRAM_RANKS 1 // 512MB * 8 ranks => 4GB per DIMM +#define LOG2_NVRAM_RANKS 0 +#define NVRAM_BANKS 8 // 64MB * 8 banks => 512MB per rank +#define LOG2_NVRAM_BANKS 3 +#define NVRAM_ROWS 65536 // 2KB * 32K rows => 64MB per bank +#define LOG2_NVRAM_ROWS 16 +#define NVRAM_COLUMNS 128 // 64B * 32 column chunks (Assuming 1B DRAM cell * 8 chips * 8 transactions = 64B size of column chunks) => 2KB per row +#define LOG2_NVRAM_COLUMNS 7 +#define NVRAM_ROW_SIZE (BLOCK_SIZE*NVRAM_COLUMNS/1024) + +#define NVRAM_SIZE (NVRAM_CHANNELS*NVRAM_RANKS*NVRAM_BANKS*NVRAM_ROWS*NVRAM_ROW_SIZE/1024) +#define NVRAM_PAGES ((NVRAM_SIZE<<10)>>2) //#define DRAM_PAGES 10 using namespace std; diff --git a/inc/dram_controller.h b/inc/dram_controller.h index 455f8bf..d221218 100644 --- a/inc/dram_controller.h +++ b/inc/dram_controller.h @@ -12,6 +12,7 @@ #define tRCD_DRAM_NANOSECONDS 15 #define tCAS_DRAM_NANOSECONDS 12.5 + // the data bus must wait this amount of time when switching between reads and writes, and vice versa #define DRAM_DBUS_TURN_AROUND_TIME ((15*CPU_FREQ)/2000) // 7.5 ns extern uint32_t DRAM_MTPS, DRAM_DBUS_RETURN_TIME; @@ -21,7 +22,119 @@ extern uint32_t DRAM_MTPS, DRAM_DBUS_RETURN_TIME; #define DRAM_WRITE_LOW_WM ((DRAM_WQ_SIZE*3)>>2) // 6/8th #define MIN_DRAM_WRITES_PER_SWITCH (DRAM_WQ_SIZE*1/4) -void print_dram_config(); + + + +/////////////// NVRAM Config//////////////////////////. +#define NVRAM_CHANNEL_WIDTH 8 // 8B +#define NVRAM_WQ_SIZE 128 +#define NVRAM_RQ_SIZE 128 + +#define tRP_NVRAM_NANOSECONDS 22 +#define tRCD_NVRAM_NANOSECONDS 22 +#define tCAS_NVRAM_NANOSECONDS 15 + + +// the data bus must wait this amount of time when switching between reads and writes, and vice versa +#define NVRAM_DBUS_TURN_AROUND_TIME ((18*CPU_FREQ)/2000) // ?? ns +extern uint32_t NVRAM_MTPS, NVRAM_DBUS_RETURN_TIME; + +// these values control when to send out a burst of writes +#define NVRAM_WRITE_HIGH_WM ((NVRAM_WQ_SIZE*7)>>3) // 7/8th +#define NVRAM_WRITE_LOW_WM ((NVRAM_WQ_SIZE*3)>>2) // 6/8th +#define MIN_NVRAM_WRITES_PER_SWITCH (NVRAM_WQ_SIZE*1/4) + + +void print_dram_config(); +void print_NVram_config(); + + +////////////////// NVRAM ///////////////////////////////////// + +class MEMORY_CONTROLLER_NV : public MEMORY { + public: + const string NAME; + + DRAM_ARRAY NVram_array[NVRAM_CHANNELS][NVRAM_RANKS][NVRAM_BANKS]; + uint64_t dbus_cycle_available[NVRAM_CHANNELS], dbus_cycle_congested[NVRAM_CHANNELS], dbus_congested[NUM_TYPES+1][NUM_TYPES+1]; + uint64_t bank_cycle_available[NVRAM_CHANNELS][NVRAM_RANKS][NVRAM_BANKS]; + uint8_t do_write, write_mode[NVRAM_CHANNELS]; + uint32_t processed_writes, scheduled_reads[NVRAM_CHANNELS], scheduled_writes[NVRAM_CHANNELS]; + int fill_level; + + BANK_REQUEST bank_request[NVRAM_CHANNELS][NVRAM_RANKS][NVRAM_BANKS]; + + // queues + PACKET_QUEUE WQ[NVRAM_CHANNELS], RQ[NVRAM_CHANNELS]; + + // constructor + MEMORY_CONTROLLER_NV(string v1) : NAME (v1) { + for (uint32_t i=0; iis_WQ) { // update data bus cycle time - dbus_cycle_available[op_channel] = current_core_cycle[op_cpu] + DRAM_DBUS_RETURN_TIME; + dbus_cycle_available[op_channel] = current_core_cycle[op_cpu] + NVRAM_DBUS_RETURN_TIME; if (bank_request[op_channel][op_rank][op_bank].row_buffer_hit) queue->ROW_BUFFER_HIT++; else queue->ROW_BUFFER_MISS++; - // this bank is ready for another DRAM request + // this bank is ready for another NVRAM request bank_request[op_channel][op_rank][op_bank].request_index = -1; bank_request[op_channel][op_rank][op_bank].row_buffer_hit = 0; bank_request[op_channel][op_rank][op_bank].working = false; @@ -659,7 +659,7 @@ void MEMORY_CONTROLLER_NV::process(PACKET_QUEUE *queue) else queue->ROW_BUFFER_MISS++; - // this bank is ready for another DRAM request + // this bank is ready for another NVRAM request bank_request[op_channel][op_rank][op_bank].request_index = -1; bank_request[op_channel][op_rank][op_bank].row_buffer_hit = 0; bank_request[op_channel][op_rank][op_bank].working = false; diff --git a/src/main.cc b/src/main.cc index 39486b7..029e537 100644 --- a/src/main.cc +++ b/src/main.cc @@ -643,11 +643,11 @@ int main(int argc, char** argv) DRAM_MTPS = DRAM_IO_FREQ/4; else DRAM_MTPS = DRAM_IO_FREQ; - // if (knob_low_bandwidth) + if (knob_low_bandwidth) - NVRAM_MTPS = DRAM_MTPS/4; - // else - NVRAM_MTPS = DRAM_MTPS; + NVRAM_MTPS = NVRAM_IO_FREQ/4; + else + NVRAM_MTPS = NVRAM_IO_FREQ; // DRAM access latency tRP = (uint32_t)((1.0 * tRP_DRAM_NANOSECONDS * CPU_FREQ) / 1000); @@ -671,6 +671,7 @@ int main(int argc, char** argv) printf("Off-chip DRAM Size: %u MB Channels: %u Width: %u-bit Data Rate: %u MT/s\n", DRAM_SIZE, DRAM_CHANNELS, 8*DRAM_CHANNEL_WIDTH, DRAM_MTPS); + printf("Off-chip NVRAM Size: %u MB Channels: %u Width: %u-bit Data Rate: %u MT/s\n", NVRAM_SIZE, NVRAM_CHANNELS, 8*NVRAM_CHANNEL_WIDTH, NVRAM_MTPS); diff --git a/test10mil.txt b/test10mil.txt new file mode 100644 index 0000000..36dc958 --- /dev/null +++ b/test10mil.txt @@ -0,0 +1,1088 @@ +************************************************* + ChampSim Multicore Out-of-Order Simulator + Last compiled: Mar 20 2022 18:18:42 +************************************************* + DRAM access latency: 170 +Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s + DRAM_DBUS_RETURN_TIME: 13 + +trace_0 ./traces/437.leslie3d-265B.champsimtrace.xz +trace_1 ./traces/429.mcf-22B.champsimtrace.xz +trace_2 ./traces/436.cactusADM-1804B.champsimtrace.xz +trace_3 ./traces/403.gcc-17B.champsimtrace.xz +warmup_instructions 100000 +simulation_instructions 1000000 +champsim_seed 830 + +num_cpus 4 +cpu_freq 4000 +dram_io_freq 2400 +page_size 4096 +block_size 64 +max_read_per_cycle 20 +max_fill_per_cycle 20 +dram_channels 1 +dram_ranks 1 +dram_banks 8 +dram_rows 65536 +dram_columns 128 +dram_row_size 8 +dram_size 4096 +dram_pages 1048576 + +fetch_width 20 +decode_width 20 +exec_width 20 +lq_width 20 +sq_width 20 +retire_width 20 +scheduler_size 128 +branch_mispredict_penalty 20 +rob_size 256 +lq_size 72 +sq_size 56 +num_instr_destinations_sparc 4 +num_instr_destinations 2 +num_instr_sources 4 + +itlb_set 16 +itlb_way 8 +itlb_rq_size 16 +itlb_wq_size 16 +itlb_pq_size 0 +itlb_mshr_size 8 +itlb_latency 1 + +dtlb_set 16 +dtlb_way 4 +dtlb_rq_size 16 +dtlb_wq_size 16 +dtlb_pq_size 0 +dtlb_mshr_size 8 +dtlb_latency 1 + +stlb_set 128 +stlb_way 12 +stlb_rq_size 32 +stlb_wq_size 32 +stlb_pq_size 0 +stlb_mshr_size 16 +stlb_latency 8 + +l1i_size 32 +l1i_set 64 +l1i_way 8 +l1i_rq_size 64 +l1i_wq_size 64 +l1i_pq_size 8 +l1i_mshr_size 8 +l1i_latency 1 + +l1d_size 32 +l1d_set 64 +l1d_way 8 +l1d_rq_size 64 +l1d_wq_size 64 +l1d_pq_size 32 +l1d_mshr_size 16 +l1d_latency 4 + +l2c_size 256 +l2c_set 512 +l2c_way 8 +l2c_rq_size 32 +l2c_wq_size 32 +l2c_pq_size 16 +l2c_mshr_size 32 +l2c_latency 10 + +llc_size 8192 +llc_set 8192 +llc_way 16 +llc_rq_size 128 +llc_wq_size 128 +llc_pq_size 128 +llc_mshr_size 256 +llc_latency 20 + +dram_channel_width 8 +dram_wq_size 64 +dram_rq_size 64 +tRP 15 +tRCD 15 +tCAS 12.5 +dram_dbus_turn_around_time 30 +dram_write_high_wm 56 +dram_write_low_wm 48 +min_dram_writes_per_switch 16 +dram_mtps 2400 +dram_dbus_return_time 13 + + + +Warmup complete CPU 0 instructions: 255217 cycles: 87603 (Simulation time: 0 hr 0 min 3 sec) +Warmup complete CPU 1 instructions: 279214 cycles: 87603 (Simulation time: 0 hr 0 min 3 sec) +Warmup complete CPU 2 instructions: 197294 cycles: 87603 (Simulation time: 0 hr 0 min 3 sec) +Warmup complete CPU 3 instructions: 100001 cycles: 87603 (Simulation time: 0 hr 0 min 3 sec) + +Heartbeat CPU 0 instructions: 1000001 cycles: 1050520 heartbeat IPC: 0.95191 cumulative IPC: 0.77347 (Simulation time: 0 hr 0 min 23 sec) +Finished CPU 0 instructions: 1000000 cycles: 1296763 cumulative IPC: 0.77115 (Simulation time: 0 hr 0 min 31 sec) +Heartbeat CPU 2 instructions: 1000000 cycles: 1731713 heartbeat IPC: 0.57746 cumulative IPC: 0.48823 (Simulation time: 0 hr 0 min 40 sec) +Finished CPU 2 instructions: 1000018 cycles: 1961907 cumulative IPC: 0.50972 (Simulation time: 0 hr 0 min 49 sec) +Heartbeat CPU 1 instructions: 1000008 cycles: 2116338 heartbeat IPC: 0.47252 cumulative IPC: 0.35529 (Simulation time: 0 hr 0 min 51 sec) +Heartbeat CPU 0 instructions: 2000004 cycles: 2349326 heartbeat IPC: 0.76994 cumulative IPC: 0.77144 (Simulation time: 0 hr 0 min 58 sec) +Finished CPU 1 instructions: 1000000 cycles: 2839304 cumulative IPC: 0.35220 (Simulation time: 0 hr 1 min 16 sec) +Heartbeat CPU 3 instructions: 1000002 cycles: 3169341 heartbeat IPC: 0.31552 cumulative IPC: 0.29204 (Simulation time: 0 hr 1 min 23 sec) +Finished CPU 3 instructions: 1000003 cycles: 3416514 cumulative IPC: 0.29270 (Simulation time: 0 hr 1 min 34 sec) + +ChampSim completed all CPUs + +Total Simulation Statistics (not including warmup) + +CPU 0 cumulative IPC: 0.76735 instructions: 2621677 cycles: 3416514 +Core_0_L1D_total_access 693120 +Core_0_L1D_total_hit 663579 +Core_0_L1D_total_miss 29541 +Core_0_L1D_loads 604329 +Core_0_L1D_load_hit 581702 +Core_0_L1D_load_miss 22627 +Core_0_L1D_RFOs 88791 +Core_0_L1D_RFO_hit 81877 +Core_0_L1D_RFO_miss 6914 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 + +Core_0_L1I_total_access 449300 +Core_0_L1I_total_hit 449300 +Core_0_L1I_total_miss 0 +Core_0_L1I_loads 449300 +Core_0_L1I_load_hit 449300 +Core_0_L1I_load_miss 0 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 + +Core_0_L2C_total_access 39020 +Core_0_L2C_total_hit 24344 +Core_0_L2C_total_miss 14676 +Core_0_L2C_loads 22627 +Core_0_L2C_load_hit 10312 +Core_0_L2C_load_miss 12315 +Core_0_L2C_RFOs 6913 +Core_0_L2C_RFO_hit 4552 +Core_0_L2C_RFO_miss 2361 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 9480 +Core_0_L2C_writeback_hit 9480 +Core_0_L2C_writeback_miss 0 + +Core_0_LLC_total_access 16658 +Core_0_LLC_total_hit 1986 +Core_0_LLC_total_miss 14672 +Core_0_LLC_loads 12315 +Core_0_LLC_load_hit 3 +Core_0_LLC_load_miss 12312 +Core_0_LLC_RFOs 2361 +Core_0_LLC_RFO_hit 1 +Core_0_LLC_RFO_miss 2360 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 1982 +Core_0_LLC_writeback_hit 1982 +Core_0_LLC_writeback_miss 0 + + +CPU 1 cumulative IPC: 0.35447 instructions: 1211067 cycles: 3416514 +Core_1_L1D_total_access 412376 +Core_1_L1D_total_hit 384786 +Core_1_L1D_total_miss 27590 +Core_1_L1D_loads 146662 +Core_1_L1D_load_hit 119094 +Core_1_L1D_load_miss 27568 +Core_1_L1D_RFOs 265714 +Core_1_L1D_RFO_hit 265692 +Core_1_L1D_RFO_miss 22 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 + +Core_1_L1I_total_access 218506 +Core_1_L1I_total_hit 218506 +Core_1_L1I_total_miss 0 +Core_1_L1I_loads 218506 +Core_1_L1I_load_hit 218506 +Core_1_L1I_load_miss 0 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 + +Core_1_L2C_total_access 39923 +Core_1_L2C_total_hit 13336 +Core_1_L2C_total_miss 26587 +Core_1_L2C_loads 27531 +Core_1_L2C_load_hit 988 +Core_1_L2C_load_miss 26543 +Core_1_L2C_RFOs 22 +Core_1_L2C_RFO_hit 22 +Core_1_L2C_RFO_miss 0 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 12370 +Core_1_L2C_writeback_hit 12326 +Core_1_L2C_writeback_miss 44 + +Core_1_LLC_total_access 36707 +Core_1_LLC_total_hit 10303 +Core_1_LLC_total_miss 26404 +Core_1_LLC_loads 26543 +Core_1_LLC_load_hit 139 +Core_1_LLC_load_miss 26404 +Core_1_LLC_RFOs 0 +Core_1_LLC_RFO_hit 0 +Core_1_LLC_RFO_miss 0 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 10164 +Core_1_LLC_writeback_hit 10164 +Core_1_LLC_writeback_miss 0 + + +CPU 2 cumulative IPC: 0.49474 instructions: 1690270 cycles: 3416514 +Core_2_L1D_total_access 811764 +Core_2_L1D_total_hit 801311 +Core_2_L1D_total_miss 10453 +Core_2_L1D_loads 545637 +Core_2_L1D_load_hit 536024 +Core_2_L1D_load_miss 9613 +Core_2_L1D_RFOs 266127 +Core_2_L1D_RFO_hit 265287 +Core_2_L1D_RFO_miss 840 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 + +Core_2_L1I_total_access 385559 +Core_2_L1I_total_hit 385559 +Core_2_L1I_total_miss 0 +Core_2_L1I_loads 385559 +Core_2_L1I_load_hit 385559 +Core_2_L1I_load_miss 0 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 + +Core_2_L2C_total_access 11398 +Core_2_L2C_total_hit 5930 +Core_2_L2C_total_miss 5468 +Core_2_L2C_loads 9613 +Core_2_L2C_load_hit 4985 +Core_2_L2C_load_miss 4628 +Core_2_L2C_RFOs 840 +Core_2_L2C_RFO_hit 0 +Core_2_L2C_RFO_miss 840 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 945 +Core_2_L2C_writeback_hit 945 +Core_2_L2C_writeback_miss 0 + +Core_2_LLC_total_access 5783 +Core_2_LLC_total_hit 315 +Core_2_LLC_total_miss 5468 +Core_2_LLC_loads 4628 +Core_2_LLC_load_hit 0 +Core_2_LLC_load_miss 4628 +Core_2_LLC_RFOs 840 +Core_2_LLC_RFO_hit 0 +Core_2_LLC_RFO_miss 840 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 315 +Core_2_LLC_writeback_hit 315 +Core_2_LLC_writeback_miss 0 + + +CPU 3 cumulative IPC: 0.29270 instructions: 1000003 cycles: 3416514 +Core_3_L1D_total_access 325651 +Core_3_L1D_total_hit 318074 +Core_3_L1D_total_miss 7577 +Core_3_L1D_loads 188008 +Core_3_L1D_load_hit 180548 +Core_3_L1D_load_miss 7460 +Core_3_L1D_RFOs 137643 +Core_3_L1D_RFO_hit 137526 +Core_3_L1D_RFO_miss 117 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 + +Core_3_L1I_total_access 210082 +Core_3_L1I_total_hit 209810 +Core_3_L1I_total_miss 272 +Core_3_L1I_loads 210082 +Core_3_L1I_load_hit 209810 +Core_3_L1I_load_miss 272 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 + +Core_3_L2C_total_access 8318 +Core_3_L2C_total_hit 1016 +Core_3_L2C_total_miss 7302 +Core_3_L2C_loads 7732 +Core_3_L2C_load_hit 511 +Core_3_L2C_load_miss 7221 +Core_3_L2C_RFOs 117 +Core_3_L2C_RFO_hit 41 +Core_3_L2C_RFO_miss 76 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 469 +Core_3_L2C_writeback_hit 464 +Core_3_L2C_writeback_miss 5 + +Core_3_LLC_total_access 7487 +Core_3_LLC_total_hit 253 +Core_3_LLC_total_miss 7234 +Core_3_LLC_loads 7221 +Core_3_LLC_load_hit 61 +Core_3_LLC_load_miss 7160 +Core_3_LLC_RFOs 76 +Core_3_LLC_RFO_hit 2 +Core_3_LLC_RFO_miss 74 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 190 +Core_3_LLC_writeback_hit 190 +Core_3_LLC_writeback_miss 0 + + +[ROI Statistics] +Core_0_instructions 1000000 +Core_0_cycles 1296763 +Core_0_IPC 0.77115 + +Core_0_branch_prediction_accuracy 99.05101 +Core_0_branch_MPKI 0.23804 +Core_0_average_ROB_occupancy_at_mispredict 218.86687 + +Core_0_L1D_total_access 265941 +Core_0_L1D_total_hit 254487 +Core_0_L1D_total_miss 11454 +Core_0_L1D_total_overlap_miss 11454 +Core_0_L1D_loads 232063 +Core_0_L1D_load_hit 223290 +Core_0_L1D_load_miss 8773 +Core_0_L1D_RFOs 33878 +Core_0_L1D_RFO_hit 31197 +Core_0_L1D_RFO_miss 2681 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 +Core_0_L1D_miss_rate 0.04307 +Core_0_L1D_MPKI 11.45400 +Core_0_L1D_demand_miss 11454 +Core_0_L1D_prefetch_requested 0 +Core_0_L1D_prefetch_issued 0 +Core_0_L1D_prefetch_useful 0 +Core_0_L1D_prefetch_useless 0 +Core_0_L1D_prefetch_late 0 +Core_0_L1D_average_miss_latency 329.51816 +Core_0_L1D_active_cycles 3078962 +Core_0_L1D_active_hit_cycles 1498223 +Core_0_L1D_active_miss_cycles 2151841 +Core_0_L1D_active_pure_miss_cycles 1580739 +Core_0_L1D_active_hit_miss_overlap_cycles 571102 +Core_0_L1D_total_pure_miss 10573 +Core_0_L1D_pure_miss_rate 0.03976 +Core_0_L1D_active_cycles_per_core 3078962 +Core_0_L1D_active_hit_cycles_per_core 1498223 +Core_0_L1D_active_miss_cycles_per_core 2151841 +Core_0_L1D_active_pure_miss_cycles_per_core 1580739 +Core_0_L1D_hit_miss_overlap_cycles_per_core 571102 +Core_0_L1D_camat_per_core 11.57761 + +Core_0_L1I_total_access 172016 +Core_0_L1I_total_hit 172016 +Core_0_L1I_total_miss 0 +Core_0_L1I_total_overlap_miss 0 +Core_0_L1I_loads 172016 +Core_0_L1I_load_hit 172016 +Core_0_L1I_load_miss 0 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 +Core_0_L1I_miss_rate 0.00000 +Core_0_L1I_MPKI 0.00000 +Core_0_L1I_demand_miss 0 +Core_0_L1I_prefetch_requested 0 +Core_0_L1I_prefetch_issued 0 +Core_0_L1I_prefetch_useful 0 +Core_0_L1I_prefetch_useless 0 +Core_0_L1I_prefetch_late 0 +Core_0_L1I_average_miss_latency -nan +Core_0_L1I_active_cycles 617988 +Core_0_L1I_active_hit_cycles 617988 +Core_0_L1I_active_miss_cycles 0 +Core_0_L1I_active_pure_miss_cycles 0 +Core_0_L1I_active_hit_miss_overlap_cycles 0 +Core_0_L1I_total_pure_miss 0 +Core_0_L1I_pure_miss_rate 0.00000 +Core_0_L1I_active_cycles_per_core 617988 +Core_0_L1I_active_hit_cycles_per_core 617988 +Core_0_L1I_active_miss_cycles_per_core 0 +Core_0_L1I_active_pure_miss_cycles_per_core 0 +Core_0_L1I_hit_miss_overlap_cycles_per_core 0 +Core_0_L1I_camat_per_core 3.59262 + +Core_0_L2C_total_access 15134 +Core_0_L2C_total_hit 9493 +Core_0_L2C_total_miss 5641 +Core_0_L2C_total_overlap_miss 5641 +Core_0_L2C_loads 8773 +Core_0_L2C_load_hit 3998 +Core_0_L2C_load_miss 4775 +Core_0_L2C_RFOs 2681 +Core_0_L2C_RFO_hit 1815 +Core_0_L2C_RFO_miss 866 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 3680 +Core_0_L2C_writeback_hit 3680 +Core_0_L2C_writeback_miss 0 +Core_0_L2C_miss_rate 0.37274 +Core_0_L2C_MPKI 5.64100 +Core_0_L2C_demand_miss 5641 +Core_0_L2C_prefetch_requested 0 +Core_0_L2C_prefetch_issued 0 +Core_0_L2C_prefetch_useful 0 +Core_0_L2C_prefetch_useless 0 +Core_0_L2C_prefetch_late 0 +Core_0_L2C_average_miss_latency 594.92891 +Core_0_L2C_active_cycles 2143788 +Core_0_L2C_active_hit_cycles 369794 +Core_0_L2C_active_miss_cycles 1911521 +Core_0_L2C_active_pure_miss_cycles 1773994 +Core_0_L2C_active_hit_miss_overlap_cycles 137527 +Core_0_L2C_total_pure_miss 5641 +Core_0_L2C_pure_miss_rate 0.37274 +Core_0_L2C_active_cycles_per_core 2143788 +Core_0_L2C_active_hit_cycles_per_core 369794 +Core_0_L2C_active_miss_cycles_per_core 1911521 +Core_0_L2C_active_pure_miss_cycles_per_core 1773994 +Core_0_L2C_hit_miss_overlap_cycles_per_core 137527 +Core_0_L2C_camat_per_core 141.65376 + +Core_0_LLC_total_access 6175 +Core_0_LLC_total_hit 538 +Core_0_LLC_total_miss 5637 +Core_0_LLC_total_overlap_miss 5637 +Core_0_LLC_loads 4775 +Core_0_LLC_load_hit 3 +Core_0_LLC_load_miss 4772 +Core_0_LLC_RFOs 866 +Core_0_LLC_RFO_hit 1 +Core_0_LLC_RFO_miss 865 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 534 +Core_0_LLC_writeback_hit 534 +Core_0_LLC_writeback_miss 0 +Core_0_LLC_miss_rate 0.91287 +Core_0_LLC_MPKI 5.63700 +Core_0_LLC_demand_miss 5637 +Core_0_LLC_prefetch_requested 0 +Core_0_LLC_prefetch_issued 0 +Core_0_LLC_prefetch_useful 0 +Core_0_LLC_prefetch_useless 0 +Core_0_LLC_prefetch_late 0 +Core_0_LLC_average_miss_latency 1823.74933 +Core_0_LLC_active_cycles 3233304 +Core_0_LLC_active_hit_cycles 975696 +Core_0_LLC_active_miss_cycles 3129514 +Core_0_LLC_active_pure_miss_cycles 2257608 +Core_0_LLC_active_hit_miss_overlap_cycles 871906 +Core_0_LLC_total_pure_miss 5637 +Core_0_LLC_pure_miss_rate 0.91287 +Core_0_LLC_active_cycles_per_core 1868328 +Core_0_LLC_active_hit_cycles_per_core 303099 +Core_0_LLC_active_miss_cycles_per_core 1728837 +Core_0_LLC_active_pure_miss_cycles_per_core 1565229 +Core_0_LLC_hit_miss_overlap_cycles_per_core 163608 +Core_0_LLC_camat_per_core 302.56324 + +Core_0_major_page_fault 0 +Core_0_minor_page_fault 299 + +Core_1_instructions 1000000 +Core_1_cycles 2839304 +Core_1_IPC 0.35220 + +Core_1_branch_prediction_accuracy 97.03189 +Core_1_branch_MPKI 2.22617 +Core_1_average_ROB_occupancy_at_mispredict 119.67819 + +Core_1_L1D_total_access 341193 +Core_1_L1D_total_hit 318641 +Core_1_L1D_total_miss 22552 +Core_1_L1D_total_overlap_miss 22552 +Core_1_L1D_loads 122104 +Core_1_L1D_load_hit 99574 +Core_1_L1D_load_miss 22530 +Core_1_L1D_RFOs 219089 +Core_1_L1D_RFO_hit 219067 +Core_1_L1D_RFO_miss 22 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 +Core_1_L1D_miss_rate 0.06610 +Core_1_L1D_MPKI 22.55200 +Core_1_L1D_demand_miss 22552 +Core_1_L1D_prefetch_requested 0 +Core_1_L1D_prefetch_issued 0 +Core_1_L1D_prefetch_useful 0 +Core_1_L1D_prefetch_useless 0 +Core_1_L1D_prefetch_late 0 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+Core_3_LLC_RFOs 76 +Core_3_LLC_RFO_hit 2 +Core_3_LLC_RFO_miss 74 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 190 +Core_3_LLC_writeback_hit 190 +Core_3_LLC_writeback_miss 0 +Core_3_LLC_miss_rate 0.96621 +Core_3_LLC_MPKI 7.23400 +Core_3_LLC_demand_miss 7234 +Core_3_LLC_prefetch_requested 0 +Core_3_LLC_prefetch_issued 0 +Core_3_LLC_prefetch_useful 0 +Core_3_LLC_prefetch_useless 0 +Core_3_LLC_prefetch_late 0 +Core_3_LLC_average_miss_latency 1421.13284 +Core_3_LLC_active_cycles 3233304 +Core_3_LLC_active_hit_cycles 975696 +Core_3_LLC_active_miss_cycles 3129514 +Core_3_LLC_active_pure_miss_cycles 2257608 +Core_3_LLC_active_hit_miss_overlap_cycles 871906 +Core_3_LLC_total_pure_miss 7234 +Core_3_LLC_pure_miss_rate 0.96621 +Core_3_LLC_active_cycles_per_core 1344056 +Core_3_LLC_active_hit_cycles_per_core 150813 +Core_3_LLC_active_miss_cycles_per_core 1204709 +Core_3_LLC_active_pure_miss_cycles_per_core 1193243 +Core_3_LLC_hit_miss_overlap_cycles_per_core 11466 +Core_3_LLC_camat_per_core 179.51863 + +Core_3_major_page_fault 0 +Core_3_minor_page_fault 532 + +Channel_0_RQ_row_buffer_hit 14361 +Channel_0_RQ_row_buffer_miss 26715 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 8836 +Channel_0_RQ_row_buffer_hit 1363 +Channel_0_RQ_row_buffer_miss 11339 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 995 +avg_congested_cycle 0 9 +avg_congested_cycle 19 diff --git a/text.txt b/text.txt new file mode 100644 index 0000000..079d20a --- /dev/null +++ b/text.txt @@ -0,0 +1,1083 @@ +************************************************* + ChampSim Multicore Out-of-Order Simulator + Last compiled: Mar 20 2022 18:18:42 +************************************************* + DRAM access latency: 170 +Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s + DRAM_DBUS_RETURN_TIME: 13 + +trace_0 ./traces/403.gcc-17B.champsimtrace.xz +trace_1 ./traces/403.gcc-17B.champsimtrace.xz +trace_2 ./traces/403.gcc-17B.champsimtrace.xz +trace_3 ./traces/403.gcc-17B.champsimtrace.xz +warmup_instructions 1000 +simulation_instructions 100000 +champsim_seed 680 + +num_cpus 4 +cpu_freq 4000 +dram_io_freq 2400 +page_size 4096 +block_size 64 +max_read_per_cycle 20 +max_fill_per_cycle 20 +dram_channels 1 +dram_ranks 1 +dram_banks 8 +dram_rows 65536 +dram_columns 128 +dram_row_size 8 +dram_size 4096 +dram_pages 1048576 + +fetch_width 20 +decode_width 20 +exec_width 20 +lq_width 20 +sq_width 20 +retire_width 20 +scheduler_size 128 +branch_mispredict_penalty 20 +rob_size 256 +lq_size 72 +sq_size 56 +num_instr_destinations_sparc 4 +num_instr_destinations 2 +num_instr_sources 4 + +itlb_set 16 +itlb_way 8 +itlb_rq_size 16 +itlb_wq_size 16 +itlb_pq_size 0 +itlb_mshr_size 8 +itlb_latency 1 + +dtlb_set 16 +dtlb_way 4 +dtlb_rq_size 16 +dtlb_wq_size 16 +dtlb_pq_size 0 +dtlb_mshr_size 8 +dtlb_latency 1 + +stlb_set 128 +stlb_way 12 +stlb_rq_size 32 +stlb_wq_size 32 +stlb_pq_size 0 +stlb_mshr_size 16 +stlb_latency 8 + +l1i_size 32 +l1i_set 64 +l1i_way 8 +l1i_rq_size 64 +l1i_wq_size 64 +l1i_pq_size 8 +l1i_mshr_size 8 +l1i_latency 1 + +l1d_size 32 +l1d_set 64 +l1d_way 8 +l1d_rq_size 64 +l1d_wq_size 64 +l1d_pq_size 32 +l1d_mshr_size 16 +l1d_latency 4 + +l2c_size 256 +l2c_set 512 +l2c_way 8 +l2c_rq_size 32 +l2c_wq_size 32 +l2c_pq_size 16 +l2c_mshr_size 32 +l2c_latency 10 + +llc_size 8192 +llc_set 8192 +llc_way 16 +llc_rq_size 128 +llc_wq_size 128 +llc_pq_size 128 +llc_mshr_size 256 +llc_latency 20 + +dram_channel_width 8 +dram_wq_size 64 +dram_rq_size 64 +tRP 15 +tRCD 15 +tCAS 12.5 +dram_dbus_turn_around_time 30 +dram_write_high_wm 56 +dram_write_low_wm 48 +min_dram_writes_per_switch 16 +dram_mtps 2400 +dram_dbus_return_time 13 + + + +Warmup complete CPU 0 instructions: 1026 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 1 instructions: 1026 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 2 instructions: 1019 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) +Warmup complete CPU 3 instructions: 1001 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec) + +Finished CPU 2 instructions: 100001 cycles: 416751 cumulative IPC: 0.239954 (Simulation time: 0 hr 0 min 4 sec) +Finished CPU 3 instructions: 100000 cycles: 416781 cumulative IPC: 0.239934 (Simulation time: 0 hr 0 min 4 sec) +Finished CPU 0 instructions: 100006 cycles: 416796 cumulative IPC: 0.23994 (Simulation time: 0 hr 0 min 4 sec) +Finished CPU 1 instructions: 100006 cycles: 416847 cumulative IPC: 0.239911 (Simulation time: 0 hr 0 min 4 sec) + +ChampSim completed all CPUs + +Total Simulation Statistics (not including warmup) + +CPU 0 cumulative IPC: 0.239925 instructions: 100012 cycles: 416847 +Core_0_L1D_total_access 33589 +Core_0_L1D_total_hit 32673 +Core_0_L1D_total_miss 916 +Core_0_L1D_loads 19918 +Core_0_L1D_load_hit 19015 +Core_0_L1D_load_miss 903 +Core_0_L1D_RFOs 13671 +Core_0_L1D_RFO_hit 13658 +Core_0_L1D_RFO_miss 13 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 + +Core_0_L1I_total_access 18579 +Core_0_L1I_total_hit 18389 +Core_0_L1I_total_miss 190 +Core_0_L1I_loads 18579 +Core_0_L1I_load_hit 18389 +Core_0_L1I_load_miss 190 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 + +Core_0_L2C_total_access 1124 +Core_0_L2C_total_hit 35 +Core_0_L2C_total_miss 1089 +Core_0_L2C_loads 1093 +Core_0_L2C_load_hit 16 +Core_0_L2C_load_miss 1077 +Core_0_L2C_RFOs 13 +Core_0_L2C_RFO_hit 1 +Core_0_L2C_RFO_miss 12 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 18 +Core_0_L2C_writeback_hit 18 +Core_0_L2C_writeback_miss 0 + +Core_0_LLC_total_access 1089 +Core_0_LLC_total_hit 0 +Core_0_LLC_total_miss 1089 +Core_0_LLC_loads 1077 +Core_0_LLC_load_hit 0 +Core_0_LLC_load_miss 1077 +Core_0_LLC_RFOs 12 +Core_0_LLC_RFO_hit 0 +Core_0_LLC_RFO_miss 12 +Core_0_LLC_prefetches 0 +Core_0_LLC_prefetch_hit 0 +Core_0_LLC_prefetch_miss 0 +Core_0_LLC_writebacks 0 +Core_0_LLC_writeback_hit 0 +Core_0_LLC_writeback_miss 0 + + +CPU 1 cumulative IPC: 0.239911 instructions: 100006 cycles: 416847 +Core_1_L1D_total_access 33573 +Core_1_L1D_total_hit 32657 +Core_1_L1D_total_miss 916 +Core_1_L1D_loads 19911 +Core_1_L1D_load_hit 19008 +Core_1_L1D_load_miss 903 +Core_1_L1D_RFOs 13662 +Core_1_L1D_RFO_hit 13649 +Core_1_L1D_RFO_miss 13 +Core_1_L1D_prefetches 0 +Core_1_L1D_prefetch_hit 0 +Core_1_L1D_prefetch_miss 0 +Core_1_L1D_writebacks 0 +Core_1_L1D_writeback_hit 0 +Core_1_L1D_writeback_miss 0 + +Core_1_L1I_total_access 18579 +Core_1_L1I_total_hit 18389 +Core_1_L1I_total_miss 190 +Core_1_L1I_loads 18579 +Core_1_L1I_load_hit 18389 +Core_1_L1I_load_miss 190 +Core_1_L1I_RFOs 0 +Core_1_L1I_RFO_hit 0 +Core_1_L1I_RFO_miss 0 +Core_1_L1I_prefetches 0 +Core_1_L1I_prefetch_hit 0 +Core_1_L1I_prefetch_miss 0 +Core_1_L1I_writebacks 0 +Core_1_L1I_writeback_hit 0 +Core_1_L1I_writeback_miss 0 + +Core_1_L2C_total_access 1124 +Core_1_L2C_total_hit 35 +Core_1_L2C_total_miss 1089 +Core_1_L2C_loads 1093 +Core_1_L2C_load_hit 16 +Core_1_L2C_load_miss 1077 +Core_1_L2C_RFOs 13 +Core_1_L2C_RFO_hit 1 +Core_1_L2C_RFO_miss 12 +Core_1_L2C_prefetches 0 +Core_1_L2C_prefetch_hit 0 +Core_1_L2C_prefetch_miss 0 +Core_1_L2C_writebacks 18 +Core_1_L2C_writeback_hit 18 +Core_1_L2C_writeback_miss 0 + +Core_1_LLC_total_access 1089 +Core_1_LLC_total_hit 0 +Core_1_LLC_total_miss 1089 +Core_1_LLC_loads 1077 +Core_1_LLC_load_hit 0 +Core_1_LLC_load_miss 1077 +Core_1_LLC_RFOs 12 +Core_1_LLC_RFO_hit 0 +Core_1_LLC_RFO_miss 12 +Core_1_LLC_prefetches 0 +Core_1_LLC_prefetch_hit 0 +Core_1_LLC_prefetch_miss 0 +Core_1_LLC_writebacks 0 +Core_1_LLC_writeback_hit 0 +Core_1_LLC_writeback_miss 0 + + +CPU 2 cumulative IPC: 0.239999 instructions: 100043 cycles: 416847 +Core_2_L1D_total_access 33603 +Core_2_L1D_total_hit 32687 +Core_2_L1D_total_miss 916 +Core_2_L1D_loads 19918 +Core_2_L1D_load_hit 19015 +Core_2_L1D_load_miss 903 +Core_2_L1D_RFOs 13685 +Core_2_L1D_RFO_hit 13672 +Core_2_L1D_RFO_miss 13 +Core_2_L1D_prefetches 0 +Core_2_L1D_prefetch_hit 0 +Core_2_L1D_prefetch_miss 0 +Core_2_L1D_writebacks 0 +Core_2_L1D_writeback_hit 0 +Core_2_L1D_writeback_miss 0 + +Core_2_L1I_total_access 18579 +Core_2_L1I_total_hit 18389 +Core_2_L1I_total_miss 190 +Core_2_L1I_loads 18579 +Core_2_L1I_load_hit 18389 +Core_2_L1I_load_miss 190 +Core_2_L1I_RFOs 0 +Core_2_L1I_RFO_hit 0 +Core_2_L1I_RFO_miss 0 +Core_2_L1I_prefetches 0 +Core_2_L1I_prefetch_hit 0 +Core_2_L1I_prefetch_miss 0 +Core_2_L1I_writebacks 0 +Core_2_L1I_writeback_hit 0 +Core_2_L1I_writeback_miss 0 + +Core_2_L2C_total_access 1124 +Core_2_L2C_total_hit 35 +Core_2_L2C_total_miss 1089 +Core_2_L2C_loads 1093 +Core_2_L2C_load_hit 16 +Core_2_L2C_load_miss 1077 +Core_2_L2C_RFOs 13 +Core_2_L2C_RFO_hit 1 +Core_2_L2C_RFO_miss 12 +Core_2_L2C_prefetches 0 +Core_2_L2C_prefetch_hit 0 +Core_2_L2C_prefetch_miss 0 +Core_2_L2C_writebacks 18 +Core_2_L2C_writeback_hit 18 +Core_2_L2C_writeback_miss 0 + +Core_2_LLC_total_access 1089 +Core_2_LLC_total_hit 0 +Core_2_LLC_total_miss 1089 +Core_2_LLC_loads 1077 +Core_2_LLC_load_hit 0 +Core_2_LLC_load_miss 1077 +Core_2_LLC_RFOs 12 +Core_2_LLC_RFO_hit 0 +Core_2_LLC_RFO_miss 12 +Core_2_LLC_prefetches 0 +Core_2_LLC_prefetch_hit 0 +Core_2_LLC_prefetch_miss 0 +Core_2_LLC_writebacks 0 +Core_2_LLC_writeback_hit 0 +Core_2_LLC_writeback_miss 0 + + +CPU 3 cumulative IPC: 0.239983 instructions: 100036 cycles: 416847 +Core_3_L1D_total_access 33594 +Core_3_L1D_total_hit 32678 +Core_3_L1D_total_miss 916 +Core_3_L1D_loads 19920 +Core_3_L1D_load_hit 19017 +Core_3_L1D_load_miss 903 +Core_3_L1D_RFOs 13674 +Core_3_L1D_RFO_hit 13661 +Core_3_L1D_RFO_miss 13 +Core_3_L1D_prefetches 0 +Core_3_L1D_prefetch_hit 0 +Core_3_L1D_prefetch_miss 0 +Core_3_L1D_writebacks 0 +Core_3_L1D_writeback_hit 0 +Core_3_L1D_writeback_miss 0 + +Core_3_L1I_total_access 18579 +Core_3_L1I_total_hit 18389 +Core_3_L1I_total_miss 190 +Core_3_L1I_loads 18579 +Core_3_L1I_load_hit 18389 +Core_3_L1I_load_miss 190 +Core_3_L1I_RFOs 0 +Core_3_L1I_RFO_hit 0 +Core_3_L1I_RFO_miss 0 +Core_3_L1I_prefetches 0 +Core_3_L1I_prefetch_hit 0 +Core_3_L1I_prefetch_miss 0 +Core_3_L1I_writebacks 0 +Core_3_L1I_writeback_hit 0 +Core_3_L1I_writeback_miss 0 + +Core_3_L2C_total_access 1124 +Core_3_L2C_total_hit 35 +Core_3_L2C_total_miss 1089 +Core_3_L2C_loads 1093 +Core_3_L2C_load_hit 16 +Core_3_L2C_load_miss 1077 +Core_3_L2C_RFOs 13 +Core_3_L2C_RFO_hit 1 +Core_3_L2C_RFO_miss 12 +Core_3_L2C_prefetches 0 +Core_3_L2C_prefetch_hit 0 +Core_3_L2C_prefetch_miss 0 +Core_3_L2C_writebacks 18 +Core_3_L2C_writeback_hit 18 +Core_3_L2C_writeback_miss 0 + +Core_3_LLC_total_access 1089 +Core_3_LLC_total_hit 0 +Core_3_LLC_total_miss 1089 +Core_3_LLC_loads 1077 +Core_3_LLC_load_hit 0 +Core_3_LLC_load_miss 1077 +Core_3_LLC_RFOs 12 +Core_3_LLC_RFO_hit 0 +Core_3_LLC_RFO_miss 12 +Core_3_LLC_prefetches 0 +Core_3_LLC_prefetch_hit 0 +Core_3_LLC_prefetch_miss 0 +Core_3_LLC_writebacks 0 +Core_3_LLC_writeback_hit 0 +Core_3_LLC_writeback_miss 0 + + +[ROI Statistics] +Core_0_instructions 100006 +Core_0_cycles 416796 +Core_0_IPC 0.23994 + +Core_0_branch_prediction_accuracy 90.9586 +Core_0_branch_MPKI 16.4338 +Core_0_average_ROB_occupancy_at_mispredict 57.0998 + +Core_0_L1D_total_access 33579 +Core_0_L1D_total_hit 32663 +Core_0_L1D_total_miss 916 +Core_0_L1D_total_overlap_miss 916 +Core_0_L1D_loads 19914 +Core_0_L1D_load_hit 19011 +Core_0_L1D_load_miss 903 +Core_0_L1D_RFOs 13665 +Core_0_L1D_RFO_hit 13652 +Core_0_L1D_RFO_miss 13 +Core_0_L1D_prefetches 0 +Core_0_L1D_prefetch_hit 0 +Core_0_L1D_prefetch_miss 0 +Core_0_L1D_writebacks 0 +Core_0_L1D_writeback_hit 0 +Core_0_L1D_writeback_miss 0 +Core_0_L1D_miss_rate 0.027279 +Core_0_L1D_MPKI 9.16 +Core_0_L1D_demand_miss 916 +Core_0_L1D_prefetch_requested 0 +Core_0_L1D_prefetch_issued 0 +Core_0_L1D_prefetch_useful 0 +Core_0_L1D_prefetch_useless 0 +Core_0_L1D_prefetch_late 0 +Core_0_L1D_average_miss_latency 198.864 +Core_0_L1D_active_cycles 272565 +Core_0_L1D_active_hit_cycles 114580 +Core_0_L1D_active_miss_cycles 173650 +Core_0_L1D_active_pure_miss_cycles 157985 +Core_0_L1D_active_hit_miss_overlap_cycles 15665 +Core_0_L1D_total_pure_miss 916 +Core_0_L1D_pure_miss_rate 0.027279 +Core_0_L1D_active_cycles_per_core 272565 +Core_0_L1D_active_hit_cycles_per_core 114580 +Core_0_L1D_active_miss_cycles_per_core 173650 +Core_0_L1D_active_pure_miss_cycles_per_core 157985 +Core_0_L1D_hit_miss_overlap_cycles_per_core 15665 +Core_0_L1D_camat_per_core 8.11713 + +Core_0_L1I_total_access 18579 +Core_0_L1I_total_hit 18389 +Core_0_L1I_total_miss 190 +Core_0_L1I_total_overlap_miss 190 +Core_0_L1I_loads 18579 +Core_0_L1I_load_hit 18389 +Core_0_L1I_load_miss 190 +Core_0_L1I_RFOs 0 +Core_0_L1I_RFO_hit 0 +Core_0_L1I_RFO_miss 0 +Core_0_L1I_prefetches 0 +Core_0_L1I_prefetch_hit 0 +Core_0_L1I_prefetch_miss 0 +Core_0_L1I_writebacks 0 +Core_0_L1I_writeback_hit 0 +Core_0_L1I_writeback_miss 0 +Core_0_L1I_miss_rate 0.0102266 +Core_0_L1I_MPKI 1.9 +Core_0_L1I_demand_miss 190 +Core_0_L1I_prefetch_requested 0 +Core_0_L1I_prefetch_issued 0 +Core_0_L1I_prefetch_useful 0 +Core_0_L1I_prefetch_useless 0 +Core_0_L1I_prefetch_late 0 +Core_0_L1I_average_miss_latency 227.247 +Core_0_L1I_active_cycles 44782 +Core_0_L1I_active_hit_cycles 18441 +Core_0_L1I_active_miss_cycles 26550 +Core_0_L1I_active_pure_miss_cycles 26341 +Core_0_L1I_active_hit_miss_overlap_cycles 209 +Core_0_L1I_total_pure_miss 190 +Core_0_L1I_pure_miss_rate 0.0102266 +Core_0_L1I_active_cycles_per_core 44782 +Core_0_L1I_active_hit_cycles_per_core 18441 +Core_0_L1I_active_miss_cycles_per_core 26550 +Core_0_L1I_active_pure_miss_cycles_per_core 26341 +Core_0_L1I_hit_miss_overlap_cycles_per_core 209 +Core_0_L1I_camat_per_core 2.41036 + +Core_0_L2C_total_access 1124 +Core_0_L2C_total_hit 35 +Core_0_L2C_total_miss 1089 +Core_0_L2C_total_overlap_miss 1089 +Core_0_L2C_loads 1093 +Core_0_L2C_load_hit 16 +Core_0_L2C_load_miss 1077 +Core_0_L2C_RFOs 13 +Core_0_L2C_RFO_hit 1 +Core_0_L2C_RFO_miss 12 +Core_0_L2C_prefetches 0 +Core_0_L2C_prefetch_hit 0 +Core_0_L2C_prefetch_miss 0 +Core_0_L2C_writebacks 18 +Core_0_L2C_writeback_hit 18 +Core_0_L2C_writeback_miss 0 +Core_0_L2C_miss_rate 0.968861 +Core_0_L2C_MPKI 10.89 +Core_0_L2C_demand_miss 1089 +Core_0_L2C_prefetch_requested 0 +Core_0_L2C_prefetch_issued 0 +Core_0_L2C_prefetch_useful 0 +Core_0_L2C_prefetch_useless 0 +Core_0_L2C_prefetch_late 0 +Core_0_L2C_average_miss_latency 190.749 +Core_0_L2C_active_cycles 192987 +Core_0_L2C_active_hit_cycles 13201 +Core_0_L2C_active_miss_cycles 181763 +Core_0_L2C_active_pure_miss_cycles 179786 +Core_0_L2C_active_hit_miss_overlap_cycles 1977 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+Core_3_LLC_active_cycles_per_core 172344 +Core_3_LLC_active_hit_cycles_per_core 20768 +Core_3_LLC_active_miss_cycles_per_core 153906 +Core_3_LLC_active_pure_miss_cycles_per_core 151576 +Core_3_LLC_hit_miss_overlap_cycles_per_core 2330 +Core_3_LLC_camat_per_core 158.259 + +Core_3_major_page_fault 0 +Core_3_minor_page_fault 156 + +Channel_0_RQ_row_buffer_hit 1255 +Channel_0_RQ_row_buffer_miss 923 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 97 +Channel_0_RQ_row_buffer_hit 1254 +Channel_0_RQ_row_buffer_miss 924 +Channel_0_WQ_row_buffer_hit 0 +Channel_0_WQ_row_buffer_miss 0 +Channel_0_WQ_full 0 +Channel_0_dbus_congested 98 +avg_congested_cycle 0 10 +avg_congested_cycle 110