diff --git a/.github/workflows/compile-platform-examples.yml b/.github/workflows/compile-platform-examples.yml index 63e9f7c7..cf716f50 100644 --- a/.github/workflows/compile-platform-examples.yml +++ b/.github/workflows/compile-platform-examples.yml @@ -97,6 +97,26 @@ jobs: multiSerial: true dma: true alarmRtc: true + - fqbn: Infineon:arm:XMC1400_Arduino_Kit + i2s: false + dieTemp: true + heapMem: true + sleep1100: true + sleep4700 : false + stackMem: false + multiSerial: false + dma: false + alarmRtc: false + - fqbn: Infineon:arm:XMC4200_Platform2GO + i2s: false + dieTemp: false + heapMem: false + sleep1100: false + sleep4700 : false + stackMem: true + multiSerial: false + dma: false + alarmRtc: true # Make board type-specific customizations to the matrix jobs include: diff --git a/README.md b/README.md index 9c7e7d7d..5026f067 100644 --- a/README.md +++ b/README.md @@ -21,7 +21,7 @@ This repository integrates [Infineon's](https://www.infineon.com/) XMC microcont * [XMC1300 Sense2GoL](https://www.infineon.com/cms/de/product/evaluation-boards/demo-sense2gol/) * [XMC4400 Platform 2Go](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc_plt2go_xmc4400//) * [XMC4700 Relax Kit](https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc47_relax_v1/) -* [DEMO Radar BB XMC4700](https://www.infineon.com/cms/en/product/evaluation-boards/demo-sense2gol-pulse/) +* [XMC4700 Radar Baseboard](https://www.infineon.com/cms/en/product/evaluation-boards/demo-sense2gol-pulse/) ## Additional Information @@ -37,7 +37,7 @@ Please visit also the Wiki for additional information, e.g. datasheets, pin out * Page for [XMC1300 Sense2GoL](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC1300-Sense2GoL) * Page for [XMC4400 Platform 2Go](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC4400-Platform2Go) * Page for [XMC4700 Relax Kit](https://github.com/Infineon/XMC-for-Arduino/wiki/XMC4700-Relax-Kit) -* Page for [DEMO Radar BB XMC4700](https://github.com/Infineon/XMC-for-Arduino/wiki/DEMO-Radar-BB-XMC4700) +* Page for [XMC4700 Radar Baseboard](https://github.com/Infineon/XMC-for-Arduino/wiki/DEMO-Radar-BB-XMC4700) Additionally, please consult the [releases](https://github.com/Infineon/XMC-for-Arduino/releases) for information about the changes and new versions. diff --git a/boards.txt b/boards.txt index d071a1e3..103a4ab5 100644 --- a/boards.txt +++ b/boards.txt @@ -261,6 +261,89 @@ XMC1300_Sense2GoL.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP #XMC1400_Boot_Kit.menu.LIB.DSPNN=ARM DSP / ARM NN Framework #XMC1400_Boot_Kit.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +#################################################### +XMC1400_Arduino_Kit.name=XMC1400 Kit for Arduino +XMC1400_Arduino_Kit.upload.tool=xmcprog +XMC1400_Arduino_Kit.upload.speed=115200 +XMC1400_Arduino_Kit.upload.resetmethod=ck +XMC1400_Arduino_Kit.upload.maximum_size=204800 +XMC1400_Arduino_Kit.upload.wait_for_upload_port=true + +XMC1400_Arduino_Kit.communication=usb +XMC1400_Arduino_Kit.protocol=dragon_isp +XMC1400_Arduino_Kit.program.protocol=dragon_isp +XMC1400_Arduino_Kit.program.tool=xmcprog +XMC1400_Arduino_Kit.program.extra_params=-Pusb + +XMC1400_Arduino_Kit.serial.disableDTR=true +XMC1400_Arduino_Kit.serial.disableRTS=true + +XMC1400_Arduino_Kit.build.mcu=cortex-m0 +XMC1400_Arduino_Kit.build.f_cpu=48000000L +XMC1400_Arduino_Kit.build.board=ARM_XMC +XMC1400_Arduino_Kit.build.board.version=1402 +XMC1400_Arduino_Kit.build.board.type=T038x0200 +XMC1400_Arduino_Kit.build.board.v=0200 +XMC1400_Arduino_Kit.build.core=./ +XMC1400_Arduino_Kit.build.variant=XMC1400 +XMC1400_Arduino_Kit.build.board_variant=XMC1400_Arduino_Kit +XMC1400_Arduino_Kit.build.flash_size=200K +XMC1400_Arduino_Kit.build.flash_ld=linker_script_200k.ld +XMC1400_Arduino_Kit.build.extra_flags=-DARM_MATH_CM0 -DXMC1_SERIES + +XMC1400_Arduino_Kit.menu.UART.debug=PC +XMC1400_Arduino_Kit.menu.UART.debug.uart.selected=-DSERIAL_HOSTPC +XMC1400_Arduino_Kit.menu.UART.onBoard=On Board +XMC1400_Arduino_Kit.menu.UART.onBoard.uart.selected=-DSERIAL_ONBOARD + +XMC1400_Arduino_Kit.menu.LIB.NONE=None +XMC1400_Arduino_Kit.menu.LIB.NONE.library.selected= +XMC1400_Arduino_Kit.menu.LIB.NN=ARM NN Framework +XMC1400_Arduino_Kit.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +XMC1400_Arduino_Kit.menu.LIB.DSP=ARM DSP +XMC1400_Arduino_Kit.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP +XMC1400_Arduino_Kit.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +XMC1400_Arduino_Kit.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN + +#################################################### +XMC4200_Platform2GO.name=XMC4200 Platform 2GO +XMC4200_Platform2GO.upload.tool=xmcprog +XMC4200_Platform2GO.upload.speed=115200 +XMC4200_Platform2GO.upload.resetmethod=ck +XMC4200_Platform2GO.upload.maximum_size=262144 +XMC4200_Platform2GO.upload.wait_for_upload_port=true + +XMC4200_Platform2GO.communication=usb +XMC4200_Platform2GO.protocol=dragon_isp +XMC4200_Platform2GO.program.protocol=dragon_isp +XMC4200_Platform2GO.program.tool=xmcprog +XMC4200_Platform2GO.program.extra_params=-Pusb + +XMC4200_Platform2GO.serial.disableDTR=true +XMC4200_Platform2GO.serial.disableRTS=true + +XMC4200_Platform2GO.build.mcu=cortex-m4 +XMC4200_Platform2GO.build.f_cpu=80000000L +XMC4200_Platform2GO.build.board=ARM_XMC +XMC4200_Platform2GO.build.board.version=4200 +XMC4200_Platform2GO.build.board.type=F64x256 +XMC4200_Platform2GO.build.board.v=256 +XMC4200_Platform2GO.build.core=./ +XMC4200_Platform2GO.build.variant=XMC4200 +XMC4200_Platform2GO.build.board_variant=XMC4200_Platform2GO +XMC4200_Platform2GO.build.flash_size=256K +XMC4200_Platform2GO.build.flash_ld=linker_script.ld +XMC4200_Platform2GO.build.extra_flags=-DARM_MATH_CM4 -DARM_MATH_DSP -DINTERRUPT_USE_ERU +#-DUSB0 + +XMC4200_Platform2GO.menu.LIB.NONE=None +XMC4200_Platform2GO.menu.LIB.NONE.library.selected= +XMC4200_Platform2GO.menu.LIB.DSPNN=ARM DSP / ARM NN Framework +XMC4200_Platform2GO.menu.LIB.DSPNN.library.selected=-DARM_LIB_CMSIS_DSP -DARM_LIB_CMSIS_NN +XMC4200_Platform2GO.menu.LIB.NN=ARM NN Framework +XMC4200_Platform2GO.menu.LIB.NN.library.selected=-DARM_LIB_CMSIS_NN +XMC4200_Platform2GO.menu.LIB.DSP=ARM DSP +XMC4200_Platform2GO.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP #################################################### XMC4400_Platform2GO.name=XMC4400 Platform 2GO @@ -308,7 +391,7 @@ XMC4400_Platform2GO.menu.LIB.DSP=ARM DSP XMC4400_Platform2GO.menu.LIB.DSP.library.selected=-DARM_LIB_CMSIS_DSP #################################################### -XMC4700_Radar_Baseboard.name=DEMO Radar BB XMC4700 +XMC4700_Radar_Baseboard.name=XMC4700 Radar Baseboard XMC4700_Radar_Baseboard.upload.tool=xmcprog XMC4700_Radar_Baseboard.upload.speed=115200 XMC4700_Radar_Baseboard.upload.resetmethod=ck diff --git a/cores/Main.cpp b/cores/Main.cpp index 469da4f8..39abd394 100644 --- a/cores/Main.cpp +++ b/cores/Main.cpp @@ -41,8 +41,9 @@ int main(void) */ wiring_time_init(); wiring_analog_init(); -// Initialize the reset pin for the XMC1100 Boot Kit series -#ifdef XMC1100_Boot_Kit +// Initialize the reset pin for the XMC1100 Boot Kit series and XMC1400 Kit for Arduino as they are based on Arduino form-factor +// Hence, a dedicated reset pin is required. +#ifdef HAS_GPIO_RESET reset_init(); #endif diff --git a/cores/WInterrupts.c b/cores/WInterrupts.c index b89ece71..c18e1b49 100644 --- a/cores/WInterrupts.c +++ b/cores/WInterrupts.c @@ -42,6 +42,15 @@ void ERU0_3_IRQHandler(void) } } +#if defined(XMC4200_Platform2GO) +void ERU0_0_IRQHandler(void) +{ + if (interrupt_1_cb) + { + interrupt_1_cb(); + } +} +#else void ERU1_0_IRQHandler(void) { if (interrupt_1_cb) @@ -49,6 +58,8 @@ void ERU1_0_IRQHandler(void) interrupt_1_cb(); } } +#endif + #else void CCU40_0_IRQHandler(void) { @@ -109,10 +120,16 @@ void attachInterrupt(uint32_t interrupt_num, interrupt_cb_t callback, uint32_t m } else if (pin_irq.irq_num == 1) { - NVIC_SetPriority(ERU1_0_IRQn, 3); +#if defined(XMC4200_Platform2GO) + NVIC_SetPriority(ERU0_0_IRQn, 3); + interrupt_1_cb = callback; + NVIC_EnableIRQ(ERU0_0_IRQn); +#else + NVIC_SetPriority(ERU1_0_IRQn, 3); interrupt_1_cb = callback; NVIC_EnableIRQ(ERU1_0_IRQn); - } +#endif + } #else XMC_CCU4_SLICE_EVENT_CONFIG_t event_config = {0}; @@ -140,7 +157,7 @@ void attachInterrupt(uint32_t interrupt_num, interrupt_cb_t callback, uint32_t m if (pin_irq.irq_num == 0) { -#if defined(XMC1100_Boot_Kit) +#if defined(XMC1100_Boot_Kit) || defined(XMC1400_Arduino_Kit) /* P1_4 external interrupt goes through USIC to CCU4 */ XMC_USIC_CH_Enable(XMC_USIC0_CH0); XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX5, USIC0_C0_DX5_P1_4); @@ -159,9 +176,14 @@ void attachInterrupt(uint32_t interrupt_num, interrupt_cb_t callback, uint32_t m else if (pin_irq.irq_num == 1) { #if defined(XMC1300_Boot_Kit) - /* P0_13 external interrupt goes through USIC to CCU4 */ + /* P0_13 external interrupt goes through USIC to CCU4 */ XMC_USIC_CH_Enable(XMC_USIC0_CH0); XMC_USIC_CH_SetInputSource(XMC_USIC0_CH0, XMC_USIC_CH_INPUT_DX2, USIC0_C0_DX2_P0_13); +#endif +#if defined(XMC1400_Arduino_Kit) + /* P1_1 external interrupt goes through USIC to CCU4 */ + XMC_USIC_CH_Enable(XMC_USIC0_CH1); + XMC_USIC_CH_SetInputSource(XMC_USIC0_CH1, XMC_USIC_CH_INPUT_DX2, USIC0_C1_DX2_P1_1); #endif XMC_CCU4_SLICE_EnableMultipleEvents(pin_irq.slice, XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1); XMC_CCU4_SLICE_SetInterruptNode(pin_irq.slice, XMC_CCU4_SLICE_IRQ_ID_EVENT1, 1); @@ -190,7 +212,11 @@ void detachInterrupt(uint32_t interrupt_num) break; case 1: - NVIC_DisableIRQ(ERU1_0_IRQn); +#if defined(XMC4200_Platform2GO) + NVIC_DisableIRQ(ERU0_0_IRQn); +#else + NVIC_DisableIRQ(ERU1_0_IRQn); +#endif break; #else switch (interrupt_num) diff --git a/cores/reset.c b/cores/reset.c index 2a3434de..e243ed41 100644 --- a/cores/reset.c +++ b/cores/reset.c @@ -25,8 +25,8 @@ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include -#ifdef XMC1100_Boot_Kit +#include +#ifdef HAS_GPIO_RESET #include #include diff --git a/cores/reset.h b/cores/reset.h index ab9677e4..1ebd26be 100644 --- a/cores/reset.h +++ b/cores/reset.h @@ -29,8 +29,6 @@ #ifndef Reset_h #define Reset_h -#include - //**************************************************************************** // @External Prototypes //**************************************************************************** diff --git a/cores/wiring_analog.c b/cores/wiring_analog.c index 643d4a3d..5fc4b102 100644 --- a/cores/wiring_analog.c +++ b/cores/wiring_analog.c @@ -295,7 +295,7 @@ if( ( resource = scan_map_table( mapping_pin_PWM4, pin ) ) >= 0 ) ( XMC_GPIO_MODE_OUTPUT_PUSH_PULL | pwm4->port_mode ) ); XMC_CCU4_SLICE_StartTimer( pwm4->slice ); } -#ifdef CCU8V2 +#if defined(CCU8V2) || defined(CCU8V1) else if( ( resource = scan_map_table( mapping_pin_PWM8, pin ) ) >= 0 ) { @@ -391,7 +391,7 @@ if( frequency < PCLK ) } ret = 0; } -#ifdef CCU8V2 +#if defined (CCU8V2) || defined (CCU8V1) else if ( ( resource = scan_map_table( mapping_pin_PWM8, pin ) ) >= 0 ) { diff --git a/cores/wiring_time.h b/cores/wiring_time.h index 14fd4ddd..e0effddd 100644 --- a/cores/wiring_time.h +++ b/cores/wiring_time.h @@ -86,6 +86,37 @@ extern "C" { asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ asm volatile("nop");} + +#elif ((UC_FAMILY == XMC4) && (F_CPU == 80000000U)) +// 80 NOPS +#define NOPS_FOR_USEC() { asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ + asm volatile("nop"); asm volatile("nop");} + #elif ((UC_FAMILY == XMC1) && (F_CPU == 32000000U)) // 16 NOPS #define NOPS_FOR_USEC() { asm volatile("nop"); asm volatile("nop"); asm volatile("nop");\ diff --git a/keywords.txt b/keywords.txt index e5fdacd6..4a2f3bb9 100644 --- a/keywords.txt +++ b/keywords.txt @@ -54,7 +54,7 @@ LED6 LITERAL1 BUTTON1 LITERAL1 BUTTON2 LITERAL1 -# Radar Baseboard XMC4700 only +# XMC4700 Radar Baseboard only LED_RED LITERAL1 LED_BLUE LITERAL1 LED_GREEN LITERAL1 \ No newline at end of file diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/README.md b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/README.md index b14c2dc8..dbeaedb5 100644 --- a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/README.md +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/README.md @@ -91,7 +91,7 @@ Two Arduino sketch examples are provided in the current library release. These e This example sketch runs the Pulsed Doppler firmware and uses the on-board LED to indicate detection of motion and direction of motion. **Hardware required:** -Radar Baseboard XMC4700 and BGT24LTR11 Shield +XMC4700 Radar Baseboard and BGT24LTR11 Shield **Steps:** 1. In Arduino IDE, navigate to **File** --> **Examples** --> **IFXRadarPulsedDoppler** --> **Radar_Pulsed_Doppler_LED** @@ -108,11 +108,11 @@ Radar Baseboard XMC4700 and BGT24LTR11 Shield ![Done Compiling](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_done_compiling.png) -4. Attach the BGT24LTR11 Shield to the Radar Baseboard XMC4700 via the SAMTEC connectors. +4. Attach the BGT24LTR11 Shield to the XMC4700 Radar Baseboard via the SAMTEC connectors. ![Connecting Boards](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_connecting_boards.png) -5. Connect the Radar Baseboard XMC4700 to the PC via a USB cable onto the **Debug** USB port. +5. Connect the XMC4700 Radar Baseboard to the PC via a USB cable onto the **Debug** USB port. ![Debug Port](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_debug_port.png) @@ -139,7 +139,7 @@ This example sketch runs the Pulsed Doppler firmware and projects the results of and at the same time uses an external RGB LED to indicate motion and direction of motion. **Hardware required:** -1) Radar Baseboard XMC4700 and BGT24LTR11 Shield +1) XMC4700 Radar Baseboard and BGT24LTR11 Shield 2) Annikken Andee U Shield (https://www.annikken.com/andee-u) 3) RGB LED Lighting Shield with XMC1202 (https://www.infineon.com/cms/en/product/evaluation-boards/kit_led_xmc1202_as_01/) @@ -158,25 +158,25 @@ and at the same time uses an external RGB LED to indicate motion and direction o ![Done Compiling](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_done_compiling.png) -4. Attach the BGT24LTR11 Shield to the Radar Baseboard XMC4700 via the SAMTEC connectors. +4. Attach the BGT24LTR11 Shield to the XMC4700 Radar Baseboardvia the SAMTEC connectors. ![Connecting Boards](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_connecting_boards.png) -5. Stack the RGB LED Lighting Shield with XMC1202 onto the Radar Baseboard XMC4700 via the Arduino stack headers. +5. Stack the RGB LED Lighting Shield with XMC1202 onto the XMC4700 Radar Baseboard via the Arduino stack headers. Also connect an RGB LED and a 24 VDC power adapter to the RGB LED Lighting Shield. **Do not turn the power on yet!** For more information on setting up of the RGB LED Lighting Shield, please refer to [Infineon RGB LED Lighting Shield with XMC1202 for Arduino - User Manual](https://www.infineon.com/dgdl/Infineon-Board_Manual_-_XMC1202_-_RGB_LED_Lighting_Shield_with_XMC1202_for_Arduino_-_v1_0-UM-v01_00-EN.pdf?fileId=5546d46249be182c0149ccca3860734d). ![RGB LED Shield Setup](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_RGB_LED_Shield_Setup.png) 6. Stack the Annikken Andee U shield onto the setup. Notice that there are several jumper wires on the Annikken Andee U board. -This is due to the hardware modifications required on the Radar Baseboard regarding the ISCP header as mentioned in [the XMC4700 Radar Baseboard Wiki](https://github.com/Infineon/XMC-for-Arduino/wiki/Radar-Baseboard-XMC4700). +This is due to the hardware modifications required on the Radar Baseboard regarding the ISCP header as mentioned in [the XMC4700 Radar BaseboardWiki](https://github.com/Infineon/XMC-for-Arduino/wiki/Radar-Baseboard-XMC4700). The second diagram below illustrates the required connections. ![Annikken Andee U](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_Annikken_Andee_U.png) ![Andee Jumpers](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_Andee_Jumpers.png) -7. Turn on the 24 VDC power supply to the RGB LED Lighting Shield and connect the Radar Baseboard XMC4700 to the PC via a USB cable onto the **Debug** USB port. +7. Turn on the 24 VDC power supply to the RGB LED Lighting Shield and connect the XMC4700 Radar Baseboard to the PC via a USB cable onto the **Debug** USB port. ![Debug Port](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_debug_port.png) @@ -200,7 +200,7 @@ The RGB LED should turn on with white light, while the on-board LED will cycle b ![Andee GUI](https://raw.githubusercontent.com/infineon/assets/master/Pictures/rbb_Andee-GUI.png) -In case this does not happen, disconnect from the app, press the reset button on the Radar Baseboard XMC4700 and retry the connection. +In case this does not happen, disconnect from the app, press the reset button on the XMC4700 Radar Baseboard and retry the connection. Make some movement in front of the radar board and observe the measured speed and detected direction on the GUI. You may also observe the light from the RGB LED changing with regards to the motion and its direction. diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_LED/Radar_Pulsed_Doppler_LED.ino b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_LED/Radar_Pulsed_Doppler_LED.ino index ad8fe1a9..326a9278 100644 --- a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_LED/Radar_Pulsed_Doppler_LED.ino +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_LED/Radar_Pulsed_Doppler_LED.ino @@ -1,52 +1,72 @@ #include +#include // IFX Radar Pulsed Doppler Object IFXRadarPulsedDoppler radarDev; +LED Led; -void myResultCallback() +void myErrorCallback( uint32_t error ) +{ + + + Led.On( LED_GREEN ); + Led.On( LED_RED ); + Led.On( LED_BLUE ); + + while( 1 ) + ; +} + + +void myResultCallback(void) { uint8_t targetDirection = radarDev.getDirection(); if(targetDirection == 1) { // turn on Red LED for departing target - digitalWrite(LED_GREEN, HIGH); - digitalWrite(LED_RED, LOW); - digitalWrite(LED_BLUE, HIGH); + Led.Off( LED_GREEN ); + Led.On( LED_RED ); + Led.Off( LED_BLUE ); } else if(targetDirection == 2) { // turn on Green LED for approaching target - digitalWrite(LED_GREEN, LOW); - digitalWrite(LED_RED, HIGH); - digitalWrite(LED_BLUE, HIGH); + Led.On( LED_GREEN ); + Led.Off( LED_RED ); + Led.Off( LED_BLUE ); } else if(radarDev.targetAvailable() == true) { // turn on Blue LED for just normal motion with no meaningful direction - digitalWrite(LED_GREEN, HIGH); - digitalWrite(LED_RED, HIGH); - digitalWrite(LED_BLUE, LOW); + Led.Off( LED_GREEN ); + Led.Off( LED_RED ); + Led.On( LED_BLUE ); } else { // turn off LEDs for no motion - digitalWrite(LED_GREEN, HIGH); - digitalWrite(LED_RED, HIGH); - digitalWrite(LED_BLUE, HIGH); + Led.Off( LED_GREEN ); + Led.Off( LED_RED ); + Led.Off( LED_BLUE ); } } void setup() { - // put your setup code here, to run once: - pinMode(LED_RED, OUTPUT); - digitalWrite(LED_RED, HIGH); - pinMode(LED_GREEN, OUTPUT); - digitalWrite(LED_GREEN, LOW); - pinMode(LED_BLUE, OUTPUT); - digitalWrite(LED_BLUE, HIGH); - radarDev.initHW(); + Led.Add( LED_RED ); + Led.Add( LED_GREEN ); + Led.Add( LED_BLUE ); + + Led.Off( LED_RED ); + Led.Off( LED_GREEN ); + Led.Off( LED_BLUE ); + radarDev.registerResultCallback(myResultCallback); + radarDev.registerErrorCallback(myErrorCallback); + + radarDev.initHW(); + + // start the radarDevice, to read the default parameter radarDev.begin(); } @@ -55,3 +75,4 @@ void loop() { // put your main code here, to run repeatedly: radarDev.run(); } + diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_plotter/Radar_Pulsed_Doppler_plotter.ino b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_plotter/Radar_Pulsed_Doppler_plotter.ino new file mode 100644 index 00000000..f02cd7b5 --- /dev/null +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_plotter/Radar_Pulsed_Doppler_plotter.ino @@ -0,0 +1,123 @@ +#include +#include + +// IFX Radar Pulsed Doppler Object +IFXRadarPulsedDoppler radarDev; +LED Led; + +void myErrorCallback(uint32_t error) +{ + Serial.print("--- ERROR: 0x"); + Serial.println( error, HEX); + + Led.On( LED_GREEN ); + Led.On( LED_RED ); + Led.On( LED_BLUE ); + + while( 1 ) + ; +} + + +void myResultCallback(void) +{ + uint8_t targetDirection = radarDev.getDirection(); + if(targetDirection == 1) + { + // turn on Red LED for departing target + Led.Off( LED_GREEN ); + Led.On( LED_RED ); + Led.Off( LED_BLUE ); + } + else if(targetDirection == 2) + { + // turn on Green LED for approaching target + Led.On( LED_GREEN ); + Led.Off( LED_RED ); + Led.Off( LED_BLUE ); + } + else if(radarDev.targetAvailable() == true) + { + // turn on Blue LED for just normal motion with no meaningful direction + Led.Off( LED_GREEN ); + Led.Off( LED_RED ); + Led.On( LED_BLUE ); + } + else + { + // turn off LEDs for no motion + Led.Off( LED_GREEN ); + Led.Off( LED_RED ); + Led.Off( LED_BLUE ); + } +} + + +float raw_i[256]; +float raw_q[256]; + + +void myRawDataCallback( raw_data_context_t context ) +{ + uint32_t frameCnt = radarDev.getRawDataFrameCount( context ); + uint16_t numSamples = radarDev.getNumRawDataSamples( context ); + + radarDev.getRawData( context, raw_i, raw_q, 256 ); + + for( uint32_t i = 0; i < numSamples; i++ ) + { + Serial.print( raw_i[i] ); + Serial.print("\t"); + Serial.print( raw_q[i] ); + Serial.println( "" ); + } +} + +void setup() { + + Led.Add( LED_RED ); + Led.Add( LED_GREEN ); + Led.Add( LED_BLUE ); + + Led.Off( LED_RED ); + Led.Off( LED_GREEN ); + Led.Off( LED_BLUE ); + + Serial.begin(500000); //This baudrate is required to show continuous wave on serial plotter, at minimum framerate (continuous sampling!) + + radarDev.registerResultCallback(myResultCallback); + radarDev.registerErrorCallback(myErrorCallback); + radarDev.registerRawDataCallback(myRawDataCallback ); // register a handler to receive raw data + //radarDev.enableAlgoProcessing( false ); // set to false to disables the lib internal radar algo processing + + radarDev.initHW(); + + // start the radarDevice, to read the default parameter + radarDev.begin(); + + // set minimum Frame period, to get continuous sampling of data, a skip count is required to remove the transient + // in analog baseband after frame pause + // set skip count to zero, in countinuous mode there is not transient that needs to be skipped. + radarDev.setSkipSamples( 0 ); + + // read minimum possible Frame period (after setting skip count!) + uint32_t minFramePeriod = radarDev.getMinFramePeriod(); + + // stop the device to change parameters + radarDev.end(); + radarDev.setFramePeriod( minFramePeriod ); + + // legend for Serial Plotter: + Serial.print("I-Signal\tQ-Signal-"); + Serial.println(minFramePeriod); + + // Restart the radar device + radarDev.begin(); + +} + +void loop() { + // put your main code here, to run repeatedly: + radarDev.run(); +} + diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_serial/Radar_Pulsed_Doppler_serial.ino b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_serial/Radar_Pulsed_Doppler_serial.ino new file mode 100644 index 00000000..417eebeb --- /dev/null +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/examples/Radar_Pulsed_Doppler_serial/Radar_Pulsed_Doppler_serial.ino @@ -0,0 +1,110 @@ +#include +#include + +// IFX Radar Pulsed Doppler Object +IFXRadarPulsedDoppler radarDev; +LED Led; + +void myErrorCallback( uint32_t error ) +{ + Serial.print("--- ERROR: 0x"); + Serial.println( error, HEX); + + Led.On( LED_GREEN ); + Led.On( LED_RED ); + Led.On( LED_BLUE ); + + while( 1 ) + ; +} + + +void myResultCallback(void) +{ + uint8_t targetDirection = radarDev.getDirection(); + if(targetDirection == 1) + { + // turn on Red LED for departing target + Led.Off( LED_GREEN ); + Led.On( LED_RED ); + Led.Off( LED_BLUE ); + Serial.println("departing"); + } + else if(targetDirection == 2) + { + // turn on Green LED for approaching target + Led.On( LED_GREEN ); + Led.Off( LED_RED ); + Led.Off( LED_BLUE ); + Serial.println("approaching"); + } + else if(radarDev.targetAvailable() == true) + { + // turn on Blue LED for just normal motion with no meaningful direction + Led.Off( LED_GREEN ); + Led.Off( LED_RED ); + Led.On( LED_BLUE ); + Serial.println("motion"); + } + else + { + // turn off LEDs for no motion + Led.Off( LED_GREEN ); + Led.Off( LED_RED ); + Led.Off( LED_BLUE ); + } +} + + + +float raw_i[256]; +float raw_q[256]; + + +void setup() { + + Led.Add( LED_RED ); + Led.Add( LED_GREEN ); + Led.Add( LED_BLUE ); + + Led.Off( LED_RED ); + Led.Off( LED_GREEN ); + Led.Off( LED_BLUE ); + + Serial.begin(115200); + + radarDev.registerResultCallback(myResultCallback); + radarDev.registerErrorCallback(myErrorCallback); + + radarDev.initHW(); + + // start the radarDevice, to read the default parameter + radarDev.begin(); + // dump default settings to serial port + radarDev.parameterDump(&Serial); + + + + Serial.println("---------------------"); + // stop the device to change parameters + radarDev.end(); + + // apply very insensitive setting + + radarDev.setMotionSensitivity(300); + radarDev.setDopplerSensitivity(500); + + radarDev.parameterDump(&Serial); + + + Serial.println("---------------------"); + // Restart the radar device + radarDev.begin(); + +} + +void loop() { + // put your main code here, to run repeatedly: + radarDev.run(); +} + diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/keywords.txt b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/keywords.txt index ac5f23d1..297cbe7e 100644 --- a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/keywords.txt +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/keywords.txt @@ -6,22 +6,23 @@ # Datatypes (KEYWORD1) ####################################### -IFXRadarPulsedDoppler KEYWORD1 IFXRadarPulsedDoppler +IFXRadarPulsedDoppler KEYWORD1 +raw_data_context_t KEYWORD1 ####################################### # Methods and Functions (KEYWORD2) ####################################### setMinSpeed KEYWORD2 -getMinSpeed KEYWORD2 -setMaxSpeed KEYWORD2 -getMaxSpeed KEYWORD2 -setMotionSensitivity KEYWORD2 +getMinSpeed KEYWORD2 +setMaxSpeed KEYWORD2 +getMaxSpeed KEYWORD2 +setMotionSensitivity KEYWORD2 getMotionSensitivity KEYWORD2 -setDopplerSensitivity KEYWORD2 -getDopplerSensitivity KEYWORD2 -setFramePeriod KEYWORD2 -getFramePeriod KEYWORD2 +setDopplerSensitivity KEYWORD2 +getDopplerSensitivity KEYWORD2 +setFramePeriod KEYWORD2 +getFramePeriod KEYWORD2 setSampleFreq KEYWORD2 getSampleFreq KEYWORD2 setSkipSamples KEYWORD2 @@ -30,21 +31,27 @@ setNumSamples KEYWORD2 getNumSamples KEYWORD2 setPulseWidth KEYWORD2 getPulseWidth KEYWORD2 -getMinFramePeriod KEYWORD2 -getCurrentConsumption KEYWORD2 -initHW KEYWORD2 -registerResultCallback KEYWORD2 +getMinFramePeriod KEYWORD2 +getCurrentConsumption KEYWORD2 +enableAlgoProcessing KEYWORD2 +initHW KEYWORD2 +registerResultCallback KEYWORD2 registerErrorCallback KEYWORD2 -begin KEYWORD2 -end KEYWORD2 -run KEYWORD2 -targetAvailable KEYWORD2 -getDopplerLevel KEYWORD2 -getDopplerFreqHz KEYWORD2 -getVelocity KEYWORD2 +registerErrorCallback KEYWORD2 +begin KEYWORD2 +end KEYWORD2 +run KEYWORD2 +targetAvailable KEYWORD2 +getDopplerLevel KEYWORD2 +getDopplerFreqHz KEYWORD2 +getVelocity KEYWORD2 getDirection KEYWORD2 -getSpeed KEYWORD2 +getSpeed KEYWORD2 getFrameCount KEYWORD2 +parameterDump KEYWORD2 +getRawData KEYWORD2 +getNumRawDataSamples KEYWORD2 +getRawDataFrameCount KEYWORD2 ####################################### # Constants (LITERAL1) diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/library.properties b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/library.properties index 833a7736..5bea736a 100644 --- a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/library.properties +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/library.properties @@ -3,7 +3,7 @@ version=1.0.1 author=Infineon Technologies maintainer=Infineon Technologies sentence=This library provides Pulsed Doppler functionality with XMC4700 Radar Baseboard and BGT24LTR11 Shield. -paragraph=Infineon's 24 GHz Sense2GoL Pulse radar system platform, is made up of the Radar Baseboard XMC4700 and BGT24LTR11 radar shield. +paragraph=Infineon's 24 GHz Sense2GoL Pulse radar system platform, is made up of the XMC4700 Radar Baseboard and BGT24LTR11 radar shield. category=Sensors url=https://www.infineon.com/cms/en/product/sensor/radar-image-sensors/radar-sensors/radar-sensors-for-consumer-and-iot/ architectures=xmc,arm diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.cpp b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.cpp index f8cd0be3..80872b94 100644 --- a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.cpp +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.cpp @@ -3,7 +3,6 @@ IFXRadarPulsedDoppler::IFXRadarPulsedDoppler() { - this->result_handler_registered = false; this->error_handler_registered = false; this->outDev = NULL; } @@ -66,15 +65,19 @@ float IFXRadarPulsedDoppler::getDopplerSensitivity(void) return threshold; } -uint8_t IFXRadarPulsedDoppler::setFramePeriod(uint8_t periodUs) +bool IFXRadarPulsedDoppler::setFramePeriod(uint32_t periodUs) { - uint8_t status = radar_ard_set_frame_period_usec(periodUs); - return status; + + uint8_t retValue = radar_ard_set_frame_period_usec(periodUs); + if( retValue ) + return true; + + return false; } -uint8_t IFXRadarPulsedDoppler::getFramePeriod(void) +uint32_t IFXRadarPulsedDoppler::getFramePeriod(void) { - uint8_t periodUs = radar_ard_get_frame_period_usec(); + uint32_t periodUs = radar_ard_get_frame_period_usec(); return periodUs; } @@ -138,14 +141,35 @@ float IFXRadarPulsedDoppler::getCurrentConsumption(void) return currentMA; } -void IFXRadarPulsedDoppler::registerResultCallback(void(*callBackPtr)) // register algo done callback function +bool IFXRadarPulsedDoppler::enableAlgoProcessing( bool enableAlgo ) +{ + uint8_t currStatus = 0; + if(enableAlgo) + currStatus = radar_ard_set_do_algo_processing( 1 ); + else + currStatus = radar_ard_set_do_algo_processing( 0 ); + + if( currStatus ) + return true; + + return false; +} + + + +void IFXRadarPulsedDoppler::registerResultCallback(void(*callBackPtr)( void ) ) // register algo done callback function +{ + (void) radar_ard_register_result_handler(callBackPtr); +} + +void IFXRadarPulsedDoppler::registerErrorCallback(void(*callBackPtr)(uint32_t)) { - radar_ard_register_result_handler(callBackPtr); + (void) radar_ard_register_error_handler(callBackPtr); } -void IFXRadarPulsedDoppler::registerErrorCallback(void(*callBackPtr)) +void IFXRadarPulsedDoppler::registerRawDataCallback(void(*callBackPtr)(raw_data_context_t)) { - radar_ard_register_error_handler(callBackPtr); + (void) radar_ard_register_raw_data_handler(callBackPtr); } void IFXRadarPulsedDoppler::initHW(void) @@ -256,6 +280,23 @@ uint32_t IFXRadarPulsedDoppler::getFrameCount(void) return radar_ard_get_frame_count( ); } + // raw data context functions, call only in raw_data_callback +uint32_t IFXRadarPulsedDoppler::getRawDataFrameCount( raw_data_context_t raw_data_context ) +{ + return radar_ard_get_frame_raw_data( raw_data_context ); +} + +void IFXRadarPulsedDoppler::getRawData( raw_data_context_t raw_data_context, float *p_raw_data_i, float *p_raw_data_q, uint16_t max_num_samples, uint8_t high_gain_input ) +{ + radar_ard_get_raw_data( raw_data_context, p_raw_data_i, p_raw_data_q, max_num_samples, high_gain_input ); +} + +uint16_t IFXRadarPulsedDoppler::getNumRawDataSamples( raw_data_context_t raw_data_context ) +{ + return radar_ard_get_num_raw_data_samples( raw_data_context ); +} + +// debug functions void IFXRadarPulsedDoppler::parameterDump( void ) { parameterDump(this->outDev); @@ -279,11 +320,11 @@ void IFXRadarPulsedDoppler::parameterDump(Print *outDev) outDev->print(radar_ard_get_min_speed_kmph()); outDev->println(" km/h"); - outDev->print("minimum speed : "); + outDev->print("maximum speed : "); outDev->print(radar_ard_get_max_speed_kmph()); outDev->println(" km/h"); - outDev->print("minimum speed : "); + outDev->print("sampling frequency : "); outDev->print(radar_ard_get_adc_sampling_freq_hz()); outDev->println(" Hz"); diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.h b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.h index 7b763e8a..0f7e177f 100644 --- a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.h +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/IFXRadarPulsedDoppler.h @@ -5,7 +5,6 @@ class IFXRadarPulsedDoppler { private: - bool result_handler_registered; bool error_handler_registered; Print *outDev; @@ -21,8 +20,8 @@ class IFXRadarPulsedDoppler float getMotionSensitivity(void); uint8_t setDopplerSensitivity(float threshold); // threshold that will determine motion with direction (departing/approaching) or not float getDopplerSensitivity(void); - uint8_t setFramePeriod(uint8_t periodUs); // frame period in usec - uint8_t getFramePeriod(void); + bool setFramePeriod(uint32_t periodUs); // frame period in usec + uint32_t getFramePeriod(void); uint8_t setSampleFreq(uint32_t frequencyHz); // ADC sampling frequency in Hz uint32_t getSampleFreq(void); uint8_t setSkipSamples(uint32_t numSamples); // number of samples to skip @@ -33,11 +32,13 @@ class IFXRadarPulsedDoppler uint32_t getPulseWidth(void); uint32_t getMinFramePeriod(void); // get the minimum frame period in usec float getCurrentConsumption(void); // get the current consumed by the board in mA + bool enableAlgoProcessing( bool do_processing = true ); // control functions void initHW(void); - void registerResultCallback(void(*callBackPtr)); // register function to be called when also process is done - void registerErrorCallback(void(*callBackPtr)); // register function to be called in case of error + void registerResultCallback(void(*callBackPtr)(void)); // register function to be called when also process is done + void registerErrorCallback(void(*callBackPtr)(uint32_t error)); // register function to be called in case of error + void registerRawDataCallback(void(*callBackPtr)(raw_data_context_t context)); // register function to be called for raw data void begin(void); void end(void); void run(void); // run radar process @@ -51,6 +52,12 @@ class IFXRadarPulsedDoppler float getSpeed(void); // get speed value without sign uint32_t getFrameCount(void); // get frame count of result + // raw data context functions, call only in raw_data_callback + uint32_t getRawDataFrameCount( raw_data_context_t raw_data_context ); + void getRawData( raw_data_context_t raw_data_context, float *p_raw_data_i, float *p_raw_data_q, uint16_t max_num_samples, uint8_t high_gain_input=1 ); + uint16_t getNumRawDataSamples( raw_data_context_t raw_data_context ); + + // debug functions void parameterDump(Print *outDev); void parameterDump(); diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/arduino_adapt.h b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/arduino_adapt.h index 0763b02d..191455f3 100644 --- a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/arduino_adapt.h +++ b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/arduino_adapt.h @@ -5,7 +5,7 @@ */ /* =========================================================================== -** Copyright (C) 2019 Infineon Technologies AG +** Copyright (C) 2019-2021 Infineon Technologies AG ** All rights reserved. ** =========================================================================== ** @@ -123,6 +123,9 @@ extern "C" #define RADAR_ERR_UNSUPPORTED_RESOLUTION 0x0051 /**< The specified sample resolution is out of range. */ + +#define RADAR_ERR_INVALID_POINTER 0x0052 /**< Invalid pointer as argument */ + #define RF_SHIELD_BOARD_INVALID_PARAM 0xFE01 /**< Status in case of invalid parameter */ #define RF_SHIELD_BOARD_SUPPORTED 0xFE02 /**< Status for supported RF shield with valid board ID */ #define RF_SHIELD_BOARD_UNSUPPORTED 0xFE03 /**< Status for unsupported RF shield board @@ -139,8 +142,13 @@ extern "C" ============================================================================== */ +typedef void* raw_data_context_t; + typedef void(*ard_error_handler_cb)(uint32_t error); typedef void(*ard_result_handler_cb)( void ); +typedef void(*ard_raw_data_handler_cb)(raw_data_context_t context); + + /* ============================================================================== @@ -152,6 +160,8 @@ ard_error_handler_cb radar_ard_register_error_handler( ard_error_handler_cb hand ard_result_handler_cb radar_ard_register_result_handler( ard_result_handler_cb handler); +ard_raw_data_handler_cb radar_ard_register_raw_data_handler( ard_raw_data_handler_cb handler); + void radar_ard_init(void); uint8_t radar_ard_is_initalized( void ); @@ -226,7 +236,19 @@ uint8_t radar_ard_is_motion( void ); uint32_t radar_ard_get_frame_count( void ); +uint8_t radar_ard_set_do_algo_processing( uint8_t do_processing ); + +/* for usage in raw data handler only */ +uint32_t radar_ard_get_frame_raw_data( raw_data_context_t p_raw_data_context ); + +void radar_ard_get_raw_data( raw_data_context_t raw_data_context, float *p_raw_data_i, float *p_raw_data_q, uint16_t max_num_samples, uint8_t high_gain_input ); + +uint16_t radar_ard_get_num_raw_data_samples( raw_data_context_t p_raw_data_context ); + +/* --- End of File -------------------------------------------------------- */ + /* --- Close open blocks -------------------------------------------------- */ + /* Disable C linkage for C++ files */ #ifdef __cplusplus } /* extern "C" */ diff --git a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/cortex-m4/libRadar_S2GL_Pulsed_Doppler_lib.a b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/cortex-m4/libRadar_S2GL_Pulsed_Doppler_lib.a index a9f86bca..1b6b799f 100644 Binary files a/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/cortex-m4/libRadar_S2GL_Pulsed_Doppler_lib.a and b/libraries/BGT24LTR11-Pulsed-Doppler-Radar/src/cortex-m4/libRadar_S2GL_Pulsed_Doppler_lib.a differ diff --git a/libraries/DeviceControlXMC/src/utility/timer.c b/libraries/DeviceControlXMC/src/utility/timer.c index 4c1a3978..e3577d77 100644 --- a/libraries/DeviceControlXMC/src/utility/timer.c +++ b/libraries/DeviceControlXMC/src/utility/timer.c @@ -49,6 +49,8 @@ #include #include +#include "Arduino.h" // since interrupt symbols are defined in pins_arduino.h for XMC 1400 series instead of the device-specific header file (XMC1400.h). + /********************************************************************************************************************* * API IMPLEMENTATION ********************************************************************************************************************/ diff --git a/libraries/LED/Readme.md b/libraries/LED/Readme.md index d104e4af..e8ba79f5 100644 --- a/libraries/LED/Readme.md +++ b/libraries/LED/Readme.md @@ -5,18 +5,19 @@ **Author** | : | Paul Carpenter | | | PC Services | | | www.pcserviceselectronics.co.uk -**Version** | : | V1.00 -**Date** | : | July 2018 +**Version** | : | V1.0.3 +**Updated** | : | August 2022 +Date | : | July 2018 -Infineon XMC-for-Arduino RTC Library, to assist in making board agnostic examples that +Infineon XMC-for-Arduino LED Library, to assist in making board agnostic examples that will work the same across all boards. This file will be available in the library folder. Often it is useful to have an example and have LED change state when things happen or -errors occur, so to make this easier it is better to use on board LEDs that will always +errors occur, so to make this easier it is better to use on board LEDs that will always be there. Unfortunately if you are writing an example to use across many boards the -XMC boards do not all work the same way. This library enables examples or applications to -use the on board LEDs in the same way across all boards that any example supports. This -is encapsulating the LED drive primarily for easier use of on board LEDs in examples that +XMC boards do not all work the same way. This library enables examples or applications to +use the on board LEDs in the same way across all boards that any example supports. This +is encapsulating the LED drive primarily for easier use of on board LEDs in examples that work on all or many of the boards. ## Table of Contents @@ -35,28 +36,32 @@ Unfortunately the on-board LEDs on the XMC range of boards work differently betw models. There is no consistent, on board LED driven by the same state to be ON across all models of board so we end up with -| Board | ON state | -| :---- | :---: | - XMC1100 Boot Kit | Low - XMC1100 XMC2GO | High - XMC1100 XMC H Bridge2GO | High - XMC1300 Boot Kit | Low - XMC1300 Sense2GOL | Low - XMC4700 Relax Kit | Low +| Board | Normal LEDs
ON state | LED_BUILTIN
Separate | LED_BUILTIN
ON state +| :---- | :---: | :---: | :---: | + XMC1100 Boot Kit | Low | Yes | High + XMC1100 XMC2GO | High | No | High + XMC1100 XMC H Bridge2GO | High| No | High + XMC1300 Boot Kit | Low | No | Low + XMC1300 Sense2GOL | Low| No | Low + XMC1400 Arduino Kit | Low | Yes | High + XMC4200 Platform2Go | High| No | High + XMC4400 Platform2Go | High| No | High + XMC4700 Relax Kit | High| No | High + XMC4700 Relax Kit Lite | High| No | High [Back to top](#table-of-contents) ### LEDs on Different Boards Matrix of available on board LED names or LED they map to, known currently. -| LED Macro | XMC1100
Boot Kit | XMC1100
XMC2GO | XMC1100
HBRIDGE2GO | XMC1300
Boot Kit | XMC1300
Sense2GOL | XMC4700
Relax | -| --- | :--: | :--: | :--: | :--: | :--: | :--: | - LED_BUILTIN | Y | LED1 | LED1 | LED1 | LED1 | LED1 - LED1 | Y | Y | Y | Y | Y | Y - LED2 | Y | Y | Y | Y | Y | Y - LED3 | Y | - | - | Y | Y | - - LED4 | Y | - | - | Y | - | - - LED5 | Y | - | - | Y | - | - - LED5 | Y | - | - | Y | - | - +| LED Macro | XMC1100
Boot Kit | XMC1100
XMC2GO | XMC1100
HBRIDGE2GO | XMC1300
Boot Kit | XMC1300
Sense2GOL | XMC1400
Arduino Kit | XMC4200
Platform2Go | XMC4400
Platform2Go | XMC4700
Relax Kit | XMC4700
Relax Kit Lite | +| --- | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | + LED_BUILTIN | Y | LED1 | LED1 | LED1 | LED1 | Y | LED1 | LED1 | LED1 | LED1 + LED1 | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y + LED2 | Y | Y | Y | Y | Y | Y | - | Y | Y | Y + LED3 | Y | - | - | Y | Y | - | - | - | - | - + LED4 | Y | - | - | Y | - | - | - | - | - | - + LED5 | Y | - | - | Y | - | - | - | - | - | - + LED6 | Y | - | - | Y | - | - | - | - | - | - [Back to top](#table-of-contents) ## Requirements for Adding New Boards @@ -84,7 +89,7 @@ See [LEDs on Different Boards](#leds-on-different-boards "Number of LEDs on boar All functions have a Arduino Pin reference passed in or a macro that defines it e.g. LED1 or LED2. -Note at present all boards have **2** LEDs as a minimum some have 3 or 6 LEDs. Obviously only reference +Note at present all boards have **2** LEDs as a minimum some have 3 or 6 LEDs. Obviously only reference LEDs that actually exist for the boards are supported. This library uses NO RAM storage it is mainly software encapsulation/wrappers to other functions. @@ -121,11 +126,13 @@ Led.Add( LED1 ); // Add LED (configure for output) ## Examples This is here for completeness of Arduino IDE library structure. ### Simple LED -This example simply +This example works on all currently known boards simply - In setup() sets up two LEDs - In loop() - - Waits one second - - Toggles LED1 + - Waits one second + - Toggles LED1 - Turns Off LED2 +If a board like **XMC4200 Platform2Go** with only **ONE** LED is in use **only LED1 function is used** + [Back to top](#table-of-contents) diff --git a/libraries/LED/examples/SimpleLED/SimpleLED.ino b/libraries/LED/examples/SimpleLED/SimpleLED.ino index 2531737d..5829d2c1 100644 --- a/libraries/LED/examples/SimpleLED/SimpleLED.ino +++ b/libraries/LED/examples/SimpleLED/SimpleLED.ino @@ -1,11 +1,10 @@ /* Simple LED library flashes on board LED Every second - Simple RTC for Infineon XMC boards with RTC - Demonstrates the use of the LED library + Demonstrates the use of the on board LED library - Works with any XMC board that has TWO LEDs on board + Works with any XMC board that has at least ONE LED on board + Better with two */ -/* For on board LEDs */ #include /* Create an LED object */ @@ -14,18 +13,21 @@ LED Led; void setup( ) { Led.Add( LED1 ); // Configure the LEDs -Led.Add( LED2 ); +Led.Off( LED1 ); // Set default state of LEDs -// Set default state of LEDs +#if NUM_LEDS > 1 +Led.Add( LED2 ); Led.On( LED2 ); -Led.Off( LED1 ); +#endif } void loop( ) { delay( 1000 ); -Led.Off( LED2 ); Led.Toggle( LED1 ); +#if NUM_LEDS > 1 +Led.Off( LED2 ); +#endif } diff --git a/libraries/LED/library.properties b/libraries/LED/library.properties index 2632fc93..8638598d 100644 --- a/libraries/LED/library.properties +++ b/libraries/LED/library.properties @@ -1,5 +1,5 @@ -name=RTC -version=1.0.1 +name=LED +version=1.0.3 author=Infineon Technologies AG maintainer=Infineon Technologies AG sentence=This library allows you to enable as well as control the on board LEDs of the XMC microcontrollers. diff --git a/libraries/LED/src/LED.h b/libraries/LED/src/LED.h index 7d946fe4..52a56c8e 100644 --- a/libraries/LED/src/LED.h +++ b/libraries/LED/src/LED.h @@ -44,6 +44,10 @@ #error This board NOT supported by this library (Check pins_arduino.h) #endif +#if not defined( NUM_LEDS ) || ( NUM_LEDS < 1 ) +#error Current selected board does NOT support on board LEDs +#endif + //**************************************************************************** // @Project Includes //**************************************************************************** diff --git a/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde b/libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.ino similarity index 100% rename from libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.pde rename to libraries/OneWire/examples/DS18x20_Temperature/DS18x20_Temperature.ino diff --git a/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde b/libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.ino similarity index 100% rename from libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.pde rename to libraries/OneWire/examples/DS2408_Switch/DS2408_Switch.ino diff --git a/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde b/libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.ino similarity index 100% rename from libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.pde rename to libraries/OneWire/examples/DS250x_PROM/DS250x_PROM.ino diff --git a/libraries/SPI/src/utility/xmc_spi_conf.c b/libraries/SPI/src/utility/xmc_spi_conf.c index da24cde3..f1f9ea37 100644 --- a/libraries/SPI/src/utility/xmc_spi_conf.c +++ b/libraries/SPI/src/utility/xmc_spi_conf.c @@ -107,6 +107,46 @@ XMC_SPI_t XMC_SPI_0 = } }; +#elif defined(XMC1400_Arduino_Kit) +XMC_SPI_t XMC_SPI_0 = +{ + .channel = XMC_SPI1_CH1, + .channel_config = { + .baudrate = 15984375U, + .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, + .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, + .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE + }, + .mosi = { + .port = (XMC_GPIO_PORT_t*)PORT0_BASE, + .pin = (uint8_t)1 + }, + .mosi_config = { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT9, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + }, + .miso = { + .port = (XMC_GPIO_PORT_t*)PORT0_BASE, + .pin = (uint8_t)0 + }, + .miso_config = { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + }, + .input_source = XMC_INPUT_A, + .sclkout = { + .port = (XMC_GPIO_PORT_t*)PORT0_BASE, + .pin = (uint8_t)3 + }, + .sclkout_config = { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT8, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + } +}; + + #elif defined(XMC4400_Platform2GO) XMC_SPI_t XMC_SPI_0 = { @@ -145,6 +185,44 @@ XMC_SPI_t XMC_SPI_0 = }, }; +#elif defined(XMC4200_Platform2GO) +XMC_SPI_t XMC_SPI_0 = +{ + .channel = XMC_SPI1_CH1, + .channel_config = { + .baudrate = 20003906U, + .bus_mode = (XMC_SPI_CH_BUS_MODE_t)XMC_SPI_CH_BUS_MODE_MASTER, + .selo_inversion = XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS, + .parity_mode = XMC_USIC_CH_PARITY_MODE_NONE + }, + .mosi = { + .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)9 + }, + .mosi_config = { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM + }, + .miso = { + .port = (XMC_GPIO_PORT_t*)PORT0_BASE, + .pin = (uint8_t)0 + }, + .miso_config = { + .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + }, + .input_source = XMC_INPUT_D, + .sclkout = { + .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)8 + }, + .sclkout_config = { + .mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM + }, +}; + #elif defined(XMC4700_Relax_Kit) XMC_SPI_t XMC_SPI_0 = { diff --git a/libraries/SPI/src/utility/xmc_spi_conf.h b/libraries/SPI/src/utility/xmc_spi_conf.h index 29207886..2a1a8c9b 100644 --- a/libraries/SPI/src/utility/xmc_spi_conf.h +++ b/libraries/SPI/src/utility/xmc_spi_conf.h @@ -60,10 +60,18 @@ extern XMC_SPI_t XMC_SPI_0; #define NUM_SPI 1 extern XMC_SPI_t XMC_SPI_0; +#elif defined(XMC1400_Arduino_Kit) +#define NUM_SPI 1 +extern XMC_SPI_t XMC_SPI_0; + #elif defined(XMC4400_Platform2GO) #define NUM_SPI 1 extern XMC_SPI_t XMC_SPI_0; +#elif defined(XMC4200_Platform2GO) +#define NUM_SPI 1 +extern XMC_SPI_t XMC_SPI_0; + #elif defined(XMC4700_Relax_Kit) #define NUM_SPI 3 #define XMC_SPI_for_xmc_SD XMC_SPI_1 diff --git a/libraries/Wire/src/utility/xmc_i2c_conf.c b/libraries/Wire/src/utility/xmc_i2c_conf.c index 22b0864e..8e94726e 100644 --- a/libraries/Wire/src/utility/xmc_i2c_conf.c +++ b/libraries/Wire/src/utility/xmc_i2c_conf.c @@ -197,6 +197,40 @@ XMC_I2C_t XMC_I2C_0 = .protocol_irq_service_request = 5 }; +#elif defined(XMC1400_Arduino_Kit) +XMC_I2C_t XMC_I2C_0 = +{ + .channel = XMC_I2C0_CH0, + .channel_config = { + .baudrate = (uint32_t)(100000U), + .address = 0U + }, + .sda = { + .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)1 + }, + .sda_config = { + .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT6, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + }, + .scl = { + .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)0 + }, + .scl_config = { + .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT7, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + }, + .input_source_dx0 = XMC_INPUT_F, + .input_source_dx1 = XMC_INPUT_E, + .slave_receive_irq_num = (IRQn_Type) USIC0_4_IRQn, + .slave_receive_irq_service_request = 4 , + .protocol_irq_num = (IRQn_Type) USIC0_5_IRQn, + .protocol_irq_service_request = 5 +}; + #elif defined (XMC4400_Platform2GO) XMC_I2C_t XMC_I2C_0 = @@ -230,6 +264,38 @@ XMC_I2C_t XMC_I2C_0 = .protocol_irq_service_request = 2 }; +#elif defined (XMC4200_Platform2GO) +XMC_I2C_t XMC_I2C_0 = +{ + .channel = XMC_I2C0_CH1, + .channel_config = { + .baudrate = (uint32_t)(100000U), + .address = 0U + }, + .sda = { + .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)5 + }, + .sda_config = { + .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, + .scl = { + .port = (XMC_GPIO_PORT_t*)PORT3_BASE, + .pin = (uint8_t)0 + }, + .scl_config = { + .mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH + }, + .input_source_dx0 = XMC_INPUT_B, + .input_source_dx1 = XMC_INPUT_B, + .slave_receive_irq_num = (IRQn_Type) 84, + .slave_receive_irq_service_request = 1 , + .protocol_irq_num = (IRQn_Type) 85, + .protocol_irq_service_request = 2 +}; + #elif defined(XMC4700_Relax_Kit) XMC_I2C_t XMC_I2C_0 = diff --git a/libraries/Wire/src/utility/xmc_i2c_conf.h b/libraries/Wire/src/utility/xmc_i2c_conf.h index a7d65b94..f8045089 100644 --- a/libraries/Wire/src/utility/xmc_i2c_conf.h +++ b/libraries/Wire/src/utility/xmc_i2c_conf.h @@ -64,10 +64,17 @@ extern XMC_I2C_t XMC_I2C_1; #define NUM_I2C 1 extern XMC_I2C_t XMC_I2C_0; +#elif defined(XMC1400_Arduino_Kit) +#define NUM_I2C 1 +extern XMC_I2C_t XMC_I2C_0; + #elif defined(XMC4400_Platform2GO) #define NUM_I2C 1 extern XMC_I2C_t XMC_I2C_0; +#elif defined(XMC4200_Platform2GO) +#define NUM_I2C 1 +extern XMC_I2C_t XMC_I2C_0; #elif defined(XMC4700_Relax_Kit) #define NUM_I2C 2 diff --git a/package/package_infineon_index.template.json b/package/package_infineon_index.template.json index f626b6e2..4941015e 100644 --- a/package/package_infineon_index.template.json +++ b/package/package_infineon_index.template.json @@ -44,14 +44,20 @@ "name":"XMC4700 Relax Kit" }, { - "name":"XMC4700 DEMO Radar BB" + "name":"XMC4700 Radar Baseboard" + }, + { + "name":"XMC1400 Kit for Arduino" + }, + { + "name":"XMC4200 Platform 2Go" } ], "toolsDependencies":[ { "packager":"Infineon", "name":"arm-none-eabi-gcc", - "version":"5.4-2016q3" + "version":"10.3-2021.10" }, { "packager":"Infineon", @@ -139,6 +145,33 @@ } ] }, + { + "name":"arm-none-eabi-gcc", + "version":"10.3-2021.10", + "systems":[ + { + "host":"i686-mingw32", + "archiveFileName":"gcc-arm-none-eabi-10.3-2021.10-win32.zip", + "url":"https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-win32.zip", + "checksum":"SHA-256:d287439b3090843f3f4e29c7c41f81d958a5323aecefcf705c203bfd8ae3f2e7", + "size":"200578763" + }, + { + "host":"x86_64-apple-darwin", + "url":"https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-mac.tar.bz2", + "archiveFileName":"gcc-arm-none-eabi-10.3-2021.10-mac.tar.bz2", + "checksum":"SHA-256:fb613dacb25149f140f73fe9ff6c380bb43328e6bf813473986e9127e2bc283b", + "size":"158961466" + }, + { + "host":"x86_64-pc-linux-gnu", + "url":"https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2", + "archiveFileName":"gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2", + "checksum":"SHA-256:97dbb4f019ad1650b732faffcc881689cedc14e2b7ee863d390e0a41ef16c9a3", + "size":"157089706" + } + ] + }, { "name":"XMCFlasher", "version":"1.2.0", diff --git a/platform.txt b/platform.txt index 2cbb830b..a75bffcb 100644 --- a/platform.txt +++ b/platform.txt @@ -60,6 +60,7 @@ build.usb_manufacturer="Unknown" compiler.c.flags=-mcpu={build.mcu} -mthumb -c -g -Os {compiler.warning_flags} -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -MMD #compiler.c.extra_flags=-ftime-report compiler.c.extra_flags= +compiler.libraries.ldflags= compiler.c.elf.flags=-Os -Wl,--gc-sections -save-temps compiler.c.elf.extra_flags= @@ -96,7 +97,7 @@ recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} -DXMC{bu # ---------------- ## Combine gc-sections, archives, and objects -recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" -mthumb --specs=nosys.specs --specs=nano.specs -mcpu={build.mcu} {compiler.c.elf.flags} "-T{build.flash_ld_path}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align {object_files} "{build.path}/{archive_file}" -lm +recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" -mthumb --specs=nosys.specs --specs=nano.specs -mcpu={build.mcu} {compiler.c.elf.flags} "-T{build.flash_ld_path}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align {object_files} "{build.path}/{archive_file}" {compiler.libraries.ldflags} -lm ## Create archives # ---------------- diff --git a/resources/readme.md b/resources/readme.md index dd2e084c..3ee0be25 100644 --- a/resources/readme.md +++ b/resources/readme.md @@ -1,4 +1,24 @@ # Resources Folder ## Linked resources for Wiki and other documentation This folder contains sub-folders for documentation resources, primarily to link to files -and images for wiki. \ No newline at end of file +and images for wiki. + +### folder wiki contains + +- xmc4200-X1-X2.csv XMC4200 Platform 2 Go CSV of X1 and X2 connector pinout +- xmc4400-X1-X2.csv XMC4400 Platform 2 Go CSV of X1 and X2 connector pinout +- xmc4700-X1-X2.csv XMC4700 Relax Kit (and Lite) CSV of X1 and X2 connector pinout + +### Folder wiki/Pictures + +File/Folder | Description +| :--: | ----- | +| board_PO.jpg | JPEG updates of Pinout image for wiki | +| SVG | folder of source version(s) in SVG format | +| PNG | folder of intermediate version(s) in PNG format | + +### Folder wiki/Eagle + +File/Folder | Description +| :--: | ----- | +| INF-XMC.lbr | - Eagle library for symbol and footprints of Infineon XMC processors | diff --git a/resources/wiki/Eagle/INF-XMC.lbr b/resources/wiki/Eagle/INF-XMC.lbr new file mode 100644 index 00000000..cca901c9 --- /dev/null +++ b/resources/wiki/Eagle/INF-XMC.lbr @@ -0,0 +1,3561 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Infineon XMC1000 and XMC4000 series micros + + +TSSOP-16 pitch 0.65 mm pads 0.35 x 1.25 mm + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +TSSOP-16 pitch 0.65 mm, pads 0.35 x 1.55 mm + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +TSSOP-38 pitch 0.5 mm, pads 0.25 x 1.35 mm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +TSSOP-38 pitch 0.5 mm, pads 0.3 x 1.6 mm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +TSSOP-28 pitch 0.65mm, pads 0.35 x 1.25 mm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +TSSOP-28 pitch 0.65mm, pads .35 x 1.55 mm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>QFN48P-7X7</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + +<b>P/PG-LQFP-100</b> 0.5mm pitch Tie exposed pad with approx. 0.2mm thermal vias to GND<br> +PG-LQFP-100-11, leadframe no: C66065-A6837-C024-01-004 EPad: 7.0 x 7.0 mm <br> +LQFP-100 package with 7.0 x 7.0mm Exposed Pad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1100 series 24 pin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1100 series 38 pin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1000 38 pin Single symbol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1401 48 pin QFN Single Symbol + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1000 Series 16 Pin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1000 series 28 pin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1000 series 64 pin QFP/QFN<br> +39 digital (+4 crystals)<br> +14 analog + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +XMC1000 series 40 pin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/resources/wiki/xmc4200-X1-X2.csv b/resources/wiki/xmc4200-X1-X2.csv new file mode 100644 index 00000000..ffb054d2 --- /dev/null +++ b/resources/wiki/xmc4200-X1-X2.csv @@ -0,0 +1,75 @@ +Additional pins for port X1,,,,, +Description,Pin,Port,,X1 pin,Other +NC,,,,X1-37, +IO_1,7,P2.8,,X1-35,IOL-8 +PWM41-1 output / PWM2,6,P2.4,,X1-33,IOL-7 +PWM41-3 / PWM0 / External INT 1,3,P2.2,,X1-31,IOL-4 +CAN_TX,29,P2.0,,X1-29, +IO_2,8,P2-6,,X1-27,IOH-1 +NC,,,,X1-25, +NC,,,,X1-23, +NC,,,,X1-21, +NC,,,,X1-19, +NC,,,,X1-17, +USB Debug TX,35,P1.4,,X1-15, +PWM / PWM40-1 / GPIO4_S2GO_1,23,P1.2,,X1-13, +GPIO / External INT 0,2,P1.0,,X1-11,IOL-3 +SPI-SCK,13,P1.8,,X1-9,IOH-6 +NC,,,,X1-7, +NC,,,,X1-5, +TX,1,P2.14,,X1-3,IOL-2 +RX,0,P2.15,,X1-4,IOL-1 +NC,,,,X1-6, +SPI-CS,10,P1.7,,X1-8,IOH-3 +SPI-MOSI,11,P1.9,,X1-10,IOH-4 +PWM_MikroBus / PWM40-2,22,P1.1,,X1-12, +PWM / PWM40-0 / GPIO4_2GO_2,24,P1.3,,X1-14, +USB Debug RX,41,P1.5,,X1-16, +NC,,,,X1-18, +NC,,,,X1-20, +BUTTON1,27,P1.15,Button,X1-22,Switch +NC,,,,X1-24, +NC,,,,X1-26, +RST_MikroBus,28,P2.7,,X1-28, +GPIO1_2GO_2,30,P2.1,,X1-30, +PWM41-2 output / PWM1,5,P2.3,,X1-32,IOL-6 +I2C Data / Address SDA / A4,14,P2.5,(Hardwired to A4),X1-34,IOH-9 +IO_0,4,P2.9,,X1-36,IOL-5 +NC,,,,X1-38, +Additional pins for port X2,,,,, +Description,Pin,Port,,X2 pin,Other +A3 / ADC Input / AN_MikroBus / DAC0,19,P14.8,,X2-33,Analog-4 +NC,,,,X2-31, +NC,,,,X2-29, +NC,,,,X2-27, +A1 / ADC Input,17,P14.6,(INPUT ONLY),X2-25,Analog-2 +NC,,,,X2-23, +AN2_2GO_1 / A6 / ADC Input,41,P14.14,(INPUT ONLY),X2-21, +I2C Clock SCL / A5 - ADC Input,15,P3.0,(Hardwired to A5),X2-19,IOH-10 +NC,,,,X2-17, +INT_MikroBus,38,P0.10,,X2-15, +LED1,36,P0.1,,X2-13,LED +INT / GPIO3_2GO_2,34,P0.3,,X2-11, +INT / GPIO3_2GO_1,33,P0.5,,X2-9, +PWM80-31 output / PWM3,9,P0.11,,X2-7,IOH-2 +NC,,,,X2-5, +NC,,,,X2-3, +SPI-CS_MikroBus,31,P0.7,,X2-1, +RST / GPIO2_2GO_1,32,P0.8,,X2-4, +NC,,,,X2-6, +NC,,,,X2-8, +NC,,,,X2-10, +RST / GPIO2_2GO_2,35,P0.6,,X2-12, +GPIO1_S2GO_1,37,P0.4,,X2-14, +SPI-CS_2GO_1,39,P0.2,,X2-16, +SPI-MISO,12,P0.0,,X2-18,IOH-5 +SPI-CS_2GO_2,40,P0.9,,X2-20, +NC,,,,X2-22, +A4 / ADC Input / SDA / AN1_2GO_1,20,P14.4,(Hardwired to SDA),X2-24,Analog-5 +NC,,,,X2-26, +A2 / ADC Input,18,P14.7,(INPUT ONLY),X2-28,Amalog-3 +A5 / ADC Input / SCL / AN2_2GO_2,21,P14.5,(Hardwired to SCL),X2-30,Analog-6 +CAN_RX,42,P14.3,(INPUT ONLY),X2-32, +A0 / ADC Input,16,P14.0,Potentiometer,X2-34,Analog-1 +AN1_2GO_2 / A7 / ADC Input / DAC1,43,P14.9,,X2-36, +AREF,,,,X2-38,IOH-8 diff --git a/resources/wiki/xmc4400-X1-X2.csv b/resources/wiki/xmc4400-X1-X2.csv new file mode 100644 index 00000000..1111bec8 --- /dev/null +++ b/resources/wiki/xmc4400-X1-X2.csv @@ -0,0 +1,74 @@ +Additional pins for port X1,,,,, +Description,Pin,Port,,X1 pin,Other +GPIO / ETH_LED,25,P2.10,,X1-37, +GPIO / ETH_TXDO / PWM80-32,26,P2.8,,X1-35, +GPIO / ETH_RXER,27,P2.4,,X1-33, +GPIO / ETH_RXDO,28,P2.2,,X1-31, +GPIO / ETH_MDIO / PWM81-21,29,P2.0,,X1-29, +PWM80-13 / GPIO4_2GO_2,30,P2.6,,X1-27, +GPIO / RST,31,P5.2,,X1-25, +GPIO1_2GO_1,32,P5.0,,X1-23, +GPIO / IO_1,7,P1.14,,X1-21,IOL-8 +GPIO / CAN_TX,33,P1.12,,X1-19, +GPIO / GPIO2_2GO_1,34,P1.10,,X1-17, +GPIO / QSPI_IO1,35,P1.4,,X1-15, +GPIO / QSPI_IO3,36,P1.2,,X1-13, +GPIO / External INT 0,2,P1.0,,X1-11,IOL-3 +SPI-SCK / GPIO,13,P1.8,,X1-9,IOH-6 +GPIO / IO_0,4,P1.6,,X1-7,IOL-5 +GPIO / GPIO2_2GO_2,37,P4.0,,X1-5, +TX,1,P2.14,,X1-3,IOL-2 +RX,0,P2.15,,X1-4,IOL-1 +GPIO / IO_2,8,P4.1,,X1-6,IOH-1 +GPIO / SPI_CS_2GO_2,38,P1.7,(Chip Select - Slot 2),X1-8, +SPI-MOSI,11,P1.9,,X1-10,IOH-4 +GPIO1_2GO_2,39,P1.1,,X1-12, +GPIO / QSPI_IO3,40,P1.3,,X1-14, +GPIO / QSPI_IO0,41,P1.5,,X1-16, +GPIO / QSPI_CS,42,P1.11,,X1-18, +GPIO / CAN_RX,43,P1.13,,X1-20, +USB Debug RX,23,P1.15,,X1-22, +GPIO / ETH_INT,44,P5.1,,X1-24, +PWM81-02,45,P5.7,,X1-26, +PWM80-03 / ETH_MDC,46,P2.7,,X1-28, +"SWV **DEBUG Do NOT Use**",47,P2.1,,X1-30, +ETH_RXD1 / PWM41-2,14,P2.3,,X1-32,IOH-8 +I2C Data / Address SDA / A4 / PWM41-0,15,P2.5,(Hardwired to A4),X1-34,IOH-9 +PWM80-22 / ETH_TXD1,48,P2.9,,X1-36, +A16 / ETH_CLK,49,P15.8,,X1-38, +Additional pins for port X2,,,,, +Description,Pin,Port,,X2 pin,Other +A14 / DAC 0 Output,50,P14.8,,X2-33, +A3 / ADC Input,20,P14.3,(INPUT ONLY),X2-31,Analog-4 +A11 - ADC Input,52,P14.15,(INPUT ONLY),X2-29, +A17 - ADC Input / ETH_CRS,53,P15.9,,X2-27, +A6 / AN1_2GO_1 - ADC Input,54,P14.6,(INPUT ONLY),X2-25, +A8 / AN1_2GO_2 - ADC Input,55,P14.12,(INPUT ONLY),X2-23, +A10 / ADC Input,56,P14.14,(INPUT ONLY),X2-21, +I2C Clock SCL / A5 - ADC Input,16,P3.0,(Hardwired to A5),X2-19,IOH-10 +BUTTON2,57,P3.2,,X2-17, +INT / GPIO3_2GO_1,58,P0.10,,X2-15, +INT,59,P0.1,,X2-13, +INT / GPIO3_2GO_2,60,P0.3,,X2-11, +USB Debug TX,24,P0.5,,X2-9, +PWM80-31 output / PWM3,9,P0.11,,X2-7,IOH-2 +PWM42-3 output / PWM1,5,P3.3,,X2-5,IOL-6 +CS_2GO_1,61,P3.5,(Chip Select - Slot 1),X2-3, +LED2,62,P0.7,,X2-1, +QSPI_CLK,63,P0.8,,X2-4, +PWM42-0 / PWM0 / External INT 1,3,P3.6,,X2-6,IOL-4 +PWM42-2 output / PWM2,6,P3.4,,X2-8,IOL-7 +CS_MB,64,P0.12,(Chip Select - MikroBUS),X2-10, +LED1,65,P0.6,,X2-12, +ETH_TXEN,66,P0.4,,X2-14, +SPI-SS / PWM80-01 / PWM4,10,P0.2,,X2-16,IOH-3 +SPI-MISO,12,P0.0,,X2-18,IOH-5 +GPIO4_2GO_1 / PWM80-12 / PWM,67,P0.9,,X2-20, +BUTTON1,68,P3.1,,X2-22, +A4 / ADC Input / SDA / GPIO,21,P14.4,(Hardwired to SDA),X2-24,Analog-5 +A9 / AN2_2GO_2 - ADC Input,69,P14.13,(INPUT ONLY),X2-26, +A7 / AN2_2GO_1 - ADC Input,70,P14.7,(INPUT ONLY),X2-28, +A5 / ADC Input / SCL,22,P14.5,(Hardwired to SCL),X2-30,Analog-6 +A12 - ADC Input,51,P15.2,(INPUT ONLY),X2-32, +A13 - ADC Input,71,P15.3,(INPUT ONLY),X2-34, +A15 / DAC 1 Output,72,P14.9,,X2-36, diff --git a/resources/wiki/xmc4700-X1-X2.csv b/resources/wiki/xmc4700-X1-X2.csv index f404d588..d8b7e7b2 100644 --- a/resources/wiki/xmc4700-X1-X2.csv +++ b/resources/wiki/xmc4700-X1-X2.csv @@ -62,5 +62,5 @@ PWM43-3 / PWM19,91,P6.2,14 SPI_3 SCLK,93,P0.8,10 ,94,P3.3,8 PWM40-0 / PWM20,95,P0.15,6 -PWM40-3 / PWM22,96,P0.12,4, -ECAT0.P1_LINK_ACT,97,P3.12,2,YES Pin 23 +PWM40-3 / PWM22,96,P0.12,4 +ECAT0.P1_LINK_ACT,97,P3.12,2 diff --git a/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h b/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h index 17ac3673..6e43d49f 100644 --- a/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h +++ b/variants/XMC1100/config/XMC1100_Boot_Kit/pins_arduino.h @@ -54,6 +54,9 @@ extern const uint8_t NUM_ANALOG_INPUTS; // Indicate unit has RTC/Alarm for simpler RTC control #define HAS_RTC +// Indicate variant has a GPIO pin used for Reset pin +#define HAS_GPIO_RESET 1 + // Defines will be either set by ArduinoIDE in the menu or manually #ifdef SERIAL_HOSTPC // Comment out following line to use Serial on pins (board) @@ -65,7 +68,8 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define SERIAL_DEBUG 1 #endif -#define PWM4_TIMER_PERIOD (2041U) // Generate 490Hz @fCCU=1MHz +// Generate 490Hz @fCCU=1MHz +#define PWM4_TIMER_PERIOD (2041U) #define PCLK 64000000u @@ -88,21 +92,23 @@ extern uint8_t SCK; #define A6 6 #define A7 7 -#define AD_AUX_1 24 // AD_AUX -#define AD_AUX_2 25 // AD_AUX -#define AUX_1 26 // AUX -#define AUX_2 27 // AUX -#define AUX_3 28 // AUX -#define AUX_4 29 // AUX -#define AUX_5 30 // AUX - -#define LED_BUILTIN 13 // Standard Arduino LED pin 13 -#define LED1 26 // Extended LEDs P0.5 -#define LED2 27 // Extended LEDs P0.6 -#define LED3 0 // Extended LEDs P1.2 -#define LED4 1 // Extended LEDs P1.3 -#define LED5 2 // Extended LEDs P1.4 -#define LED6 31 // Extended LEDs P1.5 +// AD_AUX Connector +#define AD_AUX_1 24 +#define AD_AUX_2 25 +// AUX Connector +#define AUX_1 26 +#define AUX_2 27 +#define AUX_3 28 +#define AUX_4 29 +#define AUX_5 30 + +#define LED_BUILTIN 13 +#define LED1 26 +#define LED2 27 +#define LED3 0 +#define LED4 1 +#define LED5 2 +#define LED6 31 #define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) @@ -120,9 +126,9 @@ const XMC_PORT_PIN_t mapping_port_pin[] = /* 7 */ {XMC_GPIO_PORT0, 4}, // GPIO P0.4 /* 8 */ {XMC_GPIO_PORT0, 12},// GPIO P0.12 /* 9 */ {XMC_GPIO_PORT0, 8}, // PWM40-2 output P0.8 - /* 10 */ {XMC_GPIO_PORT0, 9}, // SPI-SS P0.9 - /* 11 */ {XMC_GPIO_PORT1, 1}, // SPI-MOSI P1.1 - /* 12 */ {XMC_GPIO_PORT1, 0}, // SPI-MISO P1.0 + /* 10 */ {XMC_GPIO_PORT0, 9}, // SPI-SS / PWM40-3 output P0.9 + /* 11 */ {XMC_GPIO_PORT1, 1}, // SPI-MOSI / PWM40-1 output P1.1 + /* 12 */ {XMC_GPIO_PORT1, 0}, // SPI-MISO P1.0 /* 13 */ {XMC_GPIO_PORT0, 7}, // SPI-SCK / LED BUILTIN output P0.7 /* 14 */ {XMC_GPIO_PORT2, 3}, // AREF ** DO NOT USE as GPIO or REF ** P2.3 /* 15 */ {XMC_GPIO_PORT2, 1}, // I2C Data / Address SDA / A7 ADC P2.1 @@ -163,15 +169,19 @@ const uint8_t mapping_pin_PWM4[][ 2 ] = { { 4, 1 }, { 6, 2 }, { 9, 3 }, + { 10, 4 }, + { 11, 5 }, { 255, 255 } }; /* Configurations of PWM channels for CCU4 type */ XMC_PWM4_t mapping_pwm4[] = { - {CCU40, CCU40_CC40, 0, mapping_port_pin[3], P0_0_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P0.0 - {CCU40, CCU40_CC41, 1, mapping_port_pin[4], P0_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 P0.1 - {CCU40, CCU40_CC43, 3, mapping_port_pin[6], P0_3_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P0.3 - {CCU40, CCU40_CC42, 2, mapping_port_pin[9], P0_8_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 9 P0.8 + {CCU40, CCU40_CC40, 0, mapping_port_pin[3], P0_0_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P0.0 + {CCU40, CCU40_CC41, 1, mapping_port_pin[4], P0_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 P0.1 + {CCU40, CCU40_CC43, 3, mapping_port_pin[6], P0_3_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P0.3 + {CCU40, CCU40_CC42, 2, mapping_port_pin[9], P0_8_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 9 P0.8 + {CCU40, CCU40_CC43, 3, mapping_port_pin[10], P0_9_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 10 P0.9 + {CCU40, CCU40_CC41, 1, mapping_port_pin[11], P1_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 11 P1.1 }; const uint8_t NUM_PWM = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); const uint8_t NUM_PWM4 = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); diff --git a/variants/XMC1100/config/XMC1100_H_BRIDGE2GO/pins_arduino.h b/variants/XMC1100/config/XMC1100_H_BRIDGE2GO/pins_arduino.h index 3b73f043..54293386 100644 --- a/variants/XMC1100/config/XMC1100_H_BRIDGE2GO/pins_arduino.h +++ b/variants/XMC1100/config/XMC1100_H_BRIDGE2GO/pins_arduino.h @@ -68,7 +68,8 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define SERIAL_DEBUG 1 #endif -#define PWM4_TIMER_PERIOD (2041U) // Generate 490Hz @fCCU=64MHz +// Generate 490Hz @fCCU=64MHz +#define PWM4_TIMER_PERIOD (2041U) #define PCLK 64000000u @@ -85,9 +86,9 @@ extern uint8_t SCK; #define A0 0 #define A1 1 -#define LED1 14 // Extended LEDs -#define LED2 15 // Extended LEDs -#define LED_BUILTIN LED1 //Standard Arduino LED: Used LED1 +#define LED1 14 +#define LED2 15 +#define LED_BUILTIN LED1 // H-BRIDGE2Go specific Pins #define SO PIN_SPI_MISO @@ -96,8 +97,8 @@ extern uint8_t SCK; // Following for DOCUMENTATION only //#define CSN PIN_SPI_SS -//#define DIR 6 -//#define DIS 10 +//#define DIR 6 +//#define DIS 10 //#define PWM 11 #define digitalPinToInterrupt(p) (((p) == 9) ? 0 : NOT_AN_INTERRUPT) diff --git a/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h b/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h index e8d40912..ade4a129 100644 --- a/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h +++ b/variants/XMC1100/config/XMC1100_XMC2GO/pins_arduino.h @@ -68,7 +68,8 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define SERIAL_DEBUG 1 #endif -#define PWM4_TIMER_PERIOD (2041U) // Generate 490Hz @fCCU=1MHz +// Generate 490Hz @fCCU=1MHz +#define PWM4_TIMER_PERIOD (2041U) #define PCLK 64000000u @@ -87,9 +88,9 @@ extern uint8_t SCK; #define A2 2 #define A3 3 -#define LED1 14 // Extended LEDs -#define LED2 15 // Extended LEDs -#define LED_BUILTIN LED1 //Standard Arduino LED: Used LED1 +#define LED1 14 +#define LED2 15 +#define LED_BUILTIN LED1 #define digitalPinToInterrupt(p) (((p) == 9) ? 0 : NOT_AN_INTERRUPT) diff --git a/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h b/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h index 81af9a75..8a866af5 100644 --- a/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h +++ b/variants/XMC1300/config/XMC1300_Boot_Kit/pins_arduino.h @@ -69,8 +69,10 @@ extern const uint8_t NUM_ANALOG_INPUTS; #define SERIAL_DEBUG 1 #endif -#define PWM4_TIMER_PERIOD (2041U) // Generate 490Hz @fCCU=1MHz -#define PWM8_TIMER_PERIOD (2041U) // Generate 490Hz @fCCU=1MHz +// Generate 490Hz @fCCU=1MHz +#define PWM4_TIMER_PERIOD (2041U) +// Generate 490Hz @fCCU=1MHz +#define PWM8_TIMER_PERIOD (2041U) #define PCLK 64000000u @@ -99,21 +101,21 @@ extern uint8_t SCK; #define PIN_SPI_SS_2 23 -#define AD_AUX_1 24 // AD_AUX -#define AD_AUX_2 25 // AD_AUX -#define AUX_1 26 // AUX -#define AUX_2 27 // AUX -#define AUX_3 28 // AUX -#define AUX_4 29 // AUX -#define AUX_5 30 // AUX - -#define LED1 24 // Extended LEDs P0.0 -#define LED2 25 // Extended LEDs P0.1 -#define LED3 29 // Extended LEDs P0.6 -#define LED4 30 // Extended LEDs P0.7 -#define LED5 27 // Extended LEDs P0.8 -#define LED6 28 // Extended LEDs P0.9 -#define LED_BUILTIN LED1 // Standard Arduino LED +#define AD_AUX_1 24 +#define AD_AUX_2 25 +#define AUX_1 26 +#define AUX_2 27 +#define AUX_3 28 +#define AUX_4 29 +#define AUX_5 30 + +#define LED1 24 +#define LED2 25 +#define LED3 29 +#define LED4 30 +#define LED5 27 +#define LED6 28 +#define LED_BUILTIN LED1 #define digitalPinToInterrupt(p) ((p) == 14 ? 0 : ((p) == 15 ? 1 : NOT_AN_INTERRUPT)) diff --git a/variants/XMC1300/config/XMC1300_Sense2GoL/pins_arduino.h b/variants/XMC1300/config/XMC1300_Sense2GoL/pins_arduino.h index b271fd30..10d8e980 100644 --- a/variants/XMC1300/config/XMC1300_Sense2GoL/pins_arduino.h +++ b/variants/XMC1300/config/XMC1300_Sense2GoL/pins_arduino.h @@ -58,7 +58,8 @@ extern const uint8_t NUM_ANALOG_INPUTS; // Indicate unit has RTC/Alarm #define HAS_RTC 1 -#define PWM4_TIMER_PERIOD (2041U) // Generate 490Hz @fCCU=1MHz +// Generate 490Hz @fCCU=1MHz +#define PWM4_TIMER_PERIOD (2041U) #define PCLK 64000000u @@ -76,10 +77,10 @@ extern uint8_t SCK; // Actual on board signal is TX_ON #define BGT_ON 2 -#define LED1 3 // Extended LEDs P0.5 D5 -#define LED2 5 // Extended LEDs P0.7 D4 -#define LED3 7 // Extended LEDs P0.9 D3 -#define LED_BUILTIN LED1 // Standard Arduino LED +#define LED1 3 +#define LED2 5 +#define LED3 7 +#define LED_BUILTIN LED1 // Disable external interrupt pins #define digitalPinToInterrupt(p) NOT_AN_INTERRUPT diff --git a/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h b/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h new file mode 100644 index 00000000..538d7721 --- /dev/null +++ b/variants/XMC1400/config/XMC1400_Arduino_Kit/pins_arduino.h @@ -0,0 +1,300 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA +*/ +#ifndef PINS_ARDUINO_H_ +#define PINS_ARDUINO_H_ + +//**************************************************************************** +// @Project Includes +//**************************************************************************** +#include + +//**************************************************************************** +// @Defines +//**************************************************************************** +// XMC_BOARD for stringifying into serial or other text outputs/logs +// Note the actual name XMC and number MUST have a character between +// to avoid issues with other defined macros e.g. XMC1400 +#define XMC_BOARD XMC 1400 Kit for Arduino + +/* On board LED is ON when digital output is 0, LOW, FALSE, OFF */ +#define XMC_LED_ON 0 + +// Following were defines now evaluated by compilation as const variables +// After definitions of associated mapping arrays +extern const uint8_t NUM_DIGITAL; +extern const uint8_t GND; +extern const uint8_t NUM_PWM4; +extern const uint8_t NUM_PWM; +extern const uint8_t NUM_INTERRUPT; +extern const uint8_t NUM_ANALOG_INPUTS; +#define NUM_LEDS 3 +#define NUM_SERIAL 1 +#define NUM_TONE_PINS 4 +#define NUM_TASKS_VARIANT 8 + +// Indicate unit has RTC/Alarm +#define HAS_RTC 1 + +// Indicate variant has a GPIO pin used for Reset pin +#define HAS_GPIO_RESET 1 + +// Defines will be either set by ArduinoIDE in the menu or manually +#ifdef SERIAL_HOSTPC +// Comment out following line to use Serial on pins (board) +#define SERIAL_DEBUG 1 +#elif SERIAL_ONBOARD +// No SERIAL_DEBUG will be defined, kept here for clarity +#else +// Define the SERIAL_DEBUG as default setting +#define SERIAL_DEBUG 1 +#endif + +#define PWM4_TIMER_PERIOD (2041U) // Generate 490Hz @fCCU=1MHz + +#define PCLK 96000000u //PCLK can go to this max value + +#define PIN_SPI_SS 10 +#define PIN_SPI_MOSI 11 +#define PIN_SPI_MISO 12 +#define PIN_SPI_SCK 13 + +#define A0 0 +#define A1 1 +#define A2 2 +#define A3 3 +#define A4 4 +#define A5 5 +//duplicate defines for AD_AUX_n +#define A6 6 +#define A7 7 +#define A8 8 +#define A9 9 + + +#define AD_AUX_1 6 // AD_AUX +#define AD_AUX_2 7 // AD_AUX +#define AD_AUX_3 8 // AD_AUX +#define AD_AUX_4 9 // AD_AUX + +#define AUX_1 25 // AUX + +#define LED1 13 +#define LED2 2 +#define LED3 26 +#define LED_BUILTIN LED1 + +#define EXT_INTR_0 3 +#define EXT_INTR_1 25 + +#define digitalPinToInterrupt(p) ((p) == 3 ? 0 : ((p) == 25 ? 1 : NOT_AN_INTERRUPT)) + +/* Mapping interrupt handlers. Notice that XMC1400 can have interrupt handlers working in 3 modes, the defines below assumes the mode A. + For details refer to assembly file and reference manual. +*/ +#define USIC0_0_IRQHandler IRQ9_Handler // UART +#define USIC0_0_IRQn IRQ9_IRQn + +#define CCU40_0_IRQHandler IRQ21_Handler // interrupt 1 +#define CCU40_0_IRQn IRQ21_IRQn + +#define CCU40_1_IRQHandler IRQ22_Handler // interrupt 0 +#define CCU40_1_IRQn IRQ22_IRQn + +#define USIC0_4_IRQHandler IRQ13_Handler // I2C +#define USIC0_4_IRQn IRQ13_IRQn + +#define USIC0_5_IRQHandler IRQ14_Handler // I2C +#define USIC0_5_IRQn IRQ14_IRQn + +#define SCU_1_IRQHandler IRQ1_Handler //RTC +#define SCU_1_IRQn IRQ1_IRQn + +#define ERU0_0_IRQHandler IRQ3_Handler // RESET +#define ERU0_0_IRQn IRQ3_IRQn + +#ifdef ARDUINO_MAIN +//index is Arduino pin count +// Mapping of digital pins and comments +const XMC_PORT_PIN_t mapping_port_pin[] = + { + /* 0 */ {XMC_GPIO_PORT1, 2}, // RX P1.2 + /* 1 */ {XMC_GPIO_PORT1, 3}, // TX P1.3 + /* 2 */ {XMC_GPIO_PORT0 , 5}, // GPIO / LED2 output P0.5 + /* 3 */ {XMC_GPIO_PORT1 , 1}, // External int 0 / PWM40-1 output P1.1 + /* 4 */ {XMC_GPIO_PORT1 , 0}, // PWM40-0 output P1.0 + /* 5 */ {XMC_GPIO_PORT0 , 2}, // GPIO P0.2 + /* 6 */ {XMC_GPIO_PORT0 , 6}, // PWM41-0 output P0.6 + /* 7 */ {XMC_GPIO_PORT0 , 13}, // GPIO P0.13 + /* 8 */ {XMC_GPIO_PORT0 , 12}, // GPIO P0.12 + /* 9 */ {XMC_GPIO_PORT0 , 7}, // PWM40-1 output P0.7 + /* 10 */ {XMC_GPIO_PORT0 , 4}, // SPI-SS P0.4 + /* 11 */ {XMC_GPIO_PORT0 , 1}, // SPI-MOSI P0.1 + /* 12 */ {XMC_GPIO_PORT0 , 0}, // SPI-MISO P0.0 + /* 13 */ {XMC_GPIO_PORT0 , 3}, // SPI-SCK P0.3 + /* 14 */ {XMC_GPIO_PORT2 , 3}, // AREF * DO NOT USE as GPIO or REF ** P2.3 (INPUT ONLY) + /* 15 */ {XMC_GPIO_PORT2 , 6}, // A0 / ADC Input P2.6 (INPUT ONLY) + /* 16 */ {XMC_GPIO_PORT2 , 8}, // A1 / ADC Input P2.8 (INPUT ONLY) + /* 17 */ {XMC_GPIO_PORT2 , 9}, // A2 / ADC Input P2.9 (INPUT ONLY) + /* 18 */ {XMC_GPIO_PORT2 , 10}, // A3 / ADC Input P2.10 + /* 19 */ {XMC_GPIO_PORT2 , 1}, // A4 / I2C Data / Address SDA P2.1 + /* 20 */ {XMC_GPIO_PORT2 , 0}, // A5 / I2C Clock SCL P2.0 + /* 21 */ {XMC_GPIO_PORT2 , 11}, // GPIO / AD_AUX_1 Additional Pin P2.11 + /* 22 */ {XMC_GPIO_PORT2 , 7}, // GPIO / AD_AUX_2 Additional Pin P2.7 + /* 23 */ {XMC_GPIO_PORT2 , 5}, // GPIO / AD_AUX_3 Additional Pin P2.5 + /* 24 */ {XMC_GPIO_PORT2 , 2}, // GPIO / AD_AUX_4 Additional Pin P2.2 + /* 25 */ {XMC_GPIO_PORT1 , 4}, // External int 1 P1.4 + /* 26 */ {XMC_GPIO_PORT1 , 5} // LED3 output P1.5 + }; + + +const uint8_t GND = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); +const uint8_t NUM_DIGITAL = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) );; + +const XMC_PIN_INTERRUPT_t mapping_interrupt[] = + { + /* 0 */ {CCU40, CCU40_CC41, 1, 1, CCU40_IN1_U0C1_DX2INS}, + /* 1 */ {CCU40, CCU40_CC40, 0, 0, CCU40_IN0_U0C0_DX2INS} + }; +const uint8_t NUM_INTERRUPT = ( sizeof( mapping_interrupt ) / sizeof( XMC_PIN_INTERRUPT_t ) ); + +/* Mapping of Arduino Pins to PWM4 channels as pin and index in PWM4 channel + mapping array XMC_PWM4_t mapping_pwm4[] + last entry 255 for both parts. + Putting both parts in array means if a PWM4 channel gets reassigned for + another function later a gap in channel numbers will not mess things up */ +const uint8_t mapping_pin_PWM4[][ 2 ] = { + { 3, 0 }, + { 4, 1 }, + { 6, 2 }, + { 9, 3 }, + { 255, 255 } }; + +/* Configurations of PWM channels for CCU4 type */ +XMC_PWM4_t mapping_pwm4[] = + { + {CCU40, CCU40_CC41, 1, mapping_port_pin[3], P1_1_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + {CCU40, CCU40_CC40, 0, mapping_port_pin[4], P1_0_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + {CCU41, CCU41_CC40, 0, mapping_port_pin[6], P0_6_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 4 + {CCU40, CCU40_CC41, 1, mapping_port_pin[9], P0_7_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 4 + }; + +const uint8_t NUM_PWM4 = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); +const uint8_t NUM_PWM = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); + + +/* Analog Pin mappings and configurations */ +// ADC grouping for XMC 1400 series. +XMC_ADC_t mapping_adc[] = + { + { VADC, 0, VADC_G0, 0, 4, DISABLED }, //A0 + { VADC, 1, VADC_G0, 0, 11, DISABLED }, //A1 + { VADC, 2, VADC_G0, 0, 9, DISABLED }, //A2 + { VADC, 3, VADC_G0, 0, 12, DISABLED }, //A3 + { VADC, 6, VADC_G0, 0, 7, DISABLED }, //A4 + { VADC, 5, VADC_G0, 0, 10, DISABLED }, //A5 + // Additional channels added here + { VADC, 4, VADC_G0, 0, 5, DISABLED }, //AUX 21 + { VADC, 1, VADC_G1, 1, 1, DISABLED }, //AUX 22 + { VADC, 7, VADC_G1, 1, 2, DISABLED }, //AUX 23 + { VADC, 7, VADC_G0, 0, 3, DISABLED } //AUX 24 +}; + +const uint8_t NUM_ANALOG_INPUTS = ( sizeof( mapping_adc ) / sizeof( XMC_ADC_t ) ); + +/* + * UART objects + */ +RingBuffer rx_buffer_0; +RingBuffer tx_buffer_0; + +/* First UART channel pins are swapped between debug and normal use */ +XMC_UART_t XMC_UART_0 = + { + .channel = XMC_UART0_CH1, + .rx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, +#ifdef SERIAL_DEBUG + .pin = (uint8_t)3 +#else + .pin = (uint8_t)2 +#endif + }, + .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + }, + .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, +#ifdef SERIAL_DEBUG + .pin = (uint8_t)2 +#else + .pin = (uint8_t)3 +#endif + }, + .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT7, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .input_hysteresis = XMC_GPIO_INPUT_HYSTERESIS_STANDARD + }, +#ifdef SERIAL_DEBUG + .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C1_DX0_P1_3, +#else + .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C1_DX0_P1_2, +#endif + .input_source_dx1 = XMC_INPUT_INVALID, + .input_source_dx2 = XMC_INPUT_INVALID, + .input_source_dx3 = XMC_INPUT_INVALID, + .irq_num = USIC0_0_IRQn, + .irq_service_request = 0 + }; + +HardwareSerial Serial( &XMC_UART_0, &rx_buffer_0, &tx_buffer_0 ); + +// Serial Interrupt and event handling +#ifdef __cplusplus +extern "C" { +#endif +void serialEventRun( ); +void serialEvent( ) __attribute__((weak)); + + +void serialEventRun( ) +{ +if( serialEvent ) + { + if( Serial.available( ) ) + serialEvent( ); + } +} + + +void USIC0_0_IRQHandler( ) +{ +Serial.IrqHandler( ); +} +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_MAIN */ + +#ifdef __cplusplus +extern HardwareSerial Serial; +#endif /* cplusplus */ + +#endif // PINS_ARDUINO_H_ diff --git a/variants/XMC4200/XMC4200.h b/variants/XMC4200/XMC4200.h new file mode 100644 index 00000000..427a7ce7 --- /dev/null +++ b/variants/XMC4200/XMC4200.h @@ -0,0 +1,13238 @@ +/********************************************************************************************************************* + * Copyright (c) 2011-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + *********************************************************************************************************************/ + + +/****************************************************************************************************//** + * @file XMC4200.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * XMC4200 from Infineon. + * + * @version V1.6.2 (Reference Manual v1.6) + * @date 01. Sep 2020 + * + * @note Generated with SVDConv V2.87l + * from CMSIS SVD File 'XMC4200_Processed_SVD.xml' Version 1.6.0 (Reference Manual v1.6), + * added support for ARM Compiler 6 (armclang) + *******************************************************************************************************/ + + + +/** @addtogroup Infineon + * @{ + */ + +/** @addtogroup XMC4200 + * @{ + */ + +#ifndef XMC4200_H +#define XMC4200_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- XMC4200 Specific Interrupt Numbers --------------------- */ + SCU_0_IRQn = 0, /*!< 0 System Control */ + ERU0_0_IRQn = 1, /*!< 1 External Request Unit 0 */ + ERU0_1_IRQn = 2, /*!< 2 External Request Unit 0 */ + ERU0_2_IRQn = 3, /*!< 3 External Request Unit 0 */ + ERU0_3_IRQn = 4, /*!< 4 External Request Unit 0 */ + ERU1_0_IRQn = 5, /*!< 5 External Request Unit 1 */ + ERU1_1_IRQn = 6, /*!< 6 External Request Unit 1 */ + ERU1_2_IRQn = 7, /*!< 7 External Request Unit 1 */ + ERU1_3_IRQn = 8, /*!< 8 External Request Unit 1 */ + PMU0_0_IRQn = 12, /*!< 12 Program Management Unit */ + VADC0_C0_0_IRQn = 14, /*!< 14 Analog to Digital Converter Common Block 0 */ + VADC0_C0_1_IRQn = 15, /*!< 15 Analog to Digital Converter Common Block 0 */ + VADC0_C0_2_IRQn = 16, /*!< 16 Analog to Digital Converter Common Block 0 */ + VADC0_C0_3_IRQn = 17, /*!< 17 Analog to Digital Converter Common Block 0 */ + VADC0_G0_0_IRQn = 18, /*!< 18 Analog to Digital Converter Group 0 */ + VADC0_G0_1_IRQn = 19, /*!< 19 Analog to Digital Converter Group 0 */ + VADC0_G0_2_IRQn = 20, /*!< 20 Analog to Digital Converter Group 0 */ + VADC0_G0_3_IRQn = 21, /*!< 21 Analog to Digital Converter Group 0 */ + VADC0_G1_0_IRQn = 22, /*!< 22 Analog to Digital Converter Group 1 */ + VADC0_G1_1_IRQn = 23, /*!< 23 Analog to Digital Converter Group 1 */ + VADC0_G1_2_IRQn = 24, /*!< 24 Analog to Digital Converter Group 1 */ + VADC0_G1_3_IRQn = 25, /*!< 25 Analog to Digital Converter Group 1 */ + DAC0_0_IRQn = 42, /*!< 42 Digital to Analog Converter */ + DAC0_1_IRQn = 43, /*!< 43 Digital to Analog Converter */ + CCU40_0_IRQn = 44, /*!< 44 Capture Compare Unit 4 (Module 0) */ + CCU40_1_IRQn = 45, /*!< 45 Capture Compare Unit 4 (Module 0) */ + CCU40_2_IRQn = 46, /*!< 46 Capture Compare Unit 4 (Module 0) */ + CCU40_3_IRQn = 47, /*!< 47 Capture Compare Unit 4 (Module 0) */ + CCU41_0_IRQn = 48, /*!< 48 Capture Compare Unit 4 (Module 1) */ + CCU41_1_IRQn = 49, /*!< 49 Capture Compare Unit 4 (Module 1) */ + CCU41_2_IRQn = 50, /*!< 50 Capture Compare Unit 4 (Module 1) */ + CCU41_3_IRQn = 51, /*!< 51 Capture Compare Unit 4 (Module 1) */ + CCU80_0_IRQn = 60, /*!< 60 Capture Compare Unit 8 (Module 0) */ + CCU80_1_IRQn = 61, /*!< 61 Capture Compare Unit 8 (Module 0) */ + CCU80_2_IRQn = 62, /*!< 62 Capture Compare Unit 8 (Module 0) */ + CCU80_3_IRQn = 63, /*!< 63 Capture Compare Unit 8 (Module 0) */ + POSIF0_0_IRQn = 68, /*!< 68 Position Interface (Module 0) */ + POSIF0_1_IRQn = 69, /*!< 69 Position Interface (Module 0) */ + HRPWM_0_IRQn = 72, /*!< 72 High Resolution Pulse Width Modulation (Module 0) */ + HRPWM_1_IRQn = 73, /*!< 73 High Resolution Pulse Width Modulation (Module 0) */ + HRPWM_2_IRQn = 74, /*!< 74 High Resolution Pulse Width Modulation (Module 0) */ + HRPWM_3_IRQn = 75, /*!< 75 High Resolution Pulse Width Modulation (Module 0) */ + CAN0_0_IRQn = 76, /*!< 76 MultiCAN */ + CAN0_1_IRQn = 77, /*!< 77 MultiCAN */ + CAN0_2_IRQn = 78, /*!< 78 MultiCAN */ + CAN0_3_IRQn = 79, /*!< 79 MultiCAN */ + CAN0_4_IRQn = 80, /*!< 80 MultiCAN */ + CAN0_5_IRQn = 81, /*!< 81 MultiCAN */ + CAN0_6_IRQn = 82, /*!< 82 MultiCAN */ + CAN0_7_IRQn = 83, /*!< 83 MultiCAN */ + USIC0_0_IRQn = 84, /*!< 84 Universal Serial Interface Channel (Module 0) */ + USIC0_1_IRQn = 85, /*!< 85 Universal Serial Interface Channel (Module 0) */ + USIC0_2_IRQn = 86, /*!< 86 Universal Serial Interface Channel (Module 0) */ + USIC0_3_IRQn = 87, /*!< 87 Universal Serial Interface Channel (Module 0) */ + USIC0_4_IRQn = 88, /*!< 88 Universal Serial Interface Channel (Module 0) */ + USIC0_5_IRQn = 89, /*!< 89 Universal Serial Interface Channel (Module 0) */ + USIC1_0_IRQn = 90, /*!< 90 Universal Serial Interface Channel (Module 1) */ + USIC1_1_IRQn = 91, /*!< 91 Universal Serial Interface Channel (Module 1) */ + USIC1_2_IRQn = 92, /*!< 92 Universal Serial Interface Channel (Module 1) */ + USIC1_3_IRQn = 93, /*!< 93 Universal Serial Interface Channel (Module 1) */ + USIC1_4_IRQn = 94, /*!< 94 Universal Serial Interface Channel (Module 1) */ + USIC1_5_IRQn = 95, /*!< 95 Universal Serial Interface Channel (Module 1) */ + LEDTS0_0_IRQn = 102, /*!< 102 LED and Touch Sense Control Unit (Module 0) */ + FCE0_0_IRQn = 104, /*!< 104 Flexible CRC Engine */ + GPDMA0_0_IRQn = 105, /*!< 105 General Purpose DMA Unit 0 */ + USB0_0_IRQn = 107 /*!< 107 Universal Serial Bus (Module 0) */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4200.h" /*!< XMC4200 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1<= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ PPB ================ */ +/* ================================================================================ */ + + +/** + * @brief Cortex-M4 Private Peripheral Block (PPB) + */ + +typedef struct { /*!< (@ 0xE000E000) PPB Structure */ + __I uint32_t RESERVED[2]; + __IO uint32_t ACTLR; /*!< (@ 0xE000E008) Auxiliary Control Register */ + __I uint32_t RESERVED1; + __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */ + __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */ + __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */ + __IO uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register r */ + __I uint32_t RESERVED2[56]; + __IO uint32_t NVIC_ISER0; /*!< (@ 0xE000E100) Interrupt Set-enable Register 0 */ + __IO uint32_t NVIC_ISER1; /*!< (@ 0xE000E104) Interrupt Set-enable Register 1 */ + __IO uint32_t NVIC_ISER2; /*!< (@ 0xE000E108) Interrupt Set-enable Register 2 */ + __IO uint32_t NVIC_ISER3; /*!< (@ 0xE000E10C) Interrupt Set-enable Register 3 */ + __I uint32_t RESERVED3[28]; + __IO uint32_t NVIC_ICER0; /*!< (@ 0xE000E180) Interrupt Clear-enable Register 0 */ + __IO uint32_t NVIC_ICER1; /*!< (@ 0xE000E184) Interrupt Clear-enable Register 1 */ + __IO uint32_t NVIC_ICER2; /*!< (@ 0xE000E188) Interrupt Clear-enable Register 2 */ + __IO uint32_t NVIC_ICER3; /*!< (@ 0xE000E18C) Interrupt Clear-enable Register 3 */ + __I uint32_t RESERVED4[28]; + __IO uint32_t NVIC_ISPR0; /*!< (@ 0xE000E200) Interrupt Set-pending Register 0 */ + __IO uint32_t NVIC_ISPR1; /*!< (@ 0xE000E204) Interrupt Set-pending Register 1 */ + __IO uint32_t NVIC_ISPR2; /*!< (@ 0xE000E208) Interrupt Set-pending Register 2 */ + __IO uint32_t NVIC_ISPR3; /*!< (@ 0xE000E20C) Interrupt Set-pending Register 3 */ + __I uint32_t RESERVED5[28]; + __IO uint32_t NVIC_ICPR0; /*!< (@ 0xE000E280) Interrupt Clear-pending Register 0 */ + __IO uint32_t NVIC_ICPR1; /*!< (@ 0xE000E284) Interrupt Clear-pending Register 1 */ + __IO uint32_t NVIC_ICPR2; /*!< (@ 0xE000E288) Interrupt Clear-pending Register 2 */ + __IO uint32_t NVIC_ICPR3; /*!< (@ 0xE000E28C) Interrupt Clear-pending Register 3 */ + __I uint32_t RESERVED6[28]; + __IO uint32_t NVIC_IABR0; /*!< (@ 0xE000E300) Interrupt Active Bit Register 0 */ + __IO uint32_t NVIC_IABR1; /*!< (@ 0xE000E304) Interrupt Active Bit Register 1 */ + __IO uint32_t NVIC_IABR2; /*!< (@ 0xE000E308) Interrupt Active Bit Register 2 */ + __IO uint32_t NVIC_IABR3; /*!< (@ 0xE000E30C) Interrupt Active Bit Register 3 */ + __I uint32_t RESERVED7[60]; + __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */ + __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */ + __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */ + __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */ + __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */ + __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */ + __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */ + __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */ + __IO uint32_t NVIC_IPR8; /*!< (@ 0xE000E420) Interrupt Priority Register 8 */ + __IO uint32_t NVIC_IPR9; /*!< (@ 0xE000E424) Interrupt Priority Register 9 */ + __IO uint32_t NVIC_IPR10; /*!< (@ 0xE000E428) Interrupt Priority Register 10 */ + __IO uint32_t NVIC_IPR11; /*!< (@ 0xE000E42C) Interrupt Priority Register 11 */ + __IO uint32_t NVIC_IPR12; /*!< (@ 0xE000E430) Interrupt Priority Register 12 */ + __IO uint32_t NVIC_IPR13; /*!< (@ 0xE000E434) Interrupt Priority Register 13 */ + __IO uint32_t NVIC_IPR14; /*!< (@ 0xE000E438) Interrupt Priority Register 14 */ + __IO uint32_t NVIC_IPR15; /*!< (@ 0xE000E43C) Interrupt Priority Register 15 */ + __IO uint32_t NVIC_IPR16; /*!< (@ 0xE000E440) Interrupt Priority Register 16 */ + __IO uint32_t NVIC_IPR17; /*!< (@ 0xE000E444) Interrupt Priority Register 17 */ + __IO uint32_t NVIC_IPR18; /*!< (@ 0xE000E448) Interrupt Priority Register 18 */ + __IO uint32_t NVIC_IPR19; /*!< (@ 0xE000E44C) Interrupt Priority Register 19 */ + __IO uint32_t NVIC_IPR20; /*!< (@ 0xE000E450) Interrupt Priority Register 20 */ + __IO uint32_t NVIC_IPR21; /*!< (@ 0xE000E454) Interrupt Priority Register 21 */ + __IO uint32_t NVIC_IPR22; /*!< (@ 0xE000E458) Interrupt Priority Register 22 */ + __IO uint32_t NVIC_IPR23; /*!< (@ 0xE000E45C) Interrupt Priority Register 23 */ + __IO uint32_t NVIC_IPR24; /*!< (@ 0xE000E460) Interrupt Priority Register 24 */ + __IO uint32_t NVIC_IPR25; /*!< (@ 0xE000E464) Interrupt Priority Register 25 */ + __IO uint32_t NVIC_IPR26; /*!< (@ 0xE000E468) Interrupt Priority Register 26 */ + __IO uint32_t NVIC_IPR27; /*!< (@ 0xE000E46C) Interrupt Priority Register 27 */ + __I uint32_t RESERVED8[548]; + __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */ + __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< (@ 0xE000ED08) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */ + __IO uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */ + __IO uint32_t SHPR1; /*!< (@ 0xE000ED18) System Handler Priority Register 1 */ + __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */ + __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */ + __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< (@ 0xE000ED28) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< (@ 0xE000ED2C) HardFault Status Register */ + __I uint32_t RESERVED9; + __IO uint32_t MMFAR; /*!< (@ 0xE000ED34) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< (@ 0xE000ED38) BusFault Address Register */ + __IO uint32_t AFSR; /*!< (@ 0xE000ED3C) Auxiliary Fault Status Register */ + __I uint32_t RESERVED10[18]; + __IO uint32_t CPACR; /*!< (@ 0xE000ED88) Coprocessor Access Control Register */ + __I uint32_t RESERVED11; + __I uint32_t MPU_TYPE; /*!< (@ 0xE000ED90) MPU Type Register */ + __IO uint32_t MPU_CTRL; /*!< (@ 0xE000ED94) MPU Control Register */ + __IO uint32_t MPU_RNR; /*!< (@ 0xE000ED98) MPU Region Number Register */ + __IO uint32_t MPU_RBAR; /*!< (@ 0xE000ED9C) MPU Region Base Address Register */ + __IO uint32_t MPU_RASR; /*!< (@ 0xE000EDA0) MPU Region Attribute and Size Register */ + __IO uint32_t MPU_RBAR_A1; /*!< (@ 0xE000EDA4) MPU Region Base Address Register A1 */ + __IO uint32_t MPU_RASR_A1; /*!< (@ 0xE000EDA8) MPU Region Attribute and Size Register A1 */ + __IO uint32_t MPU_RBAR_A2; /*!< (@ 0xE000EDAC) MPU Region Base Address Register A2 */ + __IO uint32_t MPU_RASR_A2; /*!< (@ 0xE000EDB0) MPU Region Attribute and Size Register A2 */ + __IO uint32_t MPU_RBAR_A3; /*!< (@ 0xE000EDB4) MPU Region Base Address Register A3 */ + __IO uint32_t MPU_RASR_A3; /*!< (@ 0xE000EDB8) MPU Region Attribute and Size Register A3 */ + __I uint32_t RESERVED12[81]; + __O uint32_t STIR; /*!< (@ 0xE000EF00) Software Trigger Interrupt Register */ + __I uint32_t RESERVED13[12]; + __IO uint32_t FPCCR; /*!< (@ 0xE000EF34) Floating-point Context Control Register */ + __IO uint32_t FPCAR; /*!< (@ 0xE000EF38) Floating-point Context Address Register */ + __IO uint32_t FPDSCR; /*!< (@ 0xE000EF3C) Floating-point Default Status Control Register */ +} PPB_Type; + + +/* ================================================================================ */ +/* ================ DLR ================ */ +/* ================================================================================ */ + + +/** + * @brief DMA Line Router (DLR) + */ + +typedef struct { /*!< (@ 0x50004900) DLR Structure */ + __I uint32_t OVRSTAT; /*!< (@ 0x50004900) Overrun Status */ + __O uint32_t OVRCLR; /*!< (@ 0x50004904) Overrun Clear */ + __IO uint32_t SRSEL0; /*!< (@ 0x50004908) Service Request Selection 0 */ + __I uint32_t RESERVED; + __IO uint32_t LNEN; /*!< (@ 0x50004910) Line Enable */ +} DLR_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ ERU [ERU0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Event Request Unit 0 (ERU) + */ + +typedef struct { /*!< (@ 0x50004800) ERU Structure */ + __IO uint32_t EXISEL; /*!< (@ 0x50004800) Event Input Select */ + __I uint32_t RESERVED[3]; + __IO uint32_t EXICON[4]; /*!< (@ 0x50004810) Event Input Control */ + __IO uint32_t EXOCON[4]; /*!< (@ 0x50004820) Event Output Trigger Control */ +} ERU_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ GPDMA0 ================ */ +/* ================================================================================ */ + + +/** + * @brief General Purpose DMA Unit 0 (GPDMA0) + */ + +typedef struct { /*!< (@ 0x500142C0) GPDMA0 Structure */ + __IO uint32_t RAWTFR; /*!< (@ 0x500142C0) Raw IntTfr Status */ + __I uint32_t RESERVED; + __IO uint32_t RAWBLOCK; /*!< (@ 0x500142C8) Raw IntBlock Status */ + __I uint32_t RESERVED1; + __IO uint32_t RAWSRCTRAN; /*!< (@ 0x500142D0) Raw IntSrcTran Status */ + __I uint32_t RESERVED2; + __IO uint32_t RAWDSTTRAN; /*!< (@ 0x500142D8) Raw IntBlock Status */ + __I uint32_t RESERVED3; + __IO uint32_t RAWERR; /*!< (@ 0x500142E0) Raw IntErr Status */ + __I uint32_t RESERVED4; + __I uint32_t STATUSTFR; /*!< (@ 0x500142E8) IntTfr Status */ + __I uint32_t RESERVED5; + __I uint32_t STATUSBLOCK; /*!< (@ 0x500142F0) IntBlock Status */ + __I uint32_t RESERVED6; + __I uint32_t STATUSSRCTRAN; /*!< (@ 0x500142F8) IntSrcTran Status */ + __I uint32_t RESERVED7; + __I uint32_t STATUSDSTTRAN; /*!< (@ 0x50014300) IntBlock Status */ + __I uint32_t RESERVED8; + __I uint32_t STATUSERR; /*!< (@ 0x50014308) IntErr Status */ + __I uint32_t RESERVED9; + __IO uint32_t MASKTFR; /*!< (@ 0x50014310) Mask for Raw IntTfr Status */ + __I uint32_t RESERVED10; + __IO uint32_t MASKBLOCK; /*!< (@ 0x50014318) Mask for Raw IntBlock Status */ + __I uint32_t RESERVED11; + __IO uint32_t MASKSRCTRAN; /*!< (@ 0x50014320) Mask for Raw IntSrcTran Status */ + __I uint32_t RESERVED12; + __IO uint32_t MASKDSTTRAN; /*!< (@ 0x50014328) Mask for Raw IntBlock Status */ + __I uint32_t RESERVED13; + __IO uint32_t MASKERR; /*!< (@ 0x50014330) Mask for Raw IntErr Status */ + __I uint32_t RESERVED14; + __O uint32_t CLEARTFR; /*!< (@ 0x50014338) IntTfr Status */ + __I uint32_t RESERVED15; + __O uint32_t CLEARBLOCK; /*!< (@ 0x50014340) IntBlock Status */ + __I uint32_t RESERVED16; + __O uint32_t CLEARSRCTRAN; /*!< (@ 0x50014348) IntSrcTran Status */ + __I uint32_t RESERVED17; + __O uint32_t CLEARDSTTRAN; /*!< (@ 0x50014350) IntBlock Status */ + __I uint32_t RESERVED18; + __O uint32_t CLEARERR; /*!< (@ 0x50014358) IntErr Status */ + __I uint32_t RESERVED19; + __I uint32_t STATUSINT; /*!< (@ 0x50014360) Combined Interrupt Status Register */ + __I uint32_t RESERVED20; + __IO uint32_t REQSRCREG; /*!< (@ 0x50014368) Source Software Transaction Request Register */ + __I uint32_t RESERVED21; + __IO uint32_t REQDSTREG; /*!< (@ 0x50014370) Destination Software Transaction Request Register */ + __I uint32_t RESERVED22; + __IO uint32_t SGLREQSRCREG; /*!< (@ 0x50014378) Single Source Transaction Request Register */ + __I uint32_t RESERVED23; + __IO uint32_t SGLREQDSTREG; /*!< (@ 0x50014380) Single Destination Transaction Request Register */ + __I uint32_t RESERVED24; + __IO uint32_t LSTSRCREG; /*!< (@ 0x50014388) Last Source Transaction Request Register */ + __I uint32_t RESERVED25; + __IO uint32_t LSTDSTREG; /*!< (@ 0x50014390) Last Destination Transaction Request Register */ + __I uint32_t RESERVED26; + __IO uint32_t DMACFGREG; /*!< (@ 0x50014398) GPDMA Configuration Register */ + __I uint32_t RESERVED27; + __IO uint32_t CHENREG; /*!< (@ 0x500143A0) GPDMA Channel Enable Register */ + __I uint32_t RESERVED28; + __I uint32_t ID; /*!< (@ 0x500143A8) GPDMA0 ID Register */ + __I uint32_t RESERVED29[19]; + __I uint32_t TYPE; /*!< (@ 0x500143F8) GPDMA Component Type */ + __I uint32_t VERSION; /*!< (@ 0x500143FC) DMA Component Version */ +} GPDMA0_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ GPDMA0_CH0_1 [GPDMA0_CH0] ================ */ +/* ================================================================================ */ + + +/** + * @brief General Purpose DMA Unit 0 (GPDMA0_CH0_1) + */ + +typedef struct { /*!< (@ 0x50014000) GPDMA0_CH0_1 Structure */ + __IO uint32_t SAR; /*!< (@ 0x50014000) Source Address Register */ + __I uint32_t RESERVED; + __IO uint32_t DAR; /*!< (@ 0x50014008) Destination Address Register */ + __I uint32_t RESERVED1; + __IO uint32_t LLP; /*!< (@ 0x50014010) Linked List Pointer Register */ + __I uint32_t RESERVED2; + __IO uint32_t CTLL; /*!< (@ 0x50014018) Control Register Low */ + __IO uint32_t CTLH; /*!< (@ 0x5001401C) Control Register High */ + __IO uint32_t SSTAT; /*!< (@ 0x50014020) Source Status Register */ + __I uint32_t RESERVED3; + __IO uint32_t DSTAT; /*!< (@ 0x50014028) Destination Status Register */ + __I uint32_t RESERVED4; + __IO uint32_t SSTATAR; /*!< (@ 0x50014030) Source Status Address Register */ + __I uint32_t RESERVED5; + __IO uint32_t DSTATAR; /*!< (@ 0x50014038) Destination Status Address Register */ + __I uint32_t RESERVED6; + __IO uint32_t CFGL; /*!< (@ 0x50014040) Configuration Register Low */ + __IO uint32_t CFGH; /*!< (@ 0x50014044) Configuration Register High */ + __IO uint32_t SGR; /*!< (@ 0x50014048) Source Gather Register */ + __I uint32_t RESERVED7; + __IO uint32_t DSR; /*!< (@ 0x50014050) Destination Scatter Register */ +} GPDMA0_CH_TypeDef; + + +/* ================================================================================ */ +/* ================ GPDMA0_CH2_7 [GPDMA0_CH2] ================ */ +/* ================================================================================ */ + + +/** + * @brief General Purpose DMA Unit 0 (GPDMA0_CH2_7) + */ + +typedef struct { /*!< (@ 0x500140B0) GPDMA0_CH2_7 Structure */ + __IO uint32_t SAR; /*!< (@ 0x500140B0) Source Address Register */ + __I uint32_t RESERVED; + __IO uint32_t DAR; /*!< (@ 0x500140B8) Destination Address Register */ + __I uint32_t RESERVED1[3]; + __IO uint32_t CTLL; /*!< (@ 0x500140C8) Control Register Low */ + __IO uint32_t CTLH; /*!< (@ 0x500140CC) Control Register High */ + __I uint32_t RESERVED2[8]; + __IO uint32_t CFGL; /*!< (@ 0x500140F0) Configuration Register Low */ + __IO uint32_t CFGH; /*!< (@ 0x500140F4) Configuration Register High */ +} GPDMA0_CH2_7_Type; + + +/* ================================================================================ */ +/* ================ FCE ================ */ +/* ================================================================================ */ + + +/** + * @brief Flexible CRC Engine (FCE) + */ + +typedef struct { /*!< (@ 0x50020000) FCE Structure */ + __IO uint32_t CLC; /*!< (@ 0x50020000) Clock Control Register */ + __I uint32_t RESERVED; + __I uint32_t ID; /*!< (@ 0x50020008) Module Identification Register */ +} FCE_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ FCE_KE [FCE_KE0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Flexible CRC Engine (FCE_KE) + */ + +typedef struct { /*!< (@ 0x50020020) FCE_KE Structure */ + __IO uint32_t IR; /*!< (@ 0x50020020) Input Register */ + __I uint32_t RES; /*!< (@ 0x50020024) CRC Result Register */ + __IO uint32_t CFG; /*!< (@ 0x50020028) CRC Configuration Register */ + __IO uint32_t STS; /*!< (@ 0x5002002C) CRC Status Register */ + __IO uint32_t LENGTH; /*!< (@ 0x50020030) CRC Length Register */ + __IO uint32_t CHECK; /*!< (@ 0x50020034) CRC Check Register */ + __IO uint32_t CRC; /*!< (@ 0x50020038) CRC Register */ + __IO uint32_t CTR; /*!< (@ 0x5002003C) CRC Test Register */ +} FCE_KE_TypeDef; + + +/* ================================================================================ */ +/* ================ PBA [PBA0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Peripheral Bridge AHB 0 (PBA) + */ + +typedef struct { /*!< (@ 0x40000000) PBA Structure */ + __IO uint32_t STS; /*!< (@ 0x40000000) Peripheral Bridge Status Register */ + __I uint32_t WADDR; /*!< (@ 0x40000004) PBA Write Error Address Register */ +} PBA_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ FLASH [FLASH0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Flash Memory Controller (FLASH) + */ + +typedef struct { /*!< (@ 0x58001000) FLASH Structure */ + __I uint32_t RESERVED[1026]; + __I uint32_t ID; /*!< (@ 0x58002008) Flash Module Identification Register */ + __I uint32_t RESERVED1; + __I uint32_t FSR; /*!< (@ 0x58002010) Flash Status Register */ + __IO uint32_t FCON; /*!< (@ 0x58002014) Flash Configuration Register */ + __IO uint32_t MARP; /*!< (@ 0x58002018) Margin Control Register PFLASH */ + __I uint32_t RESERVED2; + __I uint32_t PROCON0; /*!< (@ 0x58002020) Flash Protection Configuration Register User + 0 */ + __I uint32_t PROCON1; /*!< (@ 0x58002024) Flash Protection Configuration Register User + 1 */ + __I uint32_t PROCON2; /*!< (@ 0x58002028) Flash Protection Configuration Register User + 2 */ +} FLASH0_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ PREF ================ */ +/* ================================================================================ */ + + +/** + * @brief Prefetch Unit (PREF) + */ + +typedef struct { /*!< (@ 0x58004000) PREF Structure */ + __IO uint32_t PCON; /*!< (@ 0x58004000) Prefetch Configuration Register */ +} PREF_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ PMU [PMU0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Program Management Unit (PMU) + */ + +typedef struct { /*!< (@ 0x58000508) PMU Structure */ + __I uint32_t ID; /*!< (@ 0x58000508) PMU0 Identification Register */ +} PMU0_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ + + +/** + * @brief Watch Dog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x50008000) WDT Structure */ + __I uint32_t ID; /*!< (@ 0x50008000) WDT ID Register */ + __IO uint32_t CTR; /*!< (@ 0x50008004) WDT Control Register */ + __O uint32_t SRV; /*!< (@ 0x50008008) WDT Service Register */ + __I uint32_t TIM; /*!< (@ 0x5000800C) WDT Timer Register */ + __IO uint32_t WLB; /*!< (@ 0x50008010) WDT Window Lower Bound Register */ + __IO uint32_t WUB; /*!< (@ 0x50008014) WDT Window Upper Bound Register */ + __I uint32_t WDTSTS; /*!< (@ 0x50008018) WDT Status Register */ + __O uint32_t WDTCLR; /*!< (@ 0x5000801C) WDT Clear Register */ +} WDT_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real Time Clock (RTC) + */ + +typedef struct { /*!< (@ 0x50004A00) RTC Structure */ + __I uint32_t ID; /*!< (@ 0x50004A00) RTC ID Register */ + __IO uint32_t CTR; /*!< (@ 0x50004A04) RTC Control Register */ + __I uint32_t RAWSTAT; /*!< (@ 0x50004A08) RTC Raw Service Request Register */ + __I uint32_t STSSR; /*!< (@ 0x50004A0C) RTC Service Request Status Register */ + __IO uint32_t MSKSR; /*!< (@ 0x50004A10) RTC Service Request Mask Register */ + __O uint32_t CLRSR; /*!< (@ 0x50004A14) RTC Clear Service Request Register */ + __IO uint32_t ATIM0; /*!< (@ 0x50004A18) RTC Alarm Time Register 0 */ + __IO uint32_t ATIM1; /*!< (@ 0x50004A1C) RTC Alarm Time Register 1 */ + __IO uint32_t TIM0; /*!< (@ 0x50004A20) RTC Time Register 0 */ + __IO uint32_t TIM1; /*!< (@ 0x50004A24) RTC Time Register 1 */ +} RTC_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_CLK ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_CLK) + */ + +typedef struct { /*!< (@ 0x50004600) SCU_CLK Structure */ + __I uint32_t CLKSTAT; /*!< (@ 0x50004600) Clock Status Register */ + __O uint32_t CLKSET; /*!< (@ 0x50004604) CLK Set Register */ + __O uint32_t CLKCLR; /*!< (@ 0x50004608) CLK Clear Register */ + __IO uint32_t SYSCLKCR; /*!< (@ 0x5000460C) System Clock Control Register */ + __IO uint32_t CPUCLKCR; /*!< (@ 0x50004610) CPU Clock Control Register */ + __IO uint32_t PBCLKCR; /*!< (@ 0x50004614) Peripheral Bus Clock Control Register */ + __IO uint32_t USBCLKCR; /*!< (@ 0x50004618) USB Clock Control Register */ + __I uint32_t RESERVED; + __IO uint32_t CCUCLKCR; /*!< (@ 0x50004620) CCU Clock Control Register */ + __IO uint32_t WDTCLKCR; /*!< (@ 0x50004624) WDT Clock Control Register */ + __IO uint32_t EXTCLKCR; /*!< (@ 0x50004628) External Clock Control */ + __IO uint32_t MLINKCLKCR; /*!< (@ 0x5000462C) Multi-Link Clock Control */ + __IO uint32_t SLEEPCR; /*!< (@ 0x50004630) Sleep Control Register */ + __IO uint32_t DSLEEPCR; /*!< (@ 0x50004634) Deep Sleep Control Register */ + __I uint32_t RESERVED1[2]; + __I uint32_t CGATSTAT0; /*!< (@ 0x50004640) Peripheral 0 Clock Gating Status */ + __O uint32_t CGATSET0; /*!< (@ 0x50004644) Peripheral 0 Clock Gating Set */ + __O uint32_t CGATCLR0; /*!< (@ 0x50004648) Peripheral 0 Clock Gating Clear */ + __I uint32_t CGATSTAT1; /*!< (@ 0x5000464C) Peripheral 1 Clock Gating Status */ + __O uint32_t CGATSET1; /*!< (@ 0x50004650) Peripheral 1 Clock Gating Set */ + __O uint32_t CGATCLR1; /*!< (@ 0x50004654) Peripheral 1 Clock Gating Clear */ + __I uint32_t CGATSTAT2; /*!< (@ 0x50004658) Peripheral 2 Clock Gating Status */ + __O uint32_t CGATSET2; /*!< (@ 0x5000465C) Peripheral 2 Clock Gating Set */ + __O uint32_t CGATCLR2; /*!< (@ 0x50004660) Peripheral 2 Clock Gating Clear */ +} SCU_CLK_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_OSC ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_OSC) + */ + +typedef struct { /*!< (@ 0x50004700) SCU_OSC Structure */ + __I uint32_t OSCHPSTAT; /*!< (@ 0x50004700) OSC_HP Status Register */ + __IO uint32_t OSCHPCTRL; /*!< (@ 0x50004704) OSC_HP Control Register */ + __I uint32_t RESERVED; + __IO uint32_t CLKCALCONST; /*!< (@ 0x5000470C) Clock Calibration Constant Register */ +} SCU_OSC_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_PLL ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_PLL) + */ + +typedef struct { /*!< (@ 0x50004710) SCU_PLL Structure */ + __I uint32_t PLLSTAT; /*!< (@ 0x50004710) PLL Status Register */ + __IO uint32_t PLLCON0; /*!< (@ 0x50004714) PLL Configuration 0 Register */ + __IO uint32_t PLLCON1; /*!< (@ 0x50004718) PLL Configuration 1 Register */ + __IO uint32_t PLLCON2; /*!< (@ 0x5000471C) PLL Configuration 2 Register */ + __I uint32_t USBPLLSTAT; /*!< (@ 0x50004720) USB PLL Status Register */ + __IO uint32_t USBPLLCON; /*!< (@ 0x50004724) USB PLL Configuration Register */ + __I uint32_t RESERVED[4]; + __I uint32_t CLKMXSTAT; /*!< (@ 0x50004738) Clock Multiplexing Status Register */ +} SCU_PLL_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_GENERAL ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_GENERAL) + */ + +typedef struct { /*!< (@ 0x50004000) SCU_GENERAL Structure */ + __I uint32_t ID; /*!< (@ 0x50004000) SCU Module ID Register */ + __I uint32_t IDCHIP; /*!< (@ 0x50004004) Chip ID Register */ + __I uint32_t IDMANUF; /*!< (@ 0x50004008) Manufactory ID Register */ + __I uint32_t RESERVED; + __IO uint32_t STCON; /*!< (@ 0x50004010) Startup Configuration Register */ + __I uint32_t RESERVED1[6]; + __IO uint32_t GPR[2]; /*!< (@ 0x5000402C) General Purpose Register 0 */ + __I uint32_t RESERVED2[6]; + __IO uint32_t CCUCON; /*!< (@ 0x5000404C) CCU Control Register */ + __I uint32_t RESERVED3[15]; + __IO uint32_t DTSCON; /*!< (@ 0x5000408C) Die Temperature Sensor Control Register */ + __I uint32_t DTSSTAT; /*!< (@ 0x50004090) Die Temperature Sensor Status Register */ + __I uint32_t RESERVED4[3]; + __IO uint32_t GORCEN[2]; /*!< (@ 0x500040A0) Out of Range Comparator Enable Register 0 */ + __IO uint32_t DTEMPLIM; /*!< (@ 0x500040A8) Die Temperature Sensor Limit Register */ + __I uint32_t DTEMPALARM; /*!< (@ 0x500040AC) Die Temperature Sensor Alarm Register */ + __I uint32_t RESERVED5[5]; + __I uint32_t MIRRSTS; /*!< (@ 0x500040C4) Mirror Write Status Register */ + __IO uint32_t RMACR; /*!< (@ 0x500040C8) Retention Memory Access Control Register */ + __IO uint32_t RMDATA; /*!< (@ 0x500040CC) Retention Memory Access Data Register */ + __I uint32_t MIRRALLSTAT; /*!< (@ 0x500040D0) Mirror All Status */ + __O uint32_t MIRRALLREQ; /*!< (@ 0x500040D4) Mirror All Request */ +} SCU_GENERAL_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_INTERRUPT ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_INTERRUPT) + */ + +typedef struct { /*!< (@ 0x50004074) SCU_INTERRUPT Structure */ + __I uint32_t SRSTAT; /*!< (@ 0x50004074) SCU Service Request Status */ + __I uint32_t SRRAW; /*!< (@ 0x50004078) SCU Raw Service Request Status */ + __IO uint32_t SRMSK; /*!< (@ 0x5000407C) SCU Service Request Mask */ + __O uint32_t SRCLR; /*!< (@ 0x50004080) SCU Service Request Clear */ + __O uint32_t SRSET; /*!< (@ 0x50004084) SCU Service Request Set */ + __IO uint32_t NMIREQEN; /*!< (@ 0x50004088) SCU Service Request Mask */ +} SCU_INTERRUPT_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_PARITY ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_PARITY) + */ + +typedef struct { /*!< (@ 0x5000413C) SCU_PARITY Structure */ + __IO uint32_t PEEN; /*!< (@ 0x5000413C) Parity Error Enable Register */ + __IO uint32_t MCHKCON; /*!< (@ 0x50004140) Memory Checking Control Register */ + __IO uint32_t PETE; /*!< (@ 0x50004144) Parity Error Trap Enable Register */ + __IO uint32_t PERSTEN; /*!< (@ 0x50004148) Parity Error Reset Enable Register */ + __I uint32_t RESERVED; + __IO uint32_t PEFLAG; /*!< (@ 0x50004150) Parity Error Flag Register */ + __IO uint32_t PMTPR; /*!< (@ 0x50004154) Parity Memory Test Pattern Register */ + __IO uint32_t PMTSR; /*!< (@ 0x50004158) Parity Memory Test Select Register */ +} SCU_PARITY_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_TRAP ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_TRAP) + */ + +typedef struct { /*!< (@ 0x50004160) SCU_TRAP Structure */ + __I uint32_t TRAPSTAT; /*!< (@ 0x50004160) Trap Status Register */ + __I uint32_t TRAPRAW; /*!< (@ 0x50004164) Trap Raw Status Register */ + __IO uint32_t TRAPDIS; /*!< (@ 0x50004168) Trap Disable Register */ + __O uint32_t TRAPCLR; /*!< (@ 0x5000416C) Trap Clear Register */ + __O uint32_t TRAPSET; /*!< (@ 0x50004170) Trap Set Register */ +} SCU_TRAP_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_HIBERNATE ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_HIBERNATE) + */ + +typedef struct { /*!< (@ 0x50004300) SCU_HIBERNATE Structure */ + __I uint32_t HDSTAT; /*!< (@ 0x50004300) Hibernate Domain Status Register */ + __O uint32_t HDCLR; /*!< (@ 0x50004304) Hibernate Domain Status Clear Register */ + __O uint32_t HDSET; /*!< (@ 0x50004308) Hibernate Domain Status Set Register */ + __IO uint32_t HDCR; /*!< (@ 0x5000430C) Hibernate Domain Control Register */ + __I uint32_t RESERVED; + __IO uint32_t OSCSICTRL; /*!< (@ 0x50004314) fOSI Control Register */ + __I uint32_t OSCULSTAT; /*!< (@ 0x50004318) OSC_ULP Status Register */ + __IO uint32_t OSCULCTRL; /*!< (@ 0x5000431C) OSC_ULP Control Register */ + __IO uint32_t LPACCONF; /*!< (@ 0x50004320) Analog Wake-up Configuration Register */ + __IO uint32_t LPACTH0; /*!< (@ 0x50004324) LPAC Threshold Register 0 */ + __IO uint32_t LPACTH1; /*!< (@ 0x50004328) LPAC Threshold Register 1 */ + __I uint32_t LPACST; /*!< (@ 0x5000432C) Hibernate Analog Control State Register */ + __O uint32_t LPACCLR; /*!< (@ 0x50004330) LPAC Control Clear Register */ + __O uint32_t LPACSET; /*!< (@ 0x50004334) LPAC Control Set Register */ + __I uint32_t HINTST; /*!< (@ 0x50004338) Hibernate Internal Control State Register */ + __O uint32_t HINTCLR; /*!< (@ 0x5000433C) Hibernate Internal Control Clear Register */ + __O uint32_t HINTSET; /*!< (@ 0x50004340) Hibernate Internal Control Set Register */ +} SCU_HIBERNATE_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_POWER ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_POWER) + */ + +typedef struct { /*!< (@ 0x50004200) SCU_POWER Structure */ + __I uint32_t PWRSTAT; /*!< (@ 0x50004200) PCU Status Register */ + __O uint32_t PWRSET; /*!< (@ 0x50004204) PCU Set Control Register */ + __O uint32_t PWRCLR; /*!< (@ 0x50004208) PCU Clear Control Register */ + __I uint32_t RESERVED; + __I uint32_t EVRSTAT; /*!< (@ 0x50004210) EVR Status Register */ + __I uint32_t EVRVADCSTAT; /*!< (@ 0x50004214) EVR VADC Status Register */ + __I uint32_t RESERVED1[5]; + __IO uint32_t PWRMON; /*!< (@ 0x5000422C) Power Monitor Control */ +} SCU_POWER_TypeDef; + + +/* ================================================================================ */ +/* ================ SCU_RESET ================ */ +/* ================================================================================ */ + + +/** + * @brief System Control Unit (SCU_RESET) + */ + +typedef struct { /*!< (@ 0x50004400) SCU_RESET Structure */ + __I uint32_t RSTSTAT; /*!< (@ 0x50004400) RCU Reset Status */ + __O uint32_t RSTSET; /*!< (@ 0x50004404) RCU Reset Set Register */ + __O uint32_t RSTCLR; /*!< (@ 0x50004408) RCU Reset Clear Register */ + __I uint32_t PRSTAT0; /*!< (@ 0x5000440C) RCU Peripheral 0 Reset Status */ + __O uint32_t PRSET0; /*!< (@ 0x50004410) RCU Peripheral 0 Reset Set */ + __O uint32_t PRCLR0; /*!< (@ 0x50004414) RCU Peripheral 0 Reset Clear */ + __I uint32_t PRSTAT1; /*!< (@ 0x50004418) RCU Peripheral 1 Reset Status */ + __O uint32_t PRSET1; /*!< (@ 0x5000441C) RCU Peripheral 1 Reset Set */ + __O uint32_t PRCLR1; /*!< (@ 0x50004420) RCU Peripheral 1 Reset Clear */ + __I uint32_t PRSTAT2; /*!< (@ 0x50004424) RCU Peripheral 2 Reset Status */ + __O uint32_t PRSET2; /*!< (@ 0x50004428) RCU Peripheral 2 Reset Set */ + __O uint32_t PRCLR2; /*!< (@ 0x5000442C) RCU Peripheral 2 Reset Clear */ +} SCU_RESET_TypeDef; + + +/* ================================================================================ */ +/* ================ LEDTS [LEDTS0] ================ */ +/* ================================================================================ */ + + +/** + * @brief LED and Touch Sense Unit 0 (LEDTS) + */ + +typedef struct { /*!< (@ 0x48010000) LEDTS Structure */ + __I uint32_t ID; /*!< (@ 0x48010000) Module Identification Register */ + __IO uint32_t GLOBCTL; /*!< (@ 0x48010004) Global Control Register */ + __IO uint32_t FNCTL; /*!< (@ 0x48010008) Function Control Register */ + __O uint32_t EVFR; /*!< (@ 0x4801000C) Event Flag Register */ + __IO uint32_t TSVAL; /*!< (@ 0x48010010) Touch-sense TS-Counter Value */ + __IO uint32_t LINE0; /*!< (@ 0x48010014) Line Pattern Register 0 */ + __IO uint32_t LINE1; /*!< (@ 0x48010018) Line Pattern Register 1 */ + __IO uint32_t LDCMP0; /*!< (@ 0x4801001C) LED Compare Register 0 */ + __IO uint32_t LDCMP1; /*!< (@ 0x48010020) LED Compare Register 1 */ + __IO uint32_t TSCMP0; /*!< (@ 0x48010024) Touch-sense Compare Register 0 */ + __IO uint32_t TSCMP1; /*!< (@ 0x48010028) Touch-sense Compare Register 1 */ +} LEDTS0_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ USB [USB0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Serial Bus (USB) + */ + +typedef struct { /*!< (@ 0x50040000) USB Structure */ + __I uint32_t RESERVED[2]; + __IO uint32_t GAHBCFG; /*!< (@ 0x50040008) AHB Configuration Register */ + __IO uint32_t GUSBCFG; /*!< (@ 0x5004000C) USB Configuration Register */ + __IO uint32_t GRSTCTL; /*!< (@ 0x50040010) Reset Register */ + __IO uint32_t GINTSTS; /*!< (@ 0x50040014) Interrupt Register */ + __IO uint32_t GINTMSK; /*!< (@ 0x50040018) Interrupt Mask Register */ + __I uint32_t GRXSTSR; /*!< (@ 0x5004001C) Receive Status Debug Read Register */ + __I uint32_t GRXSTSP; /*!< (@ 0x50040020) Receive Status Read and Pop Register */ + __IO uint32_t GRXFSIZ; /*!< (@ 0x50040024) Receive FIFO Size Register */ + __IO uint32_t GNPTXFSIZ; /*!< (@ 0x50040028) Non-Periodic Transmit FIFO Size Register */ + __I uint32_t RESERVED1[4]; + __IO uint32_t GUID; /*!< (@ 0x5004003C) USB Module Identification Register */ + __I uint32_t RESERVED2[7]; + __IO uint32_t GDFIFOCFG; /*!< (@ 0x5004005C) Global DFIFO Software Config Register */ + __I uint32_t RESERVED3[41]; + __IO uint32_t DIEPTXF1; /*!< (@ 0x50040104) Device IN Endpoint 1 Transmit FIFO Size Register */ + __IO uint32_t DIEPTXF2; /*!< (@ 0x50040108) Device IN Endpoint 2 Transmit FIFO Size Register */ + __IO uint32_t DIEPTXF3; /*!< (@ 0x5004010C) Device IN Endpoint 3 Transmit FIFO Size Register */ + __IO uint32_t DIEPTXF4; /*!< (@ 0x50040110) Device IN Endpoint 4 Transmit FIFO Size Register */ + __IO uint32_t DIEPTXF5; /*!< (@ 0x50040114) Device IN Endpoint 5 Transmit FIFO Size Register */ + __IO uint32_t DIEPTXF6; /*!< (@ 0x50040118) Device IN Endpoint 6 Transmit FIFO Size Register */ + __I uint32_t RESERVED4[441]; + __IO uint32_t DCFG; /*!< (@ 0x50040800) Device Configuration Register */ + __IO uint32_t DCTL; /*!< (@ 0x50040804) Device Control Register */ + __I uint32_t DSTS; /*!< (@ 0x50040808) Device Status Register */ + __I uint32_t RESERVED5; + __IO uint32_t DIEPMSK; /*!< (@ 0x50040810) Device IN Endpoint Common Interrupt Mask Register */ + __IO uint32_t DOEPMSK; /*!< (@ 0x50040814) Device OUT Endpoint Common Interrupt Mask Register */ + __I uint32_t DAINT; /*!< (@ 0x50040818) Device All Endpoints Interrupt Register */ + __IO uint32_t DAINTMSK; /*!< (@ 0x5004081C) Device All Endpoints Interrupt Mask Register */ + __I uint32_t RESERVED6[2]; + __IO uint32_t DVBUSDIS; /*!< (@ 0x50040828) Device VBUS Discharge Time Register */ + __IO uint32_t DVBUSPULSE; /*!< (@ 0x5004082C) Device VBUS Pulsing Time Register */ + __I uint32_t RESERVED7; + __IO uint32_t DIEPEMPMSK; /*!< (@ 0x50040834) Device IN Endpoint FIFO Empty Interrupt Mask + Register */ + __I uint32_t RESERVED8[370]; + __IO uint32_t PCGCCTL; /*!< (@ 0x50040E00) Power and Clock Gating Control Register */ +} USB0_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ USB0_EP0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Serial Bus (USB0_EP0) + */ + +typedef struct { /*!< (@ 0x50040900) USB0_EP0 Structure */ + __IO uint32_t DIEPCTL0; /*!< (@ 0x50040900) Device Control IN Endpoint Control Register */ + __I uint32_t RESERVED; + __IO uint32_t DIEPINT0; /*!< (@ 0x50040908) Device Endpoint Interrupt Register */ + __I uint32_t RESERVED1; + __IO uint32_t DIEPTSIZ0; /*!< (@ 0x50040910) Device IN Endpoint Transfer Size Register */ + __IO uint32_t DIEPDMA0; /*!< (@ 0x50040914) Device Endpoint DMA Address Register */ + __I uint32_t DTXFSTS0; /*!< (@ 0x50040918) Device IN Endpoint Transmit FIFO Status Register */ + __I uint32_t DIEPDMAB0; /*!< (@ 0x5004091C) Device Endpoint DMA Buffer Address Register */ + __I uint32_t RESERVED2[120]; + __IO uint32_t DOEPCTL0; /*!< (@ 0x50040B00) Device Control OUT Endpoint Control Register */ + __I uint32_t RESERVED3; + __IO uint32_t DOEPINT0; /*!< (@ 0x50040B08) Device Endpoint Interrupt Register */ + __I uint32_t RESERVED4; + __IO uint32_t DOEPTSIZ0; /*!< (@ 0x50040B10) Device OUT Endpoint Transfer Size Register */ + __IO uint32_t DOEPDMA0; /*!< (@ 0x50040B14) Device Endpoint DMA Address Register */ + __I uint32_t RESERVED5; + __I uint32_t DOEPDMAB0; /*!< (@ 0x50040B1C) Device Endpoint DMA Buffer Address Register */ +} USB0_EP0_TypeDef; + + +/* ================================================================================ */ +/* ================ USB_EP [USB0_EP1] ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Serial Bus (USB_EP) + */ + +typedef struct { /*!< (@ 0x50040920) USB_EP Structure */ + + union { + __IO uint32_t DIEPCTL_INTBULK; /*!< (@ 0x50040920) Device Endpoint Control Register [INTBULK] */ + __IO uint32_t DIEPCTL_ISOCONT; /*!< (@ 0x50040920) Device Endpoint Control Register [ISOCONT] */ + }; + __I uint32_t RESERVED; + __IO uint32_t DIEPINT; /*!< (@ 0x50040928) Device Endpoint Interrupt Register */ + __I uint32_t RESERVED1; + __IO uint32_t DIEPTSIZ; /*!< (@ 0x50040930) Device Endpoint Transfer Size Register */ + __IO uint32_t DIEPDMA; /*!< (@ 0x50040934) Device Endpoint DMA Address Register */ + __I uint32_t DTXFSTS; /*!< (@ 0x50040938) Device IN Endpoint Transmit FIFO Status Register */ + __I uint32_t DIEPDMAB; /*!< (@ 0x5004093C) Device Endpoint DMA Buffer Address Register */ + __I uint32_t RESERVED2[120]; + + union { + __IO uint32_t DOEPCTL_INTBULK; /*!< (@ 0x50040B20) Device Endpoint Control Register [INTBULK] */ + __IO uint32_t DOEPCTL_ISOCONT; /*!< (@ 0x50040B20) Device Endpoint Control Register [ISOCONT] */ + }; + __I uint32_t RESERVED3; + __IO uint32_t DOEPINT; /*!< (@ 0x50040B28) Device Endpoint Interrupt Register */ + __I uint32_t RESERVED4; + + union { + __IO uint32_t DOEPTSIZ_CONTROL; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [CONT] */ + __IO uint32_t DOEPTSIZ_ISO; /*!< (@ 0x50040B30) Device Endpoint Transfer Size Register [ISO] */ + }; + __IO uint32_t DOEPDMA; /*!< (@ 0x50040B34) Device Endpoint DMA Address Register */ + __I uint32_t RESERVED5; + __I uint32_t DOEPDMAB; /*!< (@ 0x50040B3C) Device Endpoint DMA Buffer Address Register */ +} USB0_EP_TypeDef; + + +/* ================================================================================ */ +/* ================ USIC [USIC0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Serial Interface Controller 0 (USIC) + */ + +typedef struct { /*!< (@ 0x40030008) USIC Structure */ + __I uint32_t ID; /*!< (@ 0x40030008) Module Identification Register */ +} USIC_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ USIC_CH [USIC0_CH0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Serial Interface Controller 0 (USIC_CH) + */ + +typedef struct { /*!< (@ 0x40030000) USIC_CH Structure */ + __I uint32_t RESERVED; + __I uint32_t CCFG; /*!< (@ 0x40030004) Channel Configuration Register */ + __I uint32_t RESERVED1; + __IO uint32_t KSCFG; /*!< (@ 0x4003000C) Kernel State Configuration Register */ + __IO uint32_t FDR; /*!< (@ 0x40030010) Fractional Divider Register */ + __IO uint32_t BRG; /*!< (@ 0x40030014) Baud Rate Generator Register */ + __IO uint32_t INPR; /*!< (@ 0x40030018) Interrupt Node Pointer Register */ + __IO uint32_t DX0CR; /*!< (@ 0x4003001C) Input Control Register 0 */ + __IO uint32_t DX1CR; /*!< (@ 0x40030020) Input Control Register 1 */ + __IO uint32_t DX2CR; /*!< (@ 0x40030024) Input Control Register 2 */ + __IO uint32_t DX3CR; /*!< (@ 0x40030028) Input Control Register 3 */ + __IO uint32_t DX4CR; /*!< (@ 0x4003002C) Input Control Register 4 */ + __IO uint32_t DX5CR; /*!< (@ 0x40030030) Input Control Register 5 */ + __IO uint32_t SCTR; /*!< (@ 0x40030034) Shift Control Register */ + __IO uint32_t TCSR; /*!< (@ 0x40030038) Transmit Control/Status Register */ + + union { + __IO uint32_t PCR_IICMode; /*!< (@ 0x4003003C) Protocol Control Register [IIC Mode] */ + __IO uint32_t PCR_IISMode; /*!< (@ 0x4003003C) Protocol Control Register [IIS Mode] */ + __IO uint32_t PCR_SSCMode; /*!< (@ 0x4003003C) Protocol Control Register [SSC Mode] */ + __IO uint32_t PCR; /*!< (@ 0x4003003C) Protocol Control Register */ + __IO uint32_t PCR_ASCMode; /*!< (@ 0x4003003C) Protocol Control Register [ASC Mode] */ + }; + __IO uint32_t CCR; /*!< (@ 0x40030040) Channel Control Register */ + __IO uint32_t CMTR; /*!< (@ 0x40030044) Capture Mode Timer Register */ + + union { + __IO uint32_t PSR_IICMode; /*!< (@ 0x40030048) Protocol Status Register [IIC Mode] */ + __IO uint32_t PSR_IISMode; /*!< (@ 0x40030048) Protocol Status Register [IIS Mode] */ + __IO uint32_t PSR_SSCMode; /*!< (@ 0x40030048) Protocol Status Register [SSC Mode] */ + __IO uint32_t PSR; /*!< (@ 0x40030048) Protocol Status Register */ + __IO uint32_t PSR_ASCMode; /*!< (@ 0x40030048) Protocol Status Register [ASC Mode] */ + }; + __O uint32_t PSCR; /*!< (@ 0x4003004C) Protocol Status Clear Register */ + __I uint32_t RBUFSR; /*!< (@ 0x40030050) Receiver Buffer Status Register */ + __I uint32_t RBUF; /*!< (@ 0x40030054) Receiver Buffer Register */ + __I uint32_t RBUFD; /*!< (@ 0x40030058) Receiver Buffer Register for Debugger */ + __I uint32_t RBUF0; /*!< (@ 0x4003005C) Receiver Buffer Register 0 */ + __I uint32_t RBUF1; /*!< (@ 0x40030060) Receiver Buffer Register 1 */ + __I uint32_t RBUF01SR; /*!< (@ 0x40030064) Receiver Buffer 01 Status Register */ + __O uint32_t FMR; /*!< (@ 0x40030068) Flag Modification Register */ + __I uint32_t RESERVED2[5]; + __IO uint32_t TBUF[32]; /*!< (@ 0x40030080) Transmit Buffer */ + __IO uint32_t BYP; /*!< (@ 0x40030100) Bypass Data Register */ + __IO uint32_t BYPCR; /*!< (@ 0x40030104) Bypass Control Register */ + __IO uint32_t TBCTR; /*!< (@ 0x40030108) Transmitter Buffer Control Register */ + __IO uint32_t RBCTR; /*!< (@ 0x4003010C) Receiver Buffer Control Register */ + __I uint32_t TRBPTR; /*!< (@ 0x40030110) Transmit/Receive Buffer Pointer Register */ + __IO uint32_t TRBSR; /*!< (@ 0x40030114) Transmit/Receive Buffer Status Register */ + __O uint32_t TRBSCR; /*!< (@ 0x40030118) Transmit/Receive Buffer Status Clear Register */ + __I uint32_t OUTR; /*!< (@ 0x4003011C) Receiver Buffer Output Register */ + __I uint32_t OUTDR; /*!< (@ 0x40030120) Receiver Buffer Output Register L for Debugger */ + __I uint32_t RESERVED3[23]; + __O uint32_t IN[32]; /*!< (@ 0x40030180) Transmit FIFO Buffer */ +} USIC_CH_TypeDef; + + +/* ================================================================================ */ +/* ================ CAN ================ */ +/* ================================================================================ */ + + +/** + * @brief Controller Area Networks (CAN) + */ + +typedef struct { /*!< (@ 0x48014000) CAN Structure */ + __IO uint32_t CLC; /*!< (@ 0x48014000) CAN Clock Control Register */ + __I uint32_t RESERVED; + __I uint32_t ID; /*!< (@ 0x48014008) Module Identification Register */ + __IO uint32_t FDR; /*!< (@ 0x4801400C) CAN Fractional Divider Register */ + __I uint32_t RESERVED1[60]; + __I uint32_t LIST[8]; /*!< (@ 0x48014100) List Register */ + __I uint32_t RESERVED2[8]; + __IO uint32_t MSPND[8]; /*!< (@ 0x48014140) Message Pending Register */ + __I uint32_t RESERVED3[8]; + __I uint32_t MSID[8]; /*!< (@ 0x48014180) Message Index Register */ + __I uint32_t RESERVED4[8]; + __IO uint32_t MSIMASK; /*!< (@ 0x480141C0) Message Index Mask Register */ + __IO uint32_t PANCTR; /*!< (@ 0x480141C4) Panel Control Register */ + __IO uint32_t MCR; /*!< (@ 0x480141C8) Module Control Register */ + __O uint32_t MITR; /*!< (@ 0x480141CC) Module Interrupt Trigger Register */ +} CAN_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ CAN_NODE [CAN_NODE0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Controller Area Networks (CAN_NODE) + */ + +typedef struct { /*!< (@ 0x48014200) CAN_NODE Structure */ + __IO uint32_t NCR; /*!< (@ 0x48014200) Node Control Register */ + __IO uint32_t NSR; /*!< (@ 0x48014204) Node Status Register */ + __IO uint32_t NIPR; /*!< (@ 0x48014208) Node Interrupt Pointer Register */ + __IO uint32_t NPCR; /*!< (@ 0x4801420C) Node Port Control Register */ + __IO uint32_t NBTR; /*!< (@ 0x48014210) Node Bit Timing Register */ + __IO uint32_t NECNT; /*!< (@ 0x48014214) Node Error Counter Register */ + __IO uint32_t NFCR; /*!< (@ 0x48014218) Node Frame Counter Register */ +} CAN_NODE_TypeDef; + + +/* ================================================================================ */ +/* ================ CAN_MO [CAN_MO0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Controller Area Networks (CAN_MO) + */ + +typedef struct { /*!< (@ 0x48015000) CAN_MO Structure */ + __IO uint32_t MOFCR; /*!< (@ 0x48015000) Message Object Function Control Register */ + __IO uint32_t MOFGPR; /*!< (@ 0x48015004) Message Object FIFO/Gateway Pointer Register */ + __IO uint32_t MOIPR; /*!< (@ 0x48015008) Message Object Interrupt Pointer Register */ + __IO uint32_t MOAMR; /*!< (@ 0x4801500C) Message Object Acceptance Mask Register */ + __IO uint32_t MODATAL; /*!< (@ 0x48015010) Message Object Data Register Low */ + __IO uint32_t MODATAH; /*!< (@ 0x48015014) Message Object Data Register High */ + __IO uint32_t MOAR; /*!< (@ 0x48015018) Message Object Arbitration Register */ + + union { + __I uint32_t MOSTAT; /*!< (@ 0x4801501C) Message Object Status Register */ + __O uint32_t MOCTR; /*!< (@ 0x4801501C) Message Object Control Register */ + }; +} CAN_MO_TypeDef; + + +/* ================================================================================ */ +/* ================ VADC ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog to Digital Converter (VADC) + */ + +typedef struct { /*!< (@ 0x40004000) VADC Structure */ + __IO uint32_t CLC; /*!< (@ 0x40004000) Clock Control Register */ + __I uint32_t RESERVED; + __I uint32_t ID; /*!< (@ 0x40004008) Module Identification Register */ + __I uint32_t RESERVED1[7]; + __IO uint32_t OCS; /*!< (@ 0x40004028) OCDS Control and Status Register */ + __I uint32_t RESERVED2[21]; + __IO uint32_t GLOBCFG; /*!< (@ 0x40004080) Global Configuration Register */ + __I uint32_t RESERVED3[7]; + __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x400040A0) Input Class Register, Global */ + __I uint32_t RESERVED4[4]; + __IO uint32_t GLOBBOUND; /*!< (@ 0x400040B8) Global Boundary Select Register */ + __I uint32_t RESERVED5[9]; + __IO uint32_t GLOBEFLAG; /*!< (@ 0x400040E0) Global Event Flag Register */ + __I uint32_t RESERVED6[23]; + __IO uint32_t GLOBEVNP; /*!< (@ 0x40004140) Global Event Node Pointer Register */ + __I uint32_t RESERVED7[7]; + __IO uint32_t GLOBTF; /*!< (@ 0x40004160) Global Test Functions Register */ + __I uint32_t RESERVED8[7]; + __IO uint32_t BRSSEL[4]; /*!< (@ 0x40004180) Background Request Source Channel Select Register */ + __I uint32_t RESERVED9[12]; + __IO uint32_t BRSPND[4]; /*!< (@ 0x400041C0) Background Request Source Pending Register */ + __I uint32_t RESERVED10[12]; + __IO uint32_t BRSCTRL; /*!< (@ 0x40004200) Background Request Source Control Register */ + __IO uint32_t BRSMR; /*!< (@ 0x40004204) Background Request Source Mode Register */ + __I uint32_t RESERVED11[30]; + __IO uint32_t GLOBRCR; /*!< (@ 0x40004280) Global Result Control Register */ + __I uint32_t RESERVED12[31]; + __IO uint32_t GLOBRES; /*!< (@ 0x40004300) Global Result Register */ + __I uint32_t RESERVED13[31]; + __IO uint32_t GLOBRESD; /*!< (@ 0x40004380) Global Result Register, Debug */ + __I uint32_t RESERVED14[27]; + __IO uint32_t EMUXSEL; /*!< (@ 0x400043F0) External Multiplexer Select Register */ +} VADC_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ VADC_G [VADC_G0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog to Digital Converter (VADC_G) + */ + +typedef struct { /*!< (@ 0x40004400) VADC_G Structure */ + __I uint32_t RESERVED[32]; + __IO uint32_t ARBCFG; /*!< (@ 0x40004480) Arbitration Configuration Register */ + __IO uint32_t ARBPR; /*!< (@ 0x40004484) Arbitration Priority Register */ + __IO uint32_t CHASS; /*!< (@ 0x40004488) Channel Assignment Register */ + __I uint32_t RESERVED1[5]; + __IO uint32_t ICLASS[2]; /*!< (@ 0x400044A0) Input Class Register */ + __I uint32_t RESERVED2[2]; + __IO uint32_t ALIAS; /*!< (@ 0x400044B0) Alias Register */ + __I uint32_t RESERVED3; + __IO uint32_t BOUND; /*!< (@ 0x400044B8) Boundary Select Register */ + __I uint32_t RESERVED4; + __IO uint32_t SYNCTR; /*!< (@ 0x400044C0) Synchronization Control Register */ + __I uint32_t RESERVED5; + __IO uint32_t BFL; /*!< (@ 0x400044C8) Boundary Flag Register */ + __O uint32_t BFLS; /*!< (@ 0x400044CC) Boundary Flag Software Register */ + __IO uint32_t BFLC; /*!< (@ 0x400044D0) Boundary Flag Control Register */ + __IO uint32_t BFLNP; /*!< (@ 0x400044D4) Boundary Flag Node Pointer Register */ + __I uint32_t RESERVED6[10]; + __IO uint32_t QCTRL0; /*!< (@ 0x40004500) Queue 0 Source Control Register */ + __IO uint32_t QMR0; /*!< (@ 0x40004504) Queue 0 Mode Register */ + __I uint32_t QSR0; /*!< (@ 0x40004508) Queue 0 Status Register */ + __I uint32_t Q0R0; /*!< (@ 0x4000450C) Queue 0 Register 0 */ + + union { + __I uint32_t QBUR0; /*!< (@ 0x40004510) Queue 0 Backup Register */ + __O uint32_t QINR0; /*!< (@ 0x40004510) Queue 0 Input Register */ + }; + __I uint32_t RESERVED7[3]; + __IO uint32_t ASCTRL; /*!< (@ 0x40004520) Autoscan Source Control Register */ + __IO uint32_t ASMR; /*!< (@ 0x40004524) Autoscan Source Mode Register */ + __IO uint32_t ASSEL; /*!< (@ 0x40004528) Autoscan Source Channel Select Register */ + __IO uint32_t ASPND; /*!< (@ 0x4000452C) Autoscan Source Pending Register */ + __I uint32_t RESERVED8[20]; + __IO uint32_t CEFLAG; /*!< (@ 0x40004580) Channel Event Flag Register */ + __IO uint32_t REFLAG; /*!< (@ 0x40004584) Result Event Flag Register */ + __IO uint32_t SEFLAG; /*!< (@ 0x40004588) Source Event Flag Register */ + __I uint32_t RESERVED9; + __O uint32_t CEFCLR; /*!< (@ 0x40004590) Channel Event Flag Clear Register */ + __O uint32_t REFCLR; /*!< (@ 0x40004594) Result Event Flag Clear Register */ + __O uint32_t SEFCLR; /*!< (@ 0x40004598) Source Event Flag Clear Register */ + __I uint32_t RESERVED10; + __IO uint32_t CEVNP0; /*!< (@ 0x400045A0) Channel Event Node Pointer Register 0 */ + __I uint32_t RESERVED11[3]; + __IO uint32_t REVNP0; /*!< (@ 0x400045B0) Result Event Node Pointer Register 0 */ + __IO uint32_t REVNP1; /*!< (@ 0x400045B4) Result Event Node Pointer Register 1 */ + __I uint32_t RESERVED12[2]; + __IO uint32_t SEVNP; /*!< (@ 0x400045C0) Source Event Node Pointer Register */ + __I uint32_t RESERVED13; + __O uint32_t SRACT; /*!< (@ 0x400045C8) Service Request Software Activation Trigger */ + __I uint32_t RESERVED14[9]; + __IO uint32_t EMUXCTR; /*!< (@ 0x400045F0) External Multiplexer Control Register */ + __I uint32_t RESERVED15; + __IO uint32_t VFR; /*!< (@ 0x400045F8) Valid Flag Register */ + __I uint32_t RESERVED16; + __IO uint32_t CHCTR[8]; /*!< (@ 0x40004600) Channel Ctrl. Reg. */ + __I uint32_t RESERVED17[24]; + __IO uint32_t RCR[16]; /*!< (@ 0x40004680) Result Control Register */ + __I uint32_t RESERVED18[16]; + __IO uint32_t RES[16]; /*!< (@ 0x40004700) Result Register */ + __I uint32_t RESERVED19[16]; + __I uint32_t RESD[16]; /*!< (@ 0x40004780) Result Register, Debug */ +} VADC_G_TypeDef; + + +/* ================================================================================ */ +/* ================ DAC ================ */ +/* ================================================================================ */ + + +/** + * @brief Digital to Analog Converter (DAC) + */ + +typedef struct { /*!< (@ 0x48018000) DAC Structure */ + __I uint32_t ID; /*!< (@ 0x48018000) Module Identification Register */ + __IO uint32_t DAC0CFG0; /*!< (@ 0x48018004) DAC0 Configuration Register 0 */ + __IO uint32_t DAC0CFG1; /*!< (@ 0x48018008) DAC0 Configuration Register 1 */ + __IO uint32_t DAC1CFG0; /*!< (@ 0x4801800C) DAC1 Configuration Register 0 */ + __IO uint32_t DAC1CFG1; /*!< (@ 0x48018010) DAC1 Configuration Register 1 */ + __IO uint32_t DAC0DATA; /*!< (@ 0x48018014) DAC0 Data Register */ + __IO uint32_t DAC1DATA; /*!< (@ 0x48018018) DAC1 Data Register */ + __IO uint32_t DAC01DATA; /*!< (@ 0x4801801C) DAC01 Data Register */ + __IO uint32_t DAC0PATL; /*!< (@ 0x48018020) DAC0 Lower Pattern Register */ + __IO uint32_t DAC0PATH; /*!< (@ 0x48018024) DAC0 Higher Pattern Register */ + __IO uint32_t DAC1PATL; /*!< (@ 0x48018028) DAC1 Lower Pattern Register */ + __IO uint32_t DAC1PATH; /*!< (@ 0x4801802C) DAC1 Higher Pattern Register */ +} DAC_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ CCU4 [CCU40] ================ */ +/* ================================================================================ */ + + +/** + * @brief Capture Compare Unit 4 - Unit 0 (CCU4) + */ + +typedef struct { /*!< (@ 0x4000C000) CCU4 Structure */ + __IO uint32_t GCTRL; /*!< (@ 0x4000C000) Global Control Register */ + __I uint32_t GSTAT; /*!< (@ 0x4000C004) Global Status Register */ + __O uint32_t GIDLS; /*!< (@ 0x4000C008) Global Idle Set */ + __O uint32_t GIDLC; /*!< (@ 0x4000C00C) Global Idle Clear */ + __O uint32_t GCSS; /*!< (@ 0x4000C010) Global Channel Set */ + __O uint32_t GCSC; /*!< (@ 0x4000C014) Global Channel Clear */ + __I uint32_t GCST; /*!< (@ 0x4000C018) Global Channel Status */ + __I uint32_t RESERVED[13]; + __I uint32_t ECRD; /*!< (@ 0x4000C050) Extended Capture Mode Read */ + __I uint32_t RESERVED1[11]; + __I uint32_t MIDR; /*!< (@ 0x4000C080) Module Identification */ +} CCU4_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ CCU4_CC4 [CCU40_CC40] ================ */ +/* ================================================================================ */ + + +/** + * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4) + */ + +typedef struct { /*!< (@ 0x4000C100) CCU4_CC4 Structure */ + __IO uint32_t INS; /*!< (@ 0x4000C100) Input Selector Configuration */ + __IO uint32_t CMC; /*!< (@ 0x4000C104) Connection Matrix Control */ + __I uint32_t TCST; /*!< (@ 0x4000C108) Slice Timer Status */ + __O uint32_t TCSET; /*!< (@ 0x4000C10C) Slice Timer Run Set */ + __O uint32_t TCCLR; /*!< (@ 0x4000C110) Slice Timer Clear */ + __IO uint32_t TC; /*!< (@ 0x4000C114) Slice Timer Control */ + __IO uint32_t PSL; /*!< (@ 0x4000C118) Passive Level Config */ + __I uint32_t DIT; /*!< (@ 0x4000C11C) Dither Config */ + __IO uint32_t DITS; /*!< (@ 0x4000C120) Dither Shadow Register */ + __IO uint32_t PSC; /*!< (@ 0x4000C124) Prescaler Control */ + __IO uint32_t FPC; /*!< (@ 0x4000C128) Floating Prescaler Control */ + __IO uint32_t FPCS; /*!< (@ 0x4000C12C) Floating Prescaler Shadow */ + __I uint32_t PR; /*!< (@ 0x4000C130) Timer Period Value */ + __IO uint32_t PRS; /*!< (@ 0x4000C134) Timer Shadow Period Value */ + __I uint32_t CR; /*!< (@ 0x4000C138) Timer Compare Value */ + __IO uint32_t CRS; /*!< (@ 0x4000C13C) Timer Shadow Compare Value */ + __I uint32_t RESERVED[12]; + __IO uint32_t TIMER; /*!< (@ 0x4000C170) Timer Value */ + __I uint32_t CV[4]; /*!< (@ 0x4000C174) Capture Register 0 */ + __I uint32_t RESERVED1[7]; + __I uint32_t INTS; /*!< (@ 0x4000C1A0) Interrupt Status */ + __IO uint32_t INTE; /*!< (@ 0x4000C1A4) Interrupt Enable Control */ + __IO uint32_t SRS; /*!< (@ 0x4000C1A8) Service Request Selector */ + __O uint32_t SWS; /*!< (@ 0x4000C1AC) Interrupt Status Set */ + __O uint32_t SWR; /*!< (@ 0x4000C1B0) Interrupt Status Clear */ +} CCU4_CC4_TypeDef; + + +/* ================================================================================ */ +/* ================ CCU8 [CCU80] ================ */ +/* ================================================================================ */ + + +/** + * @brief Capture Compare Unit 8 - Unit 0 (CCU8) + */ + +typedef struct { /*!< (@ 0x40020000) CCU8 Structure */ + __IO uint32_t GCTRL; /*!< (@ 0x40020000) Global Control Register */ + __I uint32_t GSTAT; /*!< (@ 0x40020004) Global Status Register */ + __O uint32_t GIDLS; /*!< (@ 0x40020008) Global Idle Set */ + __O uint32_t GIDLC; /*!< (@ 0x4002000C) Global Idle Clear */ + __O uint32_t GCSS; /*!< (@ 0x40020010) Global Channel Set */ + __O uint32_t GCSC; /*!< (@ 0x40020014) Global Channel Clear */ + __I uint32_t GCST; /*!< (@ 0x40020018) Global Channel status */ + __IO uint32_t GPCHK; /*!< (@ 0x4002001C) Parity Checker Configuration */ + __I uint32_t RESERVED[12]; + __I uint32_t ECRD; /*!< (@ 0x40020050) Extended Capture Mode Read */ + __I uint32_t RESERVED1[11]; + __I uint32_t MIDR; /*!< (@ 0x40020080) Module Identification */ +} CCU8_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ CCU8_CC8 [CCU80_CC80] ================ */ +/* ================================================================================ */ + + +/** + * @brief Capture Compare Unit 8 - Unit 0 (CCU8_CC8) + */ + +typedef struct { /*!< (@ 0x40020100) CCU8_CC8 Structure */ + __IO uint32_t INS; /*!< (@ 0x40020100) Input Selector Configuration */ + __IO uint32_t CMC; /*!< (@ 0x40020104) Connection Matrix Control */ + __I uint32_t TCST; /*!< (@ 0x40020108) Slice Timer Status */ + __O uint32_t TCSET; /*!< (@ 0x4002010C) Slice Timer Run Set */ + __O uint32_t TCCLR; /*!< (@ 0x40020110) Slice Timer Clear */ + __IO uint32_t TC; /*!< (@ 0x40020114) Slice Timer Control */ + __IO uint32_t PSL; /*!< (@ 0x40020118) Passive Level Config */ + __I uint32_t DIT; /*!< (@ 0x4002011C) Dither Config */ + __IO uint32_t DITS; /*!< (@ 0x40020120) Dither Shadow Register */ + __IO uint32_t PSC; /*!< (@ 0x40020124) Prescaler Control */ + __IO uint32_t FPC; /*!< (@ 0x40020128) Floating Prescaler Control */ + __IO uint32_t FPCS; /*!< (@ 0x4002012C) Floating Prescaler Shadow */ + __I uint32_t PR; /*!< (@ 0x40020130) Timer Period Value */ + __IO uint32_t PRS; /*!< (@ 0x40020134) Timer Shadow Period Value */ + __I uint32_t CR1; /*!< (@ 0x40020138) Channel 1 Compare Value */ + __IO uint32_t CR1S; /*!< (@ 0x4002013C) Channel 1 Compare Shadow Value */ + __I uint32_t CR2; /*!< (@ 0x40020140) Channel 2 Compare Value */ + __IO uint32_t CR2S; /*!< (@ 0x40020144) Channel 2 Compare Shadow Value */ + __IO uint32_t CHC; /*!< (@ 0x40020148) Channel Control */ + __IO uint32_t DTC; /*!< (@ 0x4002014C) Dead Time Control */ + __IO uint32_t DC1R; /*!< (@ 0x40020150) Channel 1 Dead Time Values */ + __IO uint32_t DC2R; /*!< (@ 0x40020154) Channel 2 Dead Time Values */ + __I uint32_t RESERVED[6]; + __IO uint32_t TIMER; /*!< (@ 0x40020170) Timer Value */ + __I uint32_t CV[4]; /*!< (@ 0x40020174) Capture Register 0 */ + __I uint32_t RESERVED1[7]; + __I uint32_t INTS; /*!< (@ 0x400201A0) Interrupt Status */ + __IO uint32_t INTE; /*!< (@ 0x400201A4) Interrupt Enable Control */ + __IO uint32_t SRS; /*!< (@ 0x400201A8) Service Request Selector */ + __O uint32_t SWS; /*!< (@ 0x400201AC) Interrupt Status Set */ + __O uint32_t SWR; /*!< (@ 0x400201B0) Interrupt Status Clear */ + __IO uint32_t STC; /*!< (@ 0x400201B4) Shadow transfer control */ +} CCU8_CC8_TypeDef; + + +/* ================================================================================ */ +/* ================ HRPWM0 ================ */ +/* ================================================================================ */ + + +/** + * @brief High Resolution PWM Unit (HRPWM0) + */ + +typedef struct { /*!< (@ 0x40020900) HRPWM0 Structure */ + __IO uint32_t HRBSC; /*!< (@ 0x40020900) Bias and suspend configuration */ + __I uint32_t RESERVED; + __I uint32_t MIDR; /*!< (@ 0x40020908) Module identification register */ + __I uint32_t RESERVED1[2]; + __IO uint32_t GLBANA; /*!< (@ 0x40020914) Global Analog Configuration */ + __I uint32_t RESERVED2[2]; + __IO uint32_t CSGCFG; /*!< (@ 0x40020920) Global CSG configuration */ + __O uint32_t CSGSETG; /*!< (@ 0x40020924) Global CSG run bit set */ + __O uint32_t CSGCLRG; /*!< (@ 0x40020928) Global CSG run bit clear */ + __I uint32_t CSGSTATG; /*!< (@ 0x4002092C) Global CSG run bit status */ + __O uint32_t CSGFCG; /*!< (@ 0x40020930) Global CSG slope/prescaler control */ + __I uint32_t CSGFSG; /*!< (@ 0x40020934) Global CSG slope/prescaler status */ + __O uint32_t CSGTRG; /*!< (@ 0x40020938) Global CSG shadow/switch trigger */ + __O uint32_t CSGTRC; /*!< (@ 0x4002093C) Global CSG shadow trigger clear */ + __I uint32_t CSGTRSG; /*!< (@ 0x40020940) Global CSG shadow/switch status */ + __I uint32_t RESERVED3[7]; + __IO uint32_t HRCCFG; /*!< (@ 0x40020960) Global HRC configuration */ + __O uint32_t HRCSTRG; /*!< (@ 0x40020964) Global HRC shadow trigger set */ + __O uint32_t HRCCTRG; /*!< (@ 0x40020968) Global HRC shadow trigger clear */ + __I uint32_t HRCSTSG; /*!< (@ 0x4002096C) Global HRC shadow transfer status */ + __I uint32_t HRGHRS; /*!< (@ 0x40020970) High Resolution Generation Status */ +} HRPWM0_Type; + + +/* ================================================================================ */ +/* ================ HRPWM0_CSG [HRPWM0_CSG0] ================ */ +/* ================================================================================ */ + + +/** + * @brief High Resolution PWM Unit (HRPWM0_CSG) + */ + +typedef struct { /*!< (@ 0x40020A00) HRPWM0_CSG Structure */ + __IO uint32_t DCI; /*!< (@ 0x40020A00) External input selection */ + __IO uint32_t IES; /*!< (@ 0x40020A04) External input selection */ + __IO uint32_t SC; /*!< (@ 0x40020A08) Slope generation control */ + __I uint32_t PC; /*!< (@ 0x40020A0C) Pulse swallow configuration */ + __I uint32_t DSV1; /*!< (@ 0x40020A10) DAC reference value 1 */ + __IO uint32_t DSV2; /*!< (@ 0x40020A14) DAC reference value 1 */ + __IO uint32_t SDSV1; /*!< (@ 0x40020A18) Shadow reference value 1 */ + __IO uint32_t SPC; /*!< (@ 0x40020A1C) Shadow Pulse swallow value */ + __IO uint32_t CC; /*!< (@ 0x40020A20) Comparator configuration */ + __IO uint32_t PLC; /*!< (@ 0x40020A24) Passive level configuration */ + __IO uint32_t BLV; /*!< (@ 0x40020A28) Comparator blanking value */ + __IO uint32_t SRE; /*!< (@ 0x40020A2C) Service request enable */ + __IO uint32_t SRS; /*!< (@ 0x40020A30) Service request line selector */ + __O uint32_t SWS; /*!< (@ 0x40020A34) Service request SW set */ + __O uint32_t SWC; /*!< (@ 0x40020A38) Service request SW clear */ + __I uint32_t ISTAT; /*!< (@ 0x40020A3C) Service request status */ +} HRPWM0_CSG_Type; + + +/* ================================================================================ */ +/* ================ HRPWM0_HRC [HRPWM0_HRC0] ================ */ +/* ================================================================================ */ + + +/** + * @brief High Resolution PWM Unit (HRPWM0_HRC) + */ + +typedef struct { /*!< (@ 0x40021300) HRPWM0_HRC Structure */ + __IO uint32_t GC; /*!< (@ 0x40021300) HRC mode configuration */ + __IO uint32_t PL; /*!< (@ 0x40021304) HRC output passive level */ + __IO uint32_t GSEL; /*!< (@ 0x40021308) HRC global control selection */ + __IO uint32_t TSEL; /*!< (@ 0x4002130C) HRC timer selection */ + __I uint32_t SC; /*!< (@ 0x40021310) HRC current source for shadow */ + __I uint32_t DCR; /*!< (@ 0x40021314) HRC dead time rising value */ + __I uint32_t DCF; /*!< (@ 0x40021318) HRC dead time falling value */ + __I uint32_t CR1; /*!< (@ 0x4002131C) HRC rising edge value */ + __I uint32_t CR2; /*!< (@ 0x40021320) HRC falling edge value */ + __IO uint32_t SSC; /*!< (@ 0x40021324) HRC next source for shadow */ + __IO uint32_t SDCR; /*!< (@ 0x40021328) HRC shadow dead time rising */ + __IO uint32_t SDCF; /*!< (@ 0x4002132C) HRC shadow dead time falling */ + __IO uint32_t SCR1; /*!< (@ 0x40021330) HRC shadow rising edge value */ + __IO uint32_t SCR2; /*!< (@ 0x40021334) HRC shadow falling edge value */ +} HRPWM0_HRC_Type; + + +/* ================================================================================ */ +/* ================ POSIF [POSIF0] ================ */ +/* ================================================================================ */ + + +/** + * @brief Position Interface 0 (POSIF) + */ + +typedef struct { /*!< (@ 0x40028000) POSIF Structure */ + __IO uint32_t PCONF; /*!< (@ 0x40028000) Service Request Processing configuration */ + __IO uint32_t PSUS; /*!< (@ 0x40028004) Service Request Processing Suspend Config */ + __O uint32_t PRUNS; /*!< (@ 0x40028008) Service Request Processing Run Bit Set */ + __O uint32_t PRUNC; /*!< (@ 0x4002800C) Service Request Processing Run Bit Clear */ + __I uint32_t PRUN; /*!< (@ 0x40028010) Service Request Processing Run Bit Status */ + __I uint32_t RESERVED[3]; + __I uint32_t MIDR; /*!< (@ 0x40028020) Module Identification register */ + __I uint32_t RESERVED1[3]; + __I uint32_t HALP; /*!< (@ 0x40028030) Hall Sensor Patterns */ + __IO uint32_t HALPS; /*!< (@ 0x40028034) Hall Sensor Shadow Patterns */ + __I uint32_t RESERVED2[2]; + __I uint32_t MCM; /*!< (@ 0x40028040) Multi-Channel Pattern */ + __IO uint32_t MCSM; /*!< (@ 0x40028044) Multi-Channel Shadow Pattern */ + __O uint32_t MCMS; /*!< (@ 0x40028048) Multi-Channel Pattern Control set */ + __O uint32_t MCMC; /*!< (@ 0x4002804C) Multi-Channel Pattern Control clear */ + __I uint32_t MCMF; /*!< (@ 0x40028050) Multi-Channel Pattern Control flag */ + __I uint32_t RESERVED3[3]; + __IO uint32_t QDC; /*!< (@ 0x40028060) Quadrature Decoder Control */ + __I uint32_t RESERVED4[3]; + __I uint32_t PFLG; /*!< (@ 0x40028070) Service Request Processing Interrupt Flags */ + __IO uint32_t PFLGE; /*!< (@ 0x40028074) Service Request Processing Interrupt Enable */ + __O uint32_t SPFLG; /*!< (@ 0x40028078) Service Request Processing Interrupt Set */ + __O uint32_t RPFLG; /*!< (@ 0x4002807C) Service Request Processing Interrupt Clear */ + __I uint32_t RESERVED5[32]; + __I uint32_t PDBG; /*!< (@ 0x40028100) POSIF Debug register */ +} POSIF_GLOBAL_TypeDef; + + +/* ================================================================================ */ +/* ================ PORT0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Port 0 (PORT0) + */ + +typedef struct { /*!< (@ 0x48028000) PORT0 Structure */ + __IO uint32_t OUT; /*!< (@ 0x48028000) Port 0 Output Register */ + __O uint32_t OMR; /*!< (@ 0x48028004) Port 0 Output Modification Register */ + __I uint32_t RESERVED[2]; + __IO uint32_t IOCR0; /*!< (@ 0x48028010) Port 0 Input/Output Control Register 0 */ + __IO uint32_t IOCR4; /*!< (@ 0x48028014) Port 0 Input/Output Control Register 4 */ + __IO uint32_t IOCR8; /*!< (@ 0x48028018) Port 0 Input/Output Control Register 8 */ + __I uint32_t RESERVED1[2]; + __I uint32_t IN; /*!< (@ 0x48028024) Port 0 Input Register */ + __I uint32_t RESERVED2[6]; + __IO uint32_t PDR0; /*!< (@ 0x48028040) Port 0 Pad Driver Mode 0 Register */ + __IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Register */ + __I uint32_t RESERVED3[6]; + __I uint32_t PDISC; /*!< (@ 0x48028060) Port 0 Pin Function Decision Control Register */ + __I uint32_t RESERVED4[3]; + __IO uint32_t PPS; /*!< (@ 0x48028070) Port 0 Pin Power Save Register */ + __IO uint32_t HWSEL; /*!< (@ 0x48028074) Port 0 Pin Hardware Select Register */ +} PORT0_Type; + + +/* ================================================================================ */ +/* ================ PORT1 ================ */ +/* ================================================================================ */ + + +/** + * @brief Port 1 (PORT1) + */ + +typedef struct { /*!< (@ 0x48028100) PORT1 Structure */ + __IO uint32_t OUT; /*!< (@ 0x48028100) Port 1 Output Register */ + __O uint32_t OMR; /*!< (@ 0x48028104) Port 1 Output Modification Register */ + __I uint32_t RESERVED[2]; + __IO uint32_t IOCR0; /*!< (@ 0x48028110) Port 1 Input/Output Control Register 0 */ + __IO uint32_t IOCR4; /*!< (@ 0x48028114) Port 1 Input/Output Control Register 4 */ + __IO uint32_t IOCR8; /*!< (@ 0x48028118) Port 1 Input/Output Control Register 8 */ + __IO uint32_t IOCR12; /*!< (@ 0x4802811C) Port 1 Input/Output Control Register 12 */ + __I uint32_t RESERVED1; + __I uint32_t IN; /*!< (@ 0x48028124) Port 1 Input Register */ + __I uint32_t RESERVED2[6]; + __IO uint32_t PDR0; /*!< (@ 0x48028140) Port 1 Pad Driver Mode 0 Register */ + __IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Register */ + __I uint32_t RESERVED3[6]; + __I uint32_t PDISC; /*!< (@ 0x48028160) Port 1 Pin Function Decision Control Register */ + __I uint32_t RESERVED4[3]; + __IO uint32_t PPS; /*!< (@ 0x48028170) Port 1 Pin Power Save Register */ + __IO uint32_t HWSEL; /*!< (@ 0x48028174) Port 1 Pin Hardware Select Register */ +} PORT1_Type; + + +/* ================================================================================ */ +/* ================ PORT2 ================ */ +/* ================================================================================ */ + + +/** + * @brief Port 2 (PORT2) + */ + +typedef struct { /*!< (@ 0x48028200) PORT2 Structure */ + __IO uint32_t OUT; /*!< (@ 0x48028200) Port 2 Output Register */ + __O uint32_t OMR; /*!< (@ 0x48028204) Port 2 Output Modification Register */ + __I uint32_t RESERVED[2]; + __IO uint32_t IOCR0; /*!< (@ 0x48028210) Port 2 Input/Output Control Register 0 */ + __IO uint32_t IOCR4; /*!< (@ 0x48028214) Port 2 Input/Output Control Register 4 */ + __IO uint32_t IOCR8; /*!< (@ 0x48028218) Port 2 Input/Output Control Register 8 */ + __IO uint32_t IOCR12; /*!< (@ 0x4802821C) Port 2 Input/Output Control Register 12 */ + __I uint32_t RESERVED1; + __I uint32_t IN; /*!< (@ 0x48028224) Port 2 Input Register */ + __I uint32_t RESERVED2[6]; + __IO uint32_t PDR0; /*!< (@ 0x48028240) Port 2 Pad Driver Mode 0 Register */ + __IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Register */ + __I uint32_t RESERVED3[6]; + __I uint32_t PDISC; /*!< (@ 0x48028260) Port 2 Pin Function Decision Control Register */ + __I uint32_t RESERVED4[3]; + __IO uint32_t PPS; /*!< (@ 0x48028270) Port 2 Pin Power Save Register */ + __IO uint32_t HWSEL; /*!< (@ 0x48028274) Port 2 Pin Hardware Select Register */ +} PORT2_Type; + + +/* ================================================================================ */ +/* ================ PORT3 ================ */ +/* ================================================================================ */ + + +/** + * @brief Port 3 (PORT3) + */ + +typedef struct { /*!< (@ 0x48028300) PORT3 Structure */ + __IO uint32_t OUT; /*!< (@ 0x48028300) Port 3 Output Register */ + __O uint32_t OMR; /*!< (@ 0x48028304) Port 3 Output Modification Register */ + __I uint32_t RESERVED[2]; + __IO uint32_t IOCR0; /*!< (@ 0x48028310) Port 3 Input/Output Control Register 0 */ + __I uint32_t RESERVED1[4]; + __I uint32_t IN; /*!< (@ 0x48028324) Port 3 Input Register */ + __I uint32_t RESERVED2[6]; + __IO uint32_t PDR0; /*!< (@ 0x48028340) Port 3 Pad Driver Mode 0 Register */ + __I uint32_t RESERVED3[7]; + __I uint32_t PDISC; /*!< (@ 0x48028360) Port 3 Pin Function Decision Control Register */ + __I uint32_t RESERVED4[3]; + __IO uint32_t PPS; /*!< (@ 0x48028370) Port 3 Pin Power Save Register */ + __IO uint32_t HWSEL; /*!< (@ 0x48028374) Port 3 Pin Hardware Select Register */ +} PORT3_Type; + + +/* ================================================================================ */ +/* ================ PORT14 ================ */ +/* ================================================================================ */ + + +/** + * @brief Port 14 (PORT14) + */ + +typedef struct { /*!< (@ 0x48028E00) PORT14 Structure */ + __IO uint32_t OUT; /*!< (@ 0x48028E00) Port 14 Output Register */ + __O uint32_t OMR; /*!< (@ 0x48028E04) Port 14 Output Modification Register */ + __I uint32_t RESERVED[2]; + __IO uint32_t IOCR0; /*!< (@ 0x48028E10) Port 14 Input/Output Control Register 0 */ + __IO uint32_t IOCR4; /*!< (@ 0x48028E14) Port 14 Input/Output Control Register 4 */ + __IO uint32_t IOCR8; /*!< (@ 0x48028E18) Port 14 Input/Output Control Register 8 */ + __IO uint32_t IOCR12; /*!< (@ 0x48028E1C) Port 14 Input/Output Control Register 12 */ + __I uint32_t RESERVED1; + __I uint32_t IN; /*!< (@ 0x48028E24) Port 14 Input Register */ + __I uint32_t RESERVED2[14]; + __IO uint32_t PDISC; /*!< (@ 0x48028E60) Port 14 Pin Function Decision Control Register */ + __I uint32_t RESERVED3[3]; + __IO uint32_t PPS; /*!< (@ 0x48028E70) Port 14 Pin Power Save Register */ + __IO uint32_t HWSEL; /*!< (@ 0x48028E74) Port 14 Pin Hardware Select Register */ +} PORT14_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ struct 'PPB' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- PPB_ACTLR --------------------------------- */ +#define PPB_ACTLR_DISMCYCINT_Pos (0UL) /*!< PPB ACTLR: DISMCYCINT (Bit 0) */ +#define PPB_ACTLR_DISMCYCINT_Msk (0x1UL) /*!< PPB ACTLR: DISMCYCINT (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISDEFWBUF_Pos (1UL) /*!< PPB ACTLR: DISDEFWBUF (Bit 1) */ +#define PPB_ACTLR_DISDEFWBUF_Msk (0x2UL) /*!< PPB ACTLR: DISDEFWBUF (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISFOLD_Pos (2UL) /*!< PPB ACTLR: DISFOLD (Bit 2) */ +#define PPB_ACTLR_DISFOLD_Msk (0x4UL) /*!< PPB ACTLR: DISFOLD (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISFPCA_Pos (8UL) /*!< PPB ACTLR: DISFPCA (Bit 8) */ +#define PPB_ACTLR_DISFPCA_Msk (0x100UL) /*!< PPB ACTLR: DISFPCA (Bitfield-Mask: 0x01) */ +#define PPB_ACTLR_DISOOFP_Pos (9UL) /*!< PPB ACTLR: DISOOFP (Bit 9) */ +#define PPB_ACTLR_DISOOFP_Msk (0x200UL) /*!< PPB ACTLR: DISOOFP (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PPB_SYST_CSR -------------------------------- */ +#define PPB_SYST_CSR_ENABLE_Pos (0UL) /*!< PPB SYST_CSR: ENABLE (Bit 0) */ +#define PPB_SYST_CSR_ENABLE_Msk (0x1UL) /*!< PPB SYST_CSR: ENABLE (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CSR_TICKINT_Pos (1UL) /*!< PPB SYST_CSR: TICKINT (Bit 1) */ +#define PPB_SYST_CSR_TICKINT_Msk (0x2UL) /*!< PPB SYST_CSR: TICKINT (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CSR_CLKSOURCE_Pos (2UL) /*!< PPB SYST_CSR: CLKSOURCE (Bit 2) */ +#define PPB_SYST_CSR_CLKSOURCE_Msk (0x4UL) /*!< PPB SYST_CSR: CLKSOURCE (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CSR_COUNTFLAG_Pos (16UL) /*!< PPB SYST_CSR: COUNTFLAG (Bit 16) */ +#define PPB_SYST_CSR_COUNTFLAG_Msk (0x10000UL) /*!< PPB SYST_CSR: COUNTFLAG (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PPB_SYST_RVR -------------------------------- */ +#define PPB_SYST_RVR_RELOAD_Pos (0UL) /*!< PPB SYST_RVR: RELOAD (Bit 0) */ +#define PPB_SYST_RVR_RELOAD_Msk (0xffffffUL) /*!< PPB SYST_RVR: RELOAD (Bitfield-Mask: 0xffffff) */ + +/* -------------------------------- PPB_SYST_CVR -------------------------------- */ +#define PPB_SYST_CVR_CURRENT_Pos (0UL) /*!< PPB SYST_CVR: CURRENT (Bit 0) */ +#define PPB_SYST_CVR_CURRENT_Msk (0xffffffUL) /*!< PPB SYST_CVR: CURRENT (Bitfield-Mask: 0xffffff) */ + +/* ------------------------------- PPB_SYST_CALIB ------------------------------- */ +#define PPB_SYST_CALIB_TENMS_Pos (0UL) /*!< PPB SYST_CALIB: TENMS (Bit 0) */ +#define PPB_SYST_CALIB_TENMS_Msk (0xffffffUL) /*!< PPB SYST_CALIB: TENMS (Bitfield-Mask: 0xffffff) */ +#define PPB_SYST_CALIB_SKEW_Pos (30UL) /*!< PPB SYST_CALIB: SKEW (Bit 30) */ +#define PPB_SYST_CALIB_SKEW_Msk (0x40000000UL) /*!< PPB SYST_CALIB: SKEW (Bitfield-Mask: 0x01) */ +#define PPB_SYST_CALIB_NOREF_Pos (31UL) /*!< PPB SYST_CALIB: NOREF (Bit 31) */ +#define PPB_SYST_CALIB_NOREF_Msk (0x80000000UL) /*!< PPB SYST_CALIB: NOREF (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PPB_NVIC_ISER0 ------------------------------- */ +#define PPB_NVIC_ISER0_SETENA_Pos (0UL) /*!< PPB NVIC_ISER0: SETENA (Bit 0) */ +#define PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER0: SETENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ISER1 ------------------------------- */ +#define PPB_NVIC_ISER1_SETENA_Pos (0UL) /*!< PPB NVIC_ISER1: SETENA (Bit 0) */ +#define PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER1: SETENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ISER2 ------------------------------- */ +#define PPB_NVIC_ISER2_SETENA_Pos (0UL) /*!< PPB NVIC_ISER2: SETENA (Bit 0) */ +#define PPB_NVIC_ISER2_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER2: SETENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ISER3 ------------------------------- */ +#define PPB_NVIC_ISER3_SETENA_Pos (0UL) /*!< PPB NVIC_ISER3: SETENA (Bit 0) */ +#define PPB_NVIC_ISER3_SETENA_Msk (0xffffffffUL) /*!< PPB NVIC_ISER3: SETENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICER0 ------------------------------- */ +#define PPB_NVIC_ICER0_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER0: CLRENA (Bit 0) */ +#define PPB_NVIC_ICER0_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER0: CLRENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICER1 ------------------------------- */ +#define PPB_NVIC_ICER1_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER1: CLRENA (Bit 0) */ +#define PPB_NVIC_ICER1_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER1: CLRENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICER2 ------------------------------- */ +#define PPB_NVIC_ICER2_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER2: CLRENA (Bit 0) */ +#define PPB_NVIC_ICER2_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER2: CLRENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICER3 ------------------------------- */ +#define PPB_NVIC_ICER3_CLRENA_Pos (0UL) /*!< PPB NVIC_ICER3: CLRENA (Bit 0) */ +#define PPB_NVIC_ICER3_CLRENA_Msk (0xffffffffUL) /*!< PPB NVIC_ICER3: CLRENA (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ISPR0 ------------------------------- */ +#define PPB_NVIC_ISPR0_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR0: SETPEND (Bit 0) */ +#define PPB_NVIC_ISPR0_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR0: SETPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ISPR1 ------------------------------- */ +#define PPB_NVIC_ISPR1_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR1: SETPEND (Bit 0) */ +#define PPB_NVIC_ISPR1_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR1: SETPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ISPR2 ------------------------------- */ +#define PPB_NVIC_ISPR2_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR2: SETPEND (Bit 0) */ +#define PPB_NVIC_ISPR2_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR2: SETPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ISPR3 ------------------------------- */ +#define PPB_NVIC_ISPR3_SETPEND_Pos (0UL) /*!< PPB NVIC_ISPR3: SETPEND (Bit 0) */ +#define PPB_NVIC_ISPR3_SETPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ISPR3: SETPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICPR0 ------------------------------- */ +#define PPB_NVIC_ICPR0_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR0: CLRPEND (Bit 0) */ +#define PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR0: CLRPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICPR1 ------------------------------- */ +#define PPB_NVIC_ICPR1_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR1: CLRPEND (Bit 0) */ +#define PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR1: CLRPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICPR2 ------------------------------- */ +#define PPB_NVIC_ICPR2_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR2: CLRPEND (Bit 0) */ +#define PPB_NVIC_ICPR2_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR2: CLRPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_ICPR3 ------------------------------- */ +#define PPB_NVIC_ICPR3_CLRPEND_Pos (0UL) /*!< PPB NVIC_ICPR3: CLRPEND (Bit 0) */ +#define PPB_NVIC_ICPR3_CLRPEND_Msk (0xffffffffUL) /*!< PPB NVIC_ICPR3: CLRPEND (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_IABR0 ------------------------------- */ +#define PPB_NVIC_IABR0_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR0: ACTIVE (Bit 0) */ +#define PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR0: ACTIVE (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_IABR1 ------------------------------- */ +#define PPB_NVIC_IABR1_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR1: ACTIVE (Bit 0) */ +#define PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR1: ACTIVE (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_IABR2 ------------------------------- */ +#define PPB_NVIC_IABR2_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR2: ACTIVE (Bit 0) */ +#define PPB_NVIC_IABR2_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR2: ACTIVE (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- PPB_NVIC_IABR3 ------------------------------- */ +#define PPB_NVIC_IABR3_ACTIVE_Pos (0UL) /*!< PPB NVIC_IABR3: ACTIVE (Bit 0) */ +#define PPB_NVIC_IABR3_ACTIVE_Msk (0xffffffffUL) /*!< PPB NVIC_IABR3: ACTIVE (Bitfield-Mask: 0xffffffff) */ + +/* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */ +#define PPB_NVIC_IPR0_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR0: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR0_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR0: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR0_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR0: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR0_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR0: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR0_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR0: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR0_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR0: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR0_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR0: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR0_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR0: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */ +#define PPB_NVIC_IPR1_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR1: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR1_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR1: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR1_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR1: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR1_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR1: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR1_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR1: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR1_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR1: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR1_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR1: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR1_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR1: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */ +#define PPB_NVIC_IPR2_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR2: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR2_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR2: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR2_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR2: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR2_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR2: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR2_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR2: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR2_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR2: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR2_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR2: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR2_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR2: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */ +#define PPB_NVIC_IPR3_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR3: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR3_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR3: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR3_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR3: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR3_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR3: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR3_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR3: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR3_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR3: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR3_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR3: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR3_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR3: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */ +#define PPB_NVIC_IPR4_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR4: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR4_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR4: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR4_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR4: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR4_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR4: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR4_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR4: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR4_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR4: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR4_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR4: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR4_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR4: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */ +#define PPB_NVIC_IPR5_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR5: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR5_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR5: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR5_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR5: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR5_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR5: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR5_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR5: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR5_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR5: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR5_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR5: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR5_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR5: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */ +#define PPB_NVIC_IPR6_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR6: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR6_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR6: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR6_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR6: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR6_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR6: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR6_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR6: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR6_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR6: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR6_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR6: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR6_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR6: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */ +#define PPB_NVIC_IPR7_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR7: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR7_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR7: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR7_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR7: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR7_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR7: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR7_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR7: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR7_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR7: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR7_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR7: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR7_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR7: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR8 ------------------------------- */ +#define PPB_NVIC_IPR8_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR8: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR8_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR8: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR8_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR8: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR8_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR8: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR8_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR8: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR8_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR8: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR8_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR8: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR8_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR8: PRI_3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_NVIC_IPR9 ------------------------------- */ +#define PPB_NVIC_IPR9_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR9: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR9_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR9: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR9_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR9: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR9_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR9: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR9_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR9: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR9_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR9: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR9_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR9: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR9_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR9: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR10 ------------------------------- */ +#define PPB_NVIC_IPR10_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR10: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR10_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR10: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR10_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR10: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR10_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR10: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR10_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR10: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR10_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR10: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR10_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR10: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR10_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR10: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR11 ------------------------------- */ +#define PPB_NVIC_IPR11_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR11: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR11_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR11: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR11_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR11: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR11_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR11: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR11_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR11: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR11_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR11: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR11_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR11: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR11_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR11: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR12 ------------------------------- */ +#define PPB_NVIC_IPR12_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR12: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR12_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR12: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR12_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR12: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR12_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR12: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR12_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR12: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR12_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR12: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR12_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR12: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR12_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR12: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR13 ------------------------------- */ +#define PPB_NVIC_IPR13_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR13: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR13_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR13: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR13_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR13: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR13_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR13: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR13_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR13: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR13_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR13: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR13_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR13: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR13_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR13: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR14 ------------------------------- */ +#define PPB_NVIC_IPR14_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR14: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR14_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR14: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR14_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR14: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR14_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR14: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR14_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR14: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR14_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR14: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR14_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR14: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR14_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR14: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR15 ------------------------------- */ +#define PPB_NVIC_IPR15_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR15: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR15_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR15: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR15_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR15: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR15_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR15: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR15_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR15: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR15_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR15: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR15_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR15: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR15_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR15: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR16 ------------------------------- */ +#define PPB_NVIC_IPR16_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR16: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR16_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR16: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR16_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR16: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR16_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR16: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR16_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR16: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR16_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR16: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR16_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR16: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR16_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR16: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR17 ------------------------------- */ +#define PPB_NVIC_IPR17_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR17: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR17_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR17: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR17_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR17: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR17_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR17: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR17_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR17: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR17_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR17: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR17_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR17: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR17_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR17: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR18 ------------------------------- */ +#define PPB_NVIC_IPR18_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR18: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR18_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR18: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR18_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR18: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR18_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR18: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR18_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR18: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR18_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR18: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR18_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR18: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR18_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR18: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR19 ------------------------------- */ +#define PPB_NVIC_IPR19_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR19: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR19_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR19: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR19_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR19: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR19_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR19: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR19_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR19: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR19_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR19: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR19_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR19: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR19_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR19: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR20 ------------------------------- */ +#define PPB_NVIC_IPR20_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR20: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR20_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR20: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR20_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR20: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR20_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR20: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR20_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR20: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR20_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR20: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR20_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR20: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR20_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR20: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR21 ------------------------------- */ +#define PPB_NVIC_IPR21_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR21: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR21_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR21: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR21_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR21: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR21_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR21: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR21_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR21: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR21_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR21: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR21_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR21: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR21_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR21: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR22 ------------------------------- */ +#define PPB_NVIC_IPR22_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR22: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR22_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR22: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR22_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR22: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR22_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR22: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR22_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR22: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR22_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR22: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR22_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR22: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR22_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR22: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR23 ------------------------------- */ +#define PPB_NVIC_IPR23_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR23: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR23_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR23: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR23_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR23: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR23_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR23: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR23_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR23: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR23_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR23: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR23_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR23: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR23_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR23: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR24 ------------------------------- */ +#define PPB_NVIC_IPR24_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR24: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR24_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR24: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR24_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR24: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR24_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR24: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR24_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR24: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR24_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR24: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR24_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR24: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR24_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR24: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR25 ------------------------------- */ +#define PPB_NVIC_IPR25_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR25: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR25_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR25: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR25_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR25: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR25_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR25: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR25_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR25: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR25_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR25: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR25_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR25: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR25_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR25: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR26 ------------------------------- */ +#define PPB_NVIC_IPR26_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR26: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR26_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR26: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR26_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR26: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR26_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR26: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR26_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR26: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR26_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR26: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR26_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR26: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR26_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR26: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- PPB_NVIC_IPR27 ------------------------------- */ +#define PPB_NVIC_IPR27_PRI_0_Pos (0UL) /*!< PPB NVIC_IPR27: PRI_0 (Bit 0) */ +#define PPB_NVIC_IPR27_PRI_0_Msk (0xffUL) /*!< PPB NVIC_IPR27: PRI_0 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR27_PRI_1_Pos (8UL) /*!< PPB NVIC_IPR27: PRI_1 (Bit 8) */ +#define PPB_NVIC_IPR27_PRI_1_Msk (0xff00UL) /*!< PPB NVIC_IPR27: PRI_1 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR27_PRI_2_Pos (16UL) /*!< PPB NVIC_IPR27: PRI_2 (Bit 16) */ +#define PPB_NVIC_IPR27_PRI_2_Msk (0xff0000UL) /*!< PPB NVIC_IPR27: PRI_2 (Bitfield-Mask: 0xff) */ +#define PPB_NVIC_IPR27_PRI_3_Pos (24UL) /*!< PPB NVIC_IPR27: PRI_3 (Bit 24) */ +#define PPB_NVIC_IPR27_PRI_3_Msk (0xff000000UL) /*!< PPB NVIC_IPR27: PRI_3 (Bitfield-Mask: 0xff) */ + +/* ---------------------------------- PPB_CPUID --------------------------------- */ +#define PPB_CPUID_Revision_Pos (0UL) /*!< PPB CPUID: Revision (Bit 0) */ +#define PPB_CPUID_Revision_Msk (0xfUL) /*!< PPB CPUID: Revision (Bitfield-Mask: 0x0f) */ +#define PPB_CPUID_PartNo_Pos (4UL) /*!< PPB CPUID: PartNo (Bit 4) */ +#define PPB_CPUID_PartNo_Msk (0xfff0UL) /*!< PPB CPUID: PartNo (Bitfield-Mask: 0xfff) */ +#define PPB_CPUID_Constant_Pos (16UL) /*!< PPB CPUID: Constant (Bit 16) */ +#define PPB_CPUID_Constant_Msk (0xf0000UL) /*!< PPB CPUID: Constant (Bitfield-Mask: 0x0f) */ +#define PPB_CPUID_Variant_Pos (20UL) /*!< PPB CPUID: Variant (Bit 20) */ +#define PPB_CPUID_Variant_Msk (0xf00000UL) /*!< PPB CPUID: Variant (Bitfield-Mask: 0x0f) */ +#define PPB_CPUID_Implementer_Pos (24UL) /*!< PPB CPUID: Implementer (Bit 24) */ +#define PPB_CPUID_Implementer_Msk (0xff000000UL) /*!< PPB CPUID: Implementer (Bitfield-Mask: 0xff) */ + +/* ---------------------------------- PPB_ICSR ---------------------------------- */ +#define PPB_ICSR_VECTACTIVE_Pos (0UL) /*!< PPB ICSR: VECTACTIVE (Bit 0) */ +#define PPB_ICSR_VECTACTIVE_Msk (0x1ffUL) /*!< PPB ICSR: VECTACTIVE (Bitfield-Mask: 0x1ff) */ +#define PPB_ICSR_RETTOBASE_Pos (11UL) /*!< PPB ICSR: RETTOBASE (Bit 11) */ +#define PPB_ICSR_RETTOBASE_Msk (0x800UL) /*!< PPB ICSR: RETTOBASE (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_VECTPENDING_Pos (12UL) /*!< PPB ICSR: VECTPENDING (Bit 12) */ +#define PPB_ICSR_VECTPENDING_Msk (0x3f000UL) /*!< PPB ICSR: VECTPENDING (Bitfield-Mask: 0x3f) */ +#define PPB_ICSR_ISRPENDING_Pos (22UL) /*!< PPB ICSR: ISRPENDING (Bit 22) */ +#define PPB_ICSR_ISRPENDING_Msk (0x400000UL) /*!< PPB ICSR: ISRPENDING (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSTCLR_Pos (25UL) /*!< PPB ICSR: PENDSTCLR (Bit 25) */ +#define PPB_ICSR_PENDSTCLR_Msk (0x2000000UL) /*!< PPB ICSR: PENDSTCLR (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSTSET_Pos (26UL) /*!< PPB ICSR: PENDSTSET (Bit 26) */ +#define PPB_ICSR_PENDSTSET_Msk (0x4000000UL) /*!< PPB ICSR: PENDSTSET (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSVCLR_Pos (27UL) /*!< PPB ICSR: PENDSVCLR (Bit 27) */ +#define PPB_ICSR_PENDSVCLR_Msk (0x8000000UL) /*!< PPB ICSR: PENDSVCLR (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_PENDSVSET_Pos (28UL) /*!< PPB ICSR: PENDSVSET (Bit 28) */ +#define PPB_ICSR_PENDSVSET_Msk (0x10000000UL) /*!< PPB ICSR: PENDSVSET (Bitfield-Mask: 0x01) */ +#define PPB_ICSR_NMIPENDSET_Pos (31UL) /*!< PPB ICSR: NMIPENDSET (Bit 31) */ +#define PPB_ICSR_NMIPENDSET_Msk (0x80000000UL) /*!< PPB ICSR: NMIPENDSET (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PPB_VTOR ---------------------------------- */ +#define PPB_VTOR_TBLOFF_Pos (10UL) /*!< PPB VTOR: TBLOFF (Bit 10) */ +#define PPB_VTOR_TBLOFF_Msk (0xfffffc00UL) /*!< PPB VTOR: TBLOFF (Bitfield-Mask: 0x3fffff) */ + +/* ---------------------------------- PPB_AIRCR --------------------------------- */ +#define PPB_AIRCR_VECTRESET_Pos (0UL) /*!< PPB AIRCR: VECTRESET (Bit 0) */ +#define PPB_AIRCR_VECTRESET_Msk (0x1UL) /*!< PPB AIRCR: VECTRESET (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_VECTCLRACTIVE_Pos (1UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bit 1) */ +#define PPB_AIRCR_VECTCLRACTIVE_Msk (0x2UL) /*!< PPB AIRCR: VECTCLRACTIVE (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_SYSRESETREQ_Pos (2UL) /*!< PPB AIRCR: SYSRESETREQ (Bit 2) */ +#define PPB_AIRCR_SYSRESETREQ_Msk (0x4UL) /*!< PPB AIRCR: SYSRESETREQ (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_PRIGROUP_Pos (8UL) /*!< PPB AIRCR: PRIGROUP (Bit 8) */ +#define PPB_AIRCR_PRIGROUP_Msk (0x700UL) /*!< PPB AIRCR: PRIGROUP (Bitfield-Mask: 0x07) */ +#define PPB_AIRCR_ENDIANNESS_Pos (15UL) /*!< PPB AIRCR: ENDIANNESS (Bit 15) */ +#define PPB_AIRCR_ENDIANNESS_Msk (0x8000UL) /*!< PPB AIRCR: ENDIANNESS (Bitfield-Mask: 0x01) */ +#define PPB_AIRCR_VECTKEY_Pos (16UL) /*!< PPB AIRCR: VECTKEY (Bit 16) */ +#define PPB_AIRCR_VECTKEY_Msk (0xffff0000UL) /*!< PPB AIRCR: VECTKEY (Bitfield-Mask: 0xffff) */ + +/* ----------------------------------- PPB_SCR ---------------------------------- */ +#define PPB_SCR_SLEEPONEXIT_Pos (1UL) /*!< PPB SCR: SLEEPONEXIT (Bit 1) */ +#define PPB_SCR_SLEEPONEXIT_Msk (0x2UL) /*!< PPB SCR: SLEEPONEXIT (Bitfield-Mask: 0x01) */ +#define PPB_SCR_SLEEPDEEP_Pos (2UL) /*!< PPB SCR: SLEEPDEEP (Bit 2) */ +#define PPB_SCR_SLEEPDEEP_Msk (0x4UL) /*!< PPB SCR: SLEEPDEEP (Bitfield-Mask: 0x01) */ +#define PPB_SCR_SEVONPEND_Pos (4UL) /*!< PPB SCR: SEVONPEND (Bit 4) */ +#define PPB_SCR_SEVONPEND_Msk (0x10UL) /*!< PPB SCR: SEVONPEND (Bitfield-Mask: 0x01) */ + +/* ----------------------------------- PPB_CCR ---------------------------------- */ +#define PPB_CCR_NONBASETHRDENA_Pos (0UL) /*!< PPB CCR: NONBASETHRDENA (Bit 0) */ +#define PPB_CCR_NONBASETHRDENA_Msk (0x1UL) /*!< PPB CCR: NONBASETHRDENA (Bitfield-Mask: 0x01) */ +#define PPB_CCR_USERSETMPEND_Pos (1UL) /*!< PPB CCR: USERSETMPEND (Bit 1) */ +#define PPB_CCR_USERSETMPEND_Msk (0x2UL) /*!< PPB CCR: USERSETMPEND (Bitfield-Mask: 0x01) */ +#define PPB_CCR_UNALIGN_TRP_Pos (3UL) /*!< PPB CCR: UNALIGN_TRP (Bit 3) */ +#define PPB_CCR_UNALIGN_TRP_Msk (0x8UL) /*!< PPB CCR: UNALIGN_TRP (Bitfield-Mask: 0x01) */ +#define PPB_CCR_DIV_0_TRP_Pos (4UL) /*!< PPB CCR: DIV_0_TRP (Bit 4) */ +#define PPB_CCR_DIV_0_TRP_Msk (0x10UL) /*!< PPB CCR: DIV_0_TRP (Bitfield-Mask: 0x01) */ +#define PPB_CCR_BFHFNMIGN_Pos (8UL) /*!< PPB CCR: BFHFNMIGN (Bit 8) */ +#define PPB_CCR_BFHFNMIGN_Msk (0x100UL) /*!< PPB CCR: BFHFNMIGN (Bitfield-Mask: 0x01) */ +#define PPB_CCR_STKALIGN_Pos (9UL) /*!< PPB CCR: STKALIGN (Bit 9) */ +#define PPB_CCR_STKALIGN_Msk (0x200UL) /*!< PPB CCR: STKALIGN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PPB_SHPR1 --------------------------------- */ +#define PPB_SHPR1_PRI_4_Pos (0UL) /*!< PPB SHPR1: PRI_4 (Bit 0) */ +#define PPB_SHPR1_PRI_4_Msk (0xffUL) /*!< PPB SHPR1: PRI_4 (Bitfield-Mask: 0xff) */ +#define PPB_SHPR1_PRI_5_Pos (8UL) /*!< PPB SHPR1: PRI_5 (Bit 8) */ +#define PPB_SHPR1_PRI_5_Msk (0xff00UL) /*!< PPB SHPR1: PRI_5 (Bitfield-Mask: 0xff) */ +#define PPB_SHPR1_PRI_6_Pos (16UL) /*!< PPB SHPR1: PRI_6 (Bit 16) */ +#define PPB_SHPR1_PRI_6_Msk (0xff0000UL) /*!< PPB SHPR1: PRI_6 (Bitfield-Mask: 0xff) */ + +/* ---------------------------------- PPB_SHPR2 --------------------------------- */ +#define PPB_SHPR2_PRI_11_Pos (24UL) /*!< PPB SHPR2: PRI_11 (Bit 24) */ +#define PPB_SHPR2_PRI_11_Msk (0xff000000UL) /*!< PPB SHPR2: PRI_11 (Bitfield-Mask: 0xff) */ + +/* ---------------------------------- PPB_SHPR3 --------------------------------- */ +#define PPB_SHPR3_PRI_14_Pos (16UL) /*!< PPB SHPR3: PRI_14 (Bit 16) */ +#define PPB_SHPR3_PRI_14_Msk (0xff0000UL) /*!< PPB SHPR3: PRI_14 (Bitfield-Mask: 0xff) */ +#define PPB_SHPR3_PRI_15_Pos (24UL) /*!< PPB SHPR3: PRI_15 (Bit 24) */ +#define PPB_SHPR3_PRI_15_Msk (0xff000000UL) /*!< PPB SHPR3: PRI_15 (Bitfield-Mask: 0xff) */ + +/* ---------------------------------- PPB_SHCSR --------------------------------- */ +#define PPB_SHCSR_MEMFAULTACT_Pos (0UL) /*!< PPB SHCSR: MEMFAULTACT (Bit 0) */ +#define PPB_SHCSR_MEMFAULTACT_Msk (0x1UL) /*!< PPB SHCSR: MEMFAULTACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_BUSFAULTACT_Pos (1UL) /*!< PPB SHCSR: BUSFAULTACT (Bit 1) */ +#define PPB_SHCSR_BUSFAULTACT_Msk (0x2UL) /*!< PPB SHCSR: BUSFAULTACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_USGFAULTACT_Pos (3UL) /*!< PPB SHCSR: USGFAULTACT (Bit 3) */ +#define PPB_SHCSR_USGFAULTACT_Msk (0x8UL) /*!< PPB SHCSR: USGFAULTACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SVCALLACT_Pos (7UL) /*!< PPB SHCSR: SVCALLACT (Bit 7) */ +#define PPB_SHCSR_SVCALLACT_Msk (0x80UL) /*!< PPB SHCSR: SVCALLACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_MONITORACT_Pos (8UL) /*!< PPB SHCSR: MONITORACT (Bit 8) */ +#define PPB_SHCSR_MONITORACT_Msk (0x100UL) /*!< PPB SHCSR: MONITORACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_PENDSVACT_Pos (10UL) /*!< PPB SHCSR: PENDSVACT (Bit 10) */ +#define PPB_SHCSR_PENDSVACT_Msk (0x400UL) /*!< PPB SHCSR: PENDSVACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SYSTICKACT_Pos (11UL) /*!< PPB SHCSR: SYSTICKACT (Bit 11) */ +#define PPB_SHCSR_SYSTICKACT_Msk (0x800UL) /*!< PPB SHCSR: SYSTICKACT (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_USGFAULTPENDED_Pos (12UL) /*!< PPB SHCSR: USGFAULTPENDED (Bit 12) */ +#define PPB_SHCSR_USGFAULTPENDED_Msk (0x1000UL) /*!< PPB SHCSR: USGFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_MEMFAULTPENDED_Pos (13UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bit 13) */ +#define PPB_SHCSR_MEMFAULTPENDED_Msk (0x2000UL) /*!< PPB SHCSR: MEMFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_BUSFAULTPENDED_Pos (14UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bit 14) */ +#define PPB_SHCSR_BUSFAULTPENDED_Msk (0x4000UL) /*!< PPB SHCSR: BUSFAULTPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_SVCALLPENDED_Pos (15UL) /*!< PPB SHCSR: SVCALLPENDED (Bit 15) */ +#define PPB_SHCSR_SVCALLPENDED_Msk (0x8000UL) /*!< PPB SHCSR: SVCALLPENDED (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_MEMFAULTENA_Pos (16UL) /*!< PPB SHCSR: MEMFAULTENA (Bit 16) */ +#define PPB_SHCSR_MEMFAULTENA_Msk (0x10000UL) /*!< PPB SHCSR: MEMFAULTENA (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_BUSFAULTENA_Pos (17UL) /*!< PPB SHCSR: BUSFAULTENA (Bit 17) */ +#define PPB_SHCSR_BUSFAULTENA_Msk (0x20000UL) /*!< PPB SHCSR: BUSFAULTENA (Bitfield-Mask: 0x01) */ +#define PPB_SHCSR_USGFAULTENA_Pos (18UL) /*!< PPB SHCSR: USGFAULTENA (Bit 18) */ +#define PPB_SHCSR_USGFAULTENA_Msk (0x40000UL) /*!< PPB SHCSR: USGFAULTENA (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PPB_CFSR ---------------------------------- */ +#define PPB_CFSR_IACCVIOL_Pos (0UL) /*!< PPB CFSR: IACCVIOL (Bit 0) */ +#define PPB_CFSR_IACCVIOL_Msk (0x1UL) /*!< PPB CFSR: IACCVIOL (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_DACCVIOL_Pos (1UL) /*!< PPB CFSR: DACCVIOL (Bit 1) */ +#define PPB_CFSR_DACCVIOL_Msk (0x2UL) /*!< PPB CFSR: DACCVIOL (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_MUNSTKERR_Pos (3UL) /*!< PPB CFSR: MUNSTKERR (Bit 3) */ +#define PPB_CFSR_MUNSTKERR_Msk (0x8UL) /*!< PPB CFSR: MUNSTKERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_MSTKERR_Pos (4UL) /*!< PPB CFSR: MSTKERR (Bit 4) */ +#define PPB_CFSR_MSTKERR_Msk (0x10UL) /*!< PPB CFSR: MSTKERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_MLSPERR_Pos (5UL) /*!< PPB CFSR: MLSPERR (Bit 5) */ +#define PPB_CFSR_MLSPERR_Msk (0x20UL) /*!< PPB CFSR: MLSPERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_MMARVALID_Pos (7UL) /*!< PPB CFSR: MMARVALID (Bit 7) */ +#define PPB_CFSR_MMARVALID_Msk (0x80UL) /*!< PPB CFSR: MMARVALID (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_IBUSERR_Pos (8UL) /*!< PPB CFSR: IBUSERR (Bit 8) */ +#define PPB_CFSR_IBUSERR_Msk (0x100UL) /*!< PPB CFSR: IBUSERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_PRECISERR_Pos (9UL) /*!< PPB CFSR: PRECISERR (Bit 9) */ +#define PPB_CFSR_PRECISERR_Msk (0x200UL) /*!< PPB CFSR: PRECISERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_IMPRECISERR_Pos (10UL) /*!< PPB CFSR: IMPRECISERR (Bit 10) */ +#define PPB_CFSR_IMPRECISERR_Msk (0x400UL) /*!< PPB CFSR: IMPRECISERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UNSTKERR_Pos (11UL) /*!< PPB CFSR: UNSTKERR (Bit 11) */ +#define PPB_CFSR_UNSTKERR_Msk (0x800UL) /*!< PPB CFSR: UNSTKERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_STKERR_Pos (12UL) /*!< PPB CFSR: STKERR (Bit 12) */ +#define PPB_CFSR_STKERR_Msk (0x1000UL) /*!< PPB CFSR: STKERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_LSPERR_Pos (13UL) /*!< PPB CFSR: LSPERR (Bit 13) */ +#define PPB_CFSR_LSPERR_Msk (0x2000UL) /*!< PPB CFSR: LSPERR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_BFARVALID_Pos (15UL) /*!< PPB CFSR: BFARVALID (Bit 15) */ +#define PPB_CFSR_BFARVALID_Msk (0x8000UL) /*!< PPB CFSR: BFARVALID (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UNDEFINSTR_Pos (16UL) /*!< PPB CFSR: UNDEFINSTR (Bit 16) */ +#define PPB_CFSR_UNDEFINSTR_Msk (0x10000UL) /*!< PPB CFSR: UNDEFINSTR (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_INVSTATE_Pos (17UL) /*!< PPB CFSR: INVSTATE (Bit 17) */ +#define PPB_CFSR_INVSTATE_Msk (0x20000UL) /*!< PPB CFSR: INVSTATE (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_INVPC_Pos (18UL) /*!< PPB CFSR: INVPC (Bit 18) */ +#define PPB_CFSR_INVPC_Msk (0x40000UL) /*!< PPB CFSR: INVPC (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_NOCP_Pos (19UL) /*!< PPB CFSR: NOCP (Bit 19) */ +#define PPB_CFSR_NOCP_Msk (0x80000UL) /*!< PPB CFSR: NOCP (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_UNALIGNED_Pos (24UL) /*!< PPB CFSR: UNALIGNED (Bit 24) */ +#define PPB_CFSR_UNALIGNED_Msk (0x1000000UL) /*!< PPB CFSR: UNALIGNED (Bitfield-Mask: 0x01) */ +#define PPB_CFSR_DIVBYZERO_Pos (25UL) /*!< PPB CFSR: DIVBYZERO (Bit 25) */ +#define PPB_CFSR_DIVBYZERO_Msk (0x2000000UL) /*!< PPB CFSR: DIVBYZERO (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PPB_HFSR ---------------------------------- */ +#define PPB_HFSR_VECTTBL_Pos (1UL) /*!< PPB HFSR: VECTTBL (Bit 1) */ +#define PPB_HFSR_VECTTBL_Msk (0x2UL) /*!< PPB HFSR: VECTTBL (Bitfield-Mask: 0x01) */ +#define PPB_HFSR_FORCED_Pos (30UL) /*!< PPB HFSR: FORCED (Bit 30) */ +#define PPB_HFSR_FORCED_Msk (0x40000000UL) /*!< PPB HFSR: FORCED (Bitfield-Mask: 0x01) */ +#define PPB_HFSR_DEBUGEVT_Pos (31UL) /*!< PPB HFSR: DEBUGEVT (Bit 31) */ +#define PPB_HFSR_DEBUGEVT_Msk (0x80000000UL) /*!< PPB HFSR: DEBUGEVT (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PPB_MMFAR --------------------------------- */ +#define PPB_MMFAR_ADDRESS_Pos (0UL) /*!< PPB MMFAR: ADDRESS (Bit 0) */ +#define PPB_MMFAR_ADDRESS_Msk (0xffffffffUL) /*!< PPB MMFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ + +/* ---------------------------------- PPB_BFAR ---------------------------------- */ +#define PPB_BFAR_ADDRESS_Pos (0UL) /*!< PPB BFAR: ADDRESS (Bit 0) */ +#define PPB_BFAR_ADDRESS_Msk (0xffffffffUL) /*!< PPB BFAR: ADDRESS (Bitfield-Mask: 0xffffffff) */ + +/* ---------------------------------- PPB_AFSR ---------------------------------- */ +#define PPB_AFSR_VALUE_Pos (0UL) /*!< PPB AFSR: VALUE (Bit 0) */ +#define PPB_AFSR_VALUE_Msk (0xffffffffUL) /*!< PPB AFSR: VALUE (Bitfield-Mask: 0xffffffff) */ + +/* ---------------------------------- PPB_CPACR --------------------------------- */ +#define PPB_CPACR_CP10_Pos (20UL) /*!< PPB CPACR: CP10 (Bit 20) */ +#define PPB_CPACR_CP10_Msk (0x300000UL) /*!< PPB CPACR: CP10 (Bitfield-Mask: 0x03) */ +#define PPB_CPACR_CP11_Pos (22UL) /*!< PPB CPACR: CP11 (Bit 22) */ +#define PPB_CPACR_CP11_Msk (0xc00000UL) /*!< PPB CPACR: CP11 (Bitfield-Mask: 0x03) */ + +/* -------------------------------- PPB_MPU_TYPE -------------------------------- */ +#define PPB_MPU_TYPE_SEPARATE_Pos (0UL) /*!< PPB MPU_TYPE: SEPARATE (Bit 0) */ +#define PPB_MPU_TYPE_SEPARATE_Msk (0x1UL) /*!< PPB MPU_TYPE: SEPARATE (Bitfield-Mask: 0x01) */ +#define PPB_MPU_TYPE_DREGION_Pos (8UL) /*!< PPB MPU_TYPE: DREGION (Bit 8) */ +#define PPB_MPU_TYPE_DREGION_Msk (0xff00UL) /*!< PPB MPU_TYPE: DREGION (Bitfield-Mask: 0xff) */ +#define PPB_MPU_TYPE_IREGION_Pos (16UL) /*!< PPB MPU_TYPE: IREGION (Bit 16) */ +#define PPB_MPU_TYPE_IREGION_Msk (0xff0000UL) /*!< PPB MPU_TYPE: IREGION (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_MPU_CTRL -------------------------------- */ +#define PPB_MPU_CTRL_ENABLE_Pos (0UL) /*!< PPB MPU_CTRL: ENABLE (Bit 0) */ +#define PPB_MPU_CTRL_ENABLE_Msk (0x1UL) /*!< PPB MPU_CTRL: ENABLE (Bitfield-Mask: 0x01) */ +#define PPB_MPU_CTRL_HFNMIENA_Pos (1UL) /*!< PPB MPU_CTRL: HFNMIENA (Bit 1) */ +#define PPB_MPU_CTRL_HFNMIENA_Msk (0x2UL) /*!< PPB MPU_CTRL: HFNMIENA (Bitfield-Mask: 0x01) */ +#define PPB_MPU_CTRL_PRIVDEFENA_Pos (2UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bit 2) */ +#define PPB_MPU_CTRL_PRIVDEFENA_Msk (0x4UL) /*!< PPB MPU_CTRL: PRIVDEFENA (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PPB_MPU_RNR -------------------------------- */ +#define PPB_MPU_RNR_REGION_Pos (0UL) /*!< PPB MPU_RNR: REGION (Bit 0) */ +#define PPB_MPU_RNR_REGION_Msk (0xffUL) /*!< PPB MPU_RNR: REGION (Bitfield-Mask: 0xff) */ + +/* -------------------------------- PPB_MPU_RBAR -------------------------------- */ +#define PPB_MPU_RBAR_REGION_Pos (0UL) /*!< PPB MPU_RBAR: REGION (Bit 0) */ +#define PPB_MPU_RBAR_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR: REGION (Bitfield-Mask: 0x0f) */ +#define PPB_MPU_RBAR_VALID_Pos (4UL) /*!< PPB MPU_RBAR: VALID (Bit 4) */ +#define PPB_MPU_RBAR_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR: VALID (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RBAR_ADDR_Pos (9UL) /*!< PPB MPU_RBAR: ADDR (Bit 9) */ +#define PPB_MPU_RBAR_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR: ADDR (Bitfield-Mask: 0x7fffff) */ + +/* -------------------------------- PPB_MPU_RASR -------------------------------- */ +#define PPB_MPU_RASR_ENABLE_Pos (0UL) /*!< PPB MPU_RASR: ENABLE (Bit 0) */ +#define PPB_MPU_RASR_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR: ENABLE (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_SIZE_Pos (1UL) /*!< PPB MPU_RASR: SIZE (Bit 1) */ +#define PPB_MPU_RASR_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR: SIZE (Bitfield-Mask: 0x1f) */ +#define PPB_MPU_RASR_SRD_Pos (8UL) /*!< PPB MPU_RASR: SRD (Bit 8) */ +#define PPB_MPU_RASR_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR: SRD (Bitfield-Mask: 0xff) */ +#define PPB_MPU_RASR_B_Pos (16UL) /*!< PPB MPU_RASR: B (Bit 16) */ +#define PPB_MPU_RASR_B_Msk (0x10000UL) /*!< PPB MPU_RASR: B (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_C_Pos (17UL) /*!< PPB MPU_RASR: C (Bit 17) */ +#define PPB_MPU_RASR_C_Msk (0x20000UL) /*!< PPB MPU_RASR: C (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_S_Pos (18UL) /*!< PPB MPU_RASR: S (Bit 18) */ +#define PPB_MPU_RASR_S_Msk (0x40000UL) /*!< PPB MPU_RASR: S (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_TEX_Pos (19UL) /*!< PPB MPU_RASR: TEX (Bit 19) */ +#define PPB_MPU_RASR_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR: TEX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_AP_Pos (24UL) /*!< PPB MPU_RASR: AP (Bit 24) */ +#define PPB_MPU_RASR_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR: AP (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_XN_Pos (28UL) /*!< PPB MPU_RASR: XN (Bit 28) */ +#define PPB_MPU_RASR_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR: XN (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PPB_MPU_RBAR_A1 ------------------------------ */ +#define PPB_MPU_RBAR_A1_REGION_Pos (0UL) /*!< PPB MPU_RBAR_A1: REGION (Bit 0) */ +#define PPB_MPU_RBAR_A1_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR_A1: REGION (Bitfield-Mask: 0x0f) */ +#define PPB_MPU_RBAR_A1_VALID_Pos (4UL) /*!< PPB MPU_RBAR_A1: VALID (Bit 4) */ +#define PPB_MPU_RBAR_A1_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR_A1: VALID (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RBAR_A1_ADDR_Pos (9UL) /*!< PPB MPU_RBAR_A1: ADDR (Bit 9) */ +#define PPB_MPU_RBAR_A1_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR_A1: ADDR (Bitfield-Mask: 0x7fffff) */ + +/* ------------------------------- PPB_MPU_RASR_A1 ------------------------------ */ +#define PPB_MPU_RASR_A1_ENABLE_Pos (0UL) /*!< PPB MPU_RASR_A1: ENABLE (Bit 0) */ +#define PPB_MPU_RASR_A1_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR_A1: ENABLE (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A1_SIZE_Pos (1UL) /*!< PPB MPU_RASR_A1: SIZE (Bit 1) */ +#define PPB_MPU_RASR_A1_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR_A1: SIZE (Bitfield-Mask: 0x1f) */ +#define PPB_MPU_RASR_A1_SRD_Pos (8UL) /*!< PPB MPU_RASR_A1: SRD (Bit 8) */ +#define PPB_MPU_RASR_A1_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR_A1: SRD (Bitfield-Mask: 0xff) */ +#define PPB_MPU_RASR_A1_B_Pos (16UL) /*!< PPB MPU_RASR_A1: B (Bit 16) */ +#define PPB_MPU_RASR_A1_B_Msk (0x10000UL) /*!< PPB MPU_RASR_A1: B (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A1_C_Pos (17UL) /*!< PPB MPU_RASR_A1: C (Bit 17) */ +#define PPB_MPU_RASR_A1_C_Msk (0x20000UL) /*!< PPB MPU_RASR_A1: C (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A1_S_Pos (18UL) /*!< PPB MPU_RASR_A1: S (Bit 18) */ +#define PPB_MPU_RASR_A1_S_Msk (0x40000UL) /*!< PPB MPU_RASR_A1: S (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A1_TEX_Pos (19UL) /*!< PPB MPU_RASR_A1: TEX (Bit 19) */ +#define PPB_MPU_RASR_A1_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR_A1: TEX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_A1_AP_Pos (24UL) /*!< PPB MPU_RASR_A1: AP (Bit 24) */ +#define PPB_MPU_RASR_A1_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR_A1: AP (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_A1_XN_Pos (28UL) /*!< PPB MPU_RASR_A1: XN (Bit 28) */ +#define PPB_MPU_RASR_A1_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR_A1: XN (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PPB_MPU_RBAR_A2 ------------------------------ */ +#define PPB_MPU_RBAR_A2_REGION_Pos (0UL) /*!< PPB MPU_RBAR_A2: REGION (Bit 0) */ +#define PPB_MPU_RBAR_A2_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR_A2: REGION (Bitfield-Mask: 0x0f) */ +#define PPB_MPU_RBAR_A2_VALID_Pos (4UL) /*!< PPB MPU_RBAR_A2: VALID (Bit 4) */ +#define PPB_MPU_RBAR_A2_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR_A2: VALID (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RBAR_A2_ADDR_Pos (9UL) /*!< PPB MPU_RBAR_A2: ADDR (Bit 9) */ +#define PPB_MPU_RBAR_A2_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR_A2: ADDR (Bitfield-Mask: 0x7fffff) */ + +/* ------------------------------- PPB_MPU_RASR_A2 ------------------------------ */ +#define PPB_MPU_RASR_A2_ENABLE_Pos (0UL) /*!< PPB MPU_RASR_A2: ENABLE (Bit 0) */ +#define PPB_MPU_RASR_A2_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR_A2: ENABLE (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A2_SIZE_Pos (1UL) /*!< PPB MPU_RASR_A2: SIZE (Bit 1) */ +#define PPB_MPU_RASR_A2_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR_A2: SIZE (Bitfield-Mask: 0x1f) */ +#define PPB_MPU_RASR_A2_SRD_Pos (8UL) /*!< PPB MPU_RASR_A2: SRD (Bit 8) */ +#define PPB_MPU_RASR_A2_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR_A2: SRD (Bitfield-Mask: 0xff) */ +#define PPB_MPU_RASR_A2_B_Pos (16UL) /*!< PPB MPU_RASR_A2: B (Bit 16) */ +#define PPB_MPU_RASR_A2_B_Msk (0x10000UL) /*!< PPB MPU_RASR_A2: B (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A2_C_Pos (17UL) /*!< PPB MPU_RASR_A2: C (Bit 17) */ +#define PPB_MPU_RASR_A2_C_Msk (0x20000UL) /*!< PPB MPU_RASR_A2: C (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A2_S_Pos (18UL) /*!< PPB MPU_RASR_A2: S (Bit 18) */ +#define PPB_MPU_RASR_A2_S_Msk (0x40000UL) /*!< PPB MPU_RASR_A2: S (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A2_TEX_Pos (19UL) /*!< PPB MPU_RASR_A2: TEX (Bit 19) */ +#define PPB_MPU_RASR_A2_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR_A2: TEX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_A2_AP_Pos (24UL) /*!< PPB MPU_RASR_A2: AP (Bit 24) */ +#define PPB_MPU_RASR_A2_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR_A2: AP (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_A2_XN_Pos (28UL) /*!< PPB MPU_RASR_A2: XN (Bit 28) */ +#define PPB_MPU_RASR_A2_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR_A2: XN (Bitfield-Mask: 0x01) */ + +/* ------------------------------- PPB_MPU_RBAR_A3 ------------------------------ */ +#define PPB_MPU_RBAR_A3_REGION_Pos (0UL) /*!< PPB MPU_RBAR_A3: REGION (Bit 0) */ +#define PPB_MPU_RBAR_A3_REGION_Msk (0xfUL) /*!< PPB MPU_RBAR_A3: REGION (Bitfield-Mask: 0x0f) */ +#define PPB_MPU_RBAR_A3_VALID_Pos (4UL) /*!< PPB MPU_RBAR_A3: VALID (Bit 4) */ +#define PPB_MPU_RBAR_A3_VALID_Msk (0x10UL) /*!< PPB MPU_RBAR_A3: VALID (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RBAR_A3_ADDR_Pos (9UL) /*!< PPB MPU_RBAR_A3: ADDR (Bit 9) */ +#define PPB_MPU_RBAR_A3_ADDR_Msk (0xfffffe00UL) /*!< PPB MPU_RBAR_A3: ADDR (Bitfield-Mask: 0x7fffff) */ + +/* ------------------------------- PPB_MPU_RASR_A3 ------------------------------ */ +#define PPB_MPU_RASR_A3_ENABLE_Pos (0UL) /*!< PPB MPU_RASR_A3: ENABLE (Bit 0) */ +#define PPB_MPU_RASR_A3_ENABLE_Msk (0x1UL) /*!< PPB MPU_RASR_A3: ENABLE (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A3_SIZE_Pos (1UL) /*!< PPB MPU_RASR_A3: SIZE (Bit 1) */ +#define PPB_MPU_RASR_A3_SIZE_Msk (0x3eUL) /*!< PPB MPU_RASR_A3: SIZE (Bitfield-Mask: 0x1f) */ +#define PPB_MPU_RASR_A3_SRD_Pos (8UL) /*!< PPB MPU_RASR_A3: SRD (Bit 8) */ +#define PPB_MPU_RASR_A3_SRD_Msk (0xff00UL) /*!< PPB MPU_RASR_A3: SRD (Bitfield-Mask: 0xff) */ +#define PPB_MPU_RASR_A3_B_Pos (16UL) /*!< PPB MPU_RASR_A3: B (Bit 16) */ +#define PPB_MPU_RASR_A3_B_Msk (0x10000UL) /*!< PPB MPU_RASR_A3: B (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A3_C_Pos (17UL) /*!< PPB MPU_RASR_A3: C (Bit 17) */ +#define PPB_MPU_RASR_A3_C_Msk (0x20000UL) /*!< PPB MPU_RASR_A3: C (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A3_S_Pos (18UL) /*!< PPB MPU_RASR_A3: S (Bit 18) */ +#define PPB_MPU_RASR_A3_S_Msk (0x40000UL) /*!< PPB MPU_RASR_A3: S (Bitfield-Mask: 0x01) */ +#define PPB_MPU_RASR_A3_TEX_Pos (19UL) /*!< PPB MPU_RASR_A3: TEX (Bit 19) */ +#define PPB_MPU_RASR_A3_TEX_Msk (0x380000UL) /*!< PPB MPU_RASR_A3: TEX (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_A3_AP_Pos (24UL) /*!< PPB MPU_RASR_A3: AP (Bit 24) */ +#define PPB_MPU_RASR_A3_AP_Msk (0x7000000UL) /*!< PPB MPU_RASR_A3: AP (Bitfield-Mask: 0x07) */ +#define PPB_MPU_RASR_A3_XN_Pos (28UL) /*!< PPB MPU_RASR_A3: XN (Bit 28) */ +#define PPB_MPU_RASR_A3_XN_Msk (0x10000000UL) /*!< PPB MPU_RASR_A3: XN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PPB_STIR ---------------------------------- */ +#define PPB_STIR_INTID_Pos (0UL) /*!< PPB STIR: INTID (Bit 0) */ +#define PPB_STIR_INTID_Msk (0x1ffUL) /*!< PPB STIR: INTID (Bitfield-Mask: 0x1ff) */ + +/* ---------------------------------- PPB_FPCCR --------------------------------- */ +#define PPB_FPCCR_LSPACT_Pos (0UL) /*!< PPB FPCCR: LSPACT (Bit 0) */ +#define PPB_FPCCR_LSPACT_Msk (0x1UL) /*!< PPB FPCCR: LSPACT (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_USER_Pos (1UL) /*!< PPB FPCCR: USER (Bit 1) */ +#define PPB_FPCCR_USER_Msk (0x2UL) /*!< PPB FPCCR: USER (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_THREAD_Pos (3UL) /*!< PPB FPCCR: THREAD (Bit 3) */ +#define PPB_FPCCR_THREAD_Msk (0x8UL) /*!< PPB FPCCR: THREAD (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_HFRDY_Pos (4UL) /*!< PPB FPCCR: HFRDY (Bit 4) */ +#define PPB_FPCCR_HFRDY_Msk (0x10UL) /*!< PPB FPCCR: HFRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_MMRDY_Pos (5UL) /*!< PPB FPCCR: MMRDY (Bit 5) */ +#define PPB_FPCCR_MMRDY_Msk (0x20UL) /*!< PPB FPCCR: MMRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_BFRDY_Pos (6UL) /*!< PPB FPCCR: BFRDY (Bit 6) */ +#define PPB_FPCCR_BFRDY_Msk (0x40UL) /*!< PPB FPCCR: BFRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_MONRDY_Pos (8UL) /*!< PPB FPCCR: MONRDY (Bit 8) */ +#define PPB_FPCCR_MONRDY_Msk (0x100UL) /*!< PPB FPCCR: MONRDY (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_LSPEN_Pos (30UL) /*!< PPB FPCCR: LSPEN (Bit 30) */ +#define PPB_FPCCR_LSPEN_Msk (0x40000000UL) /*!< PPB FPCCR: LSPEN (Bitfield-Mask: 0x01) */ +#define PPB_FPCCR_ASPEN_Pos (31UL) /*!< PPB FPCCR: ASPEN (Bit 31) */ +#define PPB_FPCCR_ASPEN_Msk (0x80000000UL) /*!< PPB FPCCR: ASPEN (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PPB_FPCAR --------------------------------- */ +#define PPB_FPCAR_ADDRESS_Pos (3UL) /*!< PPB FPCAR: ADDRESS (Bit 3) */ +#define PPB_FPCAR_ADDRESS_Msk (0xfffffff8UL) /*!< PPB FPCAR: ADDRESS (Bitfield-Mask: 0x1fffffff) */ + +/* --------------------------------- PPB_FPDSCR --------------------------------- */ +#define PPB_FPDSCR_RMode_Pos (22UL) /*!< PPB FPDSCR: RMode (Bit 22) */ +#define PPB_FPDSCR_RMode_Msk (0xc00000UL) /*!< PPB FPDSCR: RMode (Bitfield-Mask: 0x03) */ +#define PPB_FPDSCR_FZ_Pos (24UL) /*!< PPB FPDSCR: FZ (Bit 24) */ +#define PPB_FPDSCR_FZ_Msk (0x1000000UL) /*!< PPB FPDSCR: FZ (Bitfield-Mask: 0x01) */ +#define PPB_FPDSCR_DN_Pos (25UL) /*!< PPB FPDSCR: DN (Bit 25) */ +#define PPB_FPDSCR_DN_Msk (0x2000000UL) /*!< PPB FPDSCR: DN (Bitfield-Mask: 0x01) */ +#define PPB_FPDSCR_AHP_Pos (26UL) /*!< PPB FPDSCR: AHP (Bit 26) */ +#define PPB_FPDSCR_AHP_Msk (0x4000000UL) /*!< PPB FPDSCR: AHP (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'DLR' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- DLR_OVRSTAT -------------------------------- */ +#define DLR_OVRSTAT_LN0_Pos (0UL) /*!< DLR OVRSTAT: LN0 (Bit 0) */ +#define DLR_OVRSTAT_LN0_Msk (0x1UL) /*!< DLR OVRSTAT: LN0 (Bitfield-Mask: 0x01) */ +#define DLR_OVRSTAT_LN1_Pos (1UL) /*!< DLR OVRSTAT: LN1 (Bit 1) */ +#define DLR_OVRSTAT_LN1_Msk (0x2UL) /*!< DLR OVRSTAT: LN1 (Bitfield-Mask: 0x01) */ +#define DLR_OVRSTAT_LN2_Pos (2UL) /*!< DLR OVRSTAT: LN2 (Bit 2) */ +#define DLR_OVRSTAT_LN2_Msk (0x4UL) /*!< DLR OVRSTAT: LN2 (Bitfield-Mask: 0x01) */ +#define DLR_OVRSTAT_LN3_Pos (3UL) /*!< DLR OVRSTAT: LN3 (Bit 3) */ +#define DLR_OVRSTAT_LN3_Msk (0x8UL) /*!< DLR OVRSTAT: LN3 (Bitfield-Mask: 0x01) */ +#define DLR_OVRSTAT_LN4_Pos (4UL) /*!< DLR OVRSTAT: LN4 (Bit 4) */ +#define DLR_OVRSTAT_LN4_Msk (0x10UL) /*!< DLR OVRSTAT: LN4 (Bitfield-Mask: 0x01) */ +#define DLR_OVRSTAT_LN5_Pos (5UL) /*!< DLR OVRSTAT: LN5 (Bit 5) */ +#define DLR_OVRSTAT_LN5_Msk (0x20UL) /*!< DLR OVRSTAT: LN5 (Bitfield-Mask: 0x01) */ +#define DLR_OVRSTAT_LN6_Pos (6UL) /*!< DLR OVRSTAT: LN6 (Bit 6) */ +#define DLR_OVRSTAT_LN6_Msk (0x40UL) /*!< DLR OVRSTAT: LN6 (Bitfield-Mask: 0x01) */ +#define DLR_OVRSTAT_LN7_Pos (7UL) /*!< DLR OVRSTAT: LN7 (Bit 7) */ +#define DLR_OVRSTAT_LN7_Msk (0x80UL) /*!< DLR OVRSTAT: LN7 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- DLR_OVRCLR --------------------------------- */ +#define DLR_OVRCLR_LN0_Pos (0UL) /*!< DLR OVRCLR: LN0 (Bit 0) */ +#define DLR_OVRCLR_LN0_Msk (0x1UL) /*!< DLR OVRCLR: LN0 (Bitfield-Mask: 0x01) */ +#define DLR_OVRCLR_LN1_Pos (1UL) /*!< DLR OVRCLR: LN1 (Bit 1) */ +#define DLR_OVRCLR_LN1_Msk (0x2UL) /*!< DLR OVRCLR: LN1 (Bitfield-Mask: 0x01) */ +#define DLR_OVRCLR_LN2_Pos (2UL) /*!< DLR OVRCLR: LN2 (Bit 2) */ +#define DLR_OVRCLR_LN2_Msk (0x4UL) /*!< DLR OVRCLR: LN2 (Bitfield-Mask: 0x01) */ +#define DLR_OVRCLR_LN3_Pos (3UL) /*!< DLR OVRCLR: LN3 (Bit 3) */ +#define DLR_OVRCLR_LN3_Msk (0x8UL) /*!< DLR OVRCLR: LN3 (Bitfield-Mask: 0x01) */ +#define DLR_OVRCLR_LN4_Pos (4UL) /*!< DLR OVRCLR: LN4 (Bit 4) */ +#define DLR_OVRCLR_LN4_Msk (0x10UL) /*!< DLR OVRCLR: LN4 (Bitfield-Mask: 0x01) */ +#define DLR_OVRCLR_LN5_Pos (5UL) /*!< DLR OVRCLR: LN5 (Bit 5) */ +#define DLR_OVRCLR_LN5_Msk (0x20UL) /*!< DLR OVRCLR: LN5 (Bitfield-Mask: 0x01) */ +#define DLR_OVRCLR_LN6_Pos (6UL) /*!< DLR OVRCLR: LN6 (Bit 6) */ +#define DLR_OVRCLR_LN6_Msk (0x40UL) /*!< DLR OVRCLR: LN6 (Bitfield-Mask: 0x01) */ +#define DLR_OVRCLR_LN7_Pos (7UL) /*!< DLR OVRCLR: LN7 (Bit 7) */ +#define DLR_OVRCLR_LN7_Msk (0x80UL) /*!< DLR OVRCLR: LN7 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- DLR_SRSEL0 --------------------------------- */ +#define DLR_SRSEL0_RS0_Pos (0UL) /*!< DLR SRSEL0: RS0 (Bit 0) */ +#define DLR_SRSEL0_RS0_Msk (0xfUL) /*!< DLR SRSEL0: RS0 (Bitfield-Mask: 0x0f) */ +#define DLR_SRSEL0_RS1_Pos (4UL) /*!< DLR SRSEL0: RS1 (Bit 4) */ +#define DLR_SRSEL0_RS1_Msk (0xf0UL) /*!< DLR SRSEL0: RS1 (Bitfield-Mask: 0x0f) */ +#define DLR_SRSEL0_RS2_Pos (8UL) /*!< DLR SRSEL0: RS2 (Bit 8) */ +#define DLR_SRSEL0_RS2_Msk (0xf00UL) /*!< DLR SRSEL0: RS2 (Bitfield-Mask: 0x0f) */ +#define DLR_SRSEL0_RS3_Pos (12UL) /*!< DLR SRSEL0: RS3 (Bit 12) */ +#define DLR_SRSEL0_RS3_Msk (0xf000UL) /*!< DLR SRSEL0: RS3 (Bitfield-Mask: 0x0f) */ +#define DLR_SRSEL0_RS4_Pos (16UL) /*!< DLR SRSEL0: RS4 (Bit 16) */ +#define DLR_SRSEL0_RS4_Msk (0xf0000UL) /*!< DLR SRSEL0: RS4 (Bitfield-Mask: 0x0f) */ +#define DLR_SRSEL0_RS5_Pos (20UL) /*!< DLR SRSEL0: RS5 (Bit 20) */ +#define DLR_SRSEL0_RS5_Msk (0xf00000UL) /*!< DLR SRSEL0: RS5 (Bitfield-Mask: 0x0f) */ +#define DLR_SRSEL0_RS6_Pos (24UL) /*!< DLR SRSEL0: RS6 (Bit 24) */ +#define DLR_SRSEL0_RS6_Msk (0xf000000UL) /*!< DLR SRSEL0: RS6 (Bitfield-Mask: 0x0f) */ +#define DLR_SRSEL0_RS7_Pos (28UL) /*!< DLR SRSEL0: RS7 (Bit 28) */ +#define DLR_SRSEL0_RS7_Msk (0xf0000000UL) /*!< DLR SRSEL0: RS7 (Bitfield-Mask: 0x0f) */ + +/* ---------------------------------- DLR_LNEN ---------------------------------- */ +#define DLR_LNEN_LN0_Pos (0UL) /*!< DLR LNEN: LN0 (Bit 0) */ +#define DLR_LNEN_LN0_Msk (0x1UL) /*!< DLR LNEN: LN0 (Bitfield-Mask: 0x01) */ +#define DLR_LNEN_LN1_Pos (1UL) /*!< DLR LNEN: LN1 (Bit 1) */ +#define DLR_LNEN_LN1_Msk (0x2UL) /*!< DLR LNEN: LN1 (Bitfield-Mask: 0x01) */ +#define DLR_LNEN_LN2_Pos (2UL) /*!< DLR LNEN: LN2 (Bit 2) */ +#define DLR_LNEN_LN2_Msk (0x4UL) /*!< DLR LNEN: LN2 (Bitfield-Mask: 0x01) */ +#define DLR_LNEN_LN3_Pos (3UL) /*!< DLR LNEN: LN3 (Bit 3) */ +#define DLR_LNEN_LN3_Msk (0x8UL) /*!< DLR LNEN: LN3 (Bitfield-Mask: 0x01) */ +#define DLR_LNEN_LN4_Pos (4UL) /*!< DLR LNEN: LN4 (Bit 4) */ +#define DLR_LNEN_LN4_Msk (0x10UL) /*!< DLR LNEN: LN4 (Bitfield-Mask: 0x01) */ +#define DLR_LNEN_LN5_Pos (5UL) /*!< DLR LNEN: LN5 (Bit 5) */ +#define DLR_LNEN_LN5_Msk (0x20UL) /*!< DLR LNEN: LN5 (Bitfield-Mask: 0x01) */ +#define DLR_LNEN_LN6_Pos (6UL) /*!< DLR LNEN: LN6 (Bit 6) */ +#define DLR_LNEN_LN6_Msk (0x40UL) /*!< DLR LNEN: LN6 (Bitfield-Mask: 0x01) */ +#define DLR_LNEN_LN7_Pos (7UL) /*!< DLR LNEN: LN7 (Bit 7) */ +#define DLR_LNEN_LN7_Msk (0x80UL) /*!< DLR LNEN: LN7 (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'ERU' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- ERU_EXISEL --------------------------------- */ +#define ERU_EXISEL_EXS0A_Pos (0UL) /*!< ERU EXISEL: EXS0A (Bit 0) */ +#define ERU_EXISEL_EXS0A_Msk (0x3UL) /*!< ERU EXISEL: EXS0A (Bitfield-Mask: 0x03) */ +#define ERU_EXISEL_EXS0B_Pos (2UL) /*!< ERU EXISEL: EXS0B (Bit 2) */ +#define ERU_EXISEL_EXS0B_Msk (0xcUL) /*!< ERU EXISEL: EXS0B (Bitfield-Mask: 0x03) */ +#define ERU_EXISEL_EXS1A_Pos (4UL) /*!< ERU EXISEL: EXS1A (Bit 4) */ +#define ERU_EXISEL_EXS1A_Msk (0x30UL) /*!< ERU EXISEL: EXS1A (Bitfield-Mask: 0x03) */ +#define ERU_EXISEL_EXS1B_Pos (6UL) /*!< ERU EXISEL: EXS1B (Bit 6) */ +#define ERU_EXISEL_EXS1B_Msk (0xc0UL) /*!< ERU EXISEL: EXS1B (Bitfield-Mask: 0x03) */ +#define ERU_EXISEL_EXS2A_Pos (8UL) /*!< ERU EXISEL: EXS2A (Bit 8) */ +#define ERU_EXISEL_EXS2A_Msk (0x300UL) /*!< ERU EXISEL: EXS2A (Bitfield-Mask: 0x03) */ +#define ERU_EXISEL_EXS2B_Pos (10UL) /*!< ERU EXISEL: EXS2B (Bit 10) */ +#define ERU_EXISEL_EXS2B_Msk (0xc00UL) /*!< ERU EXISEL: EXS2B (Bitfield-Mask: 0x03) */ +#define ERU_EXISEL_EXS3A_Pos (12UL) /*!< ERU EXISEL: EXS3A (Bit 12) */ +#define ERU_EXISEL_EXS3A_Msk (0x3000UL) /*!< ERU EXISEL: EXS3A (Bitfield-Mask: 0x03) */ +#define ERU_EXISEL_EXS3B_Pos (14UL) /*!< ERU EXISEL: EXS3B (Bit 14) */ +#define ERU_EXISEL_EXS3B_Msk (0xc000UL) /*!< ERU EXISEL: EXS3B (Bitfield-Mask: 0x03) */ + +/* --------------------------------- ERU_EXICON --------------------------------- */ +#define ERU_EXICON_PE_Pos (0UL) /*!< ERU EXICON: PE (Bit 0) */ +#define ERU_EXICON_PE_Msk (0x1UL) /*!< ERU EXICON: PE (Bitfield-Mask: 0x01) */ +#define ERU_EXICON_LD_Pos (1UL) /*!< ERU EXICON: LD (Bit 1) */ +#define ERU_EXICON_LD_Msk (0x2UL) /*!< ERU EXICON: LD (Bitfield-Mask: 0x01) */ +#define ERU_EXICON_RE_Pos (2UL) /*!< ERU EXICON: RE (Bit 2) */ +#define ERU_EXICON_RE_Msk (0x4UL) /*!< ERU EXICON: RE (Bitfield-Mask: 0x01) */ +#define ERU_EXICON_FE_Pos (3UL) /*!< ERU EXICON: FE (Bit 3) */ +#define ERU_EXICON_FE_Msk (0x8UL) /*!< ERU EXICON: FE (Bitfield-Mask: 0x01) */ +#define ERU_EXICON_OCS_Pos (4UL) /*!< ERU EXICON: OCS (Bit 4) */ +#define ERU_EXICON_OCS_Msk (0x70UL) /*!< ERU EXICON: OCS (Bitfield-Mask: 0x07) */ +#define ERU_EXICON_FL_Pos (7UL) /*!< ERU EXICON: FL (Bit 7) */ +#define ERU_EXICON_FL_Msk (0x80UL) /*!< ERU EXICON: FL (Bitfield-Mask: 0x01) */ +#define ERU_EXICON_SS_Pos (8UL) /*!< ERU EXICON: SS (Bit 8) */ +#define ERU_EXICON_SS_Msk (0x300UL) /*!< ERU EXICON: SS (Bitfield-Mask: 0x03) */ +#define ERU_EXICON_NA_Pos (10UL) /*!< ERU EXICON: NA (Bit 10) */ +#define ERU_EXICON_NA_Msk (0x400UL) /*!< ERU EXICON: NA (Bitfield-Mask: 0x01) */ +#define ERU_EXICON_NB_Pos (11UL) /*!< ERU EXICON: NB (Bit 11) */ +#define ERU_EXICON_NB_Msk (0x800UL) /*!< ERU EXICON: NB (Bitfield-Mask: 0x01) */ + +/* --------------------------------- ERU_EXOCON --------------------------------- */ +#define ERU_EXOCON_ISS_Pos (0UL) /*!< ERU EXOCON: ISS (Bit 0) */ +#define ERU_EXOCON_ISS_Msk (0x3UL) /*!< ERU EXOCON: ISS (Bitfield-Mask: 0x03) */ +#define ERU_EXOCON_GEEN_Pos (2UL) /*!< ERU EXOCON: GEEN (Bit 2) */ +#define ERU_EXOCON_GEEN_Msk (0x4UL) /*!< ERU EXOCON: GEEN (Bitfield-Mask: 0x01) */ +#define ERU_EXOCON_PDR_Pos (3UL) /*!< ERU EXOCON: PDR (Bit 3) */ +#define ERU_EXOCON_PDR_Msk (0x8UL) /*!< ERU EXOCON: PDR (Bitfield-Mask: 0x01) */ +#define ERU_EXOCON_GP_Pos (4UL) /*!< ERU EXOCON: GP (Bit 4) */ +#define ERU_EXOCON_GP_Msk (0x30UL) /*!< ERU EXOCON: GP (Bitfield-Mask: 0x03) */ +#define ERU_EXOCON_IPEN0_Pos (12UL) /*!< ERU EXOCON: IPEN0 (Bit 12) */ +#define ERU_EXOCON_IPEN0_Msk (0x1000UL) /*!< ERU EXOCON: IPEN0 (Bitfield-Mask: 0x01) */ +#define ERU_EXOCON_IPEN1_Pos (13UL) /*!< ERU EXOCON: IPEN1 (Bit 13) */ +#define ERU_EXOCON_IPEN1_Msk (0x2000UL) /*!< ERU EXOCON: IPEN1 (Bitfield-Mask: 0x01) */ +#define ERU_EXOCON_IPEN2_Pos (14UL) /*!< ERU EXOCON: IPEN2 (Bit 14) */ +#define ERU_EXOCON_IPEN2_Msk (0x4000UL) /*!< ERU EXOCON: IPEN2 (Bitfield-Mask: 0x01) */ +#define ERU_EXOCON_IPEN3_Pos (15UL) /*!< ERU EXOCON: IPEN3 (Bit 15) */ +#define ERU_EXOCON_IPEN3_Msk (0x8000UL) /*!< ERU EXOCON: IPEN3 (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'GPDMA0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- GPDMA0_RAWTFR ------------------------------- */ +#define GPDMA0_RAWTFR_CH0_Pos (0UL) /*!< GPDMA0 RAWTFR: CH0 (Bit 0) */ +#define GPDMA0_RAWTFR_CH0_Msk (0x1UL) /*!< GPDMA0 RAWTFR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWTFR_CH1_Pos (1UL) /*!< GPDMA0 RAWTFR: CH1 (Bit 1) */ +#define GPDMA0_RAWTFR_CH1_Msk (0x2UL) /*!< GPDMA0 RAWTFR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWTFR_CH2_Pos (2UL) /*!< GPDMA0 RAWTFR: CH2 (Bit 2) */ +#define GPDMA0_RAWTFR_CH2_Msk (0x4UL) /*!< GPDMA0 RAWTFR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWTFR_CH3_Pos (3UL) /*!< GPDMA0 RAWTFR: CH3 (Bit 3) */ +#define GPDMA0_RAWTFR_CH3_Msk (0x8UL) /*!< GPDMA0 RAWTFR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWTFR_CH4_Pos (4UL) /*!< GPDMA0 RAWTFR: CH4 (Bit 4) */ +#define GPDMA0_RAWTFR_CH4_Msk (0x10UL) /*!< GPDMA0 RAWTFR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWTFR_CH5_Pos (5UL) /*!< GPDMA0 RAWTFR: CH5 (Bit 5) */ +#define GPDMA0_RAWTFR_CH5_Msk (0x20UL) /*!< GPDMA0 RAWTFR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWTFR_CH6_Pos (6UL) /*!< GPDMA0 RAWTFR: CH6 (Bit 6) */ +#define GPDMA0_RAWTFR_CH6_Msk (0x40UL) /*!< GPDMA0 RAWTFR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWTFR_CH7_Pos (7UL) /*!< GPDMA0 RAWTFR: CH7 (Bit 7) */ +#define GPDMA0_RAWTFR_CH7_Msk (0x80UL) /*!< GPDMA0 RAWTFR: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- GPDMA0_RAWBLOCK ------------------------------ */ +#define GPDMA0_RAWBLOCK_CH0_Pos (0UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bit 0) */ +#define GPDMA0_RAWBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 RAWBLOCK: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWBLOCK_CH1_Pos (1UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bit 1) */ +#define GPDMA0_RAWBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 RAWBLOCK: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWBLOCK_CH2_Pos (2UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bit 2) */ +#define GPDMA0_RAWBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 RAWBLOCK: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWBLOCK_CH3_Pos (3UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bit 3) */ +#define GPDMA0_RAWBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 RAWBLOCK: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWBLOCK_CH4_Pos (4UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bit 4) */ +#define GPDMA0_RAWBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 RAWBLOCK: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWBLOCK_CH5_Pos (5UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bit 5) */ +#define GPDMA0_RAWBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 RAWBLOCK: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWBLOCK_CH6_Pos (6UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bit 6) */ +#define GPDMA0_RAWBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 RAWBLOCK: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWBLOCK_CH7_Pos (7UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bit 7) */ +#define GPDMA0_RAWBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 RAWBLOCK: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_RAWSRCTRAN ----------------------------- */ +#define GPDMA0_RAWSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bit 0) */ +#define GPDMA0_RAWSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 RAWSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bit 1) */ +#define GPDMA0_RAWSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 RAWSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bit 2) */ +#define GPDMA0_RAWSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 RAWSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bit 3) */ +#define GPDMA0_RAWSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 RAWSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bit 4) */ +#define GPDMA0_RAWSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 RAWSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bit 5) */ +#define GPDMA0_RAWSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 RAWSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bit 6) */ +#define GPDMA0_RAWSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 RAWSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bit 7) */ +#define GPDMA0_RAWSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 RAWSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_RAWDSTTRAN ----------------------------- */ +#define GPDMA0_RAWDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bit 0) */ +#define GPDMA0_RAWDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 RAWDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bit 1) */ +#define GPDMA0_RAWDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 RAWDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bit 2) */ +#define GPDMA0_RAWDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 RAWDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bit 3) */ +#define GPDMA0_RAWDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 RAWDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bit 4) */ +#define GPDMA0_RAWDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 RAWDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bit 5) */ +#define GPDMA0_RAWDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 RAWDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bit 6) */ +#define GPDMA0_RAWDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 RAWDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bit 7) */ +#define GPDMA0_RAWDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 RAWDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- GPDMA0_RAWERR ------------------------------- */ +#define GPDMA0_RAWERR_CH0_Pos (0UL) /*!< GPDMA0 RAWERR: CH0 (Bit 0) */ +#define GPDMA0_RAWERR_CH0_Msk (0x1UL) /*!< GPDMA0 RAWERR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWERR_CH1_Pos (1UL) /*!< GPDMA0 RAWERR: CH1 (Bit 1) */ +#define GPDMA0_RAWERR_CH1_Msk (0x2UL) /*!< GPDMA0 RAWERR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWERR_CH2_Pos (2UL) /*!< GPDMA0 RAWERR: CH2 (Bit 2) */ +#define GPDMA0_RAWERR_CH2_Msk (0x4UL) /*!< GPDMA0 RAWERR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWERR_CH3_Pos (3UL) /*!< GPDMA0 RAWERR: CH3 (Bit 3) */ +#define GPDMA0_RAWERR_CH3_Msk (0x8UL) /*!< GPDMA0 RAWERR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWERR_CH4_Pos (4UL) /*!< GPDMA0 RAWERR: CH4 (Bit 4) */ +#define GPDMA0_RAWERR_CH4_Msk (0x10UL) /*!< GPDMA0 RAWERR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWERR_CH5_Pos (5UL) /*!< GPDMA0 RAWERR: CH5 (Bit 5) */ +#define GPDMA0_RAWERR_CH5_Msk (0x20UL) /*!< GPDMA0 RAWERR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWERR_CH6_Pos (6UL) /*!< GPDMA0 RAWERR: CH6 (Bit 6) */ +#define GPDMA0_RAWERR_CH6_Msk (0x40UL) /*!< GPDMA0 RAWERR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_RAWERR_CH7_Pos (7UL) /*!< GPDMA0 RAWERR: CH7 (Bit 7) */ +#define GPDMA0_RAWERR_CH7_Msk (0x80UL) /*!< GPDMA0 RAWERR: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_STATUSTFR ------------------------------ */ +#define GPDMA0_STATUSTFR_CH0_Pos (0UL) /*!< GPDMA0 STATUSTFR: CH0 (Bit 0) */ +#define GPDMA0_STATUSTFR_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSTFR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSTFR_CH1_Pos (1UL) /*!< GPDMA0 STATUSTFR: CH1 (Bit 1) */ +#define GPDMA0_STATUSTFR_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSTFR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSTFR_CH2_Pos (2UL) /*!< GPDMA0 STATUSTFR: CH2 (Bit 2) */ +#define GPDMA0_STATUSTFR_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSTFR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSTFR_CH3_Pos (3UL) /*!< GPDMA0 STATUSTFR: CH3 (Bit 3) */ +#define GPDMA0_STATUSTFR_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSTFR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSTFR_CH4_Pos (4UL) /*!< GPDMA0 STATUSTFR: CH4 (Bit 4) */ +#define GPDMA0_STATUSTFR_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSTFR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSTFR_CH5_Pos (5UL) /*!< GPDMA0 STATUSTFR: CH5 (Bit 5) */ +#define GPDMA0_STATUSTFR_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSTFR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSTFR_CH6_Pos (6UL) /*!< GPDMA0 STATUSTFR: CH6 (Bit 6) */ +#define GPDMA0_STATUSTFR_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSTFR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSTFR_CH7_Pos (7UL) /*!< GPDMA0 STATUSTFR: CH7 (Bit 7) */ +#define GPDMA0_STATUSTFR_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSTFR: CH7 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_STATUSBLOCK ----------------------------- */ +#define GPDMA0_STATUSBLOCK_CH0_Pos (0UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bit 0) */ +#define GPDMA0_STATUSBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSBLOCK: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSBLOCK_CH1_Pos (1UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bit 1) */ +#define GPDMA0_STATUSBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSBLOCK: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSBLOCK_CH2_Pos (2UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bit 2) */ +#define GPDMA0_STATUSBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSBLOCK: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSBLOCK_CH3_Pos (3UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bit 3) */ +#define GPDMA0_STATUSBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSBLOCK: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSBLOCK_CH4_Pos (4UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bit 4) */ +#define GPDMA0_STATUSBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSBLOCK: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSBLOCK_CH5_Pos (5UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bit 5) */ +#define GPDMA0_STATUSBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSBLOCK: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSBLOCK_CH6_Pos (6UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bit 6) */ +#define GPDMA0_STATUSBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSBLOCK: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSBLOCK_CH7_Pos (7UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bit 7) */ +#define GPDMA0_STATUSBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSBLOCK: CH7 (Bitfield-Mask: 0x01) */ + +/* ---------------------------- GPDMA0_STATUSSRCTRAN ---------------------------- */ +#define GPDMA0_STATUSSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bit 0) */ +#define GPDMA0_STATUSSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bit 1) */ +#define GPDMA0_STATUSSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bit 2) */ +#define GPDMA0_STATUSSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bit 3) */ +#define GPDMA0_STATUSSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bit 4) */ +#define GPDMA0_STATUSSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bit 5) */ +#define GPDMA0_STATUSSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bit 6) */ +#define GPDMA0_STATUSSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bit 7) */ +#define GPDMA0_STATUSSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ + +/* ---------------------------- GPDMA0_STATUSDSTTRAN ---------------------------- */ +#define GPDMA0_STATUSDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bit 0) */ +#define GPDMA0_STATUSDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bit 1) */ +#define GPDMA0_STATUSDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bit 2) */ +#define GPDMA0_STATUSDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bit 3) */ +#define GPDMA0_STATUSDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bit 4) */ +#define GPDMA0_STATUSDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bit 5) */ +#define GPDMA0_STATUSDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bit 6) */ +#define GPDMA0_STATUSDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bit 7) */ +#define GPDMA0_STATUSDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_STATUSERR ------------------------------ */ +#define GPDMA0_STATUSERR_CH0_Pos (0UL) /*!< GPDMA0 STATUSERR: CH0 (Bit 0) */ +#define GPDMA0_STATUSERR_CH0_Msk (0x1UL) /*!< GPDMA0 STATUSERR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSERR_CH1_Pos (1UL) /*!< GPDMA0 STATUSERR: CH1 (Bit 1) */ +#define GPDMA0_STATUSERR_CH1_Msk (0x2UL) /*!< GPDMA0 STATUSERR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSERR_CH2_Pos (2UL) /*!< GPDMA0 STATUSERR: CH2 (Bit 2) */ +#define GPDMA0_STATUSERR_CH2_Msk (0x4UL) /*!< GPDMA0 STATUSERR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSERR_CH3_Pos (3UL) /*!< GPDMA0 STATUSERR: CH3 (Bit 3) */ +#define GPDMA0_STATUSERR_CH3_Msk (0x8UL) /*!< GPDMA0 STATUSERR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSERR_CH4_Pos (4UL) /*!< GPDMA0 STATUSERR: CH4 (Bit 4) */ +#define GPDMA0_STATUSERR_CH4_Msk (0x10UL) /*!< GPDMA0 STATUSERR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSERR_CH5_Pos (5UL) /*!< GPDMA0 STATUSERR: CH5 (Bit 5) */ +#define GPDMA0_STATUSERR_CH5_Msk (0x20UL) /*!< GPDMA0 STATUSERR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSERR_CH6_Pos (6UL) /*!< GPDMA0 STATUSERR: CH6 (Bit 6) */ +#define GPDMA0_STATUSERR_CH6_Msk (0x40UL) /*!< GPDMA0 STATUSERR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSERR_CH7_Pos (7UL) /*!< GPDMA0 STATUSERR: CH7 (Bit 7) */ +#define GPDMA0_STATUSERR_CH7_Msk (0x80UL) /*!< GPDMA0 STATUSERR: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- GPDMA0_MASKTFR ------------------------------- */ +#define GPDMA0_MASKTFR_CH0_Pos (0UL) /*!< GPDMA0 MASKTFR: CH0 (Bit 0) */ +#define GPDMA0_MASKTFR_CH0_Msk (0x1UL) /*!< GPDMA0 MASKTFR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_CH1_Pos (1UL) /*!< GPDMA0 MASKTFR: CH1 (Bit 1) */ +#define GPDMA0_MASKTFR_CH1_Msk (0x2UL) /*!< GPDMA0 MASKTFR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_CH2_Pos (2UL) /*!< GPDMA0 MASKTFR: CH2 (Bit 2) */ +#define GPDMA0_MASKTFR_CH2_Msk (0x4UL) /*!< GPDMA0 MASKTFR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_CH3_Pos (3UL) /*!< GPDMA0 MASKTFR: CH3 (Bit 3) */ +#define GPDMA0_MASKTFR_CH3_Msk (0x8UL) /*!< GPDMA0 MASKTFR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_CH4_Pos (4UL) /*!< GPDMA0 MASKTFR: CH4 (Bit 4) */ +#define GPDMA0_MASKTFR_CH4_Msk (0x10UL) /*!< GPDMA0 MASKTFR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_CH5_Pos (5UL) /*!< GPDMA0 MASKTFR: CH5 (Bit 5) */ +#define GPDMA0_MASKTFR_CH5_Msk (0x20UL) /*!< GPDMA0 MASKTFR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_CH6_Pos (6UL) /*!< GPDMA0 MASKTFR: CH6 (Bit 6) */ +#define GPDMA0_MASKTFR_CH6_Msk (0x40UL) /*!< GPDMA0 MASKTFR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_CH7_Pos (7UL) /*!< GPDMA0 MASKTFR: CH7 (Bit 7) */ +#define GPDMA0_MASKTFR_CH7_Msk (0x80UL) /*!< GPDMA0 MASKTFR: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bit 8) */ +#define GPDMA0_MASKTFR_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKTFR: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bit 9) */ +#define GPDMA0_MASKTFR_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKTFR: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bit 10) */ +#define GPDMA0_MASKTFR_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKTFR: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bit 11) */ +#define GPDMA0_MASKTFR_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKTFR: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bit 12) */ +#define GPDMA0_MASKTFR_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKTFR: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bit 13) */ +#define GPDMA0_MASKTFR_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKTFR: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bit 14) */ +#define GPDMA0_MASKTFR_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKTFR: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKTFR_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bit 15) */ +#define GPDMA0_MASKTFR_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKTFR: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_MASKBLOCK ------------------------------ */ +#define GPDMA0_MASKBLOCK_CH0_Pos (0UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bit 0) */ +#define GPDMA0_MASKBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 MASKBLOCK: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_CH1_Pos (1UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bit 1) */ +#define GPDMA0_MASKBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 MASKBLOCK: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_CH2_Pos (2UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bit 2) */ +#define GPDMA0_MASKBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 MASKBLOCK: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_CH3_Pos (3UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bit 3) */ +#define GPDMA0_MASKBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 MASKBLOCK: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_CH4_Pos (4UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bit 4) */ +#define GPDMA0_MASKBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 MASKBLOCK: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_CH5_Pos (5UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bit 5) */ +#define GPDMA0_MASKBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 MASKBLOCK: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_CH6_Pos (6UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bit 6) */ +#define GPDMA0_MASKBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 MASKBLOCK: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_CH7_Pos (7UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bit 7) */ +#define GPDMA0_MASKBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 MASKBLOCK: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bit 8) */ +#define GPDMA0_MASKBLOCK_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKBLOCK: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bit 9) */ +#define GPDMA0_MASKBLOCK_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKBLOCK: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bit 10) */ +#define GPDMA0_MASKBLOCK_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKBLOCK: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bit 11) */ +#define GPDMA0_MASKBLOCK_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKBLOCK: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bit 12) */ +#define GPDMA0_MASKBLOCK_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKBLOCK: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bit 13) */ +#define GPDMA0_MASKBLOCK_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKBLOCK: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bit 14) */ +#define GPDMA0_MASKBLOCK_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKBLOCK: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKBLOCK_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bit 15) */ +#define GPDMA0_MASKBLOCK_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKBLOCK: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_MASKSRCTRAN ----------------------------- */ +#define GPDMA0_MASKSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bit 0) */ +#define GPDMA0_MASKSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 MASKSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bit 1) */ +#define GPDMA0_MASKSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 MASKSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bit 2) */ +#define GPDMA0_MASKSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 MASKSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bit 3) */ +#define GPDMA0_MASKSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 MASKSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bit 4) */ +#define GPDMA0_MASKSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 MASKSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bit 5) */ +#define GPDMA0_MASKSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 MASKSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bit 6) */ +#define GPDMA0_MASKSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 MASKSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bit 7) */ +#define GPDMA0_MASKSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 MASKSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bit 8) */ +#define GPDMA0_MASKSRCTRAN_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bit 9) */ +#define GPDMA0_MASKSRCTRAN_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bit 10) */ +#define GPDMA0_MASKSRCTRAN_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bit 11) */ +#define GPDMA0_MASKSRCTRAN_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bit 12) */ +#define GPDMA0_MASKSRCTRAN_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bit 13) */ +#define GPDMA0_MASKSRCTRAN_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bit 14) */ +#define GPDMA0_MASKSRCTRAN_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKSRCTRAN_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bit 15) */ +#define GPDMA0_MASKSRCTRAN_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKSRCTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_MASKDSTTRAN ----------------------------- */ +#define GPDMA0_MASKDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bit 0) */ +#define GPDMA0_MASKDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 MASKDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bit 1) */ +#define GPDMA0_MASKDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 MASKDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bit 2) */ +#define GPDMA0_MASKDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 MASKDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bit 3) */ +#define GPDMA0_MASKDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 MASKDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bit 4) */ +#define GPDMA0_MASKDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 MASKDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bit 5) */ +#define GPDMA0_MASKDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 MASKDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bit 6) */ +#define GPDMA0_MASKDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 MASKDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bit 7) */ +#define GPDMA0_MASKDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 MASKDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bit 8) */ +#define GPDMA0_MASKDSTTRAN_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bit 9) */ +#define GPDMA0_MASKDSTTRAN_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bit 10) */ +#define GPDMA0_MASKDSTTRAN_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bit 11) */ +#define GPDMA0_MASKDSTTRAN_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bit 12) */ +#define GPDMA0_MASKDSTTRAN_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bit 13) */ +#define GPDMA0_MASKDSTTRAN_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bit 14) */ +#define GPDMA0_MASKDSTTRAN_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKDSTTRAN_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bit 15) */ +#define GPDMA0_MASKDSTTRAN_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKDSTTRAN: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- GPDMA0_MASKERR ------------------------------- */ +#define GPDMA0_MASKERR_CH0_Pos (0UL) /*!< GPDMA0 MASKERR: CH0 (Bit 0) */ +#define GPDMA0_MASKERR_CH0_Msk (0x1UL) /*!< GPDMA0 MASKERR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_CH1_Pos (1UL) /*!< GPDMA0 MASKERR: CH1 (Bit 1) */ +#define GPDMA0_MASKERR_CH1_Msk (0x2UL) /*!< GPDMA0 MASKERR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_CH2_Pos (2UL) /*!< GPDMA0 MASKERR: CH2 (Bit 2) */ +#define GPDMA0_MASKERR_CH2_Msk (0x4UL) /*!< GPDMA0 MASKERR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_CH3_Pos (3UL) /*!< GPDMA0 MASKERR: CH3 (Bit 3) */ +#define GPDMA0_MASKERR_CH3_Msk (0x8UL) /*!< GPDMA0 MASKERR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_CH4_Pos (4UL) /*!< GPDMA0 MASKERR: CH4 (Bit 4) */ +#define GPDMA0_MASKERR_CH4_Msk (0x10UL) /*!< GPDMA0 MASKERR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_CH5_Pos (5UL) /*!< GPDMA0 MASKERR: CH5 (Bit 5) */ +#define GPDMA0_MASKERR_CH5_Msk (0x20UL) /*!< GPDMA0 MASKERR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_CH6_Pos (6UL) /*!< GPDMA0 MASKERR: CH6 (Bit 6) */ +#define GPDMA0_MASKERR_CH6_Msk (0x40UL) /*!< GPDMA0 MASKERR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_CH7_Pos (7UL) /*!< GPDMA0 MASKERR: CH7 (Bit 7) */ +#define GPDMA0_MASKERR_CH7_Msk (0x80UL) /*!< GPDMA0 MASKERR: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH0_Pos (8UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bit 8) */ +#define GPDMA0_MASKERR_WE_CH0_Msk (0x100UL) /*!< GPDMA0 MASKERR: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH1_Pos (9UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bit 9) */ +#define GPDMA0_MASKERR_WE_CH1_Msk (0x200UL) /*!< GPDMA0 MASKERR: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH2_Pos (10UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bit 10) */ +#define GPDMA0_MASKERR_WE_CH2_Msk (0x400UL) /*!< GPDMA0 MASKERR: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH3_Pos (11UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bit 11) */ +#define GPDMA0_MASKERR_WE_CH3_Msk (0x800UL) /*!< GPDMA0 MASKERR: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH4_Pos (12UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bit 12) */ +#define GPDMA0_MASKERR_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 MASKERR: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH5_Pos (13UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bit 13) */ +#define GPDMA0_MASKERR_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 MASKERR: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH6_Pos (14UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bit 14) */ +#define GPDMA0_MASKERR_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 MASKERR: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_MASKERR_WE_CH7_Pos (15UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bit 15) */ +#define GPDMA0_MASKERR_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 MASKERR: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- GPDMA0_CLEARTFR ------------------------------ */ +#define GPDMA0_CLEARTFR_CH0_Pos (0UL) /*!< GPDMA0 CLEARTFR: CH0 (Bit 0) */ +#define GPDMA0_CLEARTFR_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARTFR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARTFR_CH1_Pos (1UL) /*!< GPDMA0 CLEARTFR: CH1 (Bit 1) */ +#define GPDMA0_CLEARTFR_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARTFR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARTFR_CH2_Pos (2UL) /*!< GPDMA0 CLEARTFR: CH2 (Bit 2) */ +#define GPDMA0_CLEARTFR_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARTFR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARTFR_CH3_Pos (3UL) /*!< GPDMA0 CLEARTFR: CH3 (Bit 3) */ +#define GPDMA0_CLEARTFR_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARTFR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARTFR_CH4_Pos (4UL) /*!< GPDMA0 CLEARTFR: CH4 (Bit 4) */ +#define GPDMA0_CLEARTFR_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARTFR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARTFR_CH5_Pos (5UL) /*!< GPDMA0 CLEARTFR: CH5 (Bit 5) */ +#define GPDMA0_CLEARTFR_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARTFR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARTFR_CH6_Pos (6UL) /*!< GPDMA0 CLEARTFR: CH6 (Bit 6) */ +#define GPDMA0_CLEARTFR_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARTFR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARTFR_CH7_Pos (7UL) /*!< GPDMA0 CLEARTFR: CH7 (Bit 7) */ +#define GPDMA0_CLEARTFR_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARTFR: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_CLEARBLOCK ----------------------------- */ +#define GPDMA0_CLEARBLOCK_CH0_Pos (0UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bit 0) */ +#define GPDMA0_CLEARBLOCK_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARBLOCK: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARBLOCK_CH1_Pos (1UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bit 1) */ +#define GPDMA0_CLEARBLOCK_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARBLOCK: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARBLOCK_CH2_Pos (2UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bit 2) */ +#define GPDMA0_CLEARBLOCK_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARBLOCK: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARBLOCK_CH3_Pos (3UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bit 3) */ +#define GPDMA0_CLEARBLOCK_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARBLOCK: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARBLOCK_CH4_Pos (4UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bit 4) */ +#define GPDMA0_CLEARBLOCK_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARBLOCK: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARBLOCK_CH5_Pos (5UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bit 5) */ +#define GPDMA0_CLEARBLOCK_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARBLOCK: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARBLOCK_CH6_Pos (6UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bit 6) */ +#define GPDMA0_CLEARBLOCK_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARBLOCK: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARBLOCK_CH7_Pos (7UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bit 7) */ +#define GPDMA0_CLEARBLOCK_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARBLOCK: CH7 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_CLEARSRCTRAN ---------------------------- */ +#define GPDMA0_CLEARSRCTRAN_CH0_Pos (0UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bit 0) */ +#define GPDMA0_CLEARSRCTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARSRCTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARSRCTRAN_CH1_Pos (1UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bit 1) */ +#define GPDMA0_CLEARSRCTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARSRCTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARSRCTRAN_CH2_Pos (2UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bit 2) */ +#define GPDMA0_CLEARSRCTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARSRCTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARSRCTRAN_CH3_Pos (3UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bit 3) */ +#define GPDMA0_CLEARSRCTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARSRCTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARSRCTRAN_CH4_Pos (4UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bit 4) */ +#define GPDMA0_CLEARSRCTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARSRCTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARSRCTRAN_CH5_Pos (5UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bit 5) */ +#define GPDMA0_CLEARSRCTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARSRCTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARSRCTRAN_CH6_Pos (6UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bit 6) */ +#define GPDMA0_CLEARSRCTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARSRCTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARSRCTRAN_CH7_Pos (7UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bit 7) */ +#define GPDMA0_CLEARSRCTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARSRCTRAN: CH7 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_CLEARDSTTRAN ---------------------------- */ +#define GPDMA0_CLEARDSTTRAN_CH0_Pos (0UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bit 0) */ +#define GPDMA0_CLEARDSTTRAN_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARDSTTRAN: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARDSTTRAN_CH1_Pos (1UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bit 1) */ +#define GPDMA0_CLEARDSTTRAN_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARDSTTRAN: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARDSTTRAN_CH2_Pos (2UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bit 2) */ +#define GPDMA0_CLEARDSTTRAN_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARDSTTRAN: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARDSTTRAN_CH3_Pos (3UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bit 3) */ +#define GPDMA0_CLEARDSTTRAN_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARDSTTRAN: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARDSTTRAN_CH4_Pos (4UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bit 4) */ +#define GPDMA0_CLEARDSTTRAN_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARDSTTRAN: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARDSTTRAN_CH5_Pos (5UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bit 5) */ +#define GPDMA0_CLEARDSTTRAN_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARDSTTRAN: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARDSTTRAN_CH6_Pos (6UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bit 6) */ +#define GPDMA0_CLEARDSTTRAN_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARDSTTRAN: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARDSTTRAN_CH7_Pos (7UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bit 7) */ +#define GPDMA0_CLEARDSTTRAN_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARDSTTRAN: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- GPDMA0_CLEARERR ------------------------------ */ +#define GPDMA0_CLEARERR_CH0_Pos (0UL) /*!< GPDMA0 CLEARERR: CH0 (Bit 0) */ +#define GPDMA0_CLEARERR_CH0_Msk (0x1UL) /*!< GPDMA0 CLEARERR: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARERR_CH1_Pos (1UL) /*!< GPDMA0 CLEARERR: CH1 (Bit 1) */ +#define GPDMA0_CLEARERR_CH1_Msk (0x2UL) /*!< GPDMA0 CLEARERR: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARERR_CH2_Pos (2UL) /*!< GPDMA0 CLEARERR: CH2 (Bit 2) */ +#define GPDMA0_CLEARERR_CH2_Msk (0x4UL) /*!< GPDMA0 CLEARERR: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARERR_CH3_Pos (3UL) /*!< GPDMA0 CLEARERR: CH3 (Bit 3) */ +#define GPDMA0_CLEARERR_CH3_Msk (0x8UL) /*!< GPDMA0 CLEARERR: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARERR_CH4_Pos (4UL) /*!< GPDMA0 CLEARERR: CH4 (Bit 4) */ +#define GPDMA0_CLEARERR_CH4_Msk (0x10UL) /*!< GPDMA0 CLEARERR: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARERR_CH5_Pos (5UL) /*!< GPDMA0 CLEARERR: CH5 (Bit 5) */ +#define GPDMA0_CLEARERR_CH5_Msk (0x20UL) /*!< GPDMA0 CLEARERR: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARERR_CH6_Pos (6UL) /*!< GPDMA0 CLEARERR: CH6 (Bit 6) */ +#define GPDMA0_CLEARERR_CH6_Msk (0x40UL) /*!< GPDMA0 CLEARERR: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_CLEARERR_CH7_Pos (7UL) /*!< GPDMA0 CLEARERR: CH7 (Bit 7) */ +#define GPDMA0_CLEARERR_CH7_Msk (0x80UL) /*!< GPDMA0 CLEARERR: CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_STATUSINT ------------------------------ */ +#define GPDMA0_STATUSINT_TFR_Pos (0UL) /*!< GPDMA0 STATUSINT: TFR (Bit 0) */ +#define GPDMA0_STATUSINT_TFR_Msk (0x1UL) /*!< GPDMA0 STATUSINT: TFR (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSINT_BLOCK_Pos (1UL) /*!< GPDMA0 STATUSINT: BLOCK (Bit 1) */ +#define GPDMA0_STATUSINT_BLOCK_Msk (0x2UL) /*!< GPDMA0 STATUSINT: BLOCK (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSINT_SRCT_Pos (2UL) /*!< GPDMA0 STATUSINT: SRCT (Bit 2) */ +#define GPDMA0_STATUSINT_SRCT_Msk (0x4UL) /*!< GPDMA0 STATUSINT: SRCT (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSINT_DSTT_Pos (3UL) /*!< GPDMA0 STATUSINT: DSTT (Bit 3) */ +#define GPDMA0_STATUSINT_DSTT_Msk (0x8UL) /*!< GPDMA0 STATUSINT: DSTT (Bitfield-Mask: 0x01) */ +#define GPDMA0_STATUSINT_ERR_Pos (4UL) /*!< GPDMA0 STATUSINT: ERR (Bit 4) */ +#define GPDMA0_STATUSINT_ERR_Msk (0x10UL) /*!< GPDMA0 STATUSINT: ERR (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_REQSRCREG ------------------------------ */ +#define GPDMA0_REQSRCREG_CH0_Pos (0UL) /*!< GPDMA0 REQSRCREG: CH0 (Bit 0) */ +#define GPDMA0_REQSRCREG_CH0_Msk (0x1UL) /*!< GPDMA0 REQSRCREG: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_CH1_Pos (1UL) /*!< GPDMA0 REQSRCREG: CH1 (Bit 1) */ +#define GPDMA0_REQSRCREG_CH1_Msk (0x2UL) /*!< GPDMA0 REQSRCREG: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_CH2_Pos (2UL) /*!< GPDMA0 REQSRCREG: CH2 (Bit 2) */ +#define GPDMA0_REQSRCREG_CH2_Msk (0x4UL) /*!< GPDMA0 REQSRCREG: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_CH3_Pos (3UL) /*!< GPDMA0 REQSRCREG: CH3 (Bit 3) */ +#define GPDMA0_REQSRCREG_CH3_Msk (0x8UL) /*!< GPDMA0 REQSRCREG: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_CH4_Pos (4UL) /*!< GPDMA0 REQSRCREG: CH4 (Bit 4) */ +#define GPDMA0_REQSRCREG_CH4_Msk (0x10UL) /*!< GPDMA0 REQSRCREG: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_CH5_Pos (5UL) /*!< GPDMA0 REQSRCREG: CH5 (Bit 5) */ +#define GPDMA0_REQSRCREG_CH5_Msk (0x20UL) /*!< GPDMA0 REQSRCREG: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_CH6_Pos (6UL) /*!< GPDMA0 REQSRCREG: CH6 (Bit 6) */ +#define GPDMA0_REQSRCREG_CH6_Msk (0x40UL) /*!< GPDMA0 REQSRCREG: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_CH7_Pos (7UL) /*!< GPDMA0 REQSRCREG: CH7 (Bit 7) */ +#define GPDMA0_REQSRCREG_CH7_Msk (0x80UL) /*!< GPDMA0 REQSRCREG: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bit 8) */ +#define GPDMA0_REQSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 REQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bit 9) */ +#define GPDMA0_REQSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 REQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bit 10) */ +#define GPDMA0_REQSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 REQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bit 11) */ +#define GPDMA0_REQSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 REQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH4_Pos (12UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bit 12) */ +#define GPDMA0_REQSRCREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 REQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH5_Pos (13UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bit 13) */ +#define GPDMA0_REQSRCREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 REQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH6_Pos (14UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bit 14) */ +#define GPDMA0_REQSRCREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 REQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQSRCREG_WE_CH7_Pos (15UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bit 15) */ +#define GPDMA0_REQSRCREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 REQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_REQDSTREG ------------------------------ */ +#define GPDMA0_REQDSTREG_CH0_Pos (0UL) /*!< GPDMA0 REQDSTREG: CH0 (Bit 0) */ +#define GPDMA0_REQDSTREG_CH0_Msk (0x1UL) /*!< GPDMA0 REQDSTREG: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_CH1_Pos (1UL) /*!< GPDMA0 REQDSTREG: CH1 (Bit 1) */ +#define GPDMA0_REQDSTREG_CH1_Msk (0x2UL) /*!< GPDMA0 REQDSTREG: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_CH2_Pos (2UL) /*!< GPDMA0 REQDSTREG: CH2 (Bit 2) */ +#define GPDMA0_REQDSTREG_CH2_Msk (0x4UL) /*!< GPDMA0 REQDSTREG: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_CH3_Pos (3UL) /*!< GPDMA0 REQDSTREG: CH3 (Bit 3) */ +#define GPDMA0_REQDSTREG_CH3_Msk (0x8UL) /*!< GPDMA0 REQDSTREG: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_CH4_Pos (4UL) /*!< GPDMA0 REQDSTREG: CH4 (Bit 4) */ +#define GPDMA0_REQDSTREG_CH4_Msk (0x10UL) /*!< GPDMA0 REQDSTREG: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_CH5_Pos (5UL) /*!< GPDMA0 REQDSTREG: CH5 (Bit 5) */ +#define GPDMA0_REQDSTREG_CH5_Msk (0x20UL) /*!< GPDMA0 REQDSTREG: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_CH6_Pos (6UL) /*!< GPDMA0 REQDSTREG: CH6 (Bit 6) */ +#define GPDMA0_REQDSTREG_CH6_Msk (0x40UL) /*!< GPDMA0 REQDSTREG: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_CH7_Pos (7UL) /*!< GPDMA0 REQDSTREG: CH7 (Bit 7) */ +#define GPDMA0_REQDSTREG_CH7_Msk (0x80UL) /*!< GPDMA0 REQDSTREG: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bit 8) */ +#define GPDMA0_REQDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 REQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bit 9) */ +#define GPDMA0_REQDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 REQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bit 10) */ +#define GPDMA0_REQDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 REQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bit 11) */ +#define GPDMA0_REQDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 REQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH4_Pos (12UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bit 12) */ +#define GPDMA0_REQDSTREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 REQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH5_Pos (13UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bit 13) */ +#define GPDMA0_REQDSTREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 REQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH6_Pos (14UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bit 14) */ +#define GPDMA0_REQDSTREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 REQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_REQDSTREG_WE_CH7_Pos (15UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bit 15) */ +#define GPDMA0_REQDSTREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 REQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_SGLREQSRCREG ---------------------------- */ +#define GPDMA0_SGLREQSRCREG_CH0_Pos (0UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bit 0) */ +#define GPDMA0_SGLREQSRCREG_CH0_Msk (0x1UL) /*!< GPDMA0 SGLREQSRCREG: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_CH1_Pos (1UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bit 1) */ +#define GPDMA0_SGLREQSRCREG_CH1_Msk (0x2UL) /*!< GPDMA0 SGLREQSRCREG: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_CH2_Pos (2UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bit 2) */ +#define GPDMA0_SGLREQSRCREG_CH2_Msk (0x4UL) /*!< GPDMA0 SGLREQSRCREG: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_CH3_Pos (3UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bit 3) */ +#define GPDMA0_SGLREQSRCREG_CH3_Msk (0x8UL) /*!< GPDMA0 SGLREQSRCREG: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_CH4_Pos (4UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bit 4) */ +#define GPDMA0_SGLREQSRCREG_CH4_Msk (0x10UL) /*!< GPDMA0 SGLREQSRCREG: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_CH5_Pos (5UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bit 5) */ +#define GPDMA0_SGLREQSRCREG_CH5_Msk (0x20UL) /*!< GPDMA0 SGLREQSRCREG: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_CH6_Pos (6UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bit 6) */ +#define GPDMA0_SGLREQSRCREG_CH6_Msk (0x40UL) /*!< GPDMA0 SGLREQSRCREG: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_CH7_Pos (7UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bit 7) */ +#define GPDMA0_SGLREQSRCREG_CH7_Msk (0x80UL) /*!< GPDMA0 SGLREQSRCREG: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bit 8) */ +#define GPDMA0_SGLREQSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bit 9) */ +#define GPDMA0_SGLREQSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bit 10) */ +#define GPDMA0_SGLREQSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bit 11) */ +#define GPDMA0_SGLREQSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH4_Pos (12UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bit 12) */ +#define GPDMA0_SGLREQSRCREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH5_Pos (13UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bit 13) */ +#define GPDMA0_SGLREQSRCREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH6_Pos (14UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bit 14) */ +#define GPDMA0_SGLREQSRCREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQSRCREG_WE_CH7_Pos (15UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bit 15) */ +#define GPDMA0_SGLREQSRCREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 SGLREQSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_SGLREQDSTREG ---------------------------- */ +#define GPDMA0_SGLREQDSTREG_CH0_Pos (0UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bit 0) */ +#define GPDMA0_SGLREQDSTREG_CH0_Msk (0x1UL) /*!< GPDMA0 SGLREQDSTREG: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_CH1_Pos (1UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bit 1) */ +#define GPDMA0_SGLREQDSTREG_CH1_Msk (0x2UL) /*!< GPDMA0 SGLREQDSTREG: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_CH2_Pos (2UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bit 2) */ +#define GPDMA0_SGLREQDSTREG_CH2_Msk (0x4UL) /*!< GPDMA0 SGLREQDSTREG: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_CH3_Pos (3UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bit 3) */ +#define GPDMA0_SGLREQDSTREG_CH3_Msk (0x8UL) /*!< GPDMA0 SGLREQDSTREG: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_CH4_Pos (4UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bit 4) */ +#define GPDMA0_SGLREQDSTREG_CH4_Msk (0x10UL) /*!< GPDMA0 SGLREQDSTREG: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_CH5_Pos (5UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bit 5) */ +#define GPDMA0_SGLREQDSTREG_CH5_Msk (0x20UL) /*!< GPDMA0 SGLREQDSTREG: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_CH6_Pos (6UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bit 6) */ +#define GPDMA0_SGLREQDSTREG_CH6_Msk (0x40UL) /*!< GPDMA0 SGLREQDSTREG: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_CH7_Pos (7UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bit 7) */ +#define GPDMA0_SGLREQDSTREG_CH7_Msk (0x80UL) /*!< GPDMA0 SGLREQDSTREG: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bit 8) */ +#define GPDMA0_SGLREQDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bit 9) */ +#define GPDMA0_SGLREQDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bit 10) */ +#define GPDMA0_SGLREQDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bit 11) */ +#define GPDMA0_SGLREQDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH4_Pos (12UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bit 12) */ +#define GPDMA0_SGLREQDSTREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH5_Pos (13UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bit 13) */ +#define GPDMA0_SGLREQDSTREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH6_Pos (14UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bit 14) */ +#define GPDMA0_SGLREQDSTREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_SGLREQDSTREG_WE_CH7_Pos (15UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bit 15) */ +#define GPDMA0_SGLREQDSTREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 SGLREQDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_LSTSRCREG ------------------------------ */ +#define GPDMA0_LSTSRCREG_CH0_Pos (0UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bit 0) */ +#define GPDMA0_LSTSRCREG_CH0_Msk (0x1UL) /*!< GPDMA0 LSTSRCREG: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_CH1_Pos (1UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bit 1) */ +#define GPDMA0_LSTSRCREG_CH1_Msk (0x2UL) /*!< GPDMA0 LSTSRCREG: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_CH2_Pos (2UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bit 2) */ +#define GPDMA0_LSTSRCREG_CH2_Msk (0x4UL) /*!< GPDMA0 LSTSRCREG: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_CH3_Pos (3UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bit 3) */ +#define GPDMA0_LSTSRCREG_CH3_Msk (0x8UL) /*!< GPDMA0 LSTSRCREG: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_CH4_Pos (4UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bit 4) */ +#define GPDMA0_LSTSRCREG_CH4_Msk (0x10UL) /*!< GPDMA0 LSTSRCREG: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_CH5_Pos (5UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bit 5) */ +#define GPDMA0_LSTSRCREG_CH5_Msk (0x20UL) /*!< GPDMA0 LSTSRCREG: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_CH6_Pos (6UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bit 6) */ +#define GPDMA0_LSTSRCREG_CH6_Msk (0x40UL) /*!< GPDMA0 LSTSRCREG: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_CH7_Pos (7UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bit 7) */ +#define GPDMA0_LSTSRCREG_CH7_Msk (0x80UL) /*!< GPDMA0 LSTSRCREG: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH0_Pos (8UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bit 8) */ +#define GPDMA0_LSTSRCREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 LSTSRCREG: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH1_Pos (9UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bit 9) */ +#define GPDMA0_LSTSRCREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 LSTSRCREG: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH2_Pos (10UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bit 10) */ +#define GPDMA0_LSTSRCREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 LSTSRCREG: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH3_Pos (11UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bit 11) */ +#define GPDMA0_LSTSRCREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 LSTSRCREG: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH4_Pos (12UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bit 12) */ +#define GPDMA0_LSTSRCREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 LSTSRCREG: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH5_Pos (13UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bit 13) */ +#define GPDMA0_LSTSRCREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 LSTSRCREG: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH6_Pos (14UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bit 14) */ +#define GPDMA0_LSTSRCREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 LSTSRCREG: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTSRCREG_WE_CH7_Pos (15UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bit 15) */ +#define GPDMA0_LSTSRCREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 LSTSRCREG: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_LSTDSTREG ------------------------------ */ +#define GPDMA0_LSTDSTREG_CH0_Pos (0UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bit 0) */ +#define GPDMA0_LSTDSTREG_CH0_Msk (0x1UL) /*!< GPDMA0 LSTDSTREG: CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_CH1_Pos (1UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bit 1) */ +#define GPDMA0_LSTDSTREG_CH1_Msk (0x2UL) /*!< GPDMA0 LSTDSTREG: CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_CH2_Pos (2UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bit 2) */ +#define GPDMA0_LSTDSTREG_CH2_Msk (0x4UL) /*!< GPDMA0 LSTDSTREG: CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_CH3_Pos (3UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bit 3) */ +#define GPDMA0_LSTDSTREG_CH3_Msk (0x8UL) /*!< GPDMA0 LSTDSTREG: CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_CH4_Pos (4UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bit 4) */ +#define GPDMA0_LSTDSTREG_CH4_Msk (0x10UL) /*!< GPDMA0 LSTDSTREG: CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_CH5_Pos (5UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bit 5) */ +#define GPDMA0_LSTDSTREG_CH5_Msk (0x20UL) /*!< GPDMA0 LSTDSTREG: CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_CH6_Pos (6UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bit 6) */ +#define GPDMA0_LSTDSTREG_CH6_Msk (0x40UL) /*!< GPDMA0 LSTDSTREG: CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_CH7_Pos (7UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bit 7) */ +#define GPDMA0_LSTDSTREG_CH7_Msk (0x80UL) /*!< GPDMA0 LSTDSTREG: CH7 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH0_Pos (8UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bit 8) */ +#define GPDMA0_LSTDSTREG_WE_CH0_Msk (0x100UL) /*!< GPDMA0 LSTDSTREG: WE_CH0 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH1_Pos (9UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bit 9) */ +#define GPDMA0_LSTDSTREG_WE_CH1_Msk (0x200UL) /*!< GPDMA0 LSTDSTREG: WE_CH1 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH2_Pos (10UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bit 10) */ +#define GPDMA0_LSTDSTREG_WE_CH2_Msk (0x400UL) /*!< GPDMA0 LSTDSTREG: WE_CH2 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH3_Pos (11UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bit 11) */ +#define GPDMA0_LSTDSTREG_WE_CH3_Msk (0x800UL) /*!< GPDMA0 LSTDSTREG: WE_CH3 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH4_Pos (12UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bit 12) */ +#define GPDMA0_LSTDSTREG_WE_CH4_Msk (0x1000UL) /*!< GPDMA0 LSTDSTREG: WE_CH4 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH5_Pos (13UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bit 13) */ +#define GPDMA0_LSTDSTREG_WE_CH5_Msk (0x2000UL) /*!< GPDMA0 LSTDSTREG: WE_CH5 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH6_Pos (14UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bit 14) */ +#define GPDMA0_LSTDSTREG_WE_CH6_Msk (0x4000UL) /*!< GPDMA0 LSTDSTREG: WE_CH6 (Bitfield-Mask: 0x01) */ +#define GPDMA0_LSTDSTREG_WE_CH7_Pos (15UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bit 15) */ +#define GPDMA0_LSTDSTREG_WE_CH7_Msk (0x8000UL) /*!< GPDMA0 LSTDSTREG: WE_CH7 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_DMACFGREG ------------------------------ */ +#define GPDMA0_DMACFGREG_DMA_EN_Pos (0UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bit 0) */ +#define GPDMA0_DMACFGREG_DMA_EN_Msk (0x1UL) /*!< GPDMA0 DMACFGREG: DMA_EN (Bitfield-Mask: 0x01) */ + +/* ------------------------------- GPDMA0_CHENREG ------------------------------- */ +#define GPDMA0_CHENREG_CH_Pos (0UL) /*!< GPDMA0 CHENREG: CH (Bit 0) */ +#define GPDMA0_CHENREG_CH_Msk (0xffUL) /*!< GPDMA0 CHENREG: CH (Bitfield-Mask: 0xff) */ +#define GPDMA0_CHENREG_WE_CH_Pos (8UL) /*!< GPDMA0 CHENREG: WE_CH (Bit 8) */ +#define GPDMA0_CHENREG_WE_CH_Msk (0xff00UL) /*!< GPDMA0 CHENREG: WE_CH (Bitfield-Mask: 0xff) */ + +/* ---------------------------------- GPDMA0_ID --------------------------------- */ +#define GPDMA0_ID_VALUE_Pos (0UL) /*!< GPDMA0 ID: VALUE (Bit 0) */ +#define GPDMA0_ID_VALUE_Msk (0xffffffffUL) /*!< GPDMA0 ID: VALUE (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------------- GPDMA0_TYPE -------------------------------- */ +#define GPDMA0_TYPE_VALUE_Pos (0UL) /*!< GPDMA0 TYPE: VALUE (Bit 0) */ +#define GPDMA0_TYPE_VALUE_Msk (0xffffffffUL) /*!< GPDMA0 TYPE: VALUE (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- GPDMA0_VERSION ------------------------------- */ +#define GPDMA0_VERSION_VALUE_Pos (0UL) /*!< GPDMA0 VERSION: VALUE (Bit 0) */ +#define GPDMA0_VERSION_VALUE_Msk (0xffffffffUL) /*!< GPDMA0 VERSION: VALUE (Bitfield-Mask: 0xffffffff) */ + + +/* ================================================================================ */ +/* ================ Group 'GPDMA0_CH0_1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ GPDMA0_CH_SAR ------------------------------ */ +#define GPDMA0_CH_SAR_SAR_Pos (0UL) /*!< GPDMA0_CH0_1 SAR: SAR (Bit 0) */ +#define GPDMA0_CH_SAR_SAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 SAR: SAR (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------ GPDMA0_CH_DAR ------------------------------ */ +#define GPDMA0_CH_DAR_DAR_Pos (0UL) /*!< GPDMA0_CH0_1 DAR: DAR (Bit 0) */ +#define GPDMA0_CH_DAR_DAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 DAR: DAR (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------ GPDMA0_CH_LLP ------------------------------ */ +#define GPDMA0_CH_LLP_LOC_Pos (2UL) /*!< GPDMA0_CH0_1 LLP: LOC (Bit 2) */ +#define GPDMA0_CH_LLP_LOC_Msk (0xfffffffcUL) /*!< GPDMA0_CH0_1 LLP: LOC (Bitfield-Mask: 0x3fffffff) */ + +/* ------------------------------ GPDMA0_CH_CTLL ----------------------------- */ +#define GPDMA0_CH_CTLL_INT_EN_Pos (0UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bit 0) */ +#define GPDMA0_CH_CTLL_INT_EN_Msk (0x1UL) /*!< GPDMA0_CH0_1 CTLL: INT_EN (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos (1UL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bit 1) */ +#define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk (0xeUL) /*!< GPDMA0_CH0_1 CTLL: DST_TR_WIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos (4UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bit 4) */ +#define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk (0x70UL) /*!< GPDMA0_CH0_1 CTLL: SRC_TR_WIDTH (Bitfield-Mask: 0x07) */ +#define GPDMA0_CH_CTLL_DINC_Pos (7UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bit 7) */ +#define GPDMA0_CH_CTLL_DINC_Msk (0x180UL) /*!< GPDMA0_CH0_1 CTLL: DINC (Bitfield-Mask: 0x03) */ +#define GPDMA0_CH_CTLL_SINC_Pos (9UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bit 9) */ +#define GPDMA0_CH_CTLL_SINC_Msk (0x600UL) /*!< GPDMA0_CH0_1 CTLL: SINC (Bitfield-Mask: 0x03) */ +#define GPDMA0_CH_CTLL_DEST_MSIZE_Pos (11UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bit 11) */ +#define GPDMA0_CH_CTLL_DEST_MSIZE_Msk (0x3800UL) /*!< GPDMA0_CH0_1 CTLL: DEST_MSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA0_CH_CTLL_SRC_MSIZE_Pos (14UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bit 14) */ +#define GPDMA0_CH_CTLL_SRC_MSIZE_Msk (0x1c000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_MSIZE (Bitfield-Mask: 0x07) */ +#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos (17UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bit 17) */ +#define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk (0x20000UL) /*!< GPDMA0_CH0_1 CTLL: SRC_GATHER_EN (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos (18UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bit 18) */ +#define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk (0x40000UL) /*!< GPDMA0_CH0_1 CTLL: DST_SCATTER_EN (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CTLL_TT_FC_Pos (20UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bit 20) */ +#define GPDMA0_CH_CTLL_TT_FC_Msk (0x700000UL) /*!< GPDMA0_CH0_1 CTLL: TT_FC (Bitfield-Mask: 0x07) */ +#define GPDMA0_CH_CTLL_LLP_DST_EN_Pos (27UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bit 27) */ +#define GPDMA0_CH_CTLL_LLP_DST_EN_Msk (0x8000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_DST_EN (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos (28UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bit 28) */ +#define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk (0x10000000UL) /*!< GPDMA0_CH0_1 CTLL: LLP_SRC_EN (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_CH_CTLH ----------------------------- */ +#define GPDMA0_CH_CTLH_BLOCK_TS_Pos (0UL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bit 0) */ +#define GPDMA0_CH_CTLH_BLOCK_TS_Msk (0xfffUL) /*!< GPDMA0_CH0_1 CTLH: BLOCK_TS (Bitfield-Mask: 0xfff) */ +#define GPDMA0_CH_CTLH_DONE_Pos (12UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bit 12) */ +#define GPDMA0_CH_CTLH_DONE_Msk (0x1000UL) /*!< GPDMA0_CH0_1 CTLH: DONE (Bitfield-Mask: 0x01) */ + +/* ----------------------------- GPDMA0_CH_SSTAT ----------------------------- */ +#define GPDMA0_CH_SSTAT_SSTAT_Pos (0UL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bit 0) */ +#define GPDMA0_CH_SSTAT_SSTAT_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTAT: SSTAT (Bitfield-Mask: 0xffffffff) */ + +/* ----------------------------- GPDMA0_CH_DSTAT ----------------------------- */ +#define GPDMA0_CH_DSTAT_DSTAT_Pos (0UL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bit 0) */ +#define GPDMA0_CH_DSTAT_DSTAT_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTAT: DSTAT (Bitfield-Mask: 0xffffffff) */ + +/* ---------------------------- GPDMA0_CH_SSTATAR ---------------------------- */ +#define GPDMA0_CH_SSTATAR_SSTATAR_Pos (0UL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bit 0) */ +#define GPDMA0_CH_SSTATAR_SSTATAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 SSTATAR: SSTATAR (Bitfield-Mask: 0xffffffff) */ + +/* ---------------------------- GPDMA0_CH_DSTATAR ---------------------------- */ +#define GPDMA0_CH_DSTATAR_DSTATAR_Pos (0UL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bit 0) */ +#define GPDMA0_CH_DSTATAR_DSTATAR_Msk (0xffffffffUL) /*!< GPDMA0_CH0_1 DSTATAR: DSTATAR (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------ GPDMA0_CH_CFGL ----------------------------- */ +#define GPDMA0_CH_CFGL_CH_PRIOR_Pos (5UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bit 5) */ +#define GPDMA0_CH_CFGL_CH_PRIOR_Msk (0xe0UL) /*!< GPDMA0_CH0_1 CFGL: CH_PRIOR (Bitfield-Mask: 0x07) */ +#define GPDMA0_CH_CFGL_CH_SUSP_Pos (8UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bit 8) */ +#define GPDMA0_CH_CFGL_CH_SUSP_Msk (0x100UL) /*!< GPDMA0_CH0_1 CFGL: CH_SUSP (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos (9UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bit 9) */ +#define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk (0x200UL) /*!< GPDMA0_CH0_1 CFGL: FIFO_EMPTY (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_HS_SEL_DST_Pos (10UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bit 10) */ +#define GPDMA0_CH_CFGL_HS_SEL_DST_Msk (0x400UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_DST (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos (11UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bit 11) */ +#define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk (0x800UL) /*!< GPDMA0_CH0_1 CFGL: HS_SEL_SRC (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_LOCK_CH_L_Pos (12UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bit 12) */ +#define GPDMA0_CH_CFGL_LOCK_CH_L_Msk (0x3000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH_L (Bitfield-Mask: 0x03) */ +#define GPDMA0_CH_CFGL_LOCK_B_L_Pos (14UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bit 14) */ +#define GPDMA0_CH_CFGL_LOCK_B_L_Msk (0xc000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B_L (Bitfield-Mask: 0x03) */ +#define GPDMA0_CH_CFGL_LOCK_CH_Pos (16UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bit 16) */ +#define GPDMA0_CH_CFGL_LOCK_CH_Msk (0x10000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_CH (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_LOCK_B_Pos (17UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bit 17) */ +#define GPDMA0_CH_CFGL_LOCK_B_Msk (0x20000UL) /*!< GPDMA0_CH0_1 CFGL: LOCK_B (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_DST_HS_POL_Pos (18UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bit 18) */ +#define GPDMA0_CH_CFGL_DST_HS_POL_Msk (0x40000UL) /*!< GPDMA0_CH0_1 CFGL: DST_HS_POL (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_SRC_HS_POL_Pos (19UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bit 19) */ +#define GPDMA0_CH_CFGL_SRC_HS_POL_Msk (0x80000UL) /*!< GPDMA0_CH0_1 CFGL: SRC_HS_POL (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_MAX_ABRST_Pos (20UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bit 20) */ +#define GPDMA0_CH_CFGL_MAX_ABRST_Msk (0x3ff00000UL) /*!< GPDMA0_CH0_1 CFGL: MAX_ABRST (Bitfield-Mask: 0x3ff) */ +#define GPDMA0_CH_CFGL_RELOAD_SRC_Pos (30UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bit 30) */ +#define GPDMA0_CH_CFGL_RELOAD_SRC_Msk (0x40000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_SRC (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGL_RELOAD_DST_Pos (31UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bit 31) */ +#define GPDMA0_CH_CFGL_RELOAD_DST_Msk (0x80000000UL) /*!< GPDMA0_CH0_1 CFGL: RELOAD_DST (Bitfield-Mask: 0x01) */ + +/* ------------------------------ GPDMA0_CH_CFGH ----------------------------- */ +#define GPDMA0_CH_CFGH_FCMODE_Pos (0UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bit 0) */ +#define GPDMA0_CH_CFGH_FCMODE_Msk (0x1UL) /*!< GPDMA0_CH0_1 CFGH: FCMODE (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGH_FIFO_MODE_Pos (1UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bit 1) */ +#define GPDMA0_CH_CFGH_FIFO_MODE_Msk (0x2UL) /*!< GPDMA0_CH0_1 CFGH: FIFO_MODE (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGH_PROTCTL_Pos (2UL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bit 2) */ +#define GPDMA0_CH_CFGH_PROTCTL_Msk (0x1cUL) /*!< GPDMA0_CH0_1 CFGH: PROTCTL (Bitfield-Mask: 0x07) */ +#define GPDMA0_CH_CFGH_DS_UPD_EN_Pos (5UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bit 5) */ +#define GPDMA0_CH_CFGH_DS_UPD_EN_Msk (0x20UL) /*!< GPDMA0_CH0_1 CFGH: DS_UPD_EN (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGH_SS_UPD_EN_Pos (6UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bit 6) */ +#define GPDMA0_CH_CFGH_SS_UPD_EN_Msk (0x40UL) /*!< GPDMA0_CH0_1 CFGH: SS_UPD_EN (Bitfield-Mask: 0x01) */ +#define GPDMA0_CH_CFGH_SRC_PER_Pos (7UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bit 7) */ +#define GPDMA0_CH_CFGH_SRC_PER_Msk (0x780UL) /*!< GPDMA0_CH0_1 CFGH: SRC_PER (Bitfield-Mask: 0x0f) */ +#define GPDMA0_CH_CFGH_DEST_PER_Pos (11UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bit 11) */ +#define GPDMA0_CH_CFGH_DEST_PER_Msk (0x7800UL) /*!< GPDMA0_CH0_1 CFGH: DEST_PER (Bitfield-Mask: 0x0f) */ + +/* ------------------------------ GPDMA0_CH_SGR ------------------------------ */ +#define GPDMA0_CH_SGR_SGI_Pos (0UL) /*!< GPDMA0_CH0_1 SGR: SGI (Bit 0) */ +#define GPDMA0_CH_SGR_SGI_Msk (0xfffffUL) /*!< GPDMA0_CH0_1 SGR: SGI (Bitfield-Mask: 0xfffff) */ +#define GPDMA0_CH_SGR_SGC_Pos (20UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bit 20) */ +#define GPDMA0_CH_SGR_SGC_Msk (0xfff00000UL) /*!< GPDMA0_CH0_1 SGR: SGC (Bitfield-Mask: 0xfff) */ + +/* ------------------------------ GPDMA0_CH_DSR ------------------------------ */ +#define GPDMA0_CH_DSR_DSI_Pos (0UL) /*!< GPDMA0_CH0_1 DSR: DSI (Bit 0) */ +#define GPDMA0_CH_DSR_DSI_Msk (0xfffffUL) /*!< GPDMA0_CH0_1 DSR: DSI (Bitfield-Mask: 0xfffff) */ +#define GPDMA0_CH_DSR_DSC_Pos (20UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bit 20) */ +#define GPDMA0_CH_DSR_DSC_Msk (0xfff00000UL) /*!< GPDMA0_CH0_1 DSR: DSC (Bitfield-Mask: 0xfff) */ + + +/* ================================================================================ */ +/* ================ struct 'FCE' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- FCE_CLC ---------------------------------- */ +#define FCE_CLC_DISR_Pos (0UL) /*!< FCE CLC: DISR (Bit 0) */ +#define FCE_CLC_DISR_Msk (0x1UL) /*!< FCE CLC: DISR (Bitfield-Mask: 0x01) */ +#define FCE_CLC_DISS_Pos (1UL) /*!< FCE CLC: DISS (Bit 1) */ +#define FCE_CLC_DISS_Msk (0x2UL) /*!< FCE CLC: DISS (Bitfield-Mask: 0x01) */ + +/* ----------------------------------- FCE_ID ----------------------------------- */ +#define FCE_ID_MOD_REV_Pos (0UL) /*!< FCE ID: MOD_REV (Bit 0) */ +#define FCE_ID_MOD_REV_Msk (0xffUL) /*!< FCE ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define FCE_ID_MOD_TYPE_Pos (8UL) /*!< FCE ID: MOD_TYPE (Bit 8) */ +#define FCE_ID_MOD_TYPE_Msk (0xff00UL) /*!< FCE ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define FCE_ID_MOD_NUMBER_Pos (16UL) /*!< FCE ID: MOD_NUMBER (Bit 16) */ +#define FCE_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< FCE ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ Group 'FCE_KE' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- FCE_KE_IR --------------------------------- */ +#define FCE_KE_IR_IR_Pos (0UL) /*!< FCE_KE IR: IR (Bit 0) */ +#define FCE_KE_IR_IR_Msk (0xffffffffUL) /*!< FCE_KE IR: IR (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------------- FCE_KE_RES --------------------------------- */ +#define FCE_KE_RES_RES_Pos (0UL) /*!< FCE_KE RES: RES (Bit 0) */ +#define FCE_KE_RES_RES_Msk (0xffffffffUL) /*!< FCE_KE RES: RES (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------------- FCE_KE_CFG --------------------------------- */ +#define FCE_KE_CFG_CMI_Pos (0UL) /*!< FCE_KE CFG: CMI (Bit 0) */ +#define FCE_KE_CFG_CMI_Msk (0x1UL) /*!< FCE_KE CFG: CMI (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_CEI_Pos (1UL) /*!< FCE_KE CFG: CEI (Bit 1) */ +#define FCE_KE_CFG_CEI_Msk (0x2UL) /*!< FCE_KE CFG: CEI (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_LEI_Pos (2UL) /*!< FCE_KE CFG: LEI (Bit 2) */ +#define FCE_KE_CFG_LEI_Msk (0x4UL) /*!< FCE_KE CFG: LEI (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_BEI_Pos (3UL) /*!< FCE_KE CFG: BEI (Bit 3) */ +#define FCE_KE_CFG_BEI_Msk (0x8UL) /*!< FCE_KE CFG: BEI (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_CCE_Pos (4UL) /*!< FCE_KE CFG: CCE (Bit 4) */ +#define FCE_KE_CFG_CCE_Msk (0x10UL) /*!< FCE_KE CFG: CCE (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_ALR_Pos (5UL) /*!< FCE_KE CFG: ALR (Bit 5) */ +#define FCE_KE_CFG_ALR_Msk (0x20UL) /*!< FCE_KE CFG: ALR (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_REFIN_Pos (8UL) /*!< FCE_KE CFG: REFIN (Bit 8) */ +#define FCE_KE_CFG_REFIN_Msk (0x100UL) /*!< FCE_KE CFG: REFIN (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_REFOUT_Pos (9UL) /*!< FCE_KE CFG: REFOUT (Bit 9) */ +#define FCE_KE_CFG_REFOUT_Msk (0x200UL) /*!< FCE_KE CFG: REFOUT (Bitfield-Mask: 0x01) */ +#define FCE_KE_CFG_XSEL_Pos (10UL) /*!< FCE_KE CFG: XSEL (Bit 10) */ +#define FCE_KE_CFG_XSEL_Msk (0x400UL) /*!< FCE_KE CFG: XSEL (Bitfield-Mask: 0x01) */ + +/* --------------------------------- FCE_KE_STS --------------------------------- */ +#define FCE_KE_STS_CMF_Pos (0UL) /*!< FCE_KE STS: CMF (Bit 0) */ +#define FCE_KE_STS_CMF_Msk (0x1UL) /*!< FCE_KE STS: CMF (Bitfield-Mask: 0x01) */ +#define FCE_KE_STS_CEF_Pos (1UL) /*!< FCE_KE STS: CEF (Bit 1) */ +#define FCE_KE_STS_CEF_Msk (0x2UL) /*!< FCE_KE STS: CEF (Bitfield-Mask: 0x01) */ +#define FCE_KE_STS_LEF_Pos (2UL) /*!< FCE_KE STS: LEF (Bit 2) */ +#define FCE_KE_STS_LEF_Msk (0x4UL) /*!< FCE_KE STS: LEF (Bitfield-Mask: 0x01) */ +#define FCE_KE_STS_BEF_Pos (3UL) /*!< FCE_KE STS: BEF (Bit 3) */ +#define FCE_KE_STS_BEF_Msk (0x8UL) /*!< FCE_KE STS: BEF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- FCE_KE_LENGTH ------------------------------- */ +#define FCE_KE_LENGTH_LENGTH_Pos (0UL) /*!< FCE_KE LENGTH: LENGTH (Bit 0) */ +#define FCE_KE_LENGTH_LENGTH_Msk (0xffffUL) /*!< FCE_KE LENGTH: LENGTH (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- FCE_KE_CHECK -------------------------------- */ +#define FCE_KE_CHECK_CHECK_Pos (0UL) /*!< FCE_KE CHECK: CHECK (Bit 0) */ +#define FCE_KE_CHECK_CHECK_Msk (0xffffffffUL) /*!< FCE_KE CHECK: CHECK (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------------- FCE_KE_CRC --------------------------------- */ +#define FCE_KE_CRC_CRC_Pos (0UL) /*!< FCE_KE CRC: CRC (Bit 0) */ +#define FCE_KE_CRC_CRC_Msk (0xffffffffUL) /*!< FCE_KE CRC: CRC (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------------- FCE_KE_CTR --------------------------------- */ +#define FCE_KE_CTR_FCM_Pos (0UL) /*!< FCE_KE CTR: FCM (Bit 0) */ +#define FCE_KE_CTR_FCM_Msk (0x1UL) /*!< FCE_KE CTR: FCM (Bitfield-Mask: 0x01) */ +#define FCE_KE_CTR_FRM_CFG_Pos (1UL) /*!< FCE_KE CTR: FRM_CFG (Bit 1) */ +#define FCE_KE_CTR_FRM_CFG_Msk (0x2UL) /*!< FCE_KE CTR: FRM_CFG (Bitfield-Mask: 0x01) */ +#define FCE_KE_CTR_FRM_CHECK_Pos (2UL) /*!< FCE_KE CTR: FRM_CHECK (Bit 2) */ +#define FCE_KE_CTR_FRM_CHECK_Msk (0x4UL) /*!< FCE_KE CTR: FRM_CHECK (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'PBA' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- PBA_STS ---------------------------------- */ +#define PBA_STS_WERR_Pos (0UL) /*!< PBA STS: WERR (Bit 0) */ +#define PBA_STS_WERR_Msk (0x1UL) /*!< PBA STS: WERR (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PBA_WADDR --------------------------------- */ +#define PBA_WADDR_WADDR_Pos (0UL) /*!< PBA WADDR: WADDR (Bit 0) */ +#define PBA_WADDR_WADDR_Msk (0xffffffffUL) /*!< PBA WADDR: WADDR (Bitfield-Mask: 0xffffffff) */ + + +/* ================================================================================ */ +/* ================ Group 'FLASH' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- FLASH_ID ---------------------------------- */ +#define FLASH_ID_MOD_REV_Pos (0UL) /*!< FLASH ID: MOD_REV (Bit 0) */ +#define FLASH_ID_MOD_REV_Msk (0xffUL) /*!< FLASH ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define FLASH_ID_MOD_TYPE_Pos (8UL) /*!< FLASH ID: MOD_TYPE (Bit 8) */ +#define FLASH_ID_MOD_TYPE_Msk (0xff00UL) /*!< FLASH ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define FLASH_ID_MOD_NUMBER_Pos (16UL) /*!< FLASH ID: MOD_NUMBER (Bit 16) */ +#define FLASH_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< FLASH ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* ---------------------------------- FLASH_FSR --------------------------------- */ +#define FLASH_FSR_PBUSY_Pos (0UL) /*!< FLASH FSR: PBUSY (Bit 0) */ +#define FLASH_FSR_PBUSY_Msk (0x1UL) /*!< FLASH FSR: PBUSY (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_FABUSY_Pos (1UL) /*!< FLASH FSR: FABUSY (Bit 1) */ +#define FLASH_FSR_FABUSY_Msk (0x2UL) /*!< FLASH FSR: FABUSY (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_PROG_Pos (4UL) /*!< FLASH FSR: PROG (Bit 4) */ +#define FLASH_FSR_PROG_Msk (0x10UL) /*!< FLASH FSR: PROG (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_ERASE_Pos (5UL) /*!< FLASH FSR: ERASE (Bit 5) */ +#define FLASH_FSR_ERASE_Msk (0x20UL) /*!< FLASH FSR: ERASE (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_PFPAGE_Pos (6UL) /*!< FLASH FSR: PFPAGE (Bit 6) */ +#define FLASH_FSR_PFPAGE_Msk (0x40UL) /*!< FLASH FSR: PFPAGE (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_PFOPER_Pos (8UL) /*!< FLASH FSR: PFOPER (Bit 8) */ +#define FLASH_FSR_PFOPER_Msk (0x100UL) /*!< FLASH FSR: PFOPER (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_SQER_Pos (10UL) /*!< FLASH FSR: SQER (Bit 10) */ +#define FLASH_FSR_SQER_Msk (0x400UL) /*!< FLASH FSR: SQER (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_PROER_Pos (11UL) /*!< FLASH FSR: PROER (Bit 11) */ +#define FLASH_FSR_PROER_Msk (0x800UL) /*!< FLASH FSR: PROER (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_PFSBER_Pos (12UL) /*!< FLASH FSR: PFSBER (Bit 12) */ +#define FLASH_FSR_PFSBER_Msk (0x1000UL) /*!< FLASH FSR: PFSBER (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_PFDBER_Pos (14UL) /*!< FLASH FSR: PFDBER (Bit 14) */ +#define FLASH_FSR_PFDBER_Msk (0x4000UL) /*!< FLASH FSR: PFDBER (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_PROIN_Pos (16UL) /*!< FLASH FSR: PROIN (Bit 16) */ +#define FLASH_FSR_PROIN_Msk (0x10000UL) /*!< FLASH FSR: PROIN (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_RPROIN_Pos (18UL) /*!< FLASH FSR: RPROIN (Bit 18) */ +#define FLASH_FSR_RPROIN_Msk (0x40000UL) /*!< FLASH FSR: RPROIN (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_RPRODIS_Pos (19UL) /*!< FLASH FSR: RPRODIS (Bit 19) */ +#define FLASH_FSR_RPRODIS_Msk (0x80000UL) /*!< FLASH FSR: RPRODIS (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_WPROIN0_Pos (21UL) /*!< FLASH FSR: WPROIN0 (Bit 21) */ +#define FLASH_FSR_WPROIN0_Msk (0x200000UL) /*!< FLASH FSR: WPROIN0 (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_WPROIN1_Pos (22UL) /*!< FLASH FSR: WPROIN1 (Bit 22) */ +#define FLASH_FSR_WPROIN1_Msk (0x400000UL) /*!< FLASH FSR: WPROIN1 (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_WPROIN2_Pos (23UL) /*!< FLASH FSR: WPROIN2 (Bit 23) */ +#define FLASH_FSR_WPROIN2_Msk (0x800000UL) /*!< FLASH FSR: WPROIN2 (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_WPRODIS0_Pos (25UL) /*!< FLASH FSR: WPRODIS0 (Bit 25) */ +#define FLASH_FSR_WPRODIS0_Msk (0x2000000UL) /*!< FLASH FSR: WPRODIS0 (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_WPRODIS1_Pos (26UL) /*!< FLASH FSR: WPRODIS1 (Bit 26) */ +#define FLASH_FSR_WPRODIS1_Msk (0x4000000UL) /*!< FLASH FSR: WPRODIS1 (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_SLM_Pos (28UL) /*!< FLASH FSR: SLM (Bit 28) */ +#define FLASH_FSR_SLM_Msk (0x10000000UL) /*!< FLASH FSR: SLM (Bitfield-Mask: 0x01) */ +#define FLASH_FSR_VER_Pos (31UL) /*!< FLASH FSR: VER (Bit 31) */ +#define FLASH_FSR_VER_Msk (0x80000000UL) /*!< FLASH FSR: VER (Bitfield-Mask: 0x01) */ + +/* --------------------------------- FLASH_FCON --------------------------------- */ +#define FLASH_FCON_WSPFLASH_Pos (0UL) /*!< FLASH FCON: WSPFLASH (Bit 0) */ +#define FLASH_FCON_WSPFLASH_Msk (0xfUL) /*!< FLASH FCON: WSPFLASH (Bitfield-Mask: 0x0f) */ +#define FLASH_FCON_WSECPF_Pos (4UL) /*!< FLASH FCON: WSECPF (Bit 4) */ +#define FLASH_FCON_WSECPF_Msk (0x10UL) /*!< FLASH FCON: WSECPF (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_IDLE_Pos (13UL) /*!< FLASH FCON: IDLE (Bit 13) */ +#define FLASH_FCON_IDLE_Msk (0x2000UL) /*!< FLASH FCON: IDLE (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_ESLDIS_Pos (14UL) /*!< FLASH FCON: ESLDIS (Bit 14) */ +#define FLASH_FCON_ESLDIS_Msk (0x4000UL) /*!< FLASH FCON: ESLDIS (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_SLEEP_Pos (15UL) /*!< FLASH FCON: SLEEP (Bit 15) */ +#define FLASH_FCON_SLEEP_Msk (0x8000UL) /*!< FLASH FCON: SLEEP (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_RPA_Pos (16UL) /*!< FLASH FCON: RPA (Bit 16) */ +#define FLASH_FCON_RPA_Msk (0x10000UL) /*!< FLASH FCON: RPA (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_DCF_Pos (17UL) /*!< FLASH FCON: DCF (Bit 17) */ +#define FLASH_FCON_DCF_Msk (0x20000UL) /*!< FLASH FCON: DCF (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_DDF_Pos (18UL) /*!< FLASH FCON: DDF (Bit 18) */ +#define FLASH_FCON_DDF_Msk (0x40000UL) /*!< FLASH FCON: DDF (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_VOPERM_Pos (24UL) /*!< FLASH FCON: VOPERM (Bit 24) */ +#define FLASH_FCON_VOPERM_Msk (0x1000000UL) /*!< FLASH FCON: VOPERM (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_SQERM_Pos (25UL) /*!< FLASH FCON: SQERM (Bit 25) */ +#define FLASH_FCON_SQERM_Msk (0x2000000UL) /*!< FLASH FCON: SQERM (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_PROERM_Pos (26UL) /*!< FLASH FCON: PROERM (Bit 26) */ +#define FLASH_FCON_PROERM_Msk (0x4000000UL) /*!< FLASH FCON: PROERM (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_PFSBERM_Pos (27UL) /*!< FLASH FCON: PFSBERM (Bit 27) */ +#define FLASH_FCON_PFSBERM_Msk (0x8000000UL) /*!< FLASH FCON: PFSBERM (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_PFDBERM_Pos (29UL) /*!< FLASH FCON: PFDBERM (Bit 29) */ +#define FLASH_FCON_PFDBERM_Msk (0x20000000UL) /*!< FLASH FCON: PFDBERM (Bitfield-Mask: 0x01) */ +#define FLASH_FCON_EOBM_Pos (31UL) /*!< FLASH FCON: EOBM (Bit 31) */ +#define FLASH_FCON_EOBM_Msk (0x80000000UL) /*!< FLASH FCON: EOBM (Bitfield-Mask: 0x01) */ + +/* --------------------------------- FLASH_MARP --------------------------------- */ +#define FLASH_MARP_MARGIN_Pos (0UL) /*!< FLASH MARP: MARGIN (Bit 0) */ +#define FLASH_MARP_MARGIN_Msk (0xfUL) /*!< FLASH MARP: MARGIN (Bitfield-Mask: 0x0f) */ +#define FLASH_MARP_TRAPDIS_Pos (15UL) /*!< FLASH MARP: TRAPDIS (Bit 15) */ +#define FLASH_MARP_TRAPDIS_Msk (0x8000UL) /*!< FLASH MARP: TRAPDIS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- FLASH_PROCON0 ------------------------------- */ +#define FLASH_PROCON0_S0L_Pos (0UL) /*!< FLASH PROCON0: S0L (Bit 0) */ +#define FLASH_PROCON0_S0L_Msk (0x1UL) /*!< FLASH PROCON0: S0L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S1L_Pos (1UL) /*!< FLASH PROCON0: S1L (Bit 1) */ +#define FLASH_PROCON0_S1L_Msk (0x2UL) /*!< FLASH PROCON0: S1L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S2L_Pos (2UL) /*!< FLASH PROCON0: S2L (Bit 2) */ +#define FLASH_PROCON0_S2L_Msk (0x4UL) /*!< FLASH PROCON0: S2L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S3L_Pos (3UL) /*!< FLASH PROCON0: S3L (Bit 3) */ +#define FLASH_PROCON0_S3L_Msk (0x8UL) /*!< FLASH PROCON0: S3L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S4L_Pos (4UL) /*!< FLASH PROCON0: S4L (Bit 4) */ +#define FLASH_PROCON0_S4L_Msk (0x10UL) /*!< FLASH PROCON0: S4L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S5L_Pos (5UL) /*!< FLASH PROCON0: S5L (Bit 5) */ +#define FLASH_PROCON0_S5L_Msk (0x20UL) /*!< FLASH PROCON0: S5L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S6L_Pos (6UL) /*!< FLASH PROCON0: S6L (Bit 6) */ +#define FLASH_PROCON0_S6L_Msk (0x40UL) /*!< FLASH PROCON0: S6L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S7L_Pos (7UL) /*!< FLASH PROCON0: S7L (Bit 7) */ +#define FLASH_PROCON0_S7L_Msk (0x80UL) /*!< FLASH PROCON0: S7L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_S8L_Pos (8UL) /*!< FLASH PROCON0: S8L (Bit 8) */ +#define FLASH_PROCON0_S8L_Msk (0x100UL) /*!< FLASH PROCON0: S8L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON0_RPRO_Pos (15UL) /*!< FLASH PROCON0: RPRO (Bit 15) */ +#define FLASH_PROCON0_RPRO_Msk (0x8000UL) /*!< FLASH PROCON0: RPRO (Bitfield-Mask: 0x01) */ + +/* -------------------------------- FLASH_PROCON1 ------------------------------- */ +#define FLASH_PROCON1_S0L_Pos (0UL) /*!< FLASH PROCON1: S0L (Bit 0) */ +#define FLASH_PROCON1_S0L_Msk (0x1UL) /*!< FLASH PROCON1: S0L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S1L_Pos (1UL) /*!< FLASH PROCON1: S1L (Bit 1) */ +#define FLASH_PROCON1_S1L_Msk (0x2UL) /*!< FLASH PROCON1: S1L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S2L_Pos (2UL) /*!< FLASH PROCON1: S2L (Bit 2) */ +#define FLASH_PROCON1_S2L_Msk (0x4UL) /*!< FLASH PROCON1: S2L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S3L_Pos (3UL) /*!< FLASH PROCON1: S3L (Bit 3) */ +#define FLASH_PROCON1_S3L_Msk (0x8UL) /*!< FLASH PROCON1: S3L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S4L_Pos (4UL) /*!< FLASH PROCON1: S4L (Bit 4) */ +#define FLASH_PROCON1_S4L_Msk (0x10UL) /*!< FLASH PROCON1: S4L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S5L_Pos (5UL) /*!< FLASH PROCON1: S5L (Bit 5) */ +#define FLASH_PROCON1_S5L_Msk (0x20UL) /*!< FLASH PROCON1: S5L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S6L_Pos (6UL) /*!< FLASH PROCON1: S6L (Bit 6) */ +#define FLASH_PROCON1_S6L_Msk (0x40UL) /*!< FLASH PROCON1: S6L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S7L_Pos (7UL) /*!< FLASH PROCON1: S7L (Bit 7) */ +#define FLASH_PROCON1_S7L_Msk (0x80UL) /*!< FLASH PROCON1: S7L (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON1_S8L_Pos (8UL) /*!< FLASH PROCON1: S8L (Bit 8) */ +#define FLASH_PROCON1_S8L_Msk (0x100UL) /*!< FLASH PROCON1: S8L (Bitfield-Mask: 0x01) */ + +/* -------------------------------- FLASH_PROCON2 ------------------------------- */ +#define FLASH_PROCON2_S0ROM_Pos (0UL) /*!< FLASH PROCON2: S0ROM (Bit 0) */ +#define FLASH_PROCON2_S0ROM_Msk (0x1UL) /*!< FLASH PROCON2: S0ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S1ROM_Pos (1UL) /*!< FLASH PROCON2: S1ROM (Bit 1) */ +#define FLASH_PROCON2_S1ROM_Msk (0x2UL) /*!< FLASH PROCON2: S1ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S2ROM_Pos (2UL) /*!< FLASH PROCON2: S2ROM (Bit 2) */ +#define FLASH_PROCON2_S2ROM_Msk (0x4UL) /*!< FLASH PROCON2: S2ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S3ROM_Pos (3UL) /*!< FLASH PROCON2: S3ROM (Bit 3) */ +#define FLASH_PROCON2_S3ROM_Msk (0x8UL) /*!< FLASH PROCON2: S3ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S4ROM_Pos (4UL) /*!< FLASH PROCON2: S4ROM (Bit 4) */ +#define FLASH_PROCON2_S4ROM_Msk (0x10UL) /*!< FLASH PROCON2: S4ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S5ROM_Pos (5UL) /*!< FLASH PROCON2: S5ROM (Bit 5) */ +#define FLASH_PROCON2_S5ROM_Msk (0x20UL) /*!< FLASH PROCON2: S5ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S6ROM_Pos (6UL) /*!< FLASH PROCON2: S6ROM (Bit 6) */ +#define FLASH_PROCON2_S6ROM_Msk (0x40UL) /*!< FLASH PROCON2: S6ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S7ROM_Pos (7UL) /*!< FLASH PROCON2: S7ROM (Bit 7) */ +#define FLASH_PROCON2_S7ROM_Msk (0x80UL) /*!< FLASH PROCON2: S7ROM (Bitfield-Mask: 0x01) */ +#define FLASH_PROCON2_S8ROM_Pos (8UL) /*!< FLASH PROCON2: S8ROM (Bit 8) */ +#define FLASH_PROCON2_S8ROM_Msk (0x100UL) /*!< FLASH PROCON2: S8ROM (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'PREF' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- PREF_PCON --------------------------------- */ +#define PREF_PCON_IBYP_Pos (0UL) /*!< PREF PCON: IBYP (Bit 0) */ +#define PREF_PCON_IBYP_Msk (0x1UL) /*!< PREF PCON: IBYP (Bitfield-Mask: 0x01) */ +#define PREF_PCON_IINV_Pos (1UL) /*!< PREF PCON: IINV (Bit 1) */ +#define PREF_PCON_IINV_Msk (0x2UL) /*!< PREF PCON: IINV (Bitfield-Mask: 0x01) */ +#define PREF_PCON_DBYP_Pos (4UL) /*!< PREF PCON: DBYP (Bit 4) */ +#define PREF_PCON_DBYP_Msk (0x10UL) /*!< PREF PCON: DBYP (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'PMU' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- PMU_ID ----------------------------------- */ +#define PMU_ID_MOD_REV_Pos (0UL) /*!< PMU ID: MOD_REV (Bit 0) */ +#define PMU_ID_MOD_REV_Msk (0xffUL) /*!< PMU ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define PMU_ID_MOD_TYPE_Pos (8UL) /*!< PMU ID: MOD_TYPE (Bit 8) */ +#define PMU_ID_MOD_TYPE_Msk (0xff00UL) /*!< PMU ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define PMU_ID_MOD_NUMBER_Pos (16UL) /*!< PMU ID: MOD_NUMBER (Bit 16) */ +#define PMU_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< PMU ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'WDT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- WDT_ID ----------------------------------- */ +#define WDT_ID_MOD_REV_Pos (0UL) /*!< WDT ID: MOD_REV (Bit 0) */ +#define WDT_ID_MOD_REV_Msk (0xffUL) /*!< WDT ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define WDT_ID_MOD_TYPE_Pos (8UL) /*!< WDT ID: MOD_TYPE (Bit 8) */ +#define WDT_ID_MOD_TYPE_Msk (0xff00UL) /*!< WDT ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define WDT_ID_MOD_NUMBER_Pos (16UL) /*!< WDT ID: MOD_NUMBER (Bit 16) */ +#define WDT_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< WDT ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* ----------------------------------- WDT_CTR ---------------------------------- */ +#define WDT_CTR_ENB_Pos (0UL) /*!< WDT CTR: ENB (Bit 0) */ +#define WDT_CTR_ENB_Msk (0x1UL) /*!< WDT CTR: ENB (Bitfield-Mask: 0x01) */ +#define WDT_CTR_PRE_Pos (1UL) /*!< WDT CTR: PRE (Bit 1) */ +#define WDT_CTR_PRE_Msk (0x2UL) /*!< WDT CTR: PRE (Bitfield-Mask: 0x01) */ +#define WDT_CTR_DSP_Pos (4UL) /*!< WDT CTR: DSP (Bit 4) */ +#define WDT_CTR_DSP_Msk (0x10UL) /*!< WDT CTR: DSP (Bitfield-Mask: 0x01) */ +#define WDT_CTR_SPW_Pos (8UL) /*!< WDT CTR: SPW (Bit 8) */ +#define WDT_CTR_SPW_Msk (0xff00UL) /*!< WDT CTR: SPW (Bitfield-Mask: 0xff) */ + +/* ----------------------------------- WDT_SRV ---------------------------------- */ +#define WDT_SRV_SRV_Pos (0UL) /*!< WDT SRV: SRV (Bit 0) */ +#define WDT_SRV_SRV_Msk (0xffffffffUL) /*!< WDT SRV: SRV (Bitfield-Mask: 0xffffffff) */ + +/* ----------------------------------- WDT_TIM ---------------------------------- */ +#define WDT_TIM_TIM_Pos (0UL) /*!< WDT TIM: TIM (Bit 0) */ +#define WDT_TIM_TIM_Msk (0xffffffffUL) /*!< WDT TIM: TIM (Bitfield-Mask: 0xffffffff) */ + +/* ----------------------------------- WDT_WLB ---------------------------------- */ +#define WDT_WLB_WLB_Pos (0UL) /*!< WDT WLB: WLB (Bit 0) */ +#define WDT_WLB_WLB_Msk (0xffffffffUL) /*!< WDT WLB: WLB (Bitfield-Mask: 0xffffffff) */ + +/* ----------------------------------- WDT_WUB ---------------------------------- */ +#define WDT_WUB_WUB_Pos (0UL) /*!< WDT WUB: WUB (Bit 0) */ +#define WDT_WUB_WUB_Msk (0xffffffffUL) /*!< WDT WUB: WUB (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------------- WDT_WDTSTS --------------------------------- */ +#define WDT_WDTSTS_ALMS_Pos (0UL) /*!< WDT WDTSTS: ALMS (Bit 0) */ +#define WDT_WDTSTS_ALMS_Msk (0x1UL) /*!< WDT WDTSTS: ALMS (Bitfield-Mask: 0x01) */ + +/* --------------------------------- WDT_WDTCLR --------------------------------- */ +#define WDT_WDTCLR_ALMC_Pos (0UL) /*!< WDT WDTCLR: ALMC (Bit 0) */ +#define WDT_WDTCLR_ALMC_Msk (0x1UL) /*!< WDT WDTCLR: ALMC (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'RTC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- RTC_ID ----------------------------------- */ +#define RTC_ID_MOD_REV_Pos (0UL) /*!< RTC ID: MOD_REV (Bit 0) */ +#define RTC_ID_MOD_REV_Msk (0xffUL) /*!< RTC ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define RTC_ID_MOD_TYPE_Pos (8UL) /*!< RTC ID: MOD_TYPE (Bit 8) */ +#define RTC_ID_MOD_TYPE_Msk (0xff00UL) /*!< RTC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define RTC_ID_MOD_NUMBER_Pos (16UL) /*!< RTC ID: MOD_NUMBER (Bit 16) */ +#define RTC_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< RTC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* ----------------------------------- RTC_CTR ---------------------------------- */ +#define RTC_CTR_ENB_Pos (0UL) /*!< RTC CTR: ENB (Bit 0) */ +#define RTC_CTR_ENB_Msk (0x1UL) /*!< RTC CTR: ENB (Bitfield-Mask: 0x01) */ +#define RTC_CTR_TAE_Pos (2UL) /*!< RTC CTR: TAE (Bit 2) */ +#define RTC_CTR_TAE_Msk (0x4UL) /*!< RTC CTR: TAE (Bitfield-Mask: 0x01) */ +#define RTC_CTR_ESEC_Pos (8UL) /*!< RTC CTR: ESEC (Bit 8) */ +#define RTC_CTR_ESEC_Msk (0x100UL) /*!< RTC CTR: ESEC (Bitfield-Mask: 0x01) */ +#define RTC_CTR_EMIC_Pos (9UL) /*!< RTC CTR: EMIC (Bit 9) */ +#define RTC_CTR_EMIC_Msk (0x200UL) /*!< RTC CTR: EMIC (Bitfield-Mask: 0x01) */ +#define RTC_CTR_EHOC_Pos (10UL) /*!< RTC CTR: EHOC (Bit 10) */ +#define RTC_CTR_EHOC_Msk (0x400UL) /*!< RTC CTR: EHOC (Bitfield-Mask: 0x01) */ +#define RTC_CTR_EDAC_Pos (11UL) /*!< RTC CTR: EDAC (Bit 11) */ +#define RTC_CTR_EDAC_Msk (0x800UL) /*!< RTC CTR: EDAC (Bitfield-Mask: 0x01) */ +#define RTC_CTR_EMOC_Pos (13UL) /*!< RTC CTR: EMOC (Bit 13) */ +#define RTC_CTR_EMOC_Msk (0x2000UL) /*!< RTC CTR: EMOC (Bitfield-Mask: 0x01) */ +#define RTC_CTR_EYEC_Pos (14UL) /*!< RTC CTR: EYEC (Bit 14) */ +#define RTC_CTR_EYEC_Msk (0x4000UL) /*!< RTC CTR: EYEC (Bitfield-Mask: 0x01) */ +#define RTC_CTR_DIV_Pos (16UL) /*!< RTC CTR: DIV (Bit 16) */ +#define RTC_CTR_DIV_Msk (0xffff0000UL) /*!< RTC CTR: DIV (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- RTC_RAWSTAT -------------------------------- */ +#define RTC_RAWSTAT_RPSE_Pos (0UL) /*!< RTC RAWSTAT: RPSE (Bit 0) */ +#define RTC_RAWSTAT_RPSE_Msk (0x1UL) /*!< RTC RAWSTAT: RPSE (Bitfield-Mask: 0x01) */ +#define RTC_RAWSTAT_RPMI_Pos (1UL) /*!< RTC RAWSTAT: RPMI (Bit 1) */ +#define RTC_RAWSTAT_RPMI_Msk (0x2UL) /*!< RTC RAWSTAT: RPMI (Bitfield-Mask: 0x01) */ +#define RTC_RAWSTAT_RPHO_Pos (2UL) /*!< RTC RAWSTAT: RPHO (Bit 2) */ +#define RTC_RAWSTAT_RPHO_Msk (0x4UL) /*!< RTC RAWSTAT: RPHO (Bitfield-Mask: 0x01) */ +#define RTC_RAWSTAT_RPDA_Pos (3UL) /*!< RTC RAWSTAT: RPDA (Bit 3) */ +#define RTC_RAWSTAT_RPDA_Msk (0x8UL) /*!< RTC RAWSTAT: RPDA (Bitfield-Mask: 0x01) */ +#define RTC_RAWSTAT_RPMO_Pos (5UL) /*!< RTC RAWSTAT: RPMO (Bit 5) */ +#define RTC_RAWSTAT_RPMO_Msk (0x20UL) /*!< RTC RAWSTAT: RPMO (Bitfield-Mask: 0x01) */ +#define RTC_RAWSTAT_RPYE_Pos (6UL) /*!< RTC RAWSTAT: RPYE (Bit 6) */ +#define RTC_RAWSTAT_RPYE_Msk (0x40UL) /*!< RTC RAWSTAT: RPYE (Bitfield-Mask: 0x01) */ +#define RTC_RAWSTAT_RAI_Pos (8UL) /*!< RTC RAWSTAT: RAI (Bit 8) */ +#define RTC_RAWSTAT_RAI_Msk (0x100UL) /*!< RTC RAWSTAT: RAI (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- RTC_STSSR --------------------------------- */ +#define RTC_STSSR_SPSE_Pos (0UL) /*!< RTC STSSR: SPSE (Bit 0) */ +#define RTC_STSSR_SPSE_Msk (0x1UL) /*!< RTC STSSR: SPSE (Bitfield-Mask: 0x01) */ +#define RTC_STSSR_SPMI_Pos (1UL) /*!< RTC STSSR: SPMI (Bit 1) */ +#define RTC_STSSR_SPMI_Msk (0x2UL) /*!< RTC STSSR: SPMI (Bitfield-Mask: 0x01) */ +#define RTC_STSSR_SPHO_Pos (2UL) /*!< RTC STSSR: SPHO (Bit 2) */ +#define RTC_STSSR_SPHO_Msk (0x4UL) /*!< RTC STSSR: SPHO (Bitfield-Mask: 0x01) */ +#define RTC_STSSR_SPDA_Pos (3UL) /*!< RTC STSSR: SPDA (Bit 3) */ +#define RTC_STSSR_SPDA_Msk (0x8UL) /*!< RTC STSSR: SPDA (Bitfield-Mask: 0x01) */ +#define RTC_STSSR_SPMO_Pos (5UL) /*!< RTC STSSR: SPMO (Bit 5) */ +#define RTC_STSSR_SPMO_Msk (0x20UL) /*!< RTC STSSR: SPMO (Bitfield-Mask: 0x01) */ +#define RTC_STSSR_SPYE_Pos (6UL) /*!< RTC STSSR: SPYE (Bit 6) */ +#define RTC_STSSR_SPYE_Msk (0x40UL) /*!< RTC STSSR: SPYE (Bitfield-Mask: 0x01) */ +#define RTC_STSSR_SAI_Pos (8UL) /*!< RTC STSSR: SAI (Bit 8) */ +#define RTC_STSSR_SAI_Msk (0x100UL) /*!< RTC STSSR: SAI (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- RTC_MSKSR --------------------------------- */ +#define RTC_MSKSR_MPSE_Pos (0UL) /*!< RTC MSKSR: MPSE (Bit 0) */ +#define RTC_MSKSR_MPSE_Msk (0x1UL) /*!< RTC MSKSR: MPSE (Bitfield-Mask: 0x01) */ +#define RTC_MSKSR_MPMI_Pos (1UL) /*!< RTC MSKSR: MPMI (Bit 1) */ +#define RTC_MSKSR_MPMI_Msk (0x2UL) /*!< RTC MSKSR: MPMI (Bitfield-Mask: 0x01) */ +#define RTC_MSKSR_MPHO_Pos (2UL) /*!< RTC MSKSR: MPHO (Bit 2) */ +#define RTC_MSKSR_MPHO_Msk (0x4UL) /*!< RTC MSKSR: MPHO (Bitfield-Mask: 0x01) */ +#define RTC_MSKSR_MPDA_Pos (3UL) /*!< RTC MSKSR: MPDA (Bit 3) */ +#define RTC_MSKSR_MPDA_Msk (0x8UL) /*!< RTC MSKSR: MPDA (Bitfield-Mask: 0x01) */ +#define RTC_MSKSR_MPMO_Pos (5UL) /*!< RTC MSKSR: MPMO (Bit 5) */ +#define RTC_MSKSR_MPMO_Msk (0x20UL) /*!< RTC MSKSR: MPMO (Bitfield-Mask: 0x01) */ +#define RTC_MSKSR_MPYE_Pos (6UL) /*!< RTC MSKSR: MPYE (Bit 6) */ +#define RTC_MSKSR_MPYE_Msk (0x40UL) /*!< RTC MSKSR: MPYE (Bitfield-Mask: 0x01) */ +#define RTC_MSKSR_MAI_Pos (8UL) /*!< RTC MSKSR: MAI (Bit 8) */ +#define RTC_MSKSR_MAI_Msk (0x100UL) /*!< RTC MSKSR: MAI (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- RTC_CLRSR --------------------------------- */ +#define RTC_CLRSR_RPSE_Pos (0UL) /*!< RTC CLRSR: RPSE (Bit 0) */ +#define RTC_CLRSR_RPSE_Msk (0x1UL) /*!< RTC CLRSR: RPSE (Bitfield-Mask: 0x01) */ +#define RTC_CLRSR_RPMI_Pos (1UL) /*!< RTC CLRSR: RPMI (Bit 1) */ +#define RTC_CLRSR_RPMI_Msk (0x2UL) /*!< RTC CLRSR: RPMI (Bitfield-Mask: 0x01) */ +#define RTC_CLRSR_RPHO_Pos (2UL) /*!< RTC CLRSR: RPHO (Bit 2) */ +#define RTC_CLRSR_RPHO_Msk (0x4UL) /*!< RTC CLRSR: RPHO (Bitfield-Mask: 0x01) */ +#define RTC_CLRSR_RPDA_Pos (3UL) /*!< RTC CLRSR: RPDA (Bit 3) */ +#define RTC_CLRSR_RPDA_Msk (0x8UL) /*!< RTC CLRSR: RPDA (Bitfield-Mask: 0x01) */ +#define RTC_CLRSR_RPMO_Pos (5UL) /*!< RTC CLRSR: RPMO (Bit 5) */ +#define RTC_CLRSR_RPMO_Msk (0x20UL) /*!< RTC CLRSR: RPMO (Bitfield-Mask: 0x01) */ +#define RTC_CLRSR_RPYE_Pos (6UL) /*!< RTC CLRSR: RPYE (Bit 6) */ +#define RTC_CLRSR_RPYE_Msk (0x40UL) /*!< RTC CLRSR: RPYE (Bitfield-Mask: 0x01) */ +#define RTC_CLRSR_RAI_Pos (8UL) /*!< RTC CLRSR: RAI (Bit 8) */ +#define RTC_CLRSR_RAI_Msk (0x100UL) /*!< RTC CLRSR: RAI (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- RTC_ATIM0 --------------------------------- */ +#define RTC_ATIM0_ASE_Pos (0UL) /*!< RTC ATIM0: ASE (Bit 0) */ +#define RTC_ATIM0_ASE_Msk (0x3fUL) /*!< RTC ATIM0: ASE (Bitfield-Mask: 0x3f) */ +#define RTC_ATIM0_AMI_Pos (8UL) /*!< RTC ATIM0: AMI (Bit 8) */ +#define RTC_ATIM0_AMI_Msk (0x3f00UL) /*!< RTC ATIM0: AMI (Bitfield-Mask: 0x3f) */ +#define RTC_ATIM0_AHO_Pos (16UL) /*!< RTC ATIM0: AHO (Bit 16) */ +#define RTC_ATIM0_AHO_Msk (0x1f0000UL) /*!< RTC ATIM0: AHO (Bitfield-Mask: 0x1f) */ +#define RTC_ATIM0_ADA_Pos (24UL) /*!< RTC ATIM0: ADA (Bit 24) */ +#define RTC_ATIM0_ADA_Msk (0x1f000000UL) /*!< RTC ATIM0: ADA (Bitfield-Mask: 0x1f) */ + +/* ---------------------------------- RTC_ATIM1 --------------------------------- */ +#define RTC_ATIM1_AMO_Pos (8UL) /*!< RTC ATIM1: AMO (Bit 8) */ +#define RTC_ATIM1_AMO_Msk (0xf00UL) /*!< RTC ATIM1: AMO (Bitfield-Mask: 0x0f) */ +#define RTC_ATIM1_AYE_Pos (16UL) /*!< RTC ATIM1: AYE (Bit 16) */ +#define RTC_ATIM1_AYE_Msk (0xffff0000UL) /*!< RTC ATIM1: AYE (Bitfield-Mask: 0xffff) */ + +/* ---------------------------------- RTC_TIM0 ---------------------------------- */ +#define RTC_TIM0_SE_Pos (0UL) /*!< RTC TIM0: SE (Bit 0) */ +#define RTC_TIM0_SE_Msk (0x3fUL) /*!< RTC TIM0: SE (Bitfield-Mask: 0x3f) */ +#define RTC_TIM0_MI_Pos (8UL) /*!< RTC TIM0: MI (Bit 8) */ +#define RTC_TIM0_MI_Msk (0x3f00UL) /*!< RTC TIM0: MI (Bitfield-Mask: 0x3f) */ +#define RTC_TIM0_HO_Pos (16UL) /*!< RTC TIM0: HO (Bit 16) */ +#define RTC_TIM0_HO_Msk (0x1f0000UL) /*!< RTC TIM0: HO (Bitfield-Mask: 0x1f) */ +#define RTC_TIM0_DA_Pos (24UL) /*!< RTC TIM0: DA (Bit 24) */ +#define RTC_TIM0_DA_Msk (0x1f000000UL) /*!< RTC TIM0: DA (Bitfield-Mask: 0x1f) */ + +/* ---------------------------------- RTC_TIM1 ---------------------------------- */ +#define RTC_TIM1_DAWE_Pos (0UL) /*!< RTC TIM1: DAWE (Bit 0) */ +#define RTC_TIM1_DAWE_Msk (0x7UL) /*!< RTC TIM1: DAWE (Bitfield-Mask: 0x07) */ +#define RTC_TIM1_MO_Pos (8UL) /*!< RTC TIM1: MO (Bit 8) */ +#define RTC_TIM1_MO_Msk (0xf00UL) /*!< RTC TIM1: MO (Bitfield-Mask: 0x0f) */ +#define RTC_TIM1_YE_Pos (16UL) /*!< RTC TIM1: YE (Bit 16) */ +#define RTC_TIM1_YE_Msk (0xffff0000UL) /*!< RTC TIM1: YE (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_CLK' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- SCU_CLK_CLKSTAT ------------------------------ */ +#define SCU_CLK_CLKSTAT_USBCST_Pos (0UL) /*!< SCU_CLK CLKSTAT: USBCST (Bit 0) */ +#define SCU_CLK_CLKSTAT_USBCST_Msk (0x1UL) /*!< SCU_CLK CLKSTAT: USBCST (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CLKSTAT_CCUCST_Pos (4UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bit 4) */ +#define SCU_CLK_CLKSTAT_CCUCST_Msk (0x10UL) /*!< SCU_CLK CLKSTAT: CCUCST (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CLKSTAT_WDTCST_Pos (5UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bit 5) */ +#define SCU_CLK_CLKSTAT_WDTCST_Msk (0x20UL) /*!< SCU_CLK CLKSTAT: WDTCST (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SCU_CLK_CLKSET ------------------------------- */ +#define SCU_CLK_CLKSET_USBCEN_Pos (0UL) /*!< SCU_CLK CLKSET: USBCEN (Bit 0) */ +#define SCU_CLK_CLKSET_USBCEN_Msk (0x1UL) /*!< SCU_CLK CLKSET: USBCEN (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CLKSET_CCUCEN_Pos (4UL) /*!< SCU_CLK CLKSET: CCUCEN (Bit 4) */ +#define SCU_CLK_CLKSET_CCUCEN_Msk (0x10UL) /*!< SCU_CLK CLKSET: CCUCEN (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CLKSET_WDTCEN_Pos (5UL) /*!< SCU_CLK CLKSET: WDTCEN (Bit 5) */ +#define SCU_CLK_CLKSET_WDTCEN_Msk (0x20UL) /*!< SCU_CLK CLKSET: WDTCEN (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SCU_CLK_CLKCLR ------------------------------- */ +#define SCU_CLK_CLKCLR_USBCDI_Pos (0UL) /*!< SCU_CLK CLKCLR: USBCDI (Bit 0) */ +#define SCU_CLK_CLKCLR_USBCDI_Msk (0x1UL) /*!< SCU_CLK CLKCLR: USBCDI (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CLKCLR_CCUCDI_Pos (4UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bit 4) */ +#define SCU_CLK_CLKCLR_CCUCDI_Msk (0x10UL) /*!< SCU_CLK CLKCLR: CCUCDI (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CLKCLR_WDTCDI_Pos (5UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bit 5) */ +#define SCU_CLK_CLKCLR_WDTCDI_Msk (0x20UL) /*!< SCU_CLK CLKCLR: WDTCDI (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_SYSCLKCR ------------------------------ */ +#define SCU_CLK_SYSCLKCR_SYSDIV_Pos (0UL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bit 0) */ +#define SCU_CLK_SYSCLKCR_SYSDIV_Msk (0xffUL) /*!< SCU_CLK SYSCLKCR: SYSDIV (Bitfield-Mask: 0xff) */ +#define SCU_CLK_SYSCLKCR_SYSSEL_Pos (16UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bit 16) */ +#define SCU_CLK_SYSCLKCR_SYSSEL_Msk (0x10000UL) /*!< SCU_CLK SYSCLKCR: SYSSEL (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CPUCLKCR ------------------------------ */ +#define SCU_CLK_CPUCLKCR_CPUDIV_Pos (0UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bit 0) */ +#define SCU_CLK_CPUCLKCR_CPUDIV_Msk (0x1UL) /*!< SCU_CLK CPUCLKCR: CPUDIV (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SCU_CLK_PBCLKCR ------------------------------ */ +#define SCU_CLK_PBCLKCR_PBDIV_Pos (0UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bit 0) */ +#define SCU_CLK_PBCLKCR_PBDIV_Msk (0x1UL) /*!< SCU_CLK PBCLKCR: PBDIV (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_USBCLKCR ------------------------------ */ +#define SCU_CLK_USBCLKCR_USBDIV_Pos (0UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bit 0) */ +#define SCU_CLK_USBCLKCR_USBDIV_Msk (0x7UL) /*!< SCU_CLK USBCLKCR: USBDIV (Bitfield-Mask: 0x07) */ +#define SCU_CLK_USBCLKCR_USBSEL_Pos (16UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bit 16) */ +#define SCU_CLK_USBCLKCR_USBSEL_Msk (0x10000UL) /*!< SCU_CLK USBCLKCR: USBSEL (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CCUCLKCR ------------------------------ */ +#define SCU_CLK_CCUCLKCR_CCUDIV_Pos (0UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bit 0) */ +#define SCU_CLK_CCUCLKCR_CCUDIV_Msk (0x1UL) /*!< SCU_CLK CCUCLKCR: CCUDIV (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_WDTCLKCR ------------------------------ */ +#define SCU_CLK_WDTCLKCR_WDTDIV_Pos (0UL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bit 0) */ +#define SCU_CLK_WDTCLKCR_WDTDIV_Msk (0xffUL) /*!< SCU_CLK WDTCLKCR: WDTDIV (Bitfield-Mask: 0xff) */ +#define SCU_CLK_WDTCLKCR_WDTSEL_Pos (16UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bit 16) */ +#define SCU_CLK_WDTCLKCR_WDTSEL_Msk (0x30000UL) /*!< SCU_CLK WDTCLKCR: WDTSEL (Bitfield-Mask: 0x03) */ + +/* ------------------------------ SCU_CLK_EXTCLKCR ------------------------------ */ +#define SCU_CLK_EXTCLKCR_ECKSEL_Pos (0UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bit 0) */ +#define SCU_CLK_EXTCLKCR_ECKSEL_Msk (0x7UL) /*!< SCU_CLK EXTCLKCR: ECKSEL (Bitfield-Mask: 0x07) */ +#define SCU_CLK_EXTCLKCR_ECKDIV_Pos (16UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bit 16) */ +#define SCU_CLK_EXTCLKCR_ECKDIV_Msk (0x1ff0000UL) /*!< SCU_CLK EXTCLKCR: ECKDIV (Bitfield-Mask: 0x1ff) */ + +/* ----------------------------- SCU_CLK_MLINKCLKCR ----------------------------- */ +#define SCU_CLK_MLINKCLKCR_SYSDIV_Pos (0UL) /*!< SCU_CLK MLINKCLKCR: SYSDIV (Bit 0) */ +#define SCU_CLK_MLINKCLKCR_SYSDIV_Msk (0xffUL) /*!< SCU_CLK MLINKCLKCR: SYSDIV (Bitfield-Mask: 0xff) */ +#define SCU_CLK_MLINKCLKCR_SYSSEL_Pos (8UL) /*!< SCU_CLK MLINKCLKCR: SYSSEL (Bit 8) */ +#define SCU_CLK_MLINKCLKCR_SYSSEL_Msk (0x100UL) /*!< SCU_CLK MLINKCLKCR: SYSSEL (Bitfield-Mask: 0x01) */ +#define SCU_CLK_MLINKCLKCR_CPUDIV_Pos (10UL) /*!< SCU_CLK MLINKCLKCR: CPUDIV (Bit 10) */ +#define SCU_CLK_MLINKCLKCR_CPUDIV_Msk (0x400UL) /*!< SCU_CLK MLINKCLKCR: CPUDIV (Bitfield-Mask: 0x01) */ +#define SCU_CLK_MLINKCLKCR_PBDIV_Pos (12UL) /*!< SCU_CLK MLINKCLKCR: PBDIV (Bit 12) */ +#define SCU_CLK_MLINKCLKCR_PBDIV_Msk (0x1000UL) /*!< SCU_CLK MLINKCLKCR: PBDIV (Bitfield-Mask: 0x01) */ +#define SCU_CLK_MLINKCLKCR_CCUDIV_Pos (14UL) /*!< SCU_CLK MLINKCLKCR: CCUDIV (Bit 14) */ +#define SCU_CLK_MLINKCLKCR_CCUDIV_Msk (0x4000UL) /*!< SCU_CLK MLINKCLKCR: CCUDIV (Bitfield-Mask: 0x01) */ +#define SCU_CLK_MLINKCLKCR_WDTDIV_Pos (16UL) /*!< SCU_CLK MLINKCLKCR: WDTDIV (Bit 16) */ +#define SCU_CLK_MLINKCLKCR_WDTDIV_Msk (0xff0000UL) /*!< SCU_CLK MLINKCLKCR: WDTDIV (Bitfield-Mask: 0xff) */ +#define SCU_CLK_MLINKCLKCR_WDTSEL_Pos (24UL) /*!< SCU_CLK MLINKCLKCR: WDTSEL (Bit 24) */ +#define SCU_CLK_MLINKCLKCR_WDTSEL_Msk (0x3000000UL) /*!< SCU_CLK MLINKCLKCR: WDTSEL (Bitfield-Mask: 0x03) */ + +/* ------------------------------- SCU_CLK_SLEEPCR ------------------------------ */ +#define SCU_CLK_SLEEPCR_SYSSEL_Pos (0UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bit 0) */ +#define SCU_CLK_SLEEPCR_SYSSEL_Msk (0x1UL) /*!< SCU_CLK SLEEPCR: SYSSEL (Bitfield-Mask: 0x01) */ +#define SCU_CLK_SLEEPCR_USBCR_Pos (16UL) /*!< SCU_CLK SLEEPCR: USBCR (Bit 16) */ +#define SCU_CLK_SLEEPCR_USBCR_Msk (0x10000UL) /*!< SCU_CLK SLEEPCR: USBCR (Bitfield-Mask: 0x01) */ +#define SCU_CLK_SLEEPCR_CCUCR_Pos (20UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bit 20) */ +#define SCU_CLK_SLEEPCR_CCUCR_Msk (0x100000UL) /*!< SCU_CLK SLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ +#define SCU_CLK_SLEEPCR_WDTCR_Pos (21UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bit 21) */ +#define SCU_CLK_SLEEPCR_WDTCR_Msk (0x200000UL) /*!< SCU_CLK SLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_DSLEEPCR ------------------------------ */ +#define SCU_CLK_DSLEEPCR_SYSSEL_Pos (0UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bit 0) */ +#define SCU_CLK_DSLEEPCR_SYSSEL_Msk (0x1UL) /*!< SCU_CLK DSLEEPCR: SYSSEL (Bitfield-Mask: 0x01) */ +#define SCU_CLK_DSLEEPCR_FPDN_Pos (11UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bit 11) */ +#define SCU_CLK_DSLEEPCR_FPDN_Msk (0x800UL) /*!< SCU_CLK DSLEEPCR: FPDN (Bitfield-Mask: 0x01) */ +#define SCU_CLK_DSLEEPCR_PLLPDN_Pos (12UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bit 12) */ +#define SCU_CLK_DSLEEPCR_PLLPDN_Msk (0x1000UL) /*!< SCU_CLK DSLEEPCR: PLLPDN (Bitfield-Mask: 0x01) */ +#define SCU_CLK_DSLEEPCR_VCOPDN_Pos (13UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bit 13) */ +#define SCU_CLK_DSLEEPCR_VCOPDN_Msk (0x2000UL) /*!< SCU_CLK DSLEEPCR: VCOPDN (Bitfield-Mask: 0x01) */ +#define SCU_CLK_DSLEEPCR_USBCR_Pos (16UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bit 16) */ +#define SCU_CLK_DSLEEPCR_USBCR_Msk (0x10000UL) /*!< SCU_CLK DSLEEPCR: USBCR (Bitfield-Mask: 0x01) */ +#define SCU_CLK_DSLEEPCR_CCUCR_Pos (20UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bit 20) */ +#define SCU_CLK_DSLEEPCR_CCUCR_Msk (0x100000UL) /*!< SCU_CLK DSLEEPCR: CCUCR (Bitfield-Mask: 0x01) */ +#define SCU_CLK_DSLEEPCR_WDTCR_Pos (21UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bit 21) */ +#define SCU_CLK_DSLEEPCR_WDTCR_Msk (0x200000UL) /*!< SCU_CLK DSLEEPCR: WDTCR (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */ +#define SCU_CLK_CGATSTAT0_VADC_Pos (0UL) /*!< SCU_CLK CGATSTAT0: VADC (Bit 0) */ +#define SCU_CLK_CGATSTAT0_VADC_Msk (0x1UL) /*!< SCU_CLK CGATSTAT0: VADC (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT0_CCU40_Pos (2UL) /*!< SCU_CLK CGATSTAT0: CCU40 (Bit 2) */ +#define SCU_CLK_CGATSTAT0_CCU40_Msk (0x4UL) /*!< SCU_CLK CGATSTAT0: CCU40 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT0_CCU41_Pos (3UL) /*!< SCU_CLK CGATSTAT0: CCU41 (Bit 3) */ +#define SCU_CLK_CGATSTAT0_CCU41_Msk (0x8UL) /*!< SCU_CLK CGATSTAT0: CCU41 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT0_CCU80_Pos (7UL) /*!< SCU_CLK CGATSTAT0: CCU80 (Bit 7) */ +#define SCU_CLK_CGATSTAT0_CCU80_Msk (0x80UL) /*!< SCU_CLK CGATSTAT0: CCU80 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT0_POSIF0_Pos (9UL) /*!< SCU_CLK CGATSTAT0: POSIF0 (Bit 9) */ +#define SCU_CLK_CGATSTAT0_POSIF0_Msk (0x200UL) /*!< SCU_CLK CGATSTAT0: POSIF0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT0_USIC0_Pos (11UL) /*!< SCU_CLK CGATSTAT0: USIC0 (Bit 11) */ +#define SCU_CLK_CGATSTAT0_USIC0_Msk (0x800UL) /*!< SCU_CLK CGATSTAT0: USIC0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT0_ERU1_Pos (16UL) /*!< SCU_CLK CGATSTAT0: ERU1 (Bit 16) */ +#define SCU_CLK_CGATSTAT0_ERU1_Msk (0x10000UL) /*!< SCU_CLK CGATSTAT0: ERU1 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT0_HRPWM0_Pos (23UL) /*!< SCU_CLK CGATSTAT0: HRPWM0 (Bit 23) */ +#define SCU_CLK_CGATSTAT0_HRPWM0_Msk (0x800000UL) /*!< SCU_CLK CGATSTAT0: HRPWM0 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */ +#define SCU_CLK_CGATSET0_VADC_Pos (0UL) /*!< SCU_CLK CGATSET0: VADC (Bit 0) */ +#define SCU_CLK_CGATSET0_VADC_Msk (0x1UL) /*!< SCU_CLK CGATSET0: VADC (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET0_CCU40_Pos (2UL) /*!< SCU_CLK CGATSET0: CCU40 (Bit 2) */ +#define SCU_CLK_CGATSET0_CCU40_Msk (0x4UL) /*!< SCU_CLK CGATSET0: CCU40 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET0_CCU41_Pos (3UL) /*!< SCU_CLK CGATSET0: CCU41 (Bit 3) */ +#define SCU_CLK_CGATSET0_CCU41_Msk (0x8UL) /*!< SCU_CLK CGATSET0: CCU41 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET0_CCU80_Pos (7UL) /*!< SCU_CLK CGATSET0: CCU80 (Bit 7) */ +#define SCU_CLK_CGATSET0_CCU80_Msk (0x80UL) /*!< SCU_CLK CGATSET0: CCU80 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET0_POSIF0_Pos (9UL) /*!< SCU_CLK CGATSET0: POSIF0 (Bit 9) */ +#define SCU_CLK_CGATSET0_POSIF0_Msk (0x200UL) /*!< SCU_CLK CGATSET0: POSIF0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET0_USIC0_Pos (11UL) /*!< SCU_CLK CGATSET0: USIC0 (Bit 11) */ +#define SCU_CLK_CGATSET0_USIC0_Msk (0x800UL) /*!< SCU_CLK CGATSET0: USIC0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET0_ERU1_Pos (16UL) /*!< SCU_CLK CGATSET0: ERU1 (Bit 16) */ +#define SCU_CLK_CGATSET0_ERU1_Msk (0x10000UL) /*!< SCU_CLK CGATSET0: ERU1 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET0_HRPWM0_Pos (23UL) /*!< SCU_CLK CGATSET0: HRPWM0 (Bit 23) */ +#define SCU_CLK_CGATSET0_HRPWM0_Msk (0x800000UL) /*!< SCU_CLK CGATSET0: HRPWM0 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */ +#define SCU_CLK_CGATCLR0_VADC_Pos (0UL) /*!< SCU_CLK CGATCLR0: VADC (Bit 0) */ +#define SCU_CLK_CGATCLR0_VADC_Msk (0x1UL) /*!< SCU_CLK CGATCLR0: VADC (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR0_CCU40_Pos (2UL) /*!< SCU_CLK CGATCLR0: CCU40 (Bit 2) */ +#define SCU_CLK_CGATCLR0_CCU40_Msk (0x4UL) /*!< SCU_CLK CGATCLR0: CCU40 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR0_CCU41_Pos (3UL) /*!< SCU_CLK CGATCLR0: CCU41 (Bit 3) */ +#define SCU_CLK_CGATCLR0_CCU41_Msk (0x8UL) /*!< SCU_CLK CGATCLR0: CCU41 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR0_CCU80_Pos (7UL) /*!< SCU_CLK CGATCLR0: CCU80 (Bit 7) */ +#define SCU_CLK_CGATCLR0_CCU80_Msk (0x80UL) /*!< SCU_CLK CGATCLR0: CCU80 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR0_POSIF0_Pos (9UL) /*!< SCU_CLK CGATCLR0: POSIF0 (Bit 9) */ +#define SCU_CLK_CGATCLR0_POSIF0_Msk (0x200UL) /*!< SCU_CLK CGATCLR0: POSIF0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR0_USIC0_Pos (11UL) /*!< SCU_CLK CGATCLR0: USIC0 (Bit 11) */ +#define SCU_CLK_CGATCLR0_USIC0_Msk (0x800UL) /*!< SCU_CLK CGATCLR0: USIC0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR0_ERU1_Pos (16UL) /*!< SCU_CLK CGATCLR0: ERU1 (Bit 16) */ +#define SCU_CLK_CGATCLR0_ERU1_Msk (0x10000UL) /*!< SCU_CLK CGATCLR0: ERU1 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR0_HRPWM0_Pos (23UL) /*!< SCU_CLK CGATCLR0: HRPWM0 (Bit 23) */ +#define SCU_CLK_CGATCLR0_HRPWM0_Msk (0x800000UL) /*!< SCU_CLK CGATCLR0: HRPWM0 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATSTAT1 ----------------------------- */ +#define SCU_CLK_CGATSTAT1_LEDTSCU0_Pos (3UL) /*!< SCU_CLK CGATSTAT1: LEDTSCU0 (Bit 3) */ +#define SCU_CLK_CGATSTAT1_LEDTSCU0_Msk (0x8UL) /*!< SCU_CLK CGATSTAT1: LEDTSCU0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT1_MCAN0_Pos (4UL) /*!< SCU_CLK CGATSTAT1: MCAN0 (Bit 4) */ +#define SCU_CLK_CGATSTAT1_MCAN0_Msk (0x10UL) /*!< SCU_CLK CGATSTAT1: MCAN0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT1_DAC_Pos (5UL) /*!< SCU_CLK CGATSTAT1: DAC (Bit 5) */ +#define SCU_CLK_CGATSTAT1_DAC_Msk (0x20UL) /*!< SCU_CLK CGATSTAT1: DAC (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT1_USIC1_Pos (7UL) /*!< SCU_CLK CGATSTAT1: USIC1 (Bit 7) */ +#define SCU_CLK_CGATSTAT1_USIC1_Msk (0x80UL) /*!< SCU_CLK CGATSTAT1: USIC1 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT1_PPORTS_Pos (9UL) /*!< SCU_CLK CGATSTAT1: PPORTS (Bit 9) */ +#define SCU_CLK_CGATSTAT1_PPORTS_Msk (0x200UL) /*!< SCU_CLK CGATSTAT1: PPORTS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATSET1 ------------------------------ */ +#define SCU_CLK_CGATSET1_LEDTSCU0_Pos (3UL) /*!< SCU_CLK CGATSET1: LEDTSCU0 (Bit 3) */ +#define SCU_CLK_CGATSET1_LEDTSCU0_Msk (0x8UL) /*!< SCU_CLK CGATSET1: LEDTSCU0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET1_MCAN0_Pos (4UL) /*!< SCU_CLK CGATSET1: MCAN0 (Bit 4) */ +#define SCU_CLK_CGATSET1_MCAN0_Msk (0x10UL) /*!< SCU_CLK CGATSET1: MCAN0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET1_DAC_Pos (5UL) /*!< SCU_CLK CGATSET1: DAC (Bit 5) */ +#define SCU_CLK_CGATSET1_DAC_Msk (0x20UL) /*!< SCU_CLK CGATSET1: DAC (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET1_USIC1_Pos (7UL) /*!< SCU_CLK CGATSET1: USIC1 (Bit 7) */ +#define SCU_CLK_CGATSET1_USIC1_Msk (0x80UL) /*!< SCU_CLK CGATSET1: USIC1 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET1_PPORTS_Pos (9UL) /*!< SCU_CLK CGATSET1: PPORTS (Bit 9) */ +#define SCU_CLK_CGATSET1_PPORTS_Msk (0x200UL) /*!< SCU_CLK CGATSET1: PPORTS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATCLR1 ------------------------------ */ +#define SCU_CLK_CGATCLR1_LEDTSCU0_Pos (3UL) /*!< SCU_CLK CGATCLR1: LEDTSCU0 (Bit 3) */ +#define SCU_CLK_CGATCLR1_LEDTSCU0_Msk (0x8UL) /*!< SCU_CLK CGATCLR1: LEDTSCU0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR1_MCAN0_Pos (4UL) /*!< SCU_CLK CGATCLR1: MCAN0 (Bit 4) */ +#define SCU_CLK_CGATCLR1_MCAN0_Msk (0x10UL) /*!< SCU_CLK CGATCLR1: MCAN0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR1_DAC_Pos (5UL) /*!< SCU_CLK CGATCLR1: DAC (Bit 5) */ +#define SCU_CLK_CGATCLR1_DAC_Msk (0x20UL) /*!< SCU_CLK CGATCLR1: DAC (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR1_USIC1_Pos (7UL) /*!< SCU_CLK CGATCLR1: USIC1 (Bit 7) */ +#define SCU_CLK_CGATCLR1_USIC1_Msk (0x80UL) /*!< SCU_CLK CGATCLR1: USIC1 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR1_PPORTS_Pos (9UL) /*!< SCU_CLK CGATCLR1: PPORTS (Bit 9) */ +#define SCU_CLK_CGATCLR1_PPORTS_Msk (0x200UL) /*!< SCU_CLK CGATCLR1: PPORTS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATSTAT2 ----------------------------- */ +#define SCU_CLK_CGATSTAT2_WDT_Pos (1UL) /*!< SCU_CLK CGATSTAT2: WDT (Bit 1) */ +#define SCU_CLK_CGATSTAT2_WDT_Msk (0x2UL) /*!< SCU_CLK CGATSTAT2: WDT (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT2_DMA0_Pos (4UL) /*!< SCU_CLK CGATSTAT2: DMA0 (Bit 4) */ +#define SCU_CLK_CGATSTAT2_DMA0_Msk (0x10UL) /*!< SCU_CLK CGATSTAT2: DMA0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT2_FCE_Pos (6UL) /*!< SCU_CLK CGATSTAT2: FCE (Bit 6) */ +#define SCU_CLK_CGATSTAT2_FCE_Msk (0x40UL) /*!< SCU_CLK CGATSTAT2: FCE (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSTAT2_USB_Pos (7UL) /*!< SCU_CLK CGATSTAT2: USB (Bit 7) */ +#define SCU_CLK_CGATSTAT2_USB_Msk (0x80UL) /*!< SCU_CLK CGATSTAT2: USB (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATSET2 ------------------------------ */ +#define SCU_CLK_CGATSET2_WDT_Pos (1UL) /*!< SCU_CLK CGATSET2: WDT (Bit 1) */ +#define SCU_CLK_CGATSET2_WDT_Msk (0x2UL) /*!< SCU_CLK CGATSET2: WDT (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET2_DMA0_Pos (4UL) /*!< SCU_CLK CGATSET2: DMA0 (Bit 4) */ +#define SCU_CLK_CGATSET2_DMA0_Msk (0x10UL) /*!< SCU_CLK CGATSET2: DMA0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET2_FCE_Pos (6UL) /*!< SCU_CLK CGATSET2: FCE (Bit 6) */ +#define SCU_CLK_CGATSET2_FCE_Msk (0x40UL) /*!< SCU_CLK CGATSET2: FCE (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATSET2_USB_Pos (7UL) /*!< SCU_CLK CGATSET2: USB (Bit 7) */ +#define SCU_CLK_CGATSET2_USB_Msk (0x80UL) /*!< SCU_CLK CGATSET2: USB (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_CLK_CGATCLR2 ------------------------------ */ +#define SCU_CLK_CGATCLR2_WDT_Pos (1UL) /*!< SCU_CLK CGATCLR2: WDT (Bit 1) */ +#define SCU_CLK_CGATCLR2_WDT_Msk (0x2UL) /*!< SCU_CLK CGATCLR2: WDT (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR2_DMA0_Pos (4UL) /*!< SCU_CLK CGATCLR2: DMA0 (Bit 4) */ +#define SCU_CLK_CGATCLR2_DMA0_Msk (0x10UL) /*!< SCU_CLK CGATCLR2: DMA0 (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR2_FCE_Pos (6UL) /*!< SCU_CLK CGATCLR2: FCE (Bit 6) */ +#define SCU_CLK_CGATCLR2_FCE_Msk (0x40UL) /*!< SCU_CLK CGATCLR2: FCE (Bitfield-Mask: 0x01) */ +#define SCU_CLK_CGATCLR2_USB_Pos (7UL) /*!< SCU_CLK CGATCLR2: USB (Bit 7) */ +#define SCU_CLK_CGATCLR2_USB_Msk (0x80UL) /*!< SCU_CLK CGATCLR2: USB (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_OSC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ SCU_OSC_OSCHPSTAT ----------------------------- */ +#define SCU_OSC_OSCHPSTAT_X1D_Pos (0UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bit 0) */ +#define SCU_OSC_OSCHPSTAT_X1D_Msk (0x1UL) /*!< SCU_OSC OSCHPSTAT: X1D (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_OSC_OSCHPCTRL ----------------------------- */ +#define SCU_OSC_OSCHPCTRL_X1DEN_Pos (0UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bit 0) */ +#define SCU_OSC_OSCHPCTRL_X1DEN_Msk (0x1UL) /*!< SCU_OSC OSCHPCTRL: X1DEN (Bitfield-Mask: 0x01) */ +#define SCU_OSC_OSCHPCTRL_SHBY_Pos (1UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bit 1) */ +#define SCU_OSC_OSCHPCTRL_SHBY_Msk (0x2UL) /*!< SCU_OSC OSCHPCTRL: SHBY (Bitfield-Mask: 0x01) */ +#define SCU_OSC_OSCHPCTRL_MODE_Pos (4UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bit 4) */ +#define SCU_OSC_OSCHPCTRL_MODE_Msk (0x30UL) /*!< SCU_OSC OSCHPCTRL: MODE (Bitfield-Mask: 0x03) */ +#define SCU_OSC_OSCHPCTRL_OSCVAL_Pos (16UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bit 16) */ +#define SCU_OSC_OSCHPCTRL_OSCVAL_Msk (0xf0000UL) /*!< SCU_OSC OSCHPCTRL: OSCVAL (Bitfield-Mask: 0x0f) */ + +/* ----------------------------- SCU_OSC_CLKCALCONST ---------------------------- */ +#define SCU_OSC_CLKCALCONST_CALIBCONST_Pos (0UL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bit 0) */ +#define SCU_OSC_CLKCALCONST_CALIBCONST_Msk (0xfUL) /*!< SCU_OSC CLKCALCONST: CALIBCONST (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_PLL' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- SCU_PLL_PLLSTAT ------------------------------ */ +#define SCU_PLL_PLLSTAT_VCOBYST_Pos (0UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bit 0) */ +#define SCU_PLL_PLLSTAT_VCOBYST_Msk (0x1UL) /*!< SCU_PLL PLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_PWDSTAT_Pos (1UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bit 1) */ +#define SCU_PLL_PLLSTAT_PWDSTAT_Msk (0x2UL) /*!< SCU_PLL PLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_VCOLOCK_Pos (2UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bit 2) */ +#define SCU_PLL_PLLSTAT_VCOLOCK_Msk (0x4UL) /*!< SCU_PLL PLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_K1RDY_Pos (4UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bit 4) */ +#define SCU_PLL_PLLSTAT_K1RDY_Msk (0x10UL) /*!< SCU_PLL PLLSTAT: K1RDY (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_K2RDY_Pos (5UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bit 5) */ +#define SCU_PLL_PLLSTAT_K2RDY_Msk (0x20UL) /*!< SCU_PLL PLLSTAT: K2RDY (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_BY_Pos (6UL) /*!< SCU_PLL PLLSTAT: BY (Bit 6) */ +#define SCU_PLL_PLLSTAT_BY_Msk (0x40UL) /*!< SCU_PLL PLLSTAT: BY (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_PLLLV_Pos (7UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bit 7) */ +#define SCU_PLL_PLLSTAT_PLLLV_Msk (0x80UL) /*!< SCU_PLL PLLSTAT: PLLLV (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_PLLHV_Pos (8UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bit 8) */ +#define SCU_PLL_PLLSTAT_PLLHV_Msk (0x100UL) /*!< SCU_PLL PLLSTAT: PLLHV (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLSTAT_PLLSP_Pos (9UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bit 9) */ +#define SCU_PLL_PLLSTAT_PLLSP_Msk (0x200UL) /*!< SCU_PLL PLLSTAT: PLLSP (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SCU_PLL_PLLCON0 ------------------------------ */ +#define SCU_PLL_PLLCON0_VCOBYP_Pos (0UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bit 0) */ +#define SCU_PLL_PLLCON0_VCOBYP_Msk (0x1UL) /*!< SCU_PLL PLLCON0: VCOBYP (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_VCOPWD_Pos (1UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bit 1) */ +#define SCU_PLL_PLLCON0_VCOPWD_Msk (0x2UL) /*!< SCU_PLL PLLCON0: VCOPWD (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_VCOTR_Pos (2UL) /*!< SCU_PLL PLLCON0: VCOTR (Bit 2) */ +#define SCU_PLL_PLLCON0_VCOTR_Msk (0x4UL) /*!< SCU_PLL PLLCON0: VCOTR (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_FINDIS_Pos (4UL) /*!< SCU_PLL PLLCON0: FINDIS (Bit 4) */ +#define SCU_PLL_PLLCON0_FINDIS_Msk (0x10UL) /*!< SCU_PLL PLLCON0: FINDIS (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_OSCDISCDIS_Pos (6UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bit 6) */ +#define SCU_PLL_PLLCON0_OSCDISCDIS_Msk (0x40UL) /*!< SCU_PLL PLLCON0: OSCDISCDIS (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_PLLPWD_Pos (16UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bit 16) */ +#define SCU_PLL_PLLCON0_PLLPWD_Msk (0x10000UL) /*!< SCU_PLL PLLCON0: PLLPWD (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_OSCRES_Pos (17UL) /*!< SCU_PLL PLLCON0: OSCRES (Bit 17) */ +#define SCU_PLL_PLLCON0_OSCRES_Msk (0x20000UL) /*!< SCU_PLL PLLCON0: OSCRES (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_RESLD_Pos (18UL) /*!< SCU_PLL PLLCON0: RESLD (Bit 18) */ +#define SCU_PLL_PLLCON0_RESLD_Msk (0x40000UL) /*!< SCU_PLL PLLCON0: RESLD (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_AOTREN_Pos (19UL) /*!< SCU_PLL PLLCON0: AOTREN (Bit 19) */ +#define SCU_PLL_PLLCON0_AOTREN_Msk (0x80000UL) /*!< SCU_PLL PLLCON0: AOTREN (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON0_FOTR_Pos (20UL) /*!< SCU_PLL PLLCON0: FOTR (Bit 20) */ +#define SCU_PLL_PLLCON0_FOTR_Msk (0x100000UL) /*!< SCU_PLL PLLCON0: FOTR (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SCU_PLL_PLLCON1 ------------------------------ */ +#define SCU_PLL_PLLCON1_K1DIV_Pos (0UL) /*!< SCU_PLL PLLCON1: K1DIV (Bit 0) */ +#define SCU_PLL_PLLCON1_K1DIV_Msk (0x7fUL) /*!< SCU_PLL PLLCON1: K1DIV (Bitfield-Mask: 0x7f) */ +#define SCU_PLL_PLLCON1_NDIV_Pos (8UL) /*!< SCU_PLL PLLCON1: NDIV (Bit 8) */ +#define SCU_PLL_PLLCON1_NDIV_Msk (0x7f00UL) /*!< SCU_PLL PLLCON1: NDIV (Bitfield-Mask: 0x7f) */ +#define SCU_PLL_PLLCON1_K2DIV_Pos (16UL) /*!< SCU_PLL PLLCON1: K2DIV (Bit 16) */ +#define SCU_PLL_PLLCON1_K2DIV_Msk (0x7f0000UL) /*!< SCU_PLL PLLCON1: K2DIV (Bitfield-Mask: 0x7f) */ +#define SCU_PLL_PLLCON1_PDIV_Pos (24UL) /*!< SCU_PLL PLLCON1: PDIV (Bit 24) */ +#define SCU_PLL_PLLCON1_PDIV_Msk (0xf000000UL) /*!< SCU_PLL PLLCON1: PDIV (Bitfield-Mask: 0x0f) */ + +/* ------------------------------- SCU_PLL_PLLCON2 ------------------------------ */ +#define SCU_PLL_PLLCON2_PINSEL_Pos (0UL) /*!< SCU_PLL PLLCON2: PINSEL (Bit 0) */ +#define SCU_PLL_PLLCON2_PINSEL_Msk (0x1UL) /*!< SCU_PLL PLLCON2: PINSEL (Bitfield-Mask: 0x01) */ +#define SCU_PLL_PLLCON2_K1INSEL_Pos (8UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bit 8) */ +#define SCU_PLL_PLLCON2_K1INSEL_Msk (0x100UL) /*!< SCU_PLL PLLCON2: K1INSEL (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_PLL_USBPLLSTAT ----------------------------- */ +#define SCU_PLL_USBPLLSTAT_VCOBYST_Pos (0UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bit 0) */ +#define SCU_PLL_USBPLLSTAT_VCOBYST_Msk (0x1UL) /*!< SCU_PLL USBPLLSTAT: VCOBYST (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos (1UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bit 1) */ +#define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk (0x2UL) /*!< SCU_PLL USBPLLSTAT: PWDSTAT (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos (2UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bit 2) */ +#define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk (0x4UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCK (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLSTAT_BY_Pos (6UL) /*!< SCU_PLL USBPLLSTAT: BY (Bit 6) */ +#define SCU_PLL_USBPLLSTAT_BY_Msk (0x40UL) /*!< SCU_PLL USBPLLSTAT: BY (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos (7UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bit 7) */ +#define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk (0x80UL) /*!< SCU_PLL USBPLLSTAT: VCOLOCKED (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_PLL_USBPLLCON ----------------------------- */ +#define SCU_PLL_USBPLLCON_VCOBYP_Pos (0UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bit 0) */ +#define SCU_PLL_USBPLLCON_VCOBYP_Msk (0x1UL) /*!< SCU_PLL USBPLLCON: VCOBYP (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLCON_VCOPWD_Pos (1UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bit 1) */ +#define SCU_PLL_USBPLLCON_VCOPWD_Msk (0x2UL) /*!< SCU_PLL USBPLLCON: VCOPWD (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLCON_VCOTR_Pos (2UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bit 2) */ +#define SCU_PLL_USBPLLCON_VCOTR_Msk (0x4UL) /*!< SCU_PLL USBPLLCON: VCOTR (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLCON_FINDIS_Pos (4UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bit 4) */ +#define SCU_PLL_USBPLLCON_FINDIS_Msk (0x10UL) /*!< SCU_PLL USBPLLCON: FINDIS (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos (6UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bit 6) */ +#define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk (0x40UL) /*!< SCU_PLL USBPLLCON: OSCDISCDIS (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLCON_NDIV_Pos (8UL) /*!< SCU_PLL USBPLLCON: NDIV (Bit 8) */ +#define SCU_PLL_USBPLLCON_NDIV_Msk (0x7f00UL) /*!< SCU_PLL USBPLLCON: NDIV (Bitfield-Mask: 0x7f) */ +#define SCU_PLL_USBPLLCON_PLLPWD_Pos (16UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bit 16) */ +#define SCU_PLL_USBPLLCON_PLLPWD_Msk (0x10000UL) /*!< SCU_PLL USBPLLCON: PLLPWD (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLCON_RESLD_Pos (18UL) /*!< SCU_PLL USBPLLCON: RESLD (Bit 18) */ +#define SCU_PLL_USBPLLCON_RESLD_Msk (0x40000UL) /*!< SCU_PLL USBPLLCON: RESLD (Bitfield-Mask: 0x01) */ +#define SCU_PLL_USBPLLCON_PDIV_Pos (24UL) /*!< SCU_PLL USBPLLCON: PDIV (Bit 24) */ +#define SCU_PLL_USBPLLCON_PDIV_Msk (0xf000000UL) /*!< SCU_PLL USBPLLCON: PDIV (Bitfield-Mask: 0x0f) */ + +/* ------------------------------ SCU_PLL_CLKMXSTAT ----------------------------- */ +#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos (0UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bit 0) */ +#define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk (0x3UL) /*!< SCU_PLL CLKMXSTAT: SYSCLKMUX (Bitfield-Mask: 0x03) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_GENERAL' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- SCU_GENERAL_ID ------------------------------- */ +#define SCU_GENERAL_ID_MOD_REV_Pos (0UL) /*!< SCU_GENERAL ID: MOD_REV (Bit 0) */ +#define SCU_GENERAL_ID_MOD_REV_Msk (0xffUL) /*!< SCU_GENERAL ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define SCU_GENERAL_ID_MOD_TYPE_Pos (8UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bit 8) */ +#define SCU_GENERAL_ID_MOD_TYPE_Msk (0xff00UL) /*!< SCU_GENERAL ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define SCU_GENERAL_ID_MOD_NUMBER_Pos (16UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bit 16) */ +#define SCU_GENERAL_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< SCU_GENERAL ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */ +#define SCU_GENERAL_IDCHIP_IDCHIP_Pos (0UL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bit 0) */ +#define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL) /*!< SCU_GENERAL IDCHIP: IDCHIP (Bitfield-Mask: 0xffffffff) */ + +/* ----------------------------- SCU_GENERAL_IDMANUF ---------------------------- */ +#define SCU_GENERAL_IDMANUF_DEPT_Pos (0UL) /*!< SCU_GENERAL IDMANUF: DEPT (Bit 0) */ +#define SCU_GENERAL_IDMANUF_DEPT_Msk (0x1fUL) /*!< SCU_GENERAL IDMANUF: DEPT (Bitfield-Mask: 0x1f) */ +#define SCU_GENERAL_IDMANUF_MANUF_Pos (5UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bit 5) */ +#define SCU_GENERAL_IDMANUF_MANUF_Msk (0xffe0UL) /*!< SCU_GENERAL IDMANUF: MANUF (Bitfield-Mask: 0x7ff) */ + +/* ------------------------------ SCU_GENERAL_STCON ----------------------------- */ +#define SCU_GENERAL_STCON_HWCON_Pos (0UL) /*!< SCU_GENERAL STCON: HWCON (Bit 0) */ +#define SCU_GENERAL_STCON_HWCON_Msk (0x3UL) /*!< SCU_GENERAL STCON: HWCON (Bitfield-Mask: 0x03) */ +#define SCU_GENERAL_STCON_SWCON_Pos (8UL) /*!< SCU_GENERAL STCON: SWCON (Bit 8) */ +#define SCU_GENERAL_STCON_SWCON_Msk (0xf00UL) /*!< SCU_GENERAL STCON: SWCON (Bitfield-Mask: 0x0f) */ + +/* ------------------------------- SCU_GENERAL_GPR ------------------------------ */ +#define SCU_GENERAL_GPR_DAT_Pos (0UL) /*!< SCU_GENERAL GPR: DAT (Bit 0) */ +#define SCU_GENERAL_GPR_DAT_Msk (0xffffffffUL) /*!< SCU_GENERAL GPR: DAT (Bitfield-Mask: 0xffffffff) */ + +/* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */ +#define SCU_GENERAL_CCUCON_GSC40_Pos (0UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bit 0) */ +#define SCU_GENERAL_CCUCON_GSC40_Msk (0x1UL) /*!< SCU_GENERAL CCUCON: GSC40 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_CCUCON_GSC41_Pos (1UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bit 1) */ +#define SCU_GENERAL_CCUCON_GSC41_Msk (0x2UL) /*!< SCU_GENERAL CCUCON: GSC41 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_CCUCON_GSC80_Pos (8UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bit 8) */ +#define SCU_GENERAL_CCUCON_GSC80_Msk (0x100UL) /*!< SCU_GENERAL CCUCON: GSC80 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_CCUCON_GSHR0_Pos (24UL) /*!< SCU_GENERAL CCUCON: GSHR0 (Bit 24) */ +#define SCU_GENERAL_CCUCON_GSHR0_Msk (0x1000000UL) /*!< SCU_GENERAL CCUCON: GSHR0 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_GENERAL_DTSCON ----------------------------- */ +#define SCU_GENERAL_DTSCON_PWD_Pos (0UL) /*!< SCU_GENERAL DTSCON: PWD (Bit 0) */ +#define SCU_GENERAL_DTSCON_PWD_Msk (0x1UL) /*!< SCU_GENERAL DTSCON: PWD (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_DTSCON_START_Pos (1UL) /*!< SCU_GENERAL DTSCON: START (Bit 1) */ +#define SCU_GENERAL_DTSCON_START_Msk (0x2UL) /*!< SCU_GENERAL DTSCON: START (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_DTSCON_OFFSET_Pos (4UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bit 4) */ +#define SCU_GENERAL_DTSCON_OFFSET_Msk (0x7f0UL) /*!< SCU_GENERAL DTSCON: OFFSET (Bitfield-Mask: 0x7f) */ +#define SCU_GENERAL_DTSCON_GAIN_Pos (11UL) /*!< SCU_GENERAL DTSCON: GAIN (Bit 11) */ +#define SCU_GENERAL_DTSCON_GAIN_Msk (0x1f800UL) /*!< SCU_GENERAL DTSCON: GAIN (Bitfield-Mask: 0x3f) */ +#define SCU_GENERAL_DTSCON_REFTRIM_Pos (17UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bit 17) */ +#define SCU_GENERAL_DTSCON_REFTRIM_Msk (0xe0000UL) /*!< SCU_GENERAL DTSCON: REFTRIM (Bitfield-Mask: 0x07) */ +#define SCU_GENERAL_DTSCON_BGTRIM_Pos (20UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bit 20) */ +#define SCU_GENERAL_DTSCON_BGTRIM_Msk (0xf00000UL) /*!< SCU_GENERAL DTSCON: BGTRIM (Bitfield-Mask: 0x0f) */ + +/* ----------------------------- SCU_GENERAL_DTSSTAT ---------------------------- */ +#define SCU_GENERAL_DTSSTAT_RESULT_Pos (0UL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bit 0) */ +#define SCU_GENERAL_DTSSTAT_RESULT_Msk (0x3ffUL) /*!< SCU_GENERAL DTSSTAT: RESULT (Bitfield-Mask: 0x3ff) */ +#define SCU_GENERAL_DTSSTAT_RDY_Pos (14UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bit 14) */ +#define SCU_GENERAL_DTSSTAT_RDY_Msk (0x4000UL) /*!< SCU_GENERAL DTSSTAT: RDY (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_DTSSTAT_BUSY_Pos (15UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bit 15) */ +#define SCU_GENERAL_DTSSTAT_BUSY_Msk (0x8000UL) /*!< SCU_GENERAL DTSSTAT: BUSY (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_GENERAL_GORCEN ----------------------------- */ +#define SCU_GENERAL_GORCEN_ENORC6_Pos (6UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bit 6) */ +#define SCU_GENERAL_GORCEN_ENORC6_Msk (0x40UL) /*!< SCU_GENERAL GORCEN: ENORC6 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_GORCEN_ENORC7_Pos (7UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bit 7) */ +#define SCU_GENERAL_GORCEN_ENORC7_Msk (0x80UL) /*!< SCU_GENERAL GORCEN: ENORC7 (Bitfield-Mask: 0x01) */ + +/* ---------------------------- SCU_GENERAL_DTEMPLIM ---------------------------- */ +#define SCU_GENERAL_DTEMPLIM_LOWER_Pos (0UL) /*!< SCU_GENERAL DTEMPLIM: LOWER (Bit 0) */ +#define SCU_GENERAL_DTEMPLIM_LOWER_Msk (0x3ffUL) /*!< SCU_GENERAL DTEMPLIM: LOWER (Bitfield-Mask: 0x3ff) */ +#define SCU_GENERAL_DTEMPLIM_UPPER_Pos (16UL) /*!< SCU_GENERAL DTEMPLIM: UPPER (Bit 16) */ +#define SCU_GENERAL_DTEMPLIM_UPPER_Msk (0x3ff0000UL) /*!< SCU_GENERAL DTEMPLIM: UPPER (Bitfield-Mask: 0x3ff) */ + +/* --------------------------- SCU_GENERAL_DTEMPALARM --------------------------- */ +#define SCU_GENERAL_DTEMPALARM_UNDERFL_Pos (0UL) /*!< SCU_GENERAL DTEMPALARM: UNDERFL (Bit 0) */ +#define SCU_GENERAL_DTEMPALARM_UNDERFL_Msk (0x1UL) /*!< SCU_GENERAL DTEMPALARM: UNDERFL (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_DTEMPALARM_OVERFL_Pos (16UL) /*!< SCU_GENERAL DTEMPALARM: OVERFL (Bit 16) */ +#define SCU_GENERAL_DTEMPALARM_OVERFL_Msk (0x10000UL) /*!< SCU_GENERAL DTEMPALARM: OVERFL (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */ +#define SCU_GENERAL_MIRRSTS_HDCLR_Pos (1UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bit 1) */ +#define SCU_GENERAL_MIRRSTS_HDCLR_Msk (0x2UL) /*!< SCU_GENERAL MIRRSTS: HDCLR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_HDSET_Pos (2UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bit 2) */ +#define SCU_GENERAL_MIRRSTS_HDSET_Msk (0x4UL) /*!< SCU_GENERAL MIRRSTS: HDSET (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_HDCR_Pos (3UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bit 3) */ +#define SCU_GENERAL_MIRRSTS_HDCR_Msk (0x8UL) /*!< SCU_GENERAL MIRRSTS: HDCR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos (5UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bit 5) */ +#define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk (0x20UL) /*!< SCU_GENERAL MIRRSTS: OSCSICTRL (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos (7UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bit 7) */ +#define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk (0x80UL) /*!< SCU_GENERAL MIRRSTS: OSCULCTRL (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos (8UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bit 8) */ +#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x100UL) /*!< SCU_GENERAL MIRRSTS: RTC_CTR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos (9UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bit 9) */ +#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x200UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos (10UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bit 10) */ +#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x400UL) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos (11UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bit 11) */ +#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x800UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos (12UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bit 12) */ +#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x1000UL) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RMX_Pos (13UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bit 13) */ +#define SCU_GENERAL_MIRRSTS_RMX_Msk (0x2000UL) /*!< SCU_GENERAL MIRRSTS: RMX (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos (14UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bit 14) */ +#define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk (0x4000UL) /*!< SCU_GENERAL MIRRSTS: RTC_MSKSR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos (15UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bit 15) */ +#define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk (0x8000UL) /*!< SCU_GENERAL MIRRSTS: RTC_CLRSR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_LPACCONF_Pos (16UL) /*!< SCU_GENERAL MIRRSTS: LPACCONF (Bit 16) */ +#define SCU_GENERAL_MIRRSTS_LPACCONF_Msk (0x10000UL) /*!< SCU_GENERAL MIRRSTS: LPACCONF (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_LPACTH0_Pos (17UL) /*!< SCU_GENERAL MIRRSTS: LPACTH0 (Bit 17) */ +#define SCU_GENERAL_MIRRSTS_LPACTH0_Msk (0x20000UL) /*!< SCU_GENERAL MIRRSTS: LPACTH0 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_LPACTH1_Pos (18UL) /*!< SCU_GENERAL MIRRSTS: LPACTH1 (Bit 18) */ +#define SCU_GENERAL_MIRRSTS_LPACTH1_Msk (0x40000UL) /*!< SCU_GENERAL MIRRSTS: LPACTH1 (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_LPACCLR_Pos (20UL) /*!< SCU_GENERAL MIRRSTS: LPACCLR (Bit 20) */ +#define SCU_GENERAL_MIRRSTS_LPACCLR_Msk (0x100000UL) /*!< SCU_GENERAL MIRRSTS: LPACCLR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_LPACSET_Pos (21UL) /*!< SCU_GENERAL MIRRSTS: LPACSET (Bit 21) */ +#define SCU_GENERAL_MIRRSTS_LPACSET_Msk (0x200000UL) /*!< SCU_GENERAL MIRRSTS: LPACSET (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_HINTCLR_Pos (23UL) /*!< SCU_GENERAL MIRRSTS: HINTCLR (Bit 23) */ +#define SCU_GENERAL_MIRRSTS_HINTCLR_Msk (0x800000UL) /*!< SCU_GENERAL MIRRSTS: HINTCLR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_MIRRSTS_HINTSET_Pos (24UL) /*!< SCU_GENERAL MIRRSTS: HINTSET (Bit 24) */ +#define SCU_GENERAL_MIRRSTS_HINTSET_Msk (0x1000000UL) /*!< SCU_GENERAL MIRRSTS: HINTSET (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_GENERAL_RMACR ----------------------------- */ +#define SCU_GENERAL_RMACR_RDWR_Pos (0UL) /*!< SCU_GENERAL RMACR: RDWR (Bit 0) */ +#define SCU_GENERAL_RMACR_RDWR_Msk (0x1UL) /*!< SCU_GENERAL RMACR: RDWR (Bitfield-Mask: 0x01) */ +#define SCU_GENERAL_RMACR_ADDR_Pos (16UL) /*!< SCU_GENERAL RMACR: ADDR (Bit 16) */ +#define SCU_GENERAL_RMACR_ADDR_Msk (0xf0000UL) /*!< SCU_GENERAL RMACR: ADDR (Bitfield-Mask: 0x0f) */ + +/* ----------------------------- SCU_GENERAL_RMDATA ----------------------------- */ +#define SCU_GENERAL_RMDATA_DATA_Pos (0UL) /*!< SCU_GENERAL RMDATA: DATA (Bit 0) */ +#define SCU_GENERAL_RMDATA_DATA_Msk (0xffffffffUL) /*!< SCU_GENERAL RMDATA: DATA (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------- SCU_GENERAL_MIRRALLSTAT -------------------------- */ +#define SCU_GENERAL_MIRRALLSTAT_BUSY_Pos (0UL) /*!< SCU_GENERAL MIRRALLSTAT: BUSY (Bit 0) */ +#define SCU_GENERAL_MIRRALLSTAT_BUSY_Msk (0x1UL) /*!< SCU_GENERAL MIRRALLSTAT: BUSY (Bitfield-Mask: 0x01) */ + +/* --------------------------- SCU_GENERAL_MIRRALLREQ --------------------------- */ +#define SCU_GENERAL_MIRRALLREQ_REQ_Pos (0UL) /*!< SCU_GENERAL MIRRALLREQ: REQ (Bit 0) */ +#define SCU_GENERAL_MIRRALLREQ_REQ_Msk (0x1UL) /*!< SCU_GENERAL MIRRALLREQ: REQ (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- SCU_INTERRUPT_SRSTAT ---------------------------- */ +#define SCU_INTERRUPT_SRSTAT_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bit 0) */ +#define SCU_INTERRUPT_SRSTAT_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRSTAT: PRWARN (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_PI_Pos (1UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bit 1) */ +#define SCU_INTERRUPT_SRSTAT_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRSTAT: PI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_AI_Pos (2UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bit 2) */ +#define SCU_INTERRUPT_SRSTAT_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRSTAT: AI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bit 3) */ +#define SCU_INTERRUPT_SRSTAT_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRSTAT: DLROVR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_LPACCR_Pos (6UL) /*!< SCU_INTERRUPT SRSTAT: LPACCR (Bit 6) */ +#define SCU_INTERRUPT_SRSTAT_LPACCR_Msk (0x40UL) /*!< SCU_INTERRUPT SRSTAT: LPACCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_LPACTH0_Pos (7UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH0 (Bit 7) */ +#define SCU_INTERRUPT_SRSTAT_LPACTH0_Msk (0x80UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_LPACTH1_Pos (8UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH1 (Bit 8) */ +#define SCU_INTERRUPT_SRSTAT_LPACTH1_Msk (0x100UL) /*!< SCU_INTERRUPT SRSTAT: LPACTH1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_LPACST_Pos (9UL) /*!< SCU_INTERRUPT SRSTAT: LPACST (Bit 9) */ +#define SCU_INTERRUPT_SRSTAT_LPACST_Msk (0x200UL) /*!< SCU_INTERRUPT SRSTAT: LPACST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_LPACCLR_Pos (10UL) /*!< SCU_INTERRUPT SRSTAT: LPACCLR (Bit 10) */ +#define SCU_INTERRUPT_SRSTAT_LPACCLR_Msk (0x400UL) /*!< SCU_INTERRUPT SRSTAT: LPACCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_LPACSET_Pos (11UL) /*!< SCU_INTERRUPT SRSTAT: LPACSET (Bit 11) */ +#define SCU_INTERRUPT_SRSTAT_LPACSET_Msk (0x800UL) /*!< SCU_INTERRUPT SRSTAT: LPACSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_HINTST_Pos (12UL) /*!< SCU_INTERRUPT SRSTAT: HINTST (Bit 12) */ +#define SCU_INTERRUPT_SRSTAT_HINTST_Msk (0x1000UL) /*!< SCU_INTERRUPT SRSTAT: HINTST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_HINTCLR_Pos (13UL) /*!< SCU_INTERRUPT SRSTAT: HINTCLR (Bit 13) */ +#define SCU_INTERRUPT_SRSTAT_HINTCLR_Msk (0x2000UL) /*!< SCU_INTERRUPT SRSTAT: HINTCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_HINTSET_Pos (14UL) /*!< SCU_INTERRUPT SRSTAT: HINTSET (Bit 14) */ +#define SCU_INTERRUPT_SRSTAT_HINTSET_Msk (0x4000UL) /*!< SCU_INTERRUPT SRSTAT: HINTSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bit 17) */ +#define SCU_INTERRUPT_SRSTAT_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRSTAT: HDCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bit 18) */ +#define SCU_INTERRUPT_SRSTAT_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRSTAT: HDSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bit 19) */ +#define SCU_INTERRUPT_SRSTAT_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRSTAT: HDCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bit 21) */ +#define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRSTAT: OSCSICTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bit 23) */ +#define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRSTAT: OSCULCTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bit 24) */ +#define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_CTR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bit 25) */ +#define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bit 26) */ +#define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_ATIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bit 27) */ +#define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bit 28) */ +#define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRSTAT: RTC_TIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSTAT_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bit 29) */ +#define SCU_INTERRUPT_SRSTAT_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRSTAT: RMX (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */ +#define SCU_INTERRUPT_SRRAW_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bit 0) */ +#define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRRAW: PRWARN (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_PI_Pos (1UL) /*!< SCU_INTERRUPT SRRAW: PI (Bit 1) */ +#define SCU_INTERRUPT_SRRAW_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRRAW: PI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_AI_Pos (2UL) /*!< SCU_INTERRUPT SRRAW: AI (Bit 2) */ +#define SCU_INTERRUPT_SRRAW_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRRAW: AI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bit 3) */ +#define SCU_INTERRUPT_SRRAW_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRRAW: DLROVR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_LPACCR_Pos (6UL) /*!< SCU_INTERRUPT SRRAW: LPACCR (Bit 6) */ +#define SCU_INTERRUPT_SRRAW_LPACCR_Msk (0x40UL) /*!< SCU_INTERRUPT SRRAW: LPACCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_LPACTH0_Pos (7UL) /*!< SCU_INTERRUPT SRRAW: LPACTH0 (Bit 7) */ +#define SCU_INTERRUPT_SRRAW_LPACTH0_Msk (0x80UL) /*!< SCU_INTERRUPT SRRAW: LPACTH0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_LPACTH1_Pos (8UL) /*!< SCU_INTERRUPT SRRAW: LPACTH1 (Bit 8) */ +#define SCU_INTERRUPT_SRRAW_LPACTH1_Msk (0x100UL) /*!< SCU_INTERRUPT SRRAW: LPACTH1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_LPACST_Pos (9UL) /*!< SCU_INTERRUPT SRRAW: LPACST (Bit 9) */ +#define SCU_INTERRUPT_SRRAW_LPACST_Msk (0x200UL) /*!< SCU_INTERRUPT SRRAW: LPACST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_LPACCLR_Pos (10UL) /*!< SCU_INTERRUPT SRRAW: LPACCLR (Bit 10) */ +#define SCU_INTERRUPT_SRRAW_LPACCLR_Msk (0x400UL) /*!< SCU_INTERRUPT SRRAW: LPACCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_LPACSET_Pos (11UL) /*!< SCU_INTERRUPT SRRAW: LPACSET (Bit 11) */ +#define SCU_INTERRUPT_SRRAW_LPACSET_Msk (0x800UL) /*!< SCU_INTERRUPT SRRAW: LPACSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_HINTST_Pos (12UL) /*!< SCU_INTERRUPT SRRAW: HINTST (Bit 12) */ +#define SCU_INTERRUPT_SRRAW_HINTST_Msk (0x1000UL) /*!< SCU_INTERRUPT SRRAW: HINTST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_HINTCLR_Pos (13UL) /*!< SCU_INTERRUPT SRRAW: HINTCLR (Bit 13) */ +#define SCU_INTERRUPT_SRRAW_HINTCLR_Msk (0x2000UL) /*!< SCU_INTERRUPT SRRAW: HINTCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_HINTSET_Pos (14UL) /*!< SCU_INTERRUPT SRRAW: HINTSET (Bit 14) */ +#define SCU_INTERRUPT_SRRAW_HINTSET_Msk (0x4000UL) /*!< SCU_INTERRUPT SRRAW: HINTSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bit 17) */ +#define SCU_INTERRUPT_SRRAW_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRRAW: HDCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bit 18) */ +#define SCU_INTERRUPT_SRRAW_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRRAW: HDSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bit 19) */ +#define SCU_INTERRUPT_SRRAW_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRRAW: HDCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bit 21) */ +#define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRRAW: OSCSICTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bit 23) */ +#define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRRAW: OSCULCTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bit 24) */ +#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_CTR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bit 25) */ +#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bit 26) */ +#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bit 27) */ +#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bit 28) */ +#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRRAW_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bit 29) */ +#define SCU_INTERRUPT_SRRAW_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRRAW: RMX (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */ +#define SCU_INTERRUPT_SRMSK_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bit 0) */ +#define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRMSK: PRWARN (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_PI_Pos (1UL) /*!< SCU_INTERRUPT SRMSK: PI (Bit 1) */ +#define SCU_INTERRUPT_SRMSK_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRMSK: PI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_AI_Pos (2UL) /*!< SCU_INTERRUPT SRMSK: AI (Bit 2) */ +#define SCU_INTERRUPT_SRMSK_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRMSK: AI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bit 3) */ +#define SCU_INTERRUPT_SRMSK_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRMSK: DLROVR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_LPACCR_Pos (6UL) /*!< SCU_INTERRUPT SRMSK: LPACCR (Bit 6) */ +#define SCU_INTERRUPT_SRMSK_LPACCR_Msk (0x40UL) /*!< SCU_INTERRUPT SRMSK: LPACCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_LPACTH0_Pos (7UL) /*!< SCU_INTERRUPT SRMSK: LPACTH0 (Bit 7) */ +#define SCU_INTERRUPT_SRMSK_LPACTH0_Msk (0x80UL) /*!< SCU_INTERRUPT SRMSK: LPACTH0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_LPACTH1_Pos (8UL) /*!< SCU_INTERRUPT SRMSK: LPACTH1 (Bit 8) */ +#define SCU_INTERRUPT_SRMSK_LPACTH1_Msk (0x100UL) /*!< SCU_INTERRUPT SRMSK: LPACTH1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_LPACST_Pos (9UL) /*!< SCU_INTERRUPT SRMSK: LPACST (Bit 9) */ +#define SCU_INTERRUPT_SRMSK_LPACST_Msk (0x200UL) /*!< SCU_INTERRUPT SRMSK: LPACST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_LPACCLR_Pos (10UL) /*!< SCU_INTERRUPT SRMSK: LPACCLR (Bit 10) */ +#define SCU_INTERRUPT_SRMSK_LPACCLR_Msk (0x400UL) /*!< SCU_INTERRUPT SRMSK: LPACCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_LPACSET_Pos (11UL) /*!< SCU_INTERRUPT SRMSK: LPACSET (Bit 11) */ +#define SCU_INTERRUPT_SRMSK_LPACSET_Msk (0x800UL) /*!< SCU_INTERRUPT SRMSK: LPACSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_HINTST_Pos (12UL) /*!< SCU_INTERRUPT SRMSK: HINTST (Bit 12) */ +#define SCU_INTERRUPT_SRMSK_HINTST_Msk (0x1000UL) /*!< SCU_INTERRUPT SRMSK: HINTST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_HINTCLR_Pos (13UL) /*!< SCU_INTERRUPT SRMSK: HINTCLR (Bit 13) */ +#define SCU_INTERRUPT_SRMSK_HINTCLR_Msk (0x2000UL) /*!< SCU_INTERRUPT SRMSK: HINTCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_HINTSET_Pos (14UL) /*!< SCU_INTERRUPT SRMSK: HINTSET (Bit 14) */ +#define SCU_INTERRUPT_SRMSK_HINTSET_Msk (0x4000UL) /*!< SCU_INTERRUPT SRMSK: HINTSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bit 17) */ +#define SCU_INTERRUPT_SRMSK_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRMSK: HDCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bit 18) */ +#define SCU_INTERRUPT_SRMSK_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRMSK: HDSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bit 19) */ +#define SCU_INTERRUPT_SRMSK_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRMSK: HDCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bit 21) */ +#define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRMSK: OSCSICTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bit 23) */ +#define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRMSK: OSCULCTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bit 24) */ +#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_CTR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bit 25) */ +#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bit 26) */ +#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bit 27) */ +#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bit 28) */ +#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRMSK_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bit 29) */ +#define SCU_INTERRUPT_SRMSK_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRMSK: RMX (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */ +#define SCU_INTERRUPT_SRCLR_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bit 0) */ +#define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRCLR: PRWARN (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_PI_Pos (1UL) /*!< SCU_INTERRUPT SRCLR: PI (Bit 1) */ +#define SCU_INTERRUPT_SRCLR_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRCLR: PI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_AI_Pos (2UL) /*!< SCU_INTERRUPT SRCLR: AI (Bit 2) */ +#define SCU_INTERRUPT_SRCLR_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRCLR: AI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bit 3) */ +#define SCU_INTERRUPT_SRCLR_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRCLR: DLROVR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_LPACCR_Pos (6UL) /*!< SCU_INTERRUPT SRCLR: LPACCR (Bit 6) */ +#define SCU_INTERRUPT_SRCLR_LPACCR_Msk (0x40UL) /*!< SCU_INTERRUPT SRCLR: LPACCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_LPACTH0_Pos (7UL) /*!< SCU_INTERRUPT SRCLR: LPACTH0 (Bit 7) */ +#define SCU_INTERRUPT_SRCLR_LPACTH0_Msk (0x80UL) /*!< SCU_INTERRUPT SRCLR: LPACTH0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_LPACTH1_Pos (8UL) /*!< SCU_INTERRUPT SRCLR: LPACTH1 (Bit 8) */ +#define SCU_INTERRUPT_SRCLR_LPACTH1_Msk (0x100UL) /*!< SCU_INTERRUPT SRCLR: LPACTH1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_LPACST_Pos (9UL) /*!< SCU_INTERRUPT SRCLR: LPACST (Bit 9) */ +#define SCU_INTERRUPT_SRCLR_LPACST_Msk (0x200UL) /*!< SCU_INTERRUPT SRCLR: LPACST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_LPACCLR_Pos (10UL) /*!< SCU_INTERRUPT SRCLR: LPACCLR (Bit 10) */ +#define SCU_INTERRUPT_SRCLR_LPACCLR_Msk (0x400UL) /*!< SCU_INTERRUPT SRCLR: LPACCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_LPACSET_Pos (11UL) /*!< SCU_INTERRUPT SRCLR: LPACSET (Bit 11) */ +#define SCU_INTERRUPT_SRCLR_LPACSET_Msk (0x800UL) /*!< SCU_INTERRUPT SRCLR: LPACSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_HINTST_Pos (12UL) /*!< SCU_INTERRUPT SRCLR: HINTST (Bit 12) */ +#define SCU_INTERRUPT_SRCLR_HINTST_Msk (0x1000UL) /*!< SCU_INTERRUPT SRCLR: HINTST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_HINTCLR_Pos (13UL) /*!< SCU_INTERRUPT SRCLR: HINTCLR (Bit 13) */ +#define SCU_INTERRUPT_SRCLR_HINTCLR_Msk (0x2000UL) /*!< SCU_INTERRUPT SRCLR: HINTCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_HINTSET_Pos (14UL) /*!< SCU_INTERRUPT SRCLR: HINTSET (Bit 14) */ +#define SCU_INTERRUPT_SRCLR_HINTSET_Msk (0x4000UL) /*!< SCU_INTERRUPT SRCLR: HINTSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_HDCLR_Pos (17UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bit 17) */ +#define SCU_INTERRUPT_SRCLR_HDCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRCLR: HDCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_HDSET_Pos (18UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bit 18) */ +#define SCU_INTERRUPT_SRCLR_HDSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRCLR: HDSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bit 19) */ +#define SCU_INTERRUPT_SRCLR_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRCLR: HDCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bit 21) */ +#define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRCLR: OSCSICTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bit 23) */ +#define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRCLR: OSCULCTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bit 24) */ +#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_CTR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bit 25) */ +#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bit 26) */ +#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bit 27) */ +#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bit 28) */ +#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRCLR_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bit 29) */ +#define SCU_INTERRUPT_SRCLR_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRCLR: RMX (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */ +#define SCU_INTERRUPT_SRSET_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bit 0) */ +#define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT SRSET: PRWARN (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_PI_Pos (1UL) /*!< SCU_INTERRUPT SRSET: PI (Bit 1) */ +#define SCU_INTERRUPT_SRSET_PI_Msk (0x2UL) /*!< SCU_INTERRUPT SRSET: PI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_AI_Pos (2UL) /*!< SCU_INTERRUPT SRSET: AI (Bit 2) */ +#define SCU_INTERRUPT_SRSET_AI_Msk (0x4UL) /*!< SCU_INTERRUPT SRSET: AI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_DLROVR_Pos (3UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bit 3) */ +#define SCU_INTERRUPT_SRSET_DLROVR_Msk (0x8UL) /*!< SCU_INTERRUPT SRSET: DLROVR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_LPACCR_Pos (6UL) /*!< SCU_INTERRUPT SRSET: LPACCR (Bit 6) */ +#define SCU_INTERRUPT_SRSET_LPACCR_Msk (0x40UL) /*!< SCU_INTERRUPT SRSET: LPACCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_LPACTH0_Pos (7UL) /*!< SCU_INTERRUPT SRSET: LPACTH0 (Bit 7) */ +#define SCU_INTERRUPT_SRSET_LPACTH0_Msk (0x80UL) /*!< SCU_INTERRUPT SRSET: LPACTH0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_LPACTH1_Pos (8UL) /*!< SCU_INTERRUPT SRSET: LPACTH1 (Bit 8) */ +#define SCU_INTERRUPT_SRSET_LPACTH1_Msk (0x100UL) /*!< SCU_INTERRUPT SRSET: LPACTH1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_LPACST_Pos (9UL) /*!< SCU_INTERRUPT SRSET: LPACST (Bit 9) */ +#define SCU_INTERRUPT_SRSET_LPACST_Msk (0x200UL) /*!< SCU_INTERRUPT SRSET: LPACST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_LPACCLR_Pos (10UL) /*!< SCU_INTERRUPT SRSET: LPACCLR (Bit 10) */ +#define SCU_INTERRUPT_SRSET_LPACCLR_Msk (0x400UL) /*!< SCU_INTERRUPT SRSET: LPACCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_LPACSET_Pos (11UL) /*!< SCU_INTERRUPT SRSET: LPACSET (Bit 11) */ +#define SCU_INTERRUPT_SRSET_LPACSET_Msk (0x800UL) /*!< SCU_INTERRUPT SRSET: LPACSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_HINTST_Pos (12UL) /*!< SCU_INTERRUPT SRSET: HINTST (Bit 12) */ +#define SCU_INTERRUPT_SRSET_HINTST_Msk (0x1000UL) /*!< SCU_INTERRUPT SRSET: HINTST (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_HINTCLR_Pos (13UL) /*!< SCU_INTERRUPT SRSET: HINTCLR (Bit 13) */ +#define SCU_INTERRUPT_SRSET_HINTCLR_Msk (0x2000UL) /*!< SCU_INTERRUPT SRSET: HINTCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_HINTSET_Pos (14UL) /*!< SCU_INTERRUPT SRSET: HINTSET (Bit 14) */ +#define SCU_INTERRUPT_SRSET_HINTSET_Msk (0x4000UL) /*!< SCU_INTERRUPT SRSET: HINTSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_HDCRCLR_Pos (17UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bit 17) */ +#define SCU_INTERRUPT_SRSET_HDCRCLR_Msk (0x20000UL) /*!< SCU_INTERRUPT SRSET: HDCRCLR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_HDCRSET_Pos (18UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bit 18) */ +#define SCU_INTERRUPT_SRSET_HDCRSET_Msk (0x40000UL) /*!< SCU_INTERRUPT SRSET: HDCRSET (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_HDCR_Pos (19UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bit 19) */ +#define SCU_INTERRUPT_SRSET_HDCR_Msk (0x80000UL) /*!< SCU_INTERRUPT SRSET: HDCR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos (21UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bit 21) */ +#define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk (0x200000UL) /*!< SCU_INTERRUPT SRSET: OSCSICTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos (23UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bit 23) */ +#define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk (0x800000UL) /*!< SCU_INTERRUPT SRSET: OSCULCTRL (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos (24UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bit 24) */ +#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x1000000UL) /*!< SCU_INTERRUPT SRSET: RTC_CTR (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos (25UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bit 25) */ +#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x2000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos (26UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bit 26) */ +#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x4000000UL) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos (27UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bit 27) */ +#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x8000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos (28UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bit 28) */ +#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x10000000UL) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_SRSET_RMX_Pos (29UL) /*!< SCU_INTERRUPT SRSET: RMX (Bit 29) */ +#define SCU_INTERRUPT_SRSET_RMX_Msk (0x20000000UL) /*!< SCU_INTERRUPT SRSET: RMX (Bitfield-Mask: 0x01) */ + +/* --------------------------- SCU_INTERRUPT_NMIREQEN --------------------------- */ +#define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos (0UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bit 0) */ +#define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk (0x1UL) /*!< SCU_INTERRUPT NMIREQEN: PRWARN (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_NMIREQEN_PI_Pos (1UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bit 1) */ +#define SCU_INTERRUPT_NMIREQEN_PI_Msk (0x2UL) /*!< SCU_INTERRUPT NMIREQEN: PI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_NMIREQEN_AI_Pos (2UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bit 2) */ +#define SCU_INTERRUPT_NMIREQEN_AI_Msk (0x4UL) /*!< SCU_INTERRUPT NMIREQEN: AI (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_NMIREQEN_ERU00_Pos (16UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bit 16) */ +#define SCU_INTERRUPT_NMIREQEN_ERU00_Msk (0x10000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU00 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_NMIREQEN_ERU01_Pos (17UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bit 17) */ +#define SCU_INTERRUPT_NMIREQEN_ERU01_Msk (0x20000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU01 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_NMIREQEN_ERU02_Pos (18UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bit 18) */ +#define SCU_INTERRUPT_NMIREQEN_ERU02_Msk (0x40000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU02 (Bitfield-Mask: 0x01) */ +#define SCU_INTERRUPT_NMIREQEN_ERU03_Pos (19UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bit 19) */ +#define SCU_INTERRUPT_NMIREQEN_ERU03_Msk (0x80000UL) /*!< SCU_INTERRUPT NMIREQEN: ERU03 (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_PARITY' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- SCU_PARITY_PEEN ------------------------------ */ +#define SCU_PARITY_PEEN_PEENPS_Pos (0UL) /*!< SCU_PARITY PEEN: PEENPS (Bit 0) */ +#define SCU_PARITY_PEEN_PEENPS_Msk (0x1UL) /*!< SCU_PARITY PEEN: PEENPS (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEEN_PEENDS1_Pos (1UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bit 1) */ +#define SCU_PARITY_PEEN_PEENDS1_Msk (0x2UL) /*!< SCU_PARITY PEEN: PEENDS1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEEN_PEENU0_Pos (8UL) /*!< SCU_PARITY PEEN: PEENU0 (Bit 8) */ +#define SCU_PARITY_PEEN_PEENU0_Msk (0x100UL) /*!< SCU_PARITY PEEN: PEENU0 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEEN_PEENU1_Pos (9UL) /*!< SCU_PARITY PEEN: PEENU1 (Bit 9) */ +#define SCU_PARITY_PEEN_PEENU1_Msk (0x200UL) /*!< SCU_PARITY PEEN: PEENU1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEEN_PEENMC_Pos (12UL) /*!< SCU_PARITY PEEN: PEENMC (Bit 12) */ +#define SCU_PARITY_PEEN_PEENMC_Msk (0x1000UL) /*!< SCU_PARITY PEEN: PEENMC (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEEN_PEENPPRF_Pos (13UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bit 13) */ +#define SCU_PARITY_PEEN_PEENPPRF_Msk (0x2000UL) /*!< SCU_PARITY PEEN: PEENPPRF (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEEN_PEENUSB_Pos (16UL) /*!< SCU_PARITY PEEN: PEENUSB (Bit 16) */ +#define SCU_PARITY_PEEN_PEENUSB_Msk (0x10000UL) /*!< SCU_PARITY PEEN: PEENUSB (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_PARITY_MCHKCON ----------------------------- */ +#define SCU_PARITY_MCHKCON_SELPS_Pos (0UL) /*!< SCU_PARITY MCHKCON: SELPS (Bit 0) */ +#define SCU_PARITY_MCHKCON_SELPS_Msk (0x1UL) /*!< SCU_PARITY MCHKCON: SELPS (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_MCHKCON_SELDS1_Pos (1UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bit 1) */ +#define SCU_PARITY_MCHKCON_SELDS1_Msk (0x2UL) /*!< SCU_PARITY MCHKCON: SELDS1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_MCHKCON_USIC0DRA_Pos (8UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bit 8) */ +#define SCU_PARITY_MCHKCON_USIC0DRA_Msk (0x100UL) /*!< SCU_PARITY MCHKCON: USIC0DRA (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_MCHKCON_USIC1DRA_Pos (9UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bit 9) */ +#define SCU_PARITY_MCHKCON_USIC1DRA_Msk (0x200UL) /*!< SCU_PARITY MCHKCON: USIC1DRA (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_MCHKCON_MCANDRA_Pos (12UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bit 12) */ +#define SCU_PARITY_MCHKCON_MCANDRA_Msk (0x1000UL) /*!< SCU_PARITY MCHKCON: MCANDRA (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_MCHKCON_PPRFDRA_Pos (13UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bit 13) */ +#define SCU_PARITY_MCHKCON_PPRFDRA_Msk (0x2000UL) /*!< SCU_PARITY MCHKCON: PPRFDRA (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_MCHKCON_SELUSB_Pos (16UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bit 16) */ +#define SCU_PARITY_MCHKCON_SELUSB_Msk (0x10000UL) /*!< SCU_PARITY MCHKCON: SELUSB (Bitfield-Mask: 0x01) */ + +/* ------------------------------- SCU_PARITY_PETE ------------------------------ */ +#define SCU_PARITY_PETE_PETEPS_Pos (0UL) /*!< SCU_PARITY PETE: PETEPS (Bit 0) */ +#define SCU_PARITY_PETE_PETEPS_Msk (0x1UL) /*!< SCU_PARITY PETE: PETEPS (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PETE_PETEDS1_Pos (1UL) /*!< SCU_PARITY PETE: PETEDS1 (Bit 1) */ +#define SCU_PARITY_PETE_PETEDS1_Msk (0x2UL) /*!< SCU_PARITY PETE: PETEDS1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PETE_PETEU0_Pos (8UL) /*!< SCU_PARITY PETE: PETEU0 (Bit 8) */ +#define SCU_PARITY_PETE_PETEU0_Msk (0x100UL) /*!< SCU_PARITY PETE: PETEU0 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PETE_PETEU1_Pos (9UL) /*!< SCU_PARITY PETE: PETEU1 (Bit 9) */ +#define SCU_PARITY_PETE_PETEU1_Msk (0x200UL) /*!< SCU_PARITY PETE: PETEU1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PETE_PETEMC_Pos (12UL) /*!< SCU_PARITY PETE: PETEMC (Bit 12) */ +#define SCU_PARITY_PETE_PETEMC_Msk (0x1000UL) /*!< SCU_PARITY PETE: PETEMC (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PETE_PETEPPRF_Pos (13UL) /*!< SCU_PARITY PETE: PETEPPRF (Bit 13) */ +#define SCU_PARITY_PETE_PETEPPRF_Msk (0x2000UL) /*!< SCU_PARITY PETE: PETEPPRF (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PETE_PETEUSB_Pos (16UL) /*!< SCU_PARITY PETE: PETEUSB (Bit 16) */ +#define SCU_PARITY_PETE_PETEUSB_Msk (0x10000UL) /*!< SCU_PARITY PETE: PETEUSB (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_PARITY_PERSTEN ----------------------------- */ +#define SCU_PARITY_PERSTEN_RSEN_Pos (0UL) /*!< SCU_PARITY PERSTEN: RSEN (Bit 0) */ +#define SCU_PARITY_PERSTEN_RSEN_Msk (0x1UL) /*!< SCU_PARITY PERSTEN: RSEN (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_PARITY_PEFLAG ----------------------------- */ +#define SCU_PARITY_PEFLAG_PEFPS_Pos (0UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bit 0) */ +#define SCU_PARITY_PEFLAG_PEFPS_Msk (0x1UL) /*!< SCU_PARITY PEFLAG: PEFPS (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEFLAG_PEFDS1_Pos (1UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bit 1) */ +#define SCU_PARITY_PEFLAG_PEFDS1_Msk (0x2UL) /*!< SCU_PARITY PEFLAG: PEFDS1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEFLAG_PEFU0_Pos (8UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bit 8) */ +#define SCU_PARITY_PEFLAG_PEFU0_Msk (0x100UL) /*!< SCU_PARITY PEFLAG: PEFU0 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEFLAG_PEFU1_Pos (9UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bit 9) */ +#define SCU_PARITY_PEFLAG_PEFU1_Msk (0x200UL) /*!< SCU_PARITY PEFLAG: PEFU1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEFLAG_PEFMC_Pos (12UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bit 12) */ +#define SCU_PARITY_PEFLAG_PEFMC_Msk (0x1000UL) /*!< SCU_PARITY PEFLAG: PEFMC (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEFLAG_PEFPPRF_Pos (13UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bit 13) */ +#define SCU_PARITY_PEFLAG_PEFPPRF_Msk (0x2000UL) /*!< SCU_PARITY PEFLAG: PEFPPRF (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PEFLAG_PEUSB_Pos (16UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bit 16) */ +#define SCU_PARITY_PEFLAG_PEUSB_Msk (0x10000UL) /*!< SCU_PARITY PEFLAG: PEUSB (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_PARITY_PMTPR ------------------------------ */ +#define SCU_PARITY_PMTPR_PWR_Pos (0UL) /*!< SCU_PARITY PMTPR: PWR (Bit 0) */ +#define SCU_PARITY_PMTPR_PWR_Msk (0xffUL) /*!< SCU_PARITY PMTPR: PWR (Bitfield-Mask: 0xff) */ +#define SCU_PARITY_PMTPR_PRD_Pos (8UL) /*!< SCU_PARITY PMTPR: PRD (Bit 8) */ +#define SCU_PARITY_PMTPR_PRD_Msk (0xff00UL) /*!< SCU_PARITY PMTPR: PRD (Bitfield-Mask: 0xff) */ + +/* ------------------------------ SCU_PARITY_PMTSR ------------------------------ */ +#define SCU_PARITY_PMTSR_MTENPS_Pos (0UL) /*!< SCU_PARITY PMTSR: MTENPS (Bit 0) */ +#define SCU_PARITY_PMTSR_MTENPS_Msk (0x1UL) /*!< SCU_PARITY PMTSR: MTENPS (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PMTSR_MTENDS1_Pos (1UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bit 1) */ +#define SCU_PARITY_PMTSR_MTENDS1_Msk (0x2UL) /*!< SCU_PARITY PMTSR: MTENDS1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PMTSR_MTEU0_Pos (8UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bit 8) */ +#define SCU_PARITY_PMTSR_MTEU0_Msk (0x100UL) /*!< SCU_PARITY PMTSR: MTEU0 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PMTSR_MTEU1_Pos (9UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bit 9) */ +#define SCU_PARITY_PMTSR_MTEU1_Msk (0x200UL) /*!< SCU_PARITY PMTSR: MTEU1 (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PMTSR_MTEMC_Pos (12UL) /*!< SCU_PARITY PMTSR: MTEMC (Bit 12) */ +#define SCU_PARITY_PMTSR_MTEMC_Msk (0x1000UL) /*!< SCU_PARITY PMTSR: MTEMC (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PMTSR_MTEPPRF_Pos (13UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bit 13) */ +#define SCU_PARITY_PMTSR_MTEPPRF_Msk (0x2000UL) /*!< SCU_PARITY PMTSR: MTEPPRF (Bitfield-Mask: 0x01) */ +#define SCU_PARITY_PMTSR_MTUSB_Pos (16UL) /*!< SCU_PARITY PMTSR: MTUSB (Bit 16) */ +#define SCU_PARITY_PMTSR_MTUSB_Msk (0x10000UL) /*!< SCU_PARITY PMTSR: MTUSB (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_TRAP' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ SCU_TRAP_TRAPSTAT ----------------------------- */ +#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bit 0) */ +#define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPSTAT: SOSCWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bit 2) */ +#define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPSTAT: SVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bit 3) */ +#define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPSTAT: UVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_PET_Pos (4UL) /*!< SCU_TRAP TRAPSTAT: PET (Bit 4) */ +#define SCU_TRAP_TRAPSTAT_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPSTAT: PET (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bit 5) */ +#define SCU_TRAP_TRAPSTAT_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPSTAT: BRWNT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bit 6) */ +#define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPSTAT: ULPWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bit 7) */ +#define SCU_TRAP_TRAPSTAT_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPSTAT: BWERR0T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bit 8) */ +#define SCU_TRAP_TRAPSTAT_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPSTAT: BWERR1T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_TEMPHIT_Pos (12UL) /*!< SCU_TRAP TRAPSTAT: TEMPHIT (Bit 12) */ +#define SCU_TRAP_TRAPSTAT_TEMPHIT_Msk (0x1000UL) /*!< SCU_TRAP TRAPSTAT: TEMPHIT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSTAT_TEMPLOT_Pos (13UL) /*!< SCU_TRAP TRAPSTAT: TEMPLOT (Bit 13) */ +#define SCU_TRAP_TRAPSTAT_TEMPLOT_Msk (0x2000UL) /*!< SCU_TRAP TRAPSTAT: TEMPLOT (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_TRAP_TRAPRAW ------------------------------ */ +#define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bit 0) */ +#define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPRAW: SOSCWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bit 2) */ +#define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPRAW: SVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bit 3) */ +#define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPRAW: UVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_PET_Pos (4UL) /*!< SCU_TRAP TRAPRAW: PET (Bit 4) */ +#define SCU_TRAP_TRAPRAW_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPRAW: PET (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bit 5) */ +#define SCU_TRAP_TRAPRAW_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPRAW: BRWNT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bit 6) */ +#define SCU_TRAP_TRAPRAW_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPRAW: ULPWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bit 7) */ +#define SCU_TRAP_TRAPRAW_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPRAW: BWERR0T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bit 8) */ +#define SCU_TRAP_TRAPRAW_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPRAW: BWERR1T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_TEMPHIT_Pos (12UL) /*!< SCU_TRAP TRAPRAW: TEMPHIT (Bit 12) */ +#define SCU_TRAP_TRAPRAW_TEMPHIT_Msk (0x1000UL) /*!< SCU_TRAP TRAPRAW: TEMPHIT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPRAW_TEMPLOT_Pos (13UL) /*!< SCU_TRAP TRAPRAW: TEMPLOT (Bit 13) */ +#define SCU_TRAP_TRAPRAW_TEMPLOT_Msk (0x2000UL) /*!< SCU_TRAP TRAPRAW: TEMPLOT (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_TRAP_TRAPDIS ------------------------------ */ +#define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bit 0) */ +#define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPDIS: SOSCWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bit 2) */ +#define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPDIS: SVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bit 3) */ +#define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPDIS: UVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_PET_Pos (4UL) /*!< SCU_TRAP TRAPDIS: PET (Bit 4) */ +#define SCU_TRAP_TRAPDIS_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPDIS: PET (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bit 5) */ +#define SCU_TRAP_TRAPDIS_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPDIS: BRWNT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bit 6) */ +#define SCU_TRAP_TRAPDIS_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPDIS: ULPWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bit 7) */ +#define SCU_TRAP_TRAPDIS_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPDIS: BWERR0T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bit 8) */ +#define SCU_TRAP_TRAPDIS_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPDIS: BWERR1T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_TEMPHIT_Pos (12UL) /*!< SCU_TRAP TRAPDIS: TEMPHIT (Bit 12) */ +#define SCU_TRAP_TRAPDIS_TEMPHIT_Msk (0x1000UL) /*!< SCU_TRAP TRAPDIS: TEMPHIT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPDIS_TEMPLOT_Pos (13UL) /*!< SCU_TRAP TRAPDIS: TEMPLOT (Bit 13) */ +#define SCU_TRAP_TRAPDIS_TEMPLOT_Msk (0x2000UL) /*!< SCU_TRAP TRAPDIS: TEMPLOT (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_TRAP_TRAPCLR ------------------------------ */ +#define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bit 0) */ +#define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPCLR: SOSCWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bit 2) */ +#define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPCLR: SVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bit 3) */ +#define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPCLR: UVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_PET_Pos (4UL) /*!< SCU_TRAP TRAPCLR: PET (Bit 4) */ +#define SCU_TRAP_TRAPCLR_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPCLR: PET (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bit 5) */ +#define SCU_TRAP_TRAPCLR_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPCLR: BRWNT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_ULPWDGT_Pos (6UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bit 6) */ +#define SCU_TRAP_TRAPCLR_ULPWDGT_Msk (0x40UL) /*!< SCU_TRAP TRAPCLR: ULPWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bit 7) */ +#define SCU_TRAP_TRAPCLR_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPCLR: BWERR0T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bit 8) */ +#define SCU_TRAP_TRAPCLR_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPCLR: BWERR1T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_TEMPHIT_Pos (12UL) /*!< SCU_TRAP TRAPCLR: TEMPHIT (Bit 12) */ +#define SCU_TRAP_TRAPCLR_TEMPHIT_Msk (0x1000UL) /*!< SCU_TRAP TRAPCLR: TEMPHIT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPCLR_TEMPLOT_Pos (13UL) /*!< SCU_TRAP TRAPCLR: TEMPLOT (Bit 13) */ +#define SCU_TRAP_TRAPCLR_TEMPLOT_Msk (0x2000UL) /*!< SCU_TRAP TRAPCLR: TEMPLOT (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_TRAP_TRAPSET ------------------------------ */ +#define SCU_TRAP_TRAPSET_SOSCWDGT_Pos (0UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bit 0) */ +#define SCU_TRAP_TRAPSET_SOSCWDGT_Msk (0x1UL) /*!< SCU_TRAP TRAPSET: SOSCWDGT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_SVCOLCKT_Pos (2UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bit 2) */ +#define SCU_TRAP_TRAPSET_SVCOLCKT_Msk (0x4UL) /*!< SCU_TRAP TRAPSET: SVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_UVCOLCKT_Pos (3UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bit 3) */ +#define SCU_TRAP_TRAPSET_UVCOLCKT_Msk (0x8UL) /*!< SCU_TRAP TRAPSET: UVCOLCKT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_PET_Pos (4UL) /*!< SCU_TRAP TRAPSET: PET (Bit 4) */ +#define SCU_TRAP_TRAPSET_PET_Msk (0x10UL) /*!< SCU_TRAP TRAPSET: PET (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_BRWNT_Pos (5UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bit 5) */ +#define SCU_TRAP_TRAPSET_BRWNT_Msk (0x20UL) /*!< SCU_TRAP TRAPSET: BRWNT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_ULPWDT_Pos (6UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bit 6) */ +#define SCU_TRAP_TRAPSET_ULPWDT_Msk (0x40UL) /*!< SCU_TRAP TRAPSET: ULPWDT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_BWERR0T_Pos (7UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bit 7) */ +#define SCU_TRAP_TRAPSET_BWERR0T_Msk (0x80UL) /*!< SCU_TRAP TRAPSET: BWERR0T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_BWERR1T_Pos (8UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bit 8) */ +#define SCU_TRAP_TRAPSET_BWERR1T_Msk (0x100UL) /*!< SCU_TRAP TRAPSET: BWERR1T (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_TEMPHIT_Pos (12UL) /*!< SCU_TRAP TRAPSET: TEMPHIT (Bit 12) */ +#define SCU_TRAP_TRAPSET_TEMPHIT_Msk (0x1000UL) /*!< SCU_TRAP TRAPSET: TEMPHIT (Bitfield-Mask: 0x01) */ +#define SCU_TRAP_TRAPSET_TEMPLOT_Pos (13UL) /*!< SCU_TRAP TRAPSET: TEMPLOT (Bit 13) */ +#define SCU_TRAP_TRAPSET_TEMPLOT_Msk (0x2000UL) /*!< SCU_TRAP TRAPSET: TEMPLOT (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_HIBERNATE' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------- SCU_HIBERNATE_HDSTAT ---------------------------- */ +#define SCU_HIBERNATE_HDSTAT_EPEV_Pos (0UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bit 0) */ +#define SCU_HIBERNATE_HDSTAT_EPEV_Msk (0x1UL) /*!< SCU_HIBERNATE HDSTAT: EPEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_ENEV_Pos (1UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bit 1) */ +#define SCU_HIBERNATE_HDSTAT_ENEV_Msk (0x2UL) /*!< SCU_HIBERNATE HDSTAT: ENEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_RTCEV_Pos (2UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bit 2) */ +#define SCU_HIBERNATE_HDSTAT_RTCEV_Msk (0x4UL) /*!< SCU_HIBERNATE HDSTAT: RTCEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos (3UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bit 3) */ +#define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk (0x8UL) /*!< SCU_HIBERNATE HDSTAT: ULPWDG (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos (4UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bit 4) */ +#define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk (0x10UL) /*!< SCU_HIBERNATE HDSTAT: HIBNOUT (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_VBATPEV_Pos (8UL) /*!< SCU_HIBERNATE HDSTAT: VBATPEV (Bit 8) */ +#define SCU_HIBERNATE_HDSTAT_VBATPEV_Msk (0x100UL) /*!< SCU_HIBERNATE HDSTAT: VBATPEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_VBATNEV_Pos (9UL) /*!< SCU_HIBERNATE HDSTAT: VBATNEV (Bit 9) */ +#define SCU_HIBERNATE_HDSTAT_VBATNEV_Msk (0x200UL) /*!< SCU_HIBERNATE HDSTAT: VBATNEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Pos (10UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV (Bit 10) */ +#define SCU_HIBERNATE_HDSTAT_AHIBIO0PEV_Msk (0x400UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0PEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Pos (11UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV (Bit 11) */ +#define SCU_HIBERNATE_HDSTAT_AHIBIO0NEV_Msk (0x800UL) /*!< SCU_HIBERNATE HDSTAT: AHIBIO0NEV (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_HIBERNATE_HDCLR ---------------------------- */ +#define SCU_HIBERNATE_HDCLR_EPEV_Pos (0UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bit 0) */ +#define SCU_HIBERNATE_HDCLR_EPEV_Msk (0x1UL) /*!< SCU_HIBERNATE HDCLR: EPEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCLR_ENEV_Pos (1UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bit 1) */ +#define SCU_HIBERNATE_HDCLR_ENEV_Msk (0x2UL) /*!< SCU_HIBERNATE HDCLR: ENEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCLR_RTCEV_Pos (2UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bit 2) */ +#define SCU_HIBERNATE_HDCLR_RTCEV_Msk (0x4UL) /*!< SCU_HIBERNATE HDCLR: RTCEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCLR_ULPWDG_Pos (3UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bit 3) */ +#define SCU_HIBERNATE_HDCLR_ULPWDG_Msk (0x8UL) /*!< SCU_HIBERNATE HDCLR: ULPWDG (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCLR_VBATPEV_Pos (8UL) /*!< SCU_HIBERNATE HDCLR: VBATPEV (Bit 8) */ +#define SCU_HIBERNATE_HDCLR_VBATPEV_Msk (0x100UL) /*!< SCU_HIBERNATE HDCLR: VBATPEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCLR_VBATNEV_Pos (9UL) /*!< SCU_HIBERNATE HDCLR: VBATNEV (Bit 9) */ +#define SCU_HIBERNATE_HDCLR_VBATNEV_Msk (0x200UL) /*!< SCU_HIBERNATE HDCLR: VBATNEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Pos (10UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV (Bit 10) */ +#define SCU_HIBERNATE_HDCLR_AHIBIO0PEV_Msk (0x400UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0PEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Pos (11UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV (Bit 11) */ +#define SCU_HIBERNATE_HDCLR_AHIBIO0NEV_Msk (0x800UL) /*!< SCU_HIBERNATE HDCLR: AHIBIO0NEV (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_HIBERNATE_HDSET ---------------------------- */ +#define SCU_HIBERNATE_HDSET_EPEV_Pos (0UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bit 0) */ +#define SCU_HIBERNATE_HDSET_EPEV_Msk (0x1UL) /*!< SCU_HIBERNATE HDSET: EPEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSET_ENEV_Pos (1UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bit 1) */ +#define SCU_HIBERNATE_HDSET_ENEV_Msk (0x2UL) /*!< SCU_HIBERNATE HDSET: ENEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSET_RTCEV_Pos (2UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bit 2) */ +#define SCU_HIBERNATE_HDSET_RTCEV_Msk (0x4UL) /*!< SCU_HIBERNATE HDSET: RTCEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSET_ULPWDG_Pos (3UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bit 3) */ +#define SCU_HIBERNATE_HDSET_ULPWDG_Msk (0x8UL) /*!< SCU_HIBERNATE HDSET: ULPWDG (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSET_VBATPEV_Pos (8UL) /*!< SCU_HIBERNATE HDSET: VBATPEV (Bit 8) */ +#define SCU_HIBERNATE_HDSET_VBATPEV_Msk (0x100UL) /*!< SCU_HIBERNATE HDSET: VBATPEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSET_VBATNEV_Pos (9UL) /*!< SCU_HIBERNATE HDSET: VBATNEV (Bit 9) */ +#define SCU_HIBERNATE_HDSET_VBATNEV_Msk (0x200UL) /*!< SCU_HIBERNATE HDSET: VBATNEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Pos (10UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV (Bit 10) */ +#define SCU_HIBERNATE_HDSET_AHIBIO0PEV_Msk (0x400UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0PEV (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Pos (11UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV (Bit 11) */ +#define SCU_HIBERNATE_HDSET_AHIBIO0NEV_Msk (0x800UL) /*!< SCU_HIBERNATE HDSET: AHIBIO0NEV (Bitfield-Mask: 0x01) */ + +/* ----------------------------- SCU_HIBERNATE_HDCR ----------------------------- */ +#define SCU_HIBERNATE_HDCR_WKPEP_Pos (0UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bit 0) */ +#define SCU_HIBERNATE_HDCR_WKPEP_Msk (0x1UL) /*!< SCU_HIBERNATE HDCR: WKPEP (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_WKPEN_Pos (1UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bit 1) */ +#define SCU_HIBERNATE_HDCR_WKPEN_Msk (0x2UL) /*!< SCU_HIBERNATE HDCR: WKPEN (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_RTCE_Pos (2UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bit 2) */ +#define SCU_HIBERNATE_HDCR_RTCE_Msk (0x4UL) /*!< SCU_HIBERNATE HDCR: RTCE (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos (3UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bit 3) */ +#define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk (0x8UL) /*!< SCU_HIBERNATE HDCR: ULPWDGEN (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_HIB_Pos (4UL) /*!< SCU_HIBERNATE HDCR: HIB (Bit 4) */ +#define SCU_HIBERNATE_HDCR_HIB_Msk (0x10UL) /*!< SCU_HIBERNATE HDCR: HIB (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Pos (5UL) /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL (Bit 5) */ +#define SCU_HIBERNATE_HDCR_XTALGPI1SEL_Msk (0x20UL) /*!< SCU_HIBERNATE HDCR: XTALGPI1SEL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_RCS_Pos (6UL) /*!< SCU_HIBERNATE HDCR: RCS (Bit 6) */ +#define SCU_HIBERNATE_HDCR_RCS_Msk (0x40UL) /*!< SCU_HIBERNATE HDCR: RCS (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_STDBYSEL_Pos (7UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bit 7) */ +#define SCU_HIBERNATE_HDCR_STDBYSEL_Msk (0x80UL) /*!< SCU_HIBERNATE HDCR: STDBYSEL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_WKUPSEL_Pos (8UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bit 8) */ +#define SCU_HIBERNATE_HDCR_WKUPSEL_Msk (0x100UL) /*!< SCU_HIBERNATE HDCR: WKUPSEL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_GPI0SEL_Pos (10UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bit 10) */ +#define SCU_HIBERNATE_HDCR_GPI0SEL_Msk (0x400UL) /*!< SCU_HIBERNATE HDCR: GPI0SEL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos (12UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bit 12) */ +#define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk (0x1000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0POL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_ADIG0SEL_Pos (14UL) /*!< SCU_HIBERNATE HDCR: ADIG0SEL (Bit 14) */ +#define SCU_HIBERNATE_HDCR_ADIG0SEL_Msk (0x4000UL) /*!< SCU_HIBERNATE HDCR: ADIG0SEL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos (16UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bit 16) */ +#define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk (0xf0000UL) /*!< SCU_HIBERNATE HDCR: HIBIO0SEL (Bitfield-Mask: 0x0f) */ +#define SCU_HIBERNATE_HDCR_VBATLO_Pos (24UL) /*!< SCU_HIBERNATE HDCR: VBATLO (Bit 24) */ +#define SCU_HIBERNATE_HDCR_VBATLO_Msk (0x1000000UL) /*!< SCU_HIBERNATE HDCR: VBATLO (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_VBATHI_Pos (25UL) /*!< SCU_HIBERNATE HDCR: VBATHI (Bit 25) */ +#define SCU_HIBERNATE_HDCR_VBATHI_Msk (0x2000000UL) /*!< SCU_HIBERNATE HDCR: VBATHI (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Pos (26UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0LO (Bit 26) */ +#define SCU_HIBERNATE_HDCR_AHIBIO0LO_Msk (0x4000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0LO (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Pos (27UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0HI (Bit 27) */ +#define SCU_HIBERNATE_HDCR_AHIBIO0HI_Msk (0x8000000UL) /*!< SCU_HIBERNATE HDCR: AHIBIO0HI (Bitfield-Mask: 0x01) */ + +/* --------------------------- SCU_HIBERNATE_OSCSICTRL -------------------------- */ +#define SCU_HIBERNATE_OSCSICTRL_PWD_Pos (0UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bit 0) */ +#define SCU_HIBERNATE_OSCSICTRL_PWD_Msk (0x1UL) /*!< SCU_HIBERNATE OSCSICTRL: PWD (Bitfield-Mask: 0x01) */ + +/* --------------------------- SCU_HIBERNATE_OSCULSTAT -------------------------- */ +#define SCU_HIBERNATE_OSCULSTAT_X1D_Pos (0UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bit 0) */ +#define SCU_HIBERNATE_OSCULSTAT_X1D_Msk (0x1UL) /*!< SCU_HIBERNATE OSCULSTAT: X1D (Bitfield-Mask: 0x01) */ + +/* --------------------------- SCU_HIBERNATE_OSCULCTRL -------------------------- */ +#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos (0UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bit 0) */ +#define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk (0x1UL) /*!< SCU_HIBERNATE OSCULCTRL: X1DEN (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_OSCULCTRL_MODE_Pos (4UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bit 4) */ +#define SCU_HIBERNATE_OSCULCTRL_MODE_Msk (0x30UL) /*!< SCU_HIBERNATE OSCULCTRL: MODE (Bitfield-Mask: 0x03) */ + +/* --------------------------- SCU_HIBERNATE_LPACCONF --------------------------- */ +#define SCU_HIBERNATE_LPACCONF_CMPEN_Pos (0UL) /*!< SCU_HIBERNATE LPACCONF: CMPEN (Bit 0) */ +#define SCU_HIBERNATE_LPACCONF_CMPEN_Msk (0x7UL) /*!< SCU_HIBERNATE LPACCONF: CMPEN (Bitfield-Mask: 0x07) */ +#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Pos (4UL) /*!< SCU_HIBERNATE LPACCONF: TRIGSEL (Bit 4) */ +#define SCU_HIBERNATE_LPACCONF_TRIGSEL_Msk (0x70UL) /*!< SCU_HIBERNATE LPACCONF: TRIGSEL (Bitfield-Mask: 0x07) */ +#define SCU_HIBERNATE_LPACCONF_CONVDEL_Pos (12UL) /*!< SCU_HIBERNATE LPACCONF: CONVDEL (Bit 12) */ +#define SCU_HIBERNATE_LPACCONF_CONVDEL_Msk (0x1000UL) /*!< SCU_HIBERNATE LPACCONF: CONVDEL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Pos (16UL) /*!< SCU_HIBERNATE LPACCONF: INTERVCNT (Bit 16) */ +#define SCU_HIBERNATE_LPACCONF_INTERVCNT_Msk (0xfff0000UL) /*!< SCU_HIBERNATE LPACCONF: INTERVCNT (Bitfield-Mask: 0xfff) */ +#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Pos (28UL) /*!< SCU_HIBERNATE LPACCONF: SETTLECNT (Bit 28) */ +#define SCU_HIBERNATE_LPACCONF_SETTLECNT_Msk (0xf0000000UL) /*!< SCU_HIBERNATE LPACCONF: SETTLECNT (Bitfield-Mask: 0x0f) */ + +/* ---------------------------- SCU_HIBERNATE_LPACTH0 --------------------------- */ +#define SCU_HIBERNATE_LPACTH0_VBATLO_Pos (0UL) /*!< SCU_HIBERNATE LPACTH0: VBATLO (Bit 0) */ +#define SCU_HIBERNATE_LPACTH0_VBATLO_Msk (0x3fUL) /*!< SCU_HIBERNATE LPACTH0: VBATLO (Bitfield-Mask: 0x3f) */ +#define SCU_HIBERNATE_LPACTH0_VBATHI_Pos (8UL) /*!< SCU_HIBERNATE LPACTH0: VBATHI (Bit 8) */ +#define SCU_HIBERNATE_LPACTH0_VBATHI_Msk (0x3f00UL) /*!< SCU_HIBERNATE LPACTH0: VBATHI (Bitfield-Mask: 0x3f) */ + +/* ---------------------------- SCU_HIBERNATE_LPACTH1 --------------------------- */ +#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Pos (0UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO (Bit 0) */ +#define SCU_HIBERNATE_LPACTH1_AHIBIO0LO_Msk (0x3fUL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0LO (Bitfield-Mask: 0x3f) */ +#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Pos (8UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI (Bit 8) */ +#define SCU_HIBERNATE_LPACTH1_AHIBIO0HI_Msk (0x3f00UL) /*!< SCU_HIBERNATE LPACTH1: AHIBIO0HI (Bitfield-Mask: 0x3f) */ + +/* ---------------------------- SCU_HIBERNATE_LPACST ---------------------------- */ +#define SCU_HIBERNATE_LPACST_VBATSCMP_Pos (0UL) /*!< SCU_HIBERNATE LPACST: VBATSCMP (Bit 0) */ +#define SCU_HIBERNATE_LPACST_VBATSCMP_Msk (0x1UL) /*!< SCU_HIBERNATE LPACST: VBATSCMP (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Pos (1UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP (Bit 1) */ +#define SCU_HIBERNATE_LPACST_AHIBIO0SCMP_Msk (0x2UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACST_VBATVAL_Pos (16UL) /*!< SCU_HIBERNATE LPACST: VBATVAL (Bit 16) */ +#define SCU_HIBERNATE_LPACST_VBATVAL_Msk (0x10000UL) /*!< SCU_HIBERNATE LPACST: VBATVAL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Pos (17UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL (Bit 17) */ +#define SCU_HIBERNATE_LPACST_AHIBIO0VAL_Msk (0x20000UL) /*!< SCU_HIBERNATE LPACST: AHIBIO0VAL (Bitfield-Mask: 0x01) */ + +/* ---------------------------- SCU_HIBERNATE_LPACCLR --------------------------- */ +#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Pos (0UL) /*!< SCU_HIBERNATE LPACCLR: VBATSCMP (Bit 0) */ +#define SCU_HIBERNATE_LPACCLR_VBATSCMP_Msk (0x1UL) /*!< SCU_HIBERNATE LPACCLR: VBATSCMP (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Pos (1UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP (Bit 1) */ +#define SCU_HIBERNATE_LPACCLR_AHIBIO0SCMP_Msk (0x2UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACCLR_VBATVAL_Pos (16UL) /*!< SCU_HIBERNATE LPACCLR: VBATVAL (Bit 16) */ +#define SCU_HIBERNATE_LPACCLR_VBATVAL_Msk (0x10000UL) /*!< SCU_HIBERNATE LPACCLR: VBATVAL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Pos (17UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL (Bit 17) */ +#define SCU_HIBERNATE_LPACCLR_AHIBIO0VAL_Msk (0x20000UL) /*!< SCU_HIBERNATE LPACCLR: AHIBIO0VAL (Bitfield-Mask: 0x01) */ + +/* ---------------------------- SCU_HIBERNATE_LPACSET --------------------------- */ +#define SCU_HIBERNATE_LPACSET_VBATSCMP_Pos (0UL) /*!< SCU_HIBERNATE LPACSET: VBATSCMP (Bit 0) */ +#define SCU_HIBERNATE_LPACSET_VBATSCMP_Msk (0x1UL) /*!< SCU_HIBERNATE LPACSET: VBATSCMP (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Pos (1UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP (Bit 1) */ +#define SCU_HIBERNATE_LPACSET_AHIBIO0SCMP_Msk (0x2UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0SCMP (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACSET_VBATVAL_Pos (16UL) /*!< SCU_HIBERNATE LPACSET: VBATVAL (Bit 16) */ +#define SCU_HIBERNATE_LPACSET_VBATVAL_Msk (0x10000UL) /*!< SCU_HIBERNATE LPACSET: VBATVAL (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Pos (17UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL (Bit 17) */ +#define SCU_HIBERNATE_LPACSET_AHIBIO0VAL_Msk (0x20000UL) /*!< SCU_HIBERNATE LPACSET: AHIBIO0VAL (Bitfield-Mask: 0x01) */ + +/* ---------------------------- SCU_HIBERNATE_HINTST ---------------------------- */ +#define SCU_HIBERNATE_HINTST_HIBNINT_Pos (0UL) /*!< SCU_HIBERNATE HINTST: HIBNINT (Bit 0) */ +#define SCU_HIBERNATE_HINTST_HIBNINT_Msk (0x1UL) /*!< SCU_HIBERNATE HINTST: HIBNINT (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTST_FLASHOFF_Pos (2UL) /*!< SCU_HIBERNATE HINTST: FLASHOFF (Bit 2) */ +#define SCU_HIBERNATE_HINTST_FLASHOFF_Msk (0x4UL) /*!< SCU_HIBERNATE HINTST: FLASHOFF (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTST_FLASHPD_Pos (3UL) /*!< SCU_HIBERNATE HINTST: FLASHPD (Bit 3) */ +#define SCU_HIBERNATE_HINTST_FLASHPD_Msk (0x8UL) /*!< SCU_HIBERNATE HINTST: FLASHPD (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTST_POFFD_Pos (4UL) /*!< SCU_HIBERNATE HINTST: POFFD (Bit 4) */ +#define SCU_HIBERNATE_HINTST_POFFD_Msk (0x10UL) /*!< SCU_HIBERNATE HINTST: POFFD (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTST_PPODEL_Pos (16UL) /*!< SCU_HIBERNATE HINTST: PPODEL (Bit 16) */ +#define SCU_HIBERNATE_HINTST_PPODEL_Msk (0x30000UL) /*!< SCU_HIBERNATE HINTST: PPODEL (Bitfield-Mask: 0x03) */ +#define SCU_HIBERNATE_HINTST_POFFH_Pos (20UL) /*!< SCU_HIBERNATE HINTST: POFFH (Bit 20) */ +#define SCU_HIBERNATE_HINTST_POFFH_Msk (0x100000UL) /*!< SCU_HIBERNATE HINTST: POFFH (Bitfield-Mask: 0x01) */ + +/* ---------------------------- SCU_HIBERNATE_HINTCLR --------------------------- */ +#define SCU_HIBERNATE_HINTCLR_HIBNINT_Pos (0UL) /*!< SCU_HIBERNATE HINTCLR: HIBNINT (Bit 0) */ +#define SCU_HIBERNATE_HINTCLR_HIBNINT_Msk (0x1UL) /*!< SCU_HIBERNATE HINTCLR: HIBNINT (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Pos (2UL) /*!< SCU_HIBERNATE HINTCLR: FLASHOFF (Bit 2) */ +#define SCU_HIBERNATE_HINTCLR_FLASHOFF_Msk (0x4UL) /*!< SCU_HIBERNATE HINTCLR: FLASHOFF (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTCLR_FLASHPD_Pos (3UL) /*!< SCU_HIBERNATE HINTCLR: FLASHPD (Bit 3) */ +#define SCU_HIBERNATE_HINTCLR_FLASHPD_Msk (0x8UL) /*!< SCU_HIBERNATE HINTCLR: FLASHPD (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTCLR_POFFD_Pos (4UL) /*!< SCU_HIBERNATE HINTCLR: POFFD (Bit 4) */ +#define SCU_HIBERNATE_HINTCLR_POFFD_Msk (0x10UL) /*!< SCU_HIBERNATE HINTCLR: POFFD (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTCLR_PPODEL_Pos (16UL) /*!< SCU_HIBERNATE HINTCLR: PPODEL (Bit 16) */ +#define SCU_HIBERNATE_HINTCLR_PPODEL_Msk (0x30000UL) /*!< SCU_HIBERNATE HINTCLR: PPODEL (Bitfield-Mask: 0x03) */ +#define SCU_HIBERNATE_HINTCLR_POFFH_Pos (20UL) /*!< SCU_HIBERNATE HINTCLR: POFFH (Bit 20) */ +#define SCU_HIBERNATE_HINTCLR_POFFH_Msk (0x100000UL) /*!< SCU_HIBERNATE HINTCLR: POFFH (Bitfield-Mask: 0x01) */ + +/* ---------------------------- SCU_HIBERNATE_HINTSET --------------------------- */ +#define SCU_HIBERNATE_HINTSET_HIBNINT_Pos (0UL) /*!< SCU_HIBERNATE HINTSET: HIBNINT (Bit 0) */ +#define SCU_HIBERNATE_HINTSET_HIBNINT_Msk (0x1UL) /*!< SCU_HIBERNATE HINTSET: HIBNINT (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTSET_VCOREOFF_Pos (1UL) /*!< SCU_HIBERNATE HINTSET: VCOREOFF (Bit 1) */ +#define SCU_HIBERNATE_HINTSET_VCOREOFF_Msk (0x2UL) /*!< SCU_HIBERNATE HINTSET: VCOREOFF (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTSET_FLASHOFF_Pos (2UL) /*!< SCU_HIBERNATE HINTSET: FLASHOFF (Bit 2) */ +#define SCU_HIBERNATE_HINTSET_FLASHOFF_Msk (0x4UL) /*!< SCU_HIBERNATE HINTSET: FLASHOFF (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTSET_FLASHPD_Pos (3UL) /*!< SCU_HIBERNATE HINTSET: FLASHPD (Bit 3) */ +#define SCU_HIBERNATE_HINTSET_FLASHPD_Msk (0x8UL) /*!< SCU_HIBERNATE HINTSET: FLASHPD (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTSET_POFFD_Pos (4UL) /*!< SCU_HIBERNATE HINTSET: POFFD (Bit 4) */ +#define SCU_HIBERNATE_HINTSET_POFFD_Msk (0x10UL) /*!< SCU_HIBERNATE HINTSET: POFFD (Bitfield-Mask: 0x01) */ +#define SCU_HIBERNATE_HINTSET_PPODEL_Pos (16UL) /*!< SCU_HIBERNATE HINTSET: PPODEL (Bit 16) */ +#define SCU_HIBERNATE_HINTSET_PPODEL_Msk (0x30000UL) /*!< SCU_HIBERNATE HINTSET: PPODEL (Bitfield-Mask: 0x03) */ +#define SCU_HIBERNATE_HINTSET_POFFH_Pos (20UL) /*!< SCU_HIBERNATE HINTSET: POFFH (Bit 20) */ +#define SCU_HIBERNATE_HINTSET_POFFH_Msk (0x100000UL) /*!< SCU_HIBERNATE HINTSET: POFFH (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_POWER' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ SCU_POWER_PWRSTAT ----------------------------- */ +#define SCU_POWER_PWRSTAT_HIBEN_Pos (0UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bit 0) */ +#define SCU_POWER_PWRSTAT_HIBEN_Msk (0x1UL) /*!< SCU_POWER PWRSTAT: HIBEN (Bitfield-Mask: 0x01) */ +#define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos (16UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bit 16) */ +#define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk (0x10000UL) /*!< SCU_POWER PWRSTAT: USBPHYPDQ (Bitfield-Mask: 0x01) */ +#define SCU_POWER_PWRSTAT_USBPUWQ_Pos (18UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bit 18) */ +#define SCU_POWER_PWRSTAT_USBPUWQ_Msk (0x40000UL) /*!< SCU_POWER PWRSTAT: USBPUWQ (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_POWER_PWRSET ------------------------------ */ +#define SCU_POWER_PWRSET_HIB_Pos (0UL) /*!< SCU_POWER PWRSET: HIB (Bit 0) */ +#define SCU_POWER_PWRSET_HIB_Msk (0x1UL) /*!< SCU_POWER PWRSET: HIB (Bitfield-Mask: 0x01) */ +#define SCU_POWER_PWRSET_USBPHYPDQ_Pos (16UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bit 16) */ +#define SCU_POWER_PWRSET_USBPHYPDQ_Msk (0x10000UL) /*!< SCU_POWER PWRSET: USBPHYPDQ (Bitfield-Mask: 0x01) */ +#define SCU_POWER_PWRSET_USBPUWQ_Pos (18UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bit 18) */ +#define SCU_POWER_PWRSET_USBPUWQ_Msk (0x40000UL) /*!< SCU_POWER PWRSET: USBPUWQ (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_POWER_PWRCLR ------------------------------ */ +#define SCU_POWER_PWRCLR_HIB_Pos (0UL) /*!< SCU_POWER PWRCLR: HIB (Bit 0) */ +#define SCU_POWER_PWRCLR_HIB_Msk (0x1UL) /*!< SCU_POWER PWRCLR: HIB (Bitfield-Mask: 0x01) */ +#define SCU_POWER_PWRCLR_USBPHYPDQ_Pos (16UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bit 16) */ +#define SCU_POWER_PWRCLR_USBPHYPDQ_Msk (0x10000UL) /*!< SCU_POWER PWRCLR: USBPHYPDQ (Bitfield-Mask: 0x01) */ +#define SCU_POWER_PWRCLR_USBPUWQ_Pos (18UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bit 18) */ +#define SCU_POWER_PWRCLR_USBPUWQ_Msk (0x40000UL) /*!< SCU_POWER PWRCLR: USBPUWQ (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_POWER_EVRSTAT ----------------------------- */ +#define SCU_POWER_EVRSTAT_OV13_Pos (1UL) /*!< SCU_POWER EVRSTAT: OV13 (Bit 1) */ +#define SCU_POWER_EVRSTAT_OV13_Msk (0x2UL) /*!< SCU_POWER EVRSTAT: OV13 (Bitfield-Mask: 0x01) */ + +/* ---------------------------- SCU_POWER_EVRVADCSTAT --------------------------- */ +#define SCU_POWER_EVRVADCSTAT_VADC13V_Pos (0UL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bit 0) */ +#define SCU_POWER_EVRVADCSTAT_VADC13V_Msk (0xffUL) /*!< SCU_POWER EVRVADCSTAT: VADC13V (Bitfield-Mask: 0xff) */ +#define SCU_POWER_EVRVADCSTAT_VADC33V_Pos (8UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bit 8) */ +#define SCU_POWER_EVRVADCSTAT_VADC33V_Msk (0xff00UL) /*!< SCU_POWER EVRVADCSTAT: VADC33V (Bitfield-Mask: 0xff) */ + +/* ------------------------------ SCU_POWER_PWRMON ------------------------------ */ +#define SCU_POWER_PWRMON_THRS_Pos (0UL) /*!< SCU_POWER PWRMON: THRS (Bit 0) */ +#define SCU_POWER_PWRMON_THRS_Msk (0xffUL) /*!< SCU_POWER PWRMON: THRS (Bitfield-Mask: 0xff) */ +#define SCU_POWER_PWRMON_INTV_Pos (8UL) /*!< SCU_POWER PWRMON: INTV (Bit 8) */ +#define SCU_POWER_PWRMON_INTV_Msk (0xff00UL) /*!< SCU_POWER PWRMON: INTV (Bitfield-Mask: 0xff) */ +#define SCU_POWER_PWRMON_ENB_Pos (16UL) /*!< SCU_POWER PWRMON: ENB (Bit 16) */ +#define SCU_POWER_PWRMON_ENB_Msk (0x10000UL) /*!< SCU_POWER PWRMON: ENB (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'SCU_RESET' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */ +#define SCU_RESET_RSTSTAT_RSTSTAT_Pos (0UL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bit 0) */ +#define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0xffUL) /*!< SCU_RESET RSTSTAT: RSTSTAT (Bitfield-Mask: 0xff) */ +#define SCU_RESET_RSTSTAT_HIBWK_Pos (8UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bit 8) */ +#define SCU_RESET_RSTSTAT_HIBWK_Msk (0x100UL) /*!< SCU_RESET RSTSTAT: HIBWK (Bitfield-Mask: 0x01) */ +#define SCU_RESET_RSTSTAT_HIBRS_Pos (9UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bit 9) */ +#define SCU_RESET_RSTSTAT_HIBRS_Msk (0x200UL) /*!< SCU_RESET RSTSTAT: HIBRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_RSTSTAT_LCKEN_Pos (10UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bit 10) */ +#define SCU_RESET_RSTSTAT_LCKEN_Msk (0x400UL) /*!< SCU_RESET RSTSTAT: LCKEN (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_RSTSET ------------------------------ */ +#define SCU_RESET_RSTSET_HIBWK_Pos (8UL) /*!< SCU_RESET RSTSET: HIBWK (Bit 8) */ +#define SCU_RESET_RSTSET_HIBWK_Msk (0x100UL) /*!< SCU_RESET RSTSET: HIBWK (Bitfield-Mask: 0x01) */ +#define SCU_RESET_RSTSET_HIBRS_Pos (9UL) /*!< SCU_RESET RSTSET: HIBRS (Bit 9) */ +#define SCU_RESET_RSTSET_HIBRS_Msk (0x200UL) /*!< SCU_RESET RSTSET: HIBRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_RSTSET_LCKEN_Pos (10UL) /*!< SCU_RESET RSTSET: LCKEN (Bit 10) */ +#define SCU_RESET_RSTSET_LCKEN_Msk (0x400UL) /*!< SCU_RESET RSTSET: LCKEN (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */ +#define SCU_RESET_RSTCLR_RSCLR_Pos (0UL) /*!< SCU_RESET RSTCLR: RSCLR (Bit 0) */ +#define SCU_RESET_RSTCLR_RSCLR_Msk (0x1UL) /*!< SCU_RESET RSTCLR: RSCLR (Bitfield-Mask: 0x01) */ +#define SCU_RESET_RSTCLR_HIBWK_Pos (8UL) /*!< SCU_RESET RSTCLR: HIBWK (Bit 8) */ +#define SCU_RESET_RSTCLR_HIBWK_Msk (0x100UL) /*!< SCU_RESET RSTCLR: HIBWK (Bitfield-Mask: 0x01) */ +#define SCU_RESET_RSTCLR_HIBRS_Pos (9UL) /*!< SCU_RESET RSTCLR: HIBRS (Bit 9) */ +#define SCU_RESET_RSTCLR_HIBRS_Msk (0x200UL) /*!< SCU_RESET RSTCLR: HIBRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_RSTCLR_LCKEN_Pos (10UL) /*!< SCU_RESET RSTCLR: LCKEN (Bit 10) */ +#define SCU_RESET_RSTCLR_LCKEN_Msk (0x400UL) /*!< SCU_RESET RSTCLR: LCKEN (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRSTAT0 ----------------------------- */ +#define SCU_RESET_PRSTAT0_VADCRS_Pos (0UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bit 0) */ +#define SCU_RESET_PRSTAT0_VADCRS_Msk (0x1UL) /*!< SCU_RESET PRSTAT0: VADCRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT0_CCU40RS_Pos (2UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bit 2) */ +#define SCU_RESET_PRSTAT0_CCU40RS_Msk (0x4UL) /*!< SCU_RESET PRSTAT0: CCU40RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT0_CCU41RS_Pos (3UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bit 3) */ +#define SCU_RESET_PRSTAT0_CCU41RS_Msk (0x8UL) /*!< SCU_RESET PRSTAT0: CCU41RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT0_CCU80RS_Pos (7UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bit 7) */ +#define SCU_RESET_PRSTAT0_CCU80RS_Msk (0x80UL) /*!< SCU_RESET PRSTAT0: CCU80RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT0_POSIF0RS_Pos (9UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bit 9) */ +#define SCU_RESET_PRSTAT0_POSIF0RS_Msk (0x200UL) /*!< SCU_RESET PRSTAT0: POSIF0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT0_USIC0RS_Pos (11UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bit 11) */ +#define SCU_RESET_PRSTAT0_USIC0RS_Msk (0x800UL) /*!< SCU_RESET PRSTAT0: USIC0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT0_ERU1RS_Pos (16UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bit 16) */ +#define SCU_RESET_PRSTAT0_ERU1RS_Msk (0x10000UL) /*!< SCU_RESET PRSTAT0: ERU1RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT0_HRPWM0RS_Pos (23UL) /*!< SCU_RESET PRSTAT0: HRPWM0RS (Bit 23) */ +#define SCU_RESET_PRSTAT0_HRPWM0RS_Msk (0x800000UL) /*!< SCU_RESET PRSTAT0: HRPWM0RS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRSET0 ------------------------------ */ +#define SCU_RESET_PRSET0_VADCRS_Pos (0UL) /*!< SCU_RESET PRSET0: VADCRS (Bit 0) */ +#define SCU_RESET_PRSET0_VADCRS_Msk (0x1UL) /*!< SCU_RESET PRSET0: VADCRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET0_CCU40RS_Pos (2UL) /*!< SCU_RESET PRSET0: CCU40RS (Bit 2) */ +#define SCU_RESET_PRSET0_CCU40RS_Msk (0x4UL) /*!< SCU_RESET PRSET0: CCU40RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET0_CCU41RS_Pos (3UL) /*!< SCU_RESET PRSET0: CCU41RS (Bit 3) */ +#define SCU_RESET_PRSET0_CCU41RS_Msk (0x8UL) /*!< SCU_RESET PRSET0: CCU41RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET0_CCU80RS_Pos (7UL) /*!< SCU_RESET PRSET0: CCU80RS (Bit 7) */ +#define SCU_RESET_PRSET0_CCU80RS_Msk (0x80UL) /*!< SCU_RESET PRSET0: CCU80RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET0_POSIF0RS_Pos (9UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bit 9) */ +#define SCU_RESET_PRSET0_POSIF0RS_Msk (0x200UL) /*!< SCU_RESET PRSET0: POSIF0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET0_USIC0RS_Pos (11UL) /*!< SCU_RESET PRSET0: USIC0RS (Bit 11) */ +#define SCU_RESET_PRSET0_USIC0RS_Msk (0x800UL) /*!< SCU_RESET PRSET0: USIC0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET0_ERU1RS_Pos (16UL) /*!< SCU_RESET PRSET0: ERU1RS (Bit 16) */ +#define SCU_RESET_PRSET0_ERU1RS_Msk (0x10000UL) /*!< SCU_RESET PRSET0: ERU1RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET0_HRPWM0RS_Pos (23UL) /*!< SCU_RESET PRSET0: HRPWM0RS (Bit 23) */ +#define SCU_RESET_PRSET0_HRPWM0RS_Msk (0x800000UL) /*!< SCU_RESET PRSET0: HRPWM0RS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRCLR0 ------------------------------ */ +#define SCU_RESET_PRCLR0_VADCRS_Pos (0UL) /*!< SCU_RESET PRCLR0: VADCRS (Bit 0) */ +#define SCU_RESET_PRCLR0_VADCRS_Msk (0x1UL) /*!< SCU_RESET PRCLR0: VADCRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR0_CCU40RS_Pos (2UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bit 2) */ +#define SCU_RESET_PRCLR0_CCU40RS_Msk (0x4UL) /*!< SCU_RESET PRCLR0: CCU40RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR0_CCU41RS_Pos (3UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bit 3) */ +#define SCU_RESET_PRCLR0_CCU41RS_Msk (0x8UL) /*!< SCU_RESET PRCLR0: CCU41RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR0_CCU80RS_Pos (7UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bit 7) */ +#define SCU_RESET_PRCLR0_CCU80RS_Msk (0x80UL) /*!< SCU_RESET PRCLR0: CCU80RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR0_POSIF0RS_Pos (9UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bit 9) */ +#define SCU_RESET_PRCLR0_POSIF0RS_Msk (0x200UL) /*!< SCU_RESET PRCLR0: POSIF0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR0_USIC0RS_Pos (11UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bit 11) */ +#define SCU_RESET_PRCLR0_USIC0RS_Msk (0x800UL) /*!< SCU_RESET PRCLR0: USIC0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR0_ERU1RS_Pos (16UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bit 16) */ +#define SCU_RESET_PRCLR0_ERU1RS_Msk (0x10000UL) /*!< SCU_RESET PRCLR0: ERU1RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR0_HRPWM0RS_Pos (23UL) /*!< SCU_RESET PRCLR0: HRPWM0RS (Bit 23) */ +#define SCU_RESET_PRCLR0_HRPWM0RS_Msk (0x800000UL) /*!< SCU_RESET PRCLR0: HRPWM0RS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRSTAT1 ----------------------------- */ +#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos (3UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bit 3) */ +#define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk (0x8UL) /*!< SCU_RESET PRSTAT1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT1_MCAN0RS_Pos (4UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bit 4) */ +#define SCU_RESET_PRSTAT1_MCAN0RS_Msk (0x10UL) /*!< SCU_RESET PRSTAT1: MCAN0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT1_DACRS_Pos (5UL) /*!< SCU_RESET PRSTAT1: DACRS (Bit 5) */ +#define SCU_RESET_PRSTAT1_DACRS_Msk (0x20UL) /*!< SCU_RESET PRSTAT1: DACRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT1_USIC1RS_Pos (7UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bit 7) */ +#define SCU_RESET_PRSTAT1_USIC1RS_Msk (0x80UL) /*!< SCU_RESET PRSTAT1: USIC1RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT1_PPORTSRS_Pos (9UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bit 9) */ +#define SCU_RESET_PRSTAT1_PPORTSRS_Msk (0x200UL) /*!< SCU_RESET PRSTAT1: PPORTSRS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRSET1 ------------------------------ */ +#define SCU_RESET_PRSET1_LEDTSCU0RS_Pos (3UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bit 3) */ +#define SCU_RESET_PRSET1_LEDTSCU0RS_Msk (0x8UL) /*!< SCU_RESET PRSET1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET1_MCAN0RS_Pos (4UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bit 4) */ +#define SCU_RESET_PRSET1_MCAN0RS_Msk (0x10UL) /*!< SCU_RESET PRSET1: MCAN0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET1_DACRS_Pos (5UL) /*!< SCU_RESET PRSET1: DACRS (Bit 5) */ +#define SCU_RESET_PRSET1_DACRS_Msk (0x20UL) /*!< SCU_RESET PRSET1: DACRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET1_USIC1RS_Pos (7UL) /*!< SCU_RESET PRSET1: USIC1RS (Bit 7) */ +#define SCU_RESET_PRSET1_USIC1RS_Msk (0x80UL) /*!< SCU_RESET PRSET1: USIC1RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET1_PPORTSRS_Pos (9UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bit 9) */ +#define SCU_RESET_PRSET1_PPORTSRS_Msk (0x200UL) /*!< SCU_RESET PRSET1: PPORTSRS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRCLR1 ------------------------------ */ +#define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos (3UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bit 3) */ +#define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk (0x8UL) /*!< SCU_RESET PRCLR1: LEDTSCU0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR1_MCAN0RS_Pos (4UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bit 4) */ +#define SCU_RESET_PRCLR1_MCAN0RS_Msk (0x10UL) /*!< SCU_RESET PRCLR1: MCAN0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR1_DACRS_Pos (5UL) /*!< SCU_RESET PRCLR1: DACRS (Bit 5) */ +#define SCU_RESET_PRCLR1_DACRS_Msk (0x20UL) /*!< SCU_RESET PRCLR1: DACRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR1_USIC1RS_Pos (7UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bit 7) */ +#define SCU_RESET_PRCLR1_USIC1RS_Msk (0x80UL) /*!< SCU_RESET PRCLR1: USIC1RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR1_PPORTSRS_Pos (9UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bit 9) */ +#define SCU_RESET_PRCLR1_PPORTSRS_Msk (0x200UL) /*!< SCU_RESET PRCLR1: PPORTSRS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRSTAT2 ----------------------------- */ +#define SCU_RESET_PRSTAT2_WDTRS_Pos (1UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bit 1) */ +#define SCU_RESET_PRSTAT2_WDTRS_Msk (0x2UL) /*!< SCU_RESET PRSTAT2: WDTRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT2_DMA0RS_Pos (4UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bit 4) */ +#define SCU_RESET_PRSTAT2_DMA0RS_Msk (0x10UL) /*!< SCU_RESET PRSTAT2: DMA0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT2_FCERS_Pos (6UL) /*!< SCU_RESET PRSTAT2: FCERS (Bit 6) */ +#define SCU_RESET_PRSTAT2_FCERS_Msk (0x40UL) /*!< SCU_RESET PRSTAT2: FCERS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSTAT2_USBRS_Pos (7UL) /*!< SCU_RESET PRSTAT2: USBRS (Bit 7) */ +#define SCU_RESET_PRSTAT2_USBRS_Msk (0x80UL) /*!< SCU_RESET PRSTAT2: USBRS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRSET2 ------------------------------ */ +#define SCU_RESET_PRSET2_WDTRS_Pos (1UL) /*!< SCU_RESET PRSET2: WDTRS (Bit 1) */ +#define SCU_RESET_PRSET2_WDTRS_Msk (0x2UL) /*!< SCU_RESET PRSET2: WDTRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET2_DMA0RS_Pos (4UL) /*!< SCU_RESET PRSET2: DMA0RS (Bit 4) */ +#define SCU_RESET_PRSET2_DMA0RS_Msk (0x10UL) /*!< SCU_RESET PRSET2: DMA0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET2_FCERS_Pos (6UL) /*!< SCU_RESET PRSET2: FCERS (Bit 6) */ +#define SCU_RESET_PRSET2_FCERS_Msk (0x40UL) /*!< SCU_RESET PRSET2: FCERS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRSET2_USBRS_Pos (7UL) /*!< SCU_RESET PRSET2: USBRS (Bit 7) */ +#define SCU_RESET_PRSET2_USBRS_Msk (0x80UL) /*!< SCU_RESET PRSET2: USBRS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ SCU_RESET_PRCLR2 ------------------------------ */ +#define SCU_RESET_PRCLR2_WDTRS_Pos (1UL) /*!< SCU_RESET PRCLR2: WDTRS (Bit 1) */ +#define SCU_RESET_PRCLR2_WDTRS_Msk (0x2UL) /*!< SCU_RESET PRCLR2: WDTRS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR2_DMA0RS_Pos (4UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bit 4) */ +#define SCU_RESET_PRCLR2_DMA0RS_Msk (0x10UL) /*!< SCU_RESET PRCLR2: DMA0RS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR2_FCERS_Pos (6UL) /*!< SCU_RESET PRCLR2: FCERS (Bit 6) */ +#define SCU_RESET_PRCLR2_FCERS_Msk (0x40UL) /*!< SCU_RESET PRCLR2: FCERS (Bitfield-Mask: 0x01) */ +#define SCU_RESET_PRCLR2_USBRS_Pos (7UL) /*!< SCU_RESET PRCLR2: USBRS (Bit 7) */ +#define SCU_RESET_PRCLR2_USBRS_Msk (0x80UL) /*!< SCU_RESET PRCLR2: USBRS (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'LEDTS' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- LEDTS_ID ---------------------------------- */ +#define LEDTS_ID_MOD_REV_Pos (0UL) /*!< LEDTS ID: MOD_REV (Bit 0) */ +#define LEDTS_ID_MOD_REV_Msk (0xffUL) /*!< LEDTS ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define LEDTS_ID_MOD_TYPE_Pos (8UL) /*!< LEDTS ID: MOD_TYPE (Bit 8) */ +#define LEDTS_ID_MOD_TYPE_Msk (0xff00UL) /*!< LEDTS ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define LEDTS_ID_MOD_NUMBER_Pos (16UL) /*!< LEDTS ID: MOD_NUMBER (Bit 16) */ +#define LEDTS_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< LEDTS ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- LEDTS_GLOBCTL ------------------------------- */ +#define LEDTS_GLOBCTL_TS_EN_Pos (0UL) /*!< LEDTS GLOBCTL: TS_EN (Bit 0) */ +#define LEDTS_GLOBCTL_TS_EN_Msk (0x1UL) /*!< LEDTS GLOBCTL: TS_EN (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_LD_EN_Pos (1UL) /*!< LEDTS GLOBCTL: LD_EN (Bit 1) */ +#define LEDTS_GLOBCTL_LD_EN_Msk (0x2UL) /*!< LEDTS GLOBCTL: LD_EN (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_CMTR_Pos (2UL) /*!< LEDTS GLOBCTL: CMTR (Bit 2) */ +#define LEDTS_GLOBCTL_CMTR_Msk (0x4UL) /*!< LEDTS GLOBCTL: CMTR (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_ENSYNC_Pos (3UL) /*!< LEDTS GLOBCTL: ENSYNC (Bit 3) */ +#define LEDTS_GLOBCTL_ENSYNC_Msk (0x8UL) /*!< LEDTS GLOBCTL: ENSYNC (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_SUSCFG_Pos (8UL) /*!< LEDTS GLOBCTL: SUSCFG (Bit 8) */ +#define LEDTS_GLOBCTL_SUSCFG_Msk (0x100UL) /*!< LEDTS GLOBCTL: SUSCFG (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_MASKVAL_Pos (9UL) /*!< LEDTS GLOBCTL: MASKVAL (Bit 9) */ +#define LEDTS_GLOBCTL_MASKVAL_Msk (0xe00UL) /*!< LEDTS GLOBCTL: MASKVAL (Bitfield-Mask: 0x07) */ +#define LEDTS_GLOBCTL_FENVAL_Pos (12UL) /*!< LEDTS GLOBCTL: FENVAL (Bit 12) */ +#define LEDTS_GLOBCTL_FENVAL_Msk (0x1000UL) /*!< LEDTS GLOBCTL: FENVAL (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_ITS_EN_Pos (13UL) /*!< LEDTS GLOBCTL: ITS_EN (Bit 13) */ +#define LEDTS_GLOBCTL_ITS_EN_Msk (0x2000UL) /*!< LEDTS GLOBCTL: ITS_EN (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_ITF_EN_Pos (14UL) /*!< LEDTS GLOBCTL: ITF_EN (Bit 14) */ +#define LEDTS_GLOBCTL_ITF_EN_Msk (0x4000UL) /*!< LEDTS GLOBCTL: ITF_EN (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_ITP_EN_Pos (15UL) /*!< LEDTS GLOBCTL: ITP_EN (Bit 15) */ +#define LEDTS_GLOBCTL_ITP_EN_Msk (0x8000UL) /*!< LEDTS GLOBCTL: ITP_EN (Bitfield-Mask: 0x01) */ +#define LEDTS_GLOBCTL_CLK_PS_Pos (16UL) /*!< LEDTS GLOBCTL: CLK_PS (Bit 16) */ +#define LEDTS_GLOBCTL_CLK_PS_Msk (0xffff0000UL) /*!< LEDTS GLOBCTL: CLK_PS (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- LEDTS_FNCTL -------------------------------- */ +#define LEDTS_FNCTL_PADT_Pos (0UL) /*!< LEDTS FNCTL: PADT (Bit 0) */ +#define LEDTS_FNCTL_PADT_Msk (0x7UL) /*!< LEDTS FNCTL: PADT (Bitfield-Mask: 0x07) */ +#define LEDTS_FNCTL_PADTSW_Pos (3UL) /*!< LEDTS FNCTL: PADTSW (Bit 3) */ +#define LEDTS_FNCTL_PADTSW_Msk (0x8UL) /*!< LEDTS FNCTL: PADTSW (Bitfield-Mask: 0x01) */ +#define LEDTS_FNCTL_EPULL_Pos (4UL) /*!< LEDTS FNCTL: EPULL (Bit 4) */ +#define LEDTS_FNCTL_EPULL_Msk (0x10UL) /*!< LEDTS FNCTL: EPULL (Bitfield-Mask: 0x01) */ +#define LEDTS_FNCTL_FNCOL_Pos (5UL) /*!< LEDTS FNCTL: FNCOL (Bit 5) */ +#define LEDTS_FNCTL_FNCOL_Msk (0xe0UL) /*!< LEDTS FNCTL: FNCOL (Bitfield-Mask: 0x07) */ +#define LEDTS_FNCTL_ACCCNT_Pos (16UL) /*!< LEDTS FNCTL: ACCCNT (Bit 16) */ +#define LEDTS_FNCTL_ACCCNT_Msk (0xf0000UL) /*!< LEDTS FNCTL: ACCCNT (Bitfield-Mask: 0x0f) */ +#define LEDTS_FNCTL_TSCCMP_Pos (20UL) /*!< LEDTS FNCTL: TSCCMP (Bit 20) */ +#define LEDTS_FNCTL_TSCCMP_Msk (0x100000UL) /*!< LEDTS FNCTL: TSCCMP (Bitfield-Mask: 0x01) */ +#define LEDTS_FNCTL_TSOEXT_Pos (21UL) /*!< LEDTS FNCTL: TSOEXT (Bit 21) */ +#define LEDTS_FNCTL_TSOEXT_Msk (0x600000UL) /*!< LEDTS FNCTL: TSOEXT (Bitfield-Mask: 0x03) */ +#define LEDTS_FNCTL_TSCTRR_Pos (23UL) /*!< LEDTS FNCTL: TSCTRR (Bit 23) */ +#define LEDTS_FNCTL_TSCTRR_Msk (0x800000UL) /*!< LEDTS FNCTL: TSCTRR (Bitfield-Mask: 0x01) */ +#define LEDTS_FNCTL_TSCTRSAT_Pos (24UL) /*!< LEDTS FNCTL: TSCTRSAT (Bit 24) */ +#define LEDTS_FNCTL_TSCTRSAT_Msk (0x1000000UL) /*!< LEDTS FNCTL: TSCTRSAT (Bitfield-Mask: 0x01) */ +#define LEDTS_FNCTL_NR_TSIN_Pos (25UL) /*!< LEDTS FNCTL: NR_TSIN (Bit 25) */ +#define LEDTS_FNCTL_NR_TSIN_Msk (0xe000000UL) /*!< LEDTS FNCTL: NR_TSIN (Bitfield-Mask: 0x07) */ +#define LEDTS_FNCTL_COLLEV_Pos (28UL) /*!< LEDTS FNCTL: COLLEV (Bit 28) */ +#define LEDTS_FNCTL_COLLEV_Msk (0x10000000UL) /*!< LEDTS FNCTL: COLLEV (Bitfield-Mask: 0x01) */ +#define LEDTS_FNCTL_NR_LEDCOL_Pos (29UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bit 29) */ +#define LEDTS_FNCTL_NR_LEDCOL_Msk (0xe0000000UL) /*!< LEDTS FNCTL: NR_LEDCOL (Bitfield-Mask: 0x07) */ + +/* --------------------------------- LEDTS_EVFR --------------------------------- */ +#define LEDTS_EVFR_TSF_Pos (0UL) /*!< LEDTS EVFR: TSF (Bit 0) */ +#define LEDTS_EVFR_TSF_Msk (0x1UL) /*!< LEDTS EVFR: TSF (Bitfield-Mask: 0x01) */ +#define LEDTS_EVFR_TFF_Pos (1UL) /*!< LEDTS EVFR: TFF (Bit 1) */ +#define LEDTS_EVFR_TFF_Msk (0x2UL) /*!< LEDTS EVFR: TFF (Bitfield-Mask: 0x01) */ +#define LEDTS_EVFR_TPF_Pos (2UL) /*!< LEDTS EVFR: TPF (Bit 2) */ +#define LEDTS_EVFR_TPF_Msk (0x4UL) /*!< LEDTS EVFR: TPF (Bitfield-Mask: 0x01) */ +#define LEDTS_EVFR_TSCTROVF_Pos (3UL) /*!< LEDTS EVFR: TSCTROVF (Bit 3) */ +#define LEDTS_EVFR_TSCTROVF_Msk (0x8UL) /*!< LEDTS EVFR: TSCTROVF (Bitfield-Mask: 0x01) */ +#define LEDTS_EVFR_CTSF_Pos (16UL) /*!< LEDTS EVFR: CTSF (Bit 16) */ +#define LEDTS_EVFR_CTSF_Msk (0x10000UL) /*!< LEDTS EVFR: CTSF (Bitfield-Mask: 0x01) */ +#define LEDTS_EVFR_CTFF_Pos (17UL) /*!< LEDTS EVFR: CTFF (Bit 17) */ +#define LEDTS_EVFR_CTFF_Msk (0x20000UL) /*!< LEDTS EVFR: CTFF (Bitfield-Mask: 0x01) */ +#define LEDTS_EVFR_CTPF_Pos (18UL) /*!< LEDTS EVFR: CTPF (Bit 18) */ +#define LEDTS_EVFR_CTPF_Msk (0x40000UL) /*!< LEDTS EVFR: CTPF (Bitfield-Mask: 0x01) */ + +/* --------------------------------- LEDTS_TSVAL -------------------------------- */ +#define LEDTS_TSVAL_TSCTRVALR_Pos (0UL) /*!< LEDTS TSVAL: TSCTRVALR (Bit 0) */ +#define LEDTS_TSVAL_TSCTRVALR_Msk (0xffffUL) /*!< LEDTS TSVAL: TSCTRVALR (Bitfield-Mask: 0xffff) */ +#define LEDTS_TSVAL_TSCTRVAL_Pos (16UL) /*!< LEDTS TSVAL: TSCTRVAL (Bit 16) */ +#define LEDTS_TSVAL_TSCTRVAL_Msk (0xffff0000UL) /*!< LEDTS TSVAL: TSCTRVAL (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- LEDTS_LINE0 -------------------------------- */ +#define LEDTS_LINE0_LINE_0_Pos (0UL) /*!< LEDTS LINE0: LINE_0 (Bit 0) */ +#define LEDTS_LINE0_LINE_0_Msk (0xffUL) /*!< LEDTS LINE0: LINE_0 (Bitfield-Mask: 0xff) */ +#define LEDTS_LINE0_LINE_1_Pos (8UL) /*!< LEDTS LINE0: LINE_1 (Bit 8) */ +#define LEDTS_LINE0_LINE_1_Msk (0xff00UL) /*!< LEDTS LINE0: LINE_1 (Bitfield-Mask: 0xff) */ +#define LEDTS_LINE0_LINE_2_Pos (16UL) /*!< LEDTS LINE0: LINE_2 (Bit 16) */ +#define LEDTS_LINE0_LINE_2_Msk (0xff0000UL) /*!< LEDTS LINE0: LINE_2 (Bitfield-Mask: 0xff) */ +#define LEDTS_LINE0_LINE_3_Pos (24UL) /*!< LEDTS LINE0: LINE_3 (Bit 24) */ +#define LEDTS_LINE0_LINE_3_Msk (0xff000000UL) /*!< LEDTS LINE0: LINE_3 (Bitfield-Mask: 0xff) */ + +/* --------------------------------- LEDTS_LINE1 -------------------------------- */ +#define LEDTS_LINE1_LINE_4_Pos (0UL) /*!< LEDTS LINE1: LINE_4 (Bit 0) */ +#define LEDTS_LINE1_LINE_4_Msk (0xffUL) /*!< LEDTS LINE1: LINE_4 (Bitfield-Mask: 0xff) */ +#define LEDTS_LINE1_LINE_5_Pos (8UL) /*!< LEDTS LINE1: LINE_5 (Bit 8) */ +#define LEDTS_LINE1_LINE_5_Msk (0xff00UL) /*!< LEDTS LINE1: LINE_5 (Bitfield-Mask: 0xff) */ +#define LEDTS_LINE1_LINE_6_Pos (16UL) /*!< LEDTS LINE1: LINE_6 (Bit 16) */ +#define LEDTS_LINE1_LINE_6_Msk (0xff0000UL) /*!< LEDTS LINE1: LINE_6 (Bitfield-Mask: 0xff) */ +#define LEDTS_LINE1_LINE_A_Pos (24UL) /*!< LEDTS LINE1: LINE_A (Bit 24) */ +#define LEDTS_LINE1_LINE_A_Msk (0xff000000UL) /*!< LEDTS LINE1: LINE_A (Bitfield-Mask: 0xff) */ + +/* -------------------------------- LEDTS_LDCMP0 -------------------------------- */ +#define LEDTS_LDCMP0_CMP_LD0_Pos (0UL) /*!< LEDTS LDCMP0: CMP_LD0 (Bit 0) */ +#define LEDTS_LDCMP0_CMP_LD0_Msk (0xffUL) /*!< LEDTS LDCMP0: CMP_LD0 (Bitfield-Mask: 0xff) */ +#define LEDTS_LDCMP0_CMP_LD1_Pos (8UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bit 8) */ +#define LEDTS_LDCMP0_CMP_LD1_Msk (0xff00UL) /*!< LEDTS LDCMP0: CMP_LD1 (Bitfield-Mask: 0xff) */ +#define LEDTS_LDCMP0_CMP_LD2_Pos (16UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bit 16) */ +#define LEDTS_LDCMP0_CMP_LD2_Msk (0xff0000UL) /*!< LEDTS LDCMP0: CMP_LD2 (Bitfield-Mask: 0xff) */ +#define LEDTS_LDCMP0_CMP_LD3_Pos (24UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bit 24) */ +#define LEDTS_LDCMP0_CMP_LD3_Msk (0xff000000UL) /*!< LEDTS LDCMP0: CMP_LD3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- LEDTS_LDCMP1 -------------------------------- */ +#define LEDTS_LDCMP1_CMP_LD4_Pos (0UL) /*!< LEDTS LDCMP1: CMP_LD4 (Bit 0) */ +#define LEDTS_LDCMP1_CMP_LD4_Msk (0xffUL) /*!< LEDTS LDCMP1: CMP_LD4 (Bitfield-Mask: 0xff) */ +#define LEDTS_LDCMP1_CMP_LD5_Pos (8UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bit 8) */ +#define LEDTS_LDCMP1_CMP_LD5_Msk (0xff00UL) /*!< LEDTS LDCMP1: CMP_LD5 (Bitfield-Mask: 0xff) */ +#define LEDTS_LDCMP1_CMP_LD6_Pos (16UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bit 16) */ +#define LEDTS_LDCMP1_CMP_LD6_Msk (0xff0000UL) /*!< LEDTS LDCMP1: CMP_LD6 (Bitfield-Mask: 0xff) */ +#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos (24UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bit 24) */ +#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk (0xff000000UL) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM (Bitfield-Mask: 0xff) */ + +/* -------------------------------- LEDTS_TSCMP0 -------------------------------- */ +#define LEDTS_TSCMP0_CMP_TS0_Pos (0UL) /*!< LEDTS TSCMP0: CMP_TS0 (Bit 0) */ +#define LEDTS_TSCMP0_CMP_TS0_Msk (0xffUL) /*!< LEDTS TSCMP0: CMP_TS0 (Bitfield-Mask: 0xff) */ +#define LEDTS_TSCMP0_CMP_TS1_Pos (8UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bit 8) */ +#define LEDTS_TSCMP0_CMP_TS1_Msk (0xff00UL) /*!< LEDTS TSCMP0: CMP_TS1 (Bitfield-Mask: 0xff) */ +#define LEDTS_TSCMP0_CMP_TS2_Pos (16UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bit 16) */ +#define LEDTS_TSCMP0_CMP_TS2_Msk (0xff0000UL) /*!< LEDTS TSCMP0: CMP_TS2 (Bitfield-Mask: 0xff) */ +#define LEDTS_TSCMP0_CMP_TS3_Pos (24UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bit 24) */ +#define LEDTS_TSCMP0_CMP_TS3_Msk (0xff000000UL) /*!< LEDTS TSCMP0: CMP_TS3 (Bitfield-Mask: 0xff) */ + +/* -------------------------------- LEDTS_TSCMP1 -------------------------------- */ +#define LEDTS_TSCMP1_CMP_TS4_Pos (0UL) /*!< LEDTS TSCMP1: CMP_TS4 (Bit 0) */ +#define LEDTS_TSCMP1_CMP_TS4_Msk (0xffUL) /*!< LEDTS TSCMP1: CMP_TS4 (Bitfield-Mask: 0xff) */ +#define LEDTS_TSCMP1_CMP_TS5_Pos (8UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bit 8) */ +#define LEDTS_TSCMP1_CMP_TS5_Msk (0xff00UL) /*!< LEDTS TSCMP1: CMP_TS5 (Bitfield-Mask: 0xff) */ +#define LEDTS_TSCMP1_CMP_TS6_Pos (16UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bit 16) */ +#define LEDTS_TSCMP1_CMP_TS6_Msk (0xff0000UL) /*!< LEDTS TSCMP1: CMP_TS6 (Bitfield-Mask: 0xff) */ +#define LEDTS_TSCMP1_CMP_TS7_Pos (24UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bit 24) */ +#define LEDTS_TSCMP1_CMP_TS7_Msk (0xff000000UL) /*!< LEDTS TSCMP1: CMP_TS7 (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ Group 'USB' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- USB_GAHBCFG -------------------------------- */ +#define USB_GAHBCFG_GlblIntrMsk_Pos (0UL) /*!< USB GAHBCFG: GlblIntrMsk (Bit 0) */ +#define USB_GAHBCFG_GlblIntrMsk_Msk (0x1UL) /*!< USB GAHBCFG: GlblIntrMsk (Bitfield-Mask: 0x01) */ +#define USB_GAHBCFG_HBstLen_Pos (1UL) /*!< USB GAHBCFG: HBstLen (Bit 1) */ +#define USB_GAHBCFG_HBstLen_Msk (0x1eUL) /*!< USB GAHBCFG: HBstLen (Bitfield-Mask: 0x0f) */ +#define USB_GAHBCFG_DMAEn_Pos (5UL) /*!< USB GAHBCFG: DMAEn (Bit 5) */ +#define USB_GAHBCFG_DMAEn_Msk (0x20UL) /*!< USB GAHBCFG: DMAEn (Bitfield-Mask: 0x01) */ +#define USB_GAHBCFG_NPTxFEmpLvl_Pos (7UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bit 7) */ +#define USB_GAHBCFG_NPTxFEmpLvl_Msk (0x80UL) /*!< USB GAHBCFG: NPTxFEmpLvl (Bitfield-Mask: 0x01) */ +#define USB_GAHBCFG_AHBSingle_Pos (23UL) /*!< USB GAHBCFG: AHBSingle (Bit 23) */ +#define USB_GAHBCFG_AHBSingle_Msk (0x800000UL) /*!< USB GAHBCFG: AHBSingle (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USB_GUSBCFG -------------------------------- */ +#define USB_GUSBCFG_TOutCal_Pos (0UL) /*!< USB GUSBCFG: TOutCal (Bit 0) */ +#define USB_GUSBCFG_TOutCal_Msk (0x7UL) /*!< USB GUSBCFG: TOutCal (Bitfield-Mask: 0x07) */ +#define USB_GUSBCFG_PHYSel_Pos (6UL) /*!< USB GUSBCFG: PHYSel (Bit 6) */ +#define USB_GUSBCFG_PHYSel_Msk (0x40UL) /*!< USB GUSBCFG: PHYSel (Bitfield-Mask: 0x01) */ +#define USB_GUSBCFG_USBTrdTim_Pos (10UL) /*!< USB GUSBCFG: USBTrdTim (Bit 10) */ +#define USB_GUSBCFG_USBTrdTim_Msk (0x3c00UL) /*!< USB GUSBCFG: USBTrdTim (Bitfield-Mask: 0x0f) */ +#define USB_GUSBCFG_TxEndDelay_Pos (28UL) /*!< USB GUSBCFG: TxEndDelay (Bit 28) */ +#define USB_GUSBCFG_TxEndDelay_Msk (0x10000000UL) /*!< USB GUSBCFG: TxEndDelay (Bitfield-Mask: 0x01) */ +#define USB_GUSBCFG_ForceDevMode_Pos (30UL) /*!< USB GUSBCFG: ForceDevMode (Bit 30) */ +#define USB_GUSBCFG_ForceDevMode_Msk (0x40000000UL) /*!< USB GUSBCFG: ForceDevMode (Bitfield-Mask: 0x01) */ +#define USB_GUSBCFG_CTP_Pos (31UL) /*!< USB GUSBCFG: CTP (Bit 31) */ +#define USB_GUSBCFG_CTP_Msk (0x80000000UL) /*!< USB GUSBCFG: CTP (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USB_GRSTCTL -------------------------------- */ +#define USB_GRSTCTL_CSftRst_Pos (0UL) /*!< USB GRSTCTL: CSftRst (Bit 0) */ +#define USB_GRSTCTL_CSftRst_Msk (0x1UL) /*!< USB GRSTCTL: CSftRst (Bitfield-Mask: 0x01) */ +#define USB_GRSTCTL_RxFFlsh_Pos (4UL) /*!< USB GRSTCTL: RxFFlsh (Bit 4) */ +#define USB_GRSTCTL_RxFFlsh_Msk (0x10UL) /*!< USB GRSTCTL: RxFFlsh (Bitfield-Mask: 0x01) */ +#define USB_GRSTCTL_TxFFlsh_Pos (5UL) /*!< USB GRSTCTL: TxFFlsh (Bit 5) */ +#define USB_GRSTCTL_TxFFlsh_Msk (0x20UL) /*!< USB GRSTCTL: TxFFlsh (Bitfield-Mask: 0x01) */ +#define USB_GRSTCTL_TxFNum_Pos (6UL) /*!< USB GRSTCTL: TxFNum (Bit 6) */ +#define USB_GRSTCTL_TxFNum_Msk (0x7c0UL) /*!< USB GRSTCTL: TxFNum (Bitfield-Mask: 0x1f) */ +#define USB_GRSTCTL_DMAReq_Pos (30UL) /*!< USB GRSTCTL: DMAReq (Bit 30) */ +#define USB_GRSTCTL_DMAReq_Msk (0x40000000UL) /*!< USB GRSTCTL: DMAReq (Bitfield-Mask: 0x01) */ +#define USB_GRSTCTL_AHBIdle_Pos (31UL) /*!< USB GRSTCTL: AHBIdle (Bit 31) */ +#define USB_GRSTCTL_AHBIdle_Msk (0x80000000UL) /*!< USB GRSTCTL: AHBIdle (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USB_GINTSTS -------------------------------- */ +#define USB_GINTSTS_CurMod_Pos (0UL) /*!< USB GINTSTS: CurMod (Bit 0) */ +#define USB_GINTSTS_CurMod_Msk (0x1UL) /*!< USB GINTSTS: CurMod (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_Sof_Pos (3UL) /*!< USB GINTSTS: Sof (Bit 3) */ +#define USB_GINTSTS_Sof_Msk (0x8UL) /*!< USB GINTSTS: Sof (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_RxFLvl_Pos (4UL) /*!< USB GINTSTS: RxFLvl (Bit 4) */ +#define USB_GINTSTS_RxFLvl_Msk (0x10UL) /*!< USB GINTSTS: RxFLvl (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_GINNakEff_Pos (6UL) /*!< USB GINTSTS: GINNakEff (Bit 6) */ +#define USB_GINTSTS_GINNakEff_Msk (0x40UL) /*!< USB GINTSTS: GINNakEff (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_GOUTNakEff_Pos (7UL) /*!< USB GINTSTS: GOUTNakEff (Bit 7) */ +#define USB_GINTSTS_GOUTNakEff_Msk (0x80UL) /*!< USB GINTSTS: GOUTNakEff (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_ErlySusp_Pos (10UL) /*!< USB GINTSTS: ErlySusp (Bit 10) */ +#define USB_GINTSTS_ErlySusp_Msk (0x400UL) /*!< USB GINTSTS: ErlySusp (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_USBSusp_Pos (11UL) /*!< USB GINTSTS: USBSusp (Bit 11) */ +#define USB_GINTSTS_USBSusp_Msk (0x800UL) /*!< USB GINTSTS: USBSusp (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_USBRst_Pos (12UL) /*!< USB GINTSTS: USBRst (Bit 12) */ +#define USB_GINTSTS_USBRst_Msk (0x1000UL) /*!< USB GINTSTS: USBRst (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_EnumDone_Pos (13UL) /*!< USB GINTSTS: EnumDone (Bit 13) */ +#define USB_GINTSTS_EnumDone_Msk (0x2000UL) /*!< USB GINTSTS: EnumDone (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_ISOOutDrop_Pos (14UL) /*!< USB GINTSTS: ISOOutDrop (Bit 14) */ +#define USB_GINTSTS_ISOOutDrop_Msk (0x4000UL) /*!< USB GINTSTS: ISOOutDrop (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_EOPF_Pos (15UL) /*!< USB GINTSTS: EOPF (Bit 15) */ +#define USB_GINTSTS_EOPF_Msk (0x8000UL) /*!< USB GINTSTS: EOPF (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_IEPInt_Pos (18UL) /*!< USB GINTSTS: IEPInt (Bit 18) */ +#define USB_GINTSTS_IEPInt_Msk (0x40000UL) /*!< USB GINTSTS: IEPInt (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_OEPInt_Pos (19UL) /*!< USB GINTSTS: OEPInt (Bit 19) */ +#define USB_GINTSTS_OEPInt_Msk (0x80000UL) /*!< USB GINTSTS: OEPInt (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_incompISOIN_Pos (20UL) /*!< USB GINTSTS: incompISOIN (Bit 20) */ +#define USB_GINTSTS_incompISOIN_Msk (0x100000UL) /*!< USB GINTSTS: incompISOIN (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_incomplSOOUT_Pos (21UL) /*!< USB GINTSTS: incomplSOOUT (Bit 21) */ +#define USB_GINTSTS_incomplSOOUT_Msk (0x200000UL) /*!< USB GINTSTS: incomplSOOUT (Bitfield-Mask: 0x01) */ +#define USB_GINTSTS_WkUpInt_Pos (31UL) /*!< USB GINTSTS: WkUpInt (Bit 31) */ +#define USB_GINTSTS_WkUpInt_Msk (0x80000000UL) /*!< USB GINTSTS: WkUpInt (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USB_GINTMSK -------------------------------- */ +#define USB_GINTMSK_SofMsk_Pos (3UL) /*!< USB GINTMSK: SofMsk (Bit 3) */ +#define USB_GINTMSK_SofMsk_Msk (0x8UL) /*!< USB GINTMSK: SofMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_RxFLvlMsk_Pos (4UL) /*!< USB GINTMSK: RxFLvlMsk (Bit 4) */ +#define USB_GINTMSK_RxFLvlMsk_Msk (0x10UL) /*!< USB GINTMSK: RxFLvlMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_GINNakEffMsk_Pos (6UL) /*!< USB GINTMSK: GINNakEffMsk (Bit 6) */ +#define USB_GINTMSK_GINNakEffMsk_Msk (0x40UL) /*!< USB GINTMSK: GINNakEffMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_GOUTNakEffMsk_Pos (7UL) /*!< USB GINTMSK: GOUTNakEffMsk (Bit 7) */ +#define USB_GINTMSK_GOUTNakEffMsk_Msk (0x80UL) /*!< USB GINTMSK: GOUTNakEffMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_ErlySuspMsk_Pos (10UL) /*!< USB GINTMSK: ErlySuspMsk (Bit 10) */ +#define USB_GINTMSK_ErlySuspMsk_Msk (0x400UL) /*!< USB GINTMSK: ErlySuspMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_USBSuspMsk_Pos (11UL) /*!< USB GINTMSK: USBSuspMsk (Bit 11) */ +#define USB_GINTMSK_USBSuspMsk_Msk (0x800UL) /*!< USB GINTMSK: USBSuspMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_USBRstMsk_Pos (12UL) /*!< USB GINTMSK: USBRstMsk (Bit 12) */ +#define USB_GINTMSK_USBRstMsk_Msk (0x1000UL) /*!< USB GINTMSK: USBRstMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_EnumDoneMsk_Pos (13UL) /*!< USB GINTMSK: EnumDoneMsk (Bit 13) */ +#define USB_GINTMSK_EnumDoneMsk_Msk (0x2000UL) /*!< USB GINTMSK: EnumDoneMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_ISOOutDropMsk_Pos (14UL) /*!< USB GINTMSK: ISOOutDropMsk (Bit 14) */ +#define USB_GINTMSK_ISOOutDropMsk_Msk (0x4000UL) /*!< USB GINTMSK: ISOOutDropMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_EOPFMsk_Pos (15UL) /*!< USB GINTMSK: EOPFMsk (Bit 15) */ +#define USB_GINTMSK_EOPFMsk_Msk (0x8000UL) /*!< USB GINTMSK: EOPFMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_IEPIntMsk_Pos (18UL) /*!< USB GINTMSK: IEPIntMsk (Bit 18) */ +#define USB_GINTMSK_IEPIntMsk_Msk (0x40000UL) /*!< USB GINTMSK: IEPIntMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_OEPIntMsk_Pos (19UL) /*!< USB GINTMSK: OEPIntMsk (Bit 19) */ +#define USB_GINTMSK_OEPIntMsk_Msk (0x80000UL) /*!< USB GINTMSK: OEPIntMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_incompISOINMsk_Pos (20UL) /*!< USB GINTMSK: incompISOINMsk (Bit 20) */ +#define USB_GINTMSK_incompISOINMsk_Msk (0x100000UL) /*!< USB GINTMSK: incompISOINMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_incomplSOOUTMsk_Pos (21UL) /*!< USB GINTMSK: incomplSOOUTMsk (Bit 21) */ +#define USB_GINTMSK_incomplSOOUTMsk_Msk (0x200000UL) /*!< USB GINTMSK: incomplSOOUTMsk (Bitfield-Mask: 0x01) */ +#define USB_GINTMSK_WkUpIntMsk_Pos (31UL) /*!< USB GINTMSK: WkUpIntMsk (Bit 31) */ +#define USB_GINTMSK_WkUpIntMsk_Msk (0x80000000UL) /*!< USB GINTMSK: WkUpIntMsk (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USB_GRXSTSR -------------------------------- */ +#define USB_GRXSTSR_EPNum_Pos (0UL) /*!< USB GRXSTSR: EPNum (Bit 0) */ +#define USB_GRXSTSR_EPNum_Msk (0xfUL) /*!< USB GRXSTSR: EPNum (Bitfield-Mask: 0x0f) */ +#define USB_GRXSTSR_BCnt_Pos (4UL) /*!< USB GRXSTSR: BCnt (Bit 4) */ +#define USB_GRXSTSR_BCnt_Msk (0x7ff0UL) /*!< USB GRXSTSR: BCnt (Bitfield-Mask: 0x7ff) */ +#define USB_GRXSTSR_DPID_Pos (15UL) /*!< USB GRXSTSR: DPID (Bit 15) */ +#define USB_GRXSTSR_DPID_Msk (0x18000UL) /*!< USB GRXSTSR: DPID (Bitfield-Mask: 0x03) */ +#define USB_GRXSTSR_PktSts_Pos (17UL) /*!< USB GRXSTSR: PktSts (Bit 17) */ +#define USB_GRXSTSR_PktSts_Msk (0x1e0000UL) /*!< USB GRXSTSR: PktSts (Bitfield-Mask: 0x0f) */ +#define USB_GRXSTSR_FN_Pos (21UL) /*!< USB GRXSTSR: FN (Bit 21) */ +#define USB_GRXSTSR_FN_Msk (0x1e00000UL) /*!< USB GRXSTSR: FN (Bitfield-Mask: 0x0f) */ + +/* --------------------------------- USB_GRXSTSP -------------------------------- */ +#define USB_GRXSTSP_EPNum_Pos (0UL) /*!< USB GRXSTSP: EPNum (Bit 0) */ +#define USB_GRXSTSP_EPNum_Msk (0xfUL) /*!< USB GRXSTSP: EPNum (Bitfield-Mask: 0x0f) */ +#define USB_GRXSTSP_BCnt_Pos (4UL) /*!< USB GRXSTSP: BCnt (Bit 4) */ +#define USB_GRXSTSP_BCnt_Msk (0x7ff0UL) /*!< USB GRXSTSP: BCnt (Bitfield-Mask: 0x7ff) */ +#define USB_GRXSTSP_DPID_Pos (15UL) /*!< USB GRXSTSP: DPID (Bit 15) */ +#define USB_GRXSTSP_DPID_Msk (0x18000UL) /*!< USB GRXSTSP: DPID (Bitfield-Mask: 0x03) */ +#define USB_GRXSTSP_PktSts_Pos (17UL) /*!< USB GRXSTSP: PktSts (Bit 17) */ +#define USB_GRXSTSP_PktSts_Msk (0x1e0000UL) /*!< USB GRXSTSP: PktSts (Bitfield-Mask: 0x0f) */ +#define USB_GRXSTSP_FN_Pos (21UL) /*!< USB GRXSTSP: FN (Bit 21) */ +#define USB_GRXSTSP_FN_Msk (0x1e00000UL) /*!< USB GRXSTSP: FN (Bitfield-Mask: 0x0f) */ + +/* --------------------------------- USB_GRXFSIZ -------------------------------- */ +#define USB_GRXFSIZ_RxFDep_Pos (0UL) /*!< USB GRXFSIZ: RxFDep (Bit 0) */ +#define USB_GRXFSIZ_RxFDep_Msk (0xffffUL) /*!< USB GRXFSIZ: RxFDep (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_GNPTXFSIZ ------------------------------- */ +#define USB_GNPTXFSIZ_INEPTxF0StAddr_Pos (0UL) /*!< USB GNPTXFSIZ: INEPTxF0StAddr (Bit 0) */ +#define USB_GNPTXFSIZ_INEPTxF0StAddr_Msk (0xffffUL) /*!< USB GNPTXFSIZ: INEPTxF0StAddr (Bitfield-Mask: 0xffff) */ +#define USB_GNPTXFSIZ_INEPTxF0Dep_Pos (16UL) /*!< USB GNPTXFSIZ: INEPTxF0Dep (Bit 16) */ +#define USB_GNPTXFSIZ_INEPTxF0Dep_Msk (0xffff0000UL) /*!< USB GNPTXFSIZ: INEPTxF0Dep (Bitfield-Mask: 0xffff) */ + +/* ---------------------------------- USB_GUID ---------------------------------- */ +#define USB_GUID_MOD_REV_Pos (0UL) /*!< USB GUID: MOD_REV (Bit 0) */ +#define USB_GUID_MOD_REV_Msk (0xffUL) /*!< USB GUID: MOD_REV (Bitfield-Mask: 0xff) */ +#define USB_GUID_MOD_TYPE_Pos (8UL) /*!< USB GUID: MOD_TYPE (Bit 8) */ +#define USB_GUID_MOD_TYPE_Msk (0xff00UL) /*!< USB GUID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define USB_GUID_MOD_NUMBER_Pos (16UL) /*!< USB GUID: MOD_NUMBER (Bit 16) */ +#define USB_GUID_MOD_NUMBER_Msk (0xffff0000UL) /*!< USB GUID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_GDFIFOCFG ------------------------------- */ +#define USB_GDFIFOCFG_GDFIFOCfg_Pos (0UL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bit 0) */ +#define USB_GDFIFOCFG_GDFIFOCfg_Msk (0xffffUL) /*!< USB GDFIFOCFG: GDFIFOCfg (Bitfield-Mask: 0xffff) */ +#define USB_GDFIFOCFG_EPInfoBaseAddr_Pos (16UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bit 16) */ +#define USB_GDFIFOCFG_EPInfoBaseAddr_Msk (0xffff0000UL) /*!< USB GDFIFOCFG: EPInfoBaseAddr (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DIEPTXF1 -------------------------------- */ +#define USB_DIEPTXF1_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bit 0) */ +#define USB_DIEPTXF1_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF1: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ +#define USB_DIEPTXF1_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bit 16) */ +#define USB_DIEPTXF1_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF1: INEPnTxFDep (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DIEPTXF2 -------------------------------- */ +#define USB_DIEPTXF2_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bit 0) */ +#define USB_DIEPTXF2_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF2: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ +#define USB_DIEPTXF2_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bit 16) */ +#define USB_DIEPTXF2_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF2: INEPnTxFDep (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DIEPTXF3 -------------------------------- */ +#define USB_DIEPTXF3_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bit 0) */ +#define USB_DIEPTXF3_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF3: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ +#define USB_DIEPTXF3_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bit 16) */ +#define USB_DIEPTXF3_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF3: INEPnTxFDep (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DIEPTXF4 -------------------------------- */ +#define USB_DIEPTXF4_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bit 0) */ +#define USB_DIEPTXF4_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF4: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ +#define USB_DIEPTXF4_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bit 16) */ +#define USB_DIEPTXF4_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF4: INEPnTxFDep (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DIEPTXF5 -------------------------------- */ +#define USB_DIEPTXF5_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bit 0) */ +#define USB_DIEPTXF5_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF5: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ +#define USB_DIEPTXF5_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bit 16) */ +#define USB_DIEPTXF5_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF5: INEPnTxFDep (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DIEPTXF6 -------------------------------- */ +#define USB_DIEPTXF6_INEPnTxFStAddr_Pos (0UL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bit 0) */ +#define USB_DIEPTXF6_INEPnTxFStAddr_Msk (0xffffUL) /*!< USB DIEPTXF6: INEPnTxFStAddr (Bitfield-Mask: 0xffff) */ +#define USB_DIEPTXF6_INEPnTxFDep_Pos (16UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bit 16) */ +#define USB_DIEPTXF6_INEPnTxFDep_Msk (0xffff0000UL) /*!< USB DIEPTXF6: INEPnTxFDep (Bitfield-Mask: 0xffff) */ + +/* ---------------------------------- USB_DCFG ---------------------------------- */ +#define USB_DCFG_DevSpd_Pos (0UL) /*!< USB DCFG: DevSpd (Bit 0) */ +#define USB_DCFG_DevSpd_Msk (0x3UL) /*!< USB DCFG: DevSpd (Bitfield-Mask: 0x03) */ +#define USB_DCFG_NZStsOUTHShk_Pos (2UL) /*!< USB DCFG: NZStsOUTHShk (Bit 2) */ +#define USB_DCFG_NZStsOUTHShk_Msk (0x4UL) /*!< USB DCFG: NZStsOUTHShk (Bitfield-Mask: 0x01) */ +#define USB_DCFG_DevAddr_Pos (4UL) /*!< USB DCFG: DevAddr (Bit 4) */ +#define USB_DCFG_DevAddr_Msk (0x7f0UL) /*!< USB DCFG: DevAddr (Bitfield-Mask: 0x7f) */ +#define USB_DCFG_PerFrInt_Pos (11UL) /*!< USB DCFG: PerFrInt (Bit 11) */ +#define USB_DCFG_PerFrInt_Msk (0x1800UL) /*!< USB DCFG: PerFrInt (Bitfield-Mask: 0x03) */ +#define USB_DCFG_DescDMA_Pos (23UL) /*!< USB DCFG: DescDMA (Bit 23) */ +#define USB_DCFG_DescDMA_Msk (0x800000UL) /*!< USB DCFG: DescDMA (Bitfield-Mask: 0x01) */ +#define USB_DCFG_PerSchIntvl_Pos (24UL) /*!< USB DCFG: PerSchIntvl (Bit 24) */ +#define USB_DCFG_PerSchIntvl_Msk (0x3000000UL) /*!< USB DCFG: PerSchIntvl (Bitfield-Mask: 0x03) */ + +/* ---------------------------------- USB_DCTL ---------------------------------- */ +#define USB_DCTL_RmtWkUpSig_Pos (0UL) /*!< USB DCTL: RmtWkUpSig (Bit 0) */ +#define USB_DCTL_RmtWkUpSig_Msk (0x1UL) /*!< USB DCTL: RmtWkUpSig (Bitfield-Mask: 0x01) */ +#define USB_DCTL_SftDiscon_Pos (1UL) /*!< USB DCTL: SftDiscon (Bit 1) */ +#define USB_DCTL_SftDiscon_Msk (0x2UL) /*!< USB DCTL: SftDiscon (Bitfield-Mask: 0x01) */ +#define USB_DCTL_GNPINNakSts_Pos (2UL) /*!< USB DCTL: GNPINNakSts (Bit 2) */ +#define USB_DCTL_GNPINNakSts_Msk (0x4UL) /*!< USB DCTL: GNPINNakSts (Bitfield-Mask: 0x01) */ +#define USB_DCTL_GOUTNakSts_Pos (3UL) /*!< USB DCTL: GOUTNakSts (Bit 3) */ +#define USB_DCTL_GOUTNakSts_Msk (0x8UL) /*!< USB DCTL: GOUTNakSts (Bitfield-Mask: 0x01) */ +#define USB_DCTL_SGNPInNak_Pos (7UL) /*!< USB DCTL: SGNPInNak (Bit 7) */ +#define USB_DCTL_SGNPInNak_Msk (0x80UL) /*!< USB DCTL: SGNPInNak (Bitfield-Mask: 0x01) */ +#define USB_DCTL_CGNPInNak_Pos (8UL) /*!< USB DCTL: CGNPInNak (Bit 8) */ +#define USB_DCTL_CGNPInNak_Msk (0x100UL) /*!< USB DCTL: CGNPInNak (Bitfield-Mask: 0x01) */ +#define USB_DCTL_SGOUTNak_Pos (9UL) /*!< USB DCTL: SGOUTNak (Bit 9) */ +#define USB_DCTL_SGOUTNak_Msk (0x200UL) /*!< USB DCTL: SGOUTNak (Bitfield-Mask: 0x01) */ +#define USB_DCTL_CGOUTNak_Pos (10UL) /*!< USB DCTL: CGOUTNak (Bit 10) */ +#define USB_DCTL_CGOUTNak_Msk (0x400UL) /*!< USB DCTL: CGOUTNak (Bitfield-Mask: 0x01) */ +#define USB_DCTL_GMC_Pos (13UL) /*!< USB DCTL: GMC (Bit 13) */ +#define USB_DCTL_GMC_Msk (0x6000UL) /*!< USB DCTL: GMC (Bitfield-Mask: 0x03) */ +#define USB_DCTL_IgnrFrmNum_Pos (15UL) /*!< USB DCTL: IgnrFrmNum (Bit 15) */ +#define USB_DCTL_IgnrFrmNum_Msk (0x8000UL) /*!< USB DCTL: IgnrFrmNum (Bitfield-Mask: 0x01) */ +#define USB_DCTL_NakOnBble_Pos (16UL) /*!< USB DCTL: NakOnBble (Bit 16) */ +#define USB_DCTL_NakOnBble_Msk (0x10000UL) /*!< USB DCTL: NakOnBble (Bitfield-Mask: 0x01) */ +#define USB_DCTL_EnContOnBNA_Pos (17UL) /*!< USB DCTL: EnContOnBNA (Bit 17) */ +#define USB_DCTL_EnContOnBNA_Msk (0x20000UL) /*!< USB DCTL: EnContOnBNA (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- USB_DSTS ---------------------------------- */ +#define USB_DSTS_SuspSts_Pos (0UL) /*!< USB DSTS: SuspSts (Bit 0) */ +#define USB_DSTS_SuspSts_Msk (0x1UL) /*!< USB DSTS: SuspSts (Bitfield-Mask: 0x01) */ +#define USB_DSTS_EnumSpd_Pos (1UL) /*!< USB DSTS: EnumSpd (Bit 1) */ +#define USB_DSTS_EnumSpd_Msk (0x6UL) /*!< USB DSTS: EnumSpd (Bitfield-Mask: 0x03) */ +#define USB_DSTS_ErrticErr_Pos (3UL) /*!< USB DSTS: ErrticErr (Bit 3) */ +#define USB_DSTS_ErrticErr_Msk (0x8UL) /*!< USB DSTS: ErrticErr (Bitfield-Mask: 0x01) */ +#define USB_DSTS_SOFFN_Pos (8UL) /*!< USB DSTS: SOFFN (Bit 8) */ +#define USB_DSTS_SOFFN_Msk (0x3fff00UL) /*!< USB DSTS: SOFFN (Bitfield-Mask: 0x3fff) */ + +/* --------------------------------- USB_DIEPMSK -------------------------------- */ +#define USB_DIEPMSK_XferComplMsk_Pos (0UL) /*!< USB DIEPMSK: XferComplMsk (Bit 0) */ +#define USB_DIEPMSK_XferComplMsk_Msk (0x1UL) /*!< USB DIEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_EPDisbldMsk_Pos (1UL) /*!< USB DIEPMSK: EPDisbldMsk (Bit 1) */ +#define USB_DIEPMSK_EPDisbldMsk_Msk (0x2UL) /*!< USB DIEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_AHBErrMsk_Pos (2UL) /*!< USB DIEPMSK: AHBErrMsk (Bit 2) */ +#define USB_DIEPMSK_AHBErrMsk_Msk (0x4UL) /*!< USB DIEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_TimeOUTMsk_Pos (3UL) /*!< USB DIEPMSK: TimeOUTMsk (Bit 3) */ +#define USB_DIEPMSK_TimeOUTMsk_Msk (0x8UL) /*!< USB DIEPMSK: TimeOUTMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_INTknTXFEmpMsk_Pos (4UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bit 4) */ +#define USB_DIEPMSK_INTknTXFEmpMsk_Msk (0x10UL) /*!< USB DIEPMSK: INTknTXFEmpMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_INEPNakEffMsk_Pos (6UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bit 6) */ +#define USB_DIEPMSK_INEPNakEffMsk_Msk (0x40UL) /*!< USB DIEPMSK: INEPNakEffMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_TxfifoUndrnMsk_Pos (8UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bit 8) */ +#define USB_DIEPMSK_TxfifoUndrnMsk_Msk (0x100UL) /*!< USB DIEPMSK: TxfifoUndrnMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_BNAInIntrMsk_Pos (9UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bit 9) */ +#define USB_DIEPMSK_BNAInIntrMsk_Msk (0x200UL) /*!< USB DIEPMSK: BNAInIntrMsk (Bitfield-Mask: 0x01) */ +#define USB_DIEPMSK_NAKMsk_Pos (13UL) /*!< USB DIEPMSK: NAKMsk (Bit 13) */ +#define USB_DIEPMSK_NAKMsk_Msk (0x2000UL) /*!< USB DIEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USB_DOEPMSK -------------------------------- */ +#define USB_DOEPMSK_XferComplMsk_Pos (0UL) /*!< USB DOEPMSK: XferComplMsk (Bit 0) */ +#define USB_DOEPMSK_XferComplMsk_Msk (0x1UL) /*!< USB DOEPMSK: XferComplMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_EPDisbldMsk_Pos (1UL) /*!< USB DOEPMSK: EPDisbldMsk (Bit 1) */ +#define USB_DOEPMSK_EPDisbldMsk_Msk (0x2UL) /*!< USB DOEPMSK: EPDisbldMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_AHBErrMsk_Pos (2UL) /*!< USB DOEPMSK: AHBErrMsk (Bit 2) */ +#define USB_DOEPMSK_AHBErrMsk_Msk (0x4UL) /*!< USB DOEPMSK: AHBErrMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_SetUPMsk_Pos (3UL) /*!< USB DOEPMSK: SetUPMsk (Bit 3) */ +#define USB_DOEPMSK_SetUPMsk_Msk (0x8UL) /*!< USB DOEPMSK: SetUPMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_OUTTknEPdisMsk_Pos (4UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bit 4) */ +#define USB_DOEPMSK_OUTTknEPdisMsk_Msk (0x10UL) /*!< USB DOEPMSK: OUTTknEPdisMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_Back2BackSETup_Pos (6UL) /*!< USB DOEPMSK: Back2BackSETup (Bit 6) */ +#define USB_DOEPMSK_Back2BackSETup_Msk (0x40UL) /*!< USB DOEPMSK: Back2BackSETup (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_OutPktErrMsk_Pos (8UL) /*!< USB DOEPMSK: OutPktErrMsk (Bit 8) */ +#define USB_DOEPMSK_OutPktErrMsk_Msk (0x100UL) /*!< USB DOEPMSK: OutPktErrMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_BnaOutIntrMsk_Pos (9UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bit 9) */ +#define USB_DOEPMSK_BnaOutIntrMsk_Msk (0x200UL) /*!< USB DOEPMSK: BnaOutIntrMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_BbleErrMsk_Pos (12UL) /*!< USB DOEPMSK: BbleErrMsk (Bit 12) */ +#define USB_DOEPMSK_BbleErrMsk_Msk (0x1000UL) /*!< USB DOEPMSK: BbleErrMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_NAKMsk_Pos (13UL) /*!< USB DOEPMSK: NAKMsk (Bit 13) */ +#define USB_DOEPMSK_NAKMsk_Msk (0x2000UL) /*!< USB DOEPMSK: NAKMsk (Bitfield-Mask: 0x01) */ +#define USB_DOEPMSK_NYETMsk_Pos (14UL) /*!< USB DOEPMSK: NYETMsk (Bit 14) */ +#define USB_DOEPMSK_NYETMsk_Msk (0x4000UL) /*!< USB DOEPMSK: NYETMsk (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- USB_DAINT --------------------------------- */ +#define USB_DAINT_InEpInt_Pos (0UL) /*!< USB DAINT: InEpInt (Bit 0) */ +#define USB_DAINT_InEpInt_Msk (0xffffUL) /*!< USB DAINT: InEpInt (Bitfield-Mask: 0xffff) */ +#define USB_DAINT_OutEPInt_Pos (16UL) /*!< USB DAINT: OutEPInt (Bit 16) */ +#define USB_DAINT_OutEPInt_Msk (0xffff0000UL) /*!< USB DAINT: OutEPInt (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DAINTMSK -------------------------------- */ +#define USB_DAINTMSK_InEpMsk_Pos (0UL) /*!< USB DAINTMSK: InEpMsk (Bit 0) */ +#define USB_DAINTMSK_InEpMsk_Msk (0xffffUL) /*!< USB DAINTMSK: InEpMsk (Bitfield-Mask: 0xffff) */ +#define USB_DAINTMSK_OutEpMsk_Pos (16UL) /*!< USB DAINTMSK: OutEpMsk (Bit 16) */ +#define USB_DAINTMSK_OutEpMsk_Msk (0xffff0000UL) /*!< USB DAINTMSK: OutEpMsk (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USB_DVBUSDIS -------------------------------- */ +#define USB_DVBUSDIS_DVBUSDis_Pos (0UL) /*!< USB DVBUSDIS: DVBUSDis (Bit 0) */ +#define USB_DVBUSDIS_DVBUSDis_Msk (0xffffUL) /*!< USB DVBUSDIS: DVBUSDis (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- USB_DVBUSPULSE ------------------------------- */ +#define USB_DVBUSPULSE_DVBUSPulse_Pos (0UL) /*!< USB DVBUSPULSE: DVBUSPulse (Bit 0) */ +#define USB_DVBUSPULSE_DVBUSPulse_Msk (0xfffUL) /*!< USB DVBUSPULSE: DVBUSPulse (Bitfield-Mask: 0xfff) */ + +/* ------------------------------- USB_DIEPEMPMSK ------------------------------- */ +#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos (0UL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bit 0) */ +#define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk (0xffffUL) /*!< USB DIEPEMPMSK: InEpTxfEmpMsk (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- USB_PCGCCTL -------------------------------- */ +#define USB_PCGCCTL_StopPclk_Pos (0UL) /*!< USB PCGCCTL: StopPclk (Bit 0) */ +#define USB_PCGCCTL_StopPclk_Msk (0x1UL) /*!< USB PCGCCTL: StopPclk (Bitfield-Mask: 0x01) */ +#define USB_PCGCCTL_GateHclk_Pos (1UL) /*!< USB PCGCCTL: GateHclk (Bit 1) */ +#define USB_PCGCCTL_GateHclk_Msk (0x2UL) /*!< USB PCGCCTL: GateHclk (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'USB0_EP0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------ USB_EP_DIEPCTL0 ----------------------------- */ +#define USB_EP_DIEPCTL0_MPS_Pos (0UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bit 0) */ +#define USB_EP_DIEPCTL0_MPS_Msk (0x3UL) /*!< USB0_EP0 DIEPCTL0: MPS (Bitfield-Mask: 0x03) */ +#define USB_EP_DIEPCTL0_USBActEP_Pos (15UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bit 15) */ +#define USB_EP_DIEPCTL0_USBActEP_Msk (0x8000UL) /*!< USB0_EP0 DIEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL0_NAKSts_Pos (17UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bit 17) */ +#define USB_EP_DIEPCTL0_NAKSts_Msk (0x20000UL) /*!< USB0_EP0 DIEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL0_EPType_Pos (18UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bit 18) */ +#define USB_EP_DIEPCTL0_EPType_Msk (0xc0000UL) /*!< USB0_EP0 DIEPCTL0: EPType (Bitfield-Mask: 0x03) */ +#define USB_EP_DIEPCTL0_Stall_Pos (21UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bit 21) */ +#define USB_EP_DIEPCTL0_Stall_Msk (0x200000UL) /*!< USB0_EP0 DIEPCTL0: Stall (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL0_TxFNum_Pos (22UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bit 22) */ +#define USB_EP_DIEPCTL0_TxFNum_Msk (0x3c00000UL) /*!< USB0_EP0 DIEPCTL0: TxFNum (Bitfield-Mask: 0x0f) */ +#define USB_EP_DIEPCTL0_CNAK_Pos (26UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bit 26) */ +#define USB_EP_DIEPCTL0_CNAK_Msk (0x4000000UL) /*!< USB0_EP0 DIEPCTL0: CNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL0_SNAK_Pos (27UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bit 27) */ +#define USB_EP_DIEPCTL0_SNAK_Msk (0x8000000UL) /*!< USB0_EP0 DIEPCTL0: SNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL0_EPDis_Pos (30UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bit 30) */ +#define USB_EP_DIEPCTL0_EPDis_Msk (0x40000000UL) /*!< USB0_EP0 DIEPCTL0: EPDis (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL0_EPEna_Pos (31UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bit 31) */ +#define USB_EP_DIEPCTL0_EPEna_Msk (0x80000000UL) /*!< USB0_EP0 DIEPCTL0: EPEna (Bitfield-Mask: 0x01) */ + +/* ------------------------------ USB_EP_DIEPINT0 ----------------------------- */ +#define USB_EP_DIEPINT0_XferCompl_Pos (0UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bit 0) */ +#define USB_EP_DIEPINT0_XferCompl_Msk (0x1UL) /*!< USB0_EP0 DIEPINT0: XferCompl (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT0_EPDisbld_Pos (1UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bit 1) */ +#define USB_EP_DIEPINT0_EPDisbld_Msk (0x2UL) /*!< USB0_EP0 DIEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT0_AHBErr_Pos (2UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bit 2) */ +#define USB_EP_DIEPINT0_AHBErr_Msk (0x4UL) /*!< USB0_EP0 DIEPINT0: AHBErr (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT0_TimeOUT_Pos (3UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bit 3) */ +#define USB_EP_DIEPINT0_TimeOUT_Msk (0x8UL) /*!< USB0_EP0 DIEPINT0: TimeOUT (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT0_INTknTXFEmp_Pos (4UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bit 4) */ +#define USB_EP_DIEPINT0_INTknTXFEmp_Msk (0x10UL) /*!< USB0_EP0 DIEPINT0: INTknTXFEmp (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT0_INEPNakEff_Pos (6UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bit 6) */ +#define USB_EP_DIEPINT0_INEPNakEff_Msk (0x40UL) /*!< USB0_EP0 DIEPINT0: INEPNakEff (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT0_TxFEmp_Pos (7UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bit 7) */ +#define USB_EP_DIEPINT0_TxFEmp_Msk (0x80UL) /*!< USB0_EP0 DIEPINT0: TxFEmp (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT0_BNAIntr_Pos (9UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bit 9) */ +#define USB_EP_DIEPINT0_BNAIntr_Msk (0x200UL) /*!< USB0_EP0 DIEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USB_EP_DIEPTSIZ0 ----------------------------- */ +#define USB_EP_DIEPTSIZ0_XferSize_Pos (0UL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bit 0) */ +#define USB_EP_DIEPTSIZ0_XferSize_Msk (0x7fUL) /*!< USB0_EP0 DIEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ +#define USB_EP_DIEPTSIZ0_PktCnt_Pos (19UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bit 19) */ +#define USB_EP_DIEPTSIZ0_PktCnt_Msk (0x180000UL) /*!< USB0_EP0 DIEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ + +/* ------------------------------ USB_EP_DIEPDMA0 ----------------------------- */ +#define USB_EP_DIEPDMA0_DMAAddr_Pos (0UL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bit 0) */ +#define USB_EP_DIEPDMA0_DMAAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DIEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------ USB_EP_DTXFSTS0 ----------------------------- */ +#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos (0UL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bit 0) */ +#define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0xffffUL) /*!< USB0_EP0 DTXFSTS0: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ + +/* ----------------------------- USB_EP_DIEPDMAB0 ----------------------------- */ +#define USB_EP_DIEPDMAB0_DMABufferAddr_Pos (0UL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bit 0) */ +#define USB_EP_DIEPDMAB0_DMABufferAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DIEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------ USB_EP_DOEPCTL0 ----------------------------- */ +#define USB_EP_DOEPCTL0_MPS_Pos (0UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bit 0) */ +#define USB_EP_DOEPCTL0_MPS_Msk (0x3UL) /*!< USB0_EP0 DOEPCTL0: MPS (Bitfield-Mask: 0x03) */ +#define USB_EP_DOEPCTL0_USBActEP_Pos (15UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bit 15) */ +#define USB_EP_DOEPCTL0_USBActEP_Msk (0x8000UL) /*!< USB0_EP0 DOEPCTL0: USBActEP (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL0_NAKSts_Pos (17UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bit 17) */ +#define USB_EP_DOEPCTL0_NAKSts_Msk (0x20000UL) /*!< USB0_EP0 DOEPCTL0: NAKSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL0_EPType_Pos (18UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bit 18) */ +#define USB_EP_DOEPCTL0_EPType_Msk (0xc0000UL) /*!< USB0_EP0 DOEPCTL0: EPType (Bitfield-Mask: 0x03) */ +#define USB_EP_DOEPCTL0_Snp_Pos (20UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bit 20) */ +#define USB_EP_DOEPCTL0_Snp_Msk (0x100000UL) /*!< USB0_EP0 DOEPCTL0: Snp (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL0_Stall_Pos (21UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bit 21) */ +#define USB_EP_DOEPCTL0_Stall_Msk (0x200000UL) /*!< USB0_EP0 DOEPCTL0: Stall (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL0_CNAK_Pos (26UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bit 26) */ +#define USB_EP_DOEPCTL0_CNAK_Msk (0x4000000UL) /*!< USB0_EP0 DOEPCTL0: CNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL0_SNAK_Pos (27UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bit 27) */ +#define USB_EP_DOEPCTL0_SNAK_Msk (0x8000000UL) /*!< USB0_EP0 DOEPCTL0: SNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL0_EPDis_Pos (30UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bit 30) */ +#define USB_EP_DOEPCTL0_EPDis_Msk (0x40000000UL) /*!< USB0_EP0 DOEPCTL0: EPDis (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL0_EPEna_Pos (31UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bit 31) */ +#define USB_EP_DOEPCTL0_EPEna_Msk (0x80000000UL) /*!< USB0_EP0 DOEPCTL0: EPEna (Bitfield-Mask: 0x01) */ + +/* ------------------------------ USB_EP_DOEPINT0 ----------------------------- */ +#define USB_EP_DOEPINT0_XferCompl_Pos (0UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bit 0) */ +#define USB_EP_DOEPINT0_XferCompl_Msk (0x1UL) /*!< USB0_EP0 DOEPINT0: XferCompl (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_EPDisbld_Pos (1UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bit 1) */ +#define USB_EP_DOEPINT0_EPDisbld_Msk (0x2UL) /*!< USB0_EP0 DOEPINT0: EPDisbld (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_AHBErr_Pos (2UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bit 2) */ +#define USB_EP_DOEPINT0_AHBErr_Msk (0x4UL) /*!< USB0_EP0 DOEPINT0: AHBErr (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_SetUp_Pos (3UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bit 3) */ +#define USB_EP_DOEPINT0_SetUp_Msk (0x8UL) /*!< USB0_EP0 DOEPINT0: SetUp (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_OUTTknEPdis_Pos (4UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bit 4) */ +#define USB_EP_DOEPINT0_OUTTknEPdis_Msk (0x10UL) /*!< USB0_EP0 DOEPINT0: OUTTknEPdis (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_StsPhseRcvd_Pos (5UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bit 5) */ +#define USB_EP_DOEPINT0_StsPhseRcvd_Msk (0x20UL) /*!< USB0_EP0 DOEPINT0: StsPhseRcvd (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_Back2BackSETup_Pos (6UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bit 6) */ +#define USB_EP_DOEPINT0_Back2BackSETup_Msk (0x40UL) /*!< USB0_EP0 DOEPINT0: Back2BackSETup (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_BNAIntr_Pos (9UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bit 9) */ +#define USB_EP_DOEPINT0_BNAIntr_Msk (0x200UL) /*!< USB0_EP0 DOEPINT0: BNAIntr (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_PktDrpSts_Pos (11UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bit 11) */ +#define USB_EP_DOEPINT0_PktDrpSts_Msk (0x800UL) /*!< USB0_EP0 DOEPINT0: PktDrpSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_BbleErrIntrpt_Pos (12UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bit 12) */ +#define USB_EP_DOEPINT0_BbleErrIntrpt_Msk (0x1000UL) /*!< USB0_EP0 DOEPINT0: BbleErrIntrpt (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_NAKIntrpt_Pos (13UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bit 13) */ +#define USB_EP_DOEPINT0_NAKIntrpt_Msk (0x2000UL) /*!< USB0_EP0 DOEPINT0: NAKIntrpt (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT0_NYETIntrpt_Pos (14UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bit 14) */ +#define USB_EP_DOEPINT0_NYETIntrpt_Msk (0x4000UL) /*!< USB0_EP0 DOEPINT0: NYETIntrpt (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USB_EP_DOEPTSIZ0 ----------------------------- */ +#define USB_EP_DOEPTSIZ0_XferSize_Pos (0UL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bit 0) */ +#define USB_EP_DOEPTSIZ0_XferSize_Msk (0x7fUL) /*!< USB0_EP0 DOEPTSIZ0: XferSize (Bitfield-Mask: 0x7f) */ +#define USB_EP_DOEPTSIZ0_PktCnt_Pos (19UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bit 19) */ +#define USB_EP_DOEPTSIZ0_PktCnt_Msk (0x180000UL) /*!< USB0_EP0 DOEPTSIZ0: PktCnt (Bitfield-Mask: 0x03) */ +#define USB_EP_DOEPTSIZ0_SUPCnt_Pos (29UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bit 29) */ +#define USB_EP_DOEPTSIZ0_SUPCnt_Msk (0x60000000UL) /*!< USB0_EP0 DOEPTSIZ0: SUPCnt (Bitfield-Mask: 0x03) */ + +/* ------------------------------ USB_EP_DOEPDMA0 ----------------------------- */ +#define USB_EP_DOEPDMA0_DMAAddr_Pos (0UL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bit 0) */ +#define USB_EP_DOEPDMA0_DMAAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DOEPDMA0: DMAAddr (Bitfield-Mask: 0xffffffff) */ + +/* ----------------------------- USB_EP_DOEPDMAB0 ----------------------------- */ +#define USB_EP_DOEPDMAB0_DMABufferAddr_Pos (0UL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bit 0) */ +#define USB_EP_DOEPDMAB0_DMABufferAddr_Msk (0xffffffffUL) /*!< USB0_EP0 DOEPDMAB0: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ + + +/* ================================================================================ */ +/* ================ Group 'USB_EP' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------- USB_EP_DIEPCTL_ISOCONT --------------------------- */ +#define USB_EP_DIEPCTL_ISOCONT_MPS_Pos (0UL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bit 0) */ +#define USB_EP_DIEPCTL_ISOCONT_MPS_Msk (0x7ffUL) /*!< USB_EP DIEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ +#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos (15UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bit 15) */ +#define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk (0x8000UL) /*!< USB_EP DIEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos (16UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bit 16) */ +#define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL) /*!< USB_EP DIEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos (17UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bit 17) */ +#define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk (0x20000UL) /*!< USB_EP DIEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_EPType_Pos (18UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bit 18) */ +#define USB_EP_DIEPCTL_ISOCONT_EPType_Msk (0xc0000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ +#define USB_EP_DIEPCTL_ISOCONT_Snp_Pos (20UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bit 20) */ +#define USB_EP_DIEPCTL_ISOCONT_Snp_Msk (0x100000UL) /*!< USB_EP DIEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_Stall_Pos (21UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bit 21) */ +#define USB_EP_DIEPCTL_ISOCONT_Stall_Msk (0x200000UL) /*!< USB_EP DIEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos (22UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bit 22) */ +#define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DIEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ +#define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos (26UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bit 26) */ +#define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk (0x4000000UL) /*!< USB_EP DIEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos (27UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bit 27) */ +#define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk (0x8000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos (28UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bit 28) */ +#define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos (29UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bit 29) */ +#define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL) /*!< USB_EP DIEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos (30UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bit 30) */ +#define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk (0x40000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos (31UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bit 31) */ +#define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk (0x80000000UL) /*!< USB_EP DIEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ + +/* --------------------------- USB_EP_DIEPCTL_INTBULK --------------------------- */ +#define USB_EP_DIEPCTL_INTBULK_MPS_Pos (0UL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bit 0) */ +#define USB_EP_DIEPCTL_INTBULK_MPS_Msk (0x7ffUL) /*!< USB_EP DIEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ +#define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos (15UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bit 15) */ +#define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk (0x8000UL) /*!< USB_EP DIEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_DPID_Pos (16UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bit 16) */ +#define USB_EP_DIEPCTL_INTBULK_DPID_Msk (0x10000UL) /*!< USB_EP DIEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos (17UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bit 17) */ +#define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk (0x20000UL) /*!< USB_EP DIEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_EPType_Pos (18UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bit 18) */ +#define USB_EP_DIEPCTL_INTBULK_EPType_Msk (0xc0000UL) /*!< USB_EP DIEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ +#define USB_EP_DIEPCTL_INTBULK_Snp_Pos (20UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bit 20) */ +#define USB_EP_DIEPCTL_INTBULK_Snp_Msk (0x100000UL) /*!< USB_EP DIEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_Stall_Pos (21UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bit 21) */ +#define USB_EP_DIEPCTL_INTBULK_Stall_Msk (0x200000UL) /*!< USB_EP DIEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos (22UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bit 22) */ +#define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DIEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ +#define USB_EP_DIEPCTL_INTBULK_CNAK_Pos (26UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bit 26) */ +#define USB_EP_DIEPCTL_INTBULK_CNAK_Msk (0x4000000UL) /*!< USB_EP DIEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_SNAK_Pos (27UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bit 27) */ +#define USB_EP_DIEPCTL_INTBULK_SNAK_Msk (0x8000000UL) /*!< USB_EP DIEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos (28UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bit 28) */ +#define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos (29UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bit 29) */ +#define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL) /*!< USB_EP DIEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_EPDis_Pos (30UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bit 30) */ +#define USB_EP_DIEPCTL_INTBULK_EPDis_Msk (0x40000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPCTL_INTBULK_EPEna_Pos (31UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bit 31) */ +#define USB_EP_DIEPCTL_INTBULK_EPEna_Msk (0x80000000UL) /*!< USB_EP DIEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ + +/* ------------------------------- USB_EP_DIEPINT ------------------------------- */ +#define USB_EP_DIEPINT_XferCompl_Pos (0UL) /*!< USB_EP DIEPINT: XferCompl (Bit 0) */ +#define USB_EP_DIEPINT_XferCompl_Msk (0x1UL) /*!< USB_EP DIEPINT: XferCompl (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT_EPDisbld_Pos (1UL) /*!< USB_EP DIEPINT: EPDisbld (Bit 1) */ +#define USB_EP_DIEPINT_EPDisbld_Msk (0x2UL) /*!< USB_EP DIEPINT: EPDisbld (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT_AHBErr_Pos (2UL) /*!< USB_EP DIEPINT: AHBErr (Bit 2) */ +#define USB_EP_DIEPINT_AHBErr_Msk (0x4UL) /*!< USB_EP DIEPINT: AHBErr (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT_TimeOUT_Pos (3UL) /*!< USB_EP DIEPINT: TimeOUT (Bit 3) */ +#define USB_EP_DIEPINT_TimeOUT_Msk (0x8UL) /*!< USB_EP DIEPINT: TimeOUT (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT_INTknTXFEmp_Pos (4UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bit 4) */ +#define USB_EP_DIEPINT_INTknTXFEmp_Msk (0x10UL) /*!< USB_EP DIEPINT: INTknTXFEmp (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT_INEPNakEff_Pos (6UL) /*!< USB_EP DIEPINT: INEPNakEff (Bit 6) */ +#define USB_EP_DIEPINT_INEPNakEff_Msk (0x40UL) /*!< USB_EP DIEPINT: INEPNakEff (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT_TxFEmp_Pos (7UL) /*!< USB_EP DIEPINT: TxFEmp (Bit 7) */ +#define USB_EP_DIEPINT_TxFEmp_Msk (0x80UL) /*!< USB_EP DIEPINT: TxFEmp (Bitfield-Mask: 0x01) */ +#define USB_EP_DIEPINT_BNAIntr_Pos (9UL) /*!< USB_EP DIEPINT: BNAIntr (Bit 9) */ +#define USB_EP_DIEPINT_BNAIntr_Msk (0x200UL) /*!< USB_EP DIEPINT: BNAIntr (Bitfield-Mask: 0x01) */ + +/* ------------------------------- USB_EP_DIEPTSIZ ------------------------------ */ +#define USB_EP_DIEPTSIZ_XferSize_Pos (0UL) /*!< USB_EP DIEPTSIZ: XferSize (Bit 0) */ +#define USB_EP_DIEPTSIZ_XferSize_Msk (0x7ffffUL) /*!< USB_EP DIEPTSIZ: XferSize (Bitfield-Mask: 0x7ffff) */ +#define USB_EP_DIEPTSIZ_PktCnt_Pos (19UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bit 19) */ +#define USB_EP_DIEPTSIZ_PktCnt_Msk (0x1ff80000UL) /*!< USB_EP DIEPTSIZ: PktCnt (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------- USB_EP_DIEPDMA ------------------------------- */ +#define USB_EP_DIEPDMA_DMAAddr_Pos (0UL) /*!< USB_EP DIEPDMA: DMAAddr (Bit 0) */ +#define USB_EP_DIEPDMA_DMAAddr_Msk (0xffffffffUL) /*!< USB_EP DIEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- USB_EP_DTXFSTS ------------------------------- */ +#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos (0UL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bit 0) */ +#define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk (0xffffUL) /*!< USB_EP DTXFSTS: INEPTxFSpcAvail (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- USB_EP_DIEPDMAB ------------------------------ */ +#define USB_EP_DIEPDMAB_DMABufferAddr_Pos (0UL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bit 0) */ +#define USB_EP_DIEPDMAB_DMABufferAddr_Msk (0xffffffffUL) /*!< USB_EP DIEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------- USB_EP_DOEPCTL_ISOCONT --------------------------- */ +#define USB_EP_DOEPCTL_ISOCONT_MPS_Pos (0UL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bit 0) */ +#define USB_EP_DOEPCTL_ISOCONT_MPS_Msk (0x7ffUL) /*!< USB_EP DOEPCTL_ISOCONT: MPS (Bitfield-Mask: 0x7ff) */ +#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos (15UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bit 15) */ +#define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk (0x8000UL) /*!< USB_EP DOEPCTL_ISOCONT: USBActEP (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos (16UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bit 16) */ +#define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL) /*!< USB_EP DOEPCTL_ISOCONT: EO_FrNum (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos (17UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bit 17) */ +#define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk (0x20000UL) /*!< USB_EP DOEPCTL_ISOCONT: NAKSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_EPType_Pos (18UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bit 18) */ +#define USB_EP_DOEPCTL_ISOCONT_EPType_Msk (0xc0000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPType (Bitfield-Mask: 0x03) */ +#define USB_EP_DOEPCTL_ISOCONT_Snp_Pos (20UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bit 20) */ +#define USB_EP_DOEPCTL_ISOCONT_Snp_Msk (0x100000UL) /*!< USB_EP DOEPCTL_ISOCONT: Snp (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_Stall_Pos (21UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bit 21) */ +#define USB_EP_DOEPCTL_ISOCONT_Stall_Msk (0x200000UL) /*!< USB_EP DOEPCTL_ISOCONT: Stall (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos (22UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bit 22) */ +#define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DOEPCTL_ISOCONT: TxFNum (Bitfield-Mask: 0x0f) */ +#define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos (26UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bit 26) */ +#define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk (0x4000000UL) /*!< USB_EP DOEPCTL_ISOCONT: CNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos (27UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bit 27) */ +#define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk (0x8000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos (28UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bit 28) */ +#define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetEvenFr (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos (29UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bit 29) */ +#define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL) /*!< USB_EP DOEPCTL_ISOCONT: SetOddFr (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos (30UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bit 30) */ +#define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk (0x40000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPDis (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos (31UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bit 31) */ +#define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk (0x80000000UL) /*!< USB_EP DOEPCTL_ISOCONT: EPEna (Bitfield-Mask: 0x01) */ + +/* --------------------------- USB_EP_DOEPCTL_INTBULK --------------------------- */ +#define USB_EP_DOEPCTL_INTBULK_MPS_Pos (0UL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bit 0) */ +#define USB_EP_DOEPCTL_INTBULK_MPS_Msk (0x7ffUL) /*!< USB_EP DOEPCTL_INTBULK: MPS (Bitfield-Mask: 0x7ff) */ +#define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos (15UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bit 15) */ +#define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk (0x8000UL) /*!< USB_EP DOEPCTL_INTBULK: USBActEP (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_DPID_Pos (16UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bit 16) */ +#define USB_EP_DOEPCTL_INTBULK_DPID_Msk (0x10000UL) /*!< USB_EP DOEPCTL_INTBULK: DPID (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos (17UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bit 17) */ +#define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk (0x20000UL) /*!< USB_EP DOEPCTL_INTBULK: NAKSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_EPType_Pos (18UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bit 18) */ +#define USB_EP_DOEPCTL_INTBULK_EPType_Msk (0xc0000UL) /*!< USB_EP DOEPCTL_INTBULK: EPType (Bitfield-Mask: 0x03) */ +#define USB_EP_DOEPCTL_INTBULK_Snp_Pos (20UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bit 20) */ +#define USB_EP_DOEPCTL_INTBULK_Snp_Msk (0x100000UL) /*!< USB_EP DOEPCTL_INTBULK: Snp (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_Stall_Pos (21UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bit 21) */ +#define USB_EP_DOEPCTL_INTBULK_Stall_Msk (0x200000UL) /*!< USB_EP DOEPCTL_INTBULK: Stall (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos (22UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bit 22) */ +#define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL) /*!< USB_EP DOEPCTL_INTBULK: TxFNum (Bitfield-Mask: 0x0f) */ +#define USB_EP_DOEPCTL_INTBULK_CNAK_Pos (26UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bit 26) */ +#define USB_EP_DOEPCTL_INTBULK_CNAK_Msk (0x4000000UL) /*!< USB_EP DOEPCTL_INTBULK: CNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_SNAK_Pos (27UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bit 27) */ +#define USB_EP_DOEPCTL_INTBULK_SNAK_Msk (0x8000000UL) /*!< USB_EP DOEPCTL_INTBULK: SNAK (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos (28UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bit 28) */ +#define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD0PID (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos (29UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bit 29) */ +#define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL) /*!< USB_EP DOEPCTL_INTBULK: SetD1PID (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_EPDis_Pos (30UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bit 30) */ +#define USB_EP_DOEPCTL_INTBULK_EPDis_Msk (0x40000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPDis (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPCTL_INTBULK_EPEna_Pos (31UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bit 31) */ +#define USB_EP_DOEPCTL_INTBULK_EPEna_Msk (0x80000000UL) /*!< USB_EP DOEPCTL_INTBULK: EPEna (Bitfield-Mask: 0x01) */ + +/* ------------------------------- USB_EP_DOEPINT ------------------------------- */ +#define USB_EP_DOEPINT_XferCompl_Pos (0UL) /*!< USB_EP DOEPINT: XferCompl (Bit 0) */ +#define USB_EP_DOEPINT_XferCompl_Msk (0x1UL) /*!< USB_EP DOEPINT: XferCompl (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_EPDisbld_Pos (1UL) /*!< USB_EP DOEPINT: EPDisbld (Bit 1) */ +#define USB_EP_DOEPINT_EPDisbld_Msk (0x2UL) /*!< USB_EP DOEPINT: EPDisbld (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_AHBErr_Pos (2UL) /*!< USB_EP DOEPINT: AHBErr (Bit 2) */ +#define USB_EP_DOEPINT_AHBErr_Msk (0x4UL) /*!< USB_EP DOEPINT: AHBErr (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_SetUp_Pos (3UL) /*!< USB_EP DOEPINT: SetUp (Bit 3) */ +#define USB_EP_DOEPINT_SetUp_Msk (0x8UL) /*!< USB_EP DOEPINT: SetUp (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_OUTTknEPdis_Pos (4UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bit 4) */ +#define USB_EP_DOEPINT_OUTTknEPdis_Msk (0x10UL) /*!< USB_EP DOEPINT: OUTTknEPdis (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_StsPhseRcvd_Pos (5UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bit 5) */ +#define USB_EP_DOEPINT_StsPhseRcvd_Msk (0x20UL) /*!< USB_EP DOEPINT: StsPhseRcvd (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_Back2BackSETup_Pos (6UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bit 6) */ +#define USB_EP_DOEPINT_Back2BackSETup_Msk (0x40UL) /*!< USB_EP DOEPINT: Back2BackSETup (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_BNAIntr_Pos (9UL) /*!< USB_EP DOEPINT: BNAIntr (Bit 9) */ +#define USB_EP_DOEPINT_BNAIntr_Msk (0x200UL) /*!< USB_EP DOEPINT: BNAIntr (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_PktDrpSts_Pos (11UL) /*!< USB_EP DOEPINT: PktDrpSts (Bit 11) */ +#define USB_EP_DOEPINT_PktDrpSts_Msk (0x800UL) /*!< USB_EP DOEPINT: PktDrpSts (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_BbleErrIntrpt_Pos (12UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bit 12) */ +#define USB_EP_DOEPINT_BbleErrIntrpt_Msk (0x1000UL) /*!< USB_EP DOEPINT: BbleErrIntrpt (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_NAKIntrpt_Pos (13UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bit 13) */ +#define USB_EP_DOEPINT_NAKIntrpt_Msk (0x2000UL) /*!< USB_EP DOEPINT: NAKIntrpt (Bitfield-Mask: 0x01) */ +#define USB_EP_DOEPINT_NYETIntrpt_Pos (14UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bit 14) */ +#define USB_EP_DOEPINT_NYETIntrpt_Msk (0x4000UL) /*!< USB_EP DOEPINT: NYETIntrpt (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USB_EP_DOEPTSIZ_ISO ---------------------------- */ +#define USB_EP_DOEPTSIZ_ISO_XferSize_Pos (0UL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bit 0) */ +#define USB_EP_DOEPTSIZ_ISO_XferSize_Msk (0x7ffffUL) /*!< USB_EP DOEPTSIZ_ISO: XferSize (Bitfield-Mask: 0x7ffff) */ +#define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos (19UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bit 19) */ +#define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_ISO: PktCnt (Bitfield-Mask: 0x3ff) */ +#define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos (29UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bit 29) */ +#define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk (0x60000000UL) /*!< USB_EP DOEPTSIZ_ISO: RxDPID (Bitfield-Mask: 0x03) */ + +/* --------------------------- USB_EP_DOEPTSIZ_CONTROL -------------------------- */ +#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos (0UL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bit 0) */ +#define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk (0x7ffffUL) /*!< USB_EP DOEPTSIZ_CONTROL: XferSize (Bitfield-Mask: 0x7ffff) */ +#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos (19UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bit 19) */ +#define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk (0x1ff80000UL) /*!< USB_EP DOEPTSIZ_CONTROL: PktCnt (Bitfield-Mask: 0x3ff) */ +#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos (29UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bit 29) */ +#define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk (0x60000000UL) /*!< USB_EP DOEPTSIZ_CONTROL: SUPCnt (Bitfield-Mask: 0x03) */ + +/* ------------------------------- USB_EP_DOEPDMA ------------------------------- */ +#define USB_EP_DOEPDMA_DMAAddr_Pos (0UL) /*!< USB_EP DOEPDMA: DMAAddr (Bit 0) */ +#define USB_EP_DOEPDMA_DMAAddr_Msk (0xffffffffUL) /*!< USB_EP DOEPDMA: DMAAddr (Bitfield-Mask: 0xffffffff) */ + +/* ------------------------------- USB_EP_DOEPDMAB ------------------------------ */ +#define USB_EP_DOEPDMAB_DMABufferAddr_Pos (0UL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bit 0) */ +#define USB_EP_DOEPDMAB_DMABufferAddr_Msk (0xffffffffUL) /*!< USB_EP DOEPDMAB: DMABufferAddr (Bitfield-Mask: 0xffffffff) */ + + +/* ================================================================================ */ +/* ================ Group 'USIC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- USIC_ID ---------------------------------- */ +#define USIC_ID_MOD_REV_Pos (0UL) /*!< USIC ID: MOD_REV (Bit 0) */ +#define USIC_ID_MOD_REV_Msk (0xffUL) /*!< USIC ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define USIC_ID_MOD_TYPE_Pos (8UL) /*!< USIC ID: MOD_TYPE (Bit 8) */ +#define USIC_ID_MOD_TYPE_Msk (0xff00UL) /*!< USIC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define USIC_ID_MOD_NUMBER_Pos (16UL) /*!< USIC ID: MOD_NUMBER (Bit 16) */ +#define USIC_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< USIC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ Group 'USIC_CH' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- USIC_CH_CCFG -------------------------------- */ +#define USIC_CH_CCFG_SSC_Pos (0UL) /*!< USIC_CH CCFG: SSC (Bit 0) */ +#define USIC_CH_CCFG_SSC_Msk (0x1UL) /*!< USIC_CH CCFG: SSC (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCFG_ASC_Pos (1UL) /*!< USIC_CH CCFG: ASC (Bit 1) */ +#define USIC_CH_CCFG_ASC_Msk (0x2UL) /*!< USIC_CH CCFG: ASC (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCFG_IIC_Pos (2UL) /*!< USIC_CH CCFG: IIC (Bit 2) */ +#define USIC_CH_CCFG_IIC_Msk (0x4UL) /*!< USIC_CH CCFG: IIC (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCFG_IIS_Pos (3UL) /*!< USIC_CH CCFG: IIS (Bit 3) */ +#define USIC_CH_CCFG_IIS_Msk (0x8UL) /*!< USIC_CH CCFG: IIS (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCFG_RB_Pos (6UL) /*!< USIC_CH CCFG: RB (Bit 6) */ +#define USIC_CH_CCFG_RB_Msk (0x40UL) /*!< USIC_CH CCFG: RB (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCFG_TB_Pos (7UL) /*!< USIC_CH CCFG: TB (Bit 7) */ +#define USIC_CH_CCFG_TB_Msk (0x80UL) /*!< USIC_CH CCFG: TB (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_KSCFG ------------------------------- */ +#define USIC_CH_KSCFG_MODEN_Pos (0UL) /*!< USIC_CH KSCFG: MODEN (Bit 0) */ +#define USIC_CH_KSCFG_MODEN_Msk (0x1UL) /*!< USIC_CH KSCFG: MODEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_KSCFG_BPMODEN_Pos (1UL) /*!< USIC_CH KSCFG: BPMODEN (Bit 1) */ +#define USIC_CH_KSCFG_BPMODEN_Msk (0x2UL) /*!< USIC_CH KSCFG: BPMODEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_KSCFG_NOMCFG_Pos (4UL) /*!< USIC_CH KSCFG: NOMCFG (Bit 4) */ +#define USIC_CH_KSCFG_NOMCFG_Msk (0x30UL) /*!< USIC_CH KSCFG: NOMCFG (Bitfield-Mask: 0x03) */ +#define USIC_CH_KSCFG_BPNOM_Pos (7UL) /*!< USIC_CH KSCFG: BPNOM (Bit 7) */ +#define USIC_CH_KSCFG_BPNOM_Msk (0x80UL) /*!< USIC_CH KSCFG: BPNOM (Bitfield-Mask: 0x01) */ +#define USIC_CH_KSCFG_SUMCFG_Pos (8UL) /*!< USIC_CH KSCFG: SUMCFG (Bit 8) */ +#define USIC_CH_KSCFG_SUMCFG_Msk (0x300UL) /*!< USIC_CH KSCFG: SUMCFG (Bitfield-Mask: 0x03) */ +#define USIC_CH_KSCFG_BPSUM_Pos (11UL) /*!< USIC_CH KSCFG: BPSUM (Bit 11) */ +#define USIC_CH_KSCFG_BPSUM_Msk (0x800UL) /*!< USIC_CH KSCFG: BPSUM (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USIC_CH_FDR -------------------------------- */ +#define USIC_CH_FDR_STEP_Pos (0UL) /*!< USIC_CH FDR: STEP (Bit 0) */ +#define USIC_CH_FDR_STEP_Msk (0x3ffUL) /*!< USIC_CH FDR: STEP (Bitfield-Mask: 0x3ff) */ +#define USIC_CH_FDR_DM_Pos (14UL) /*!< USIC_CH FDR: DM (Bit 14) */ +#define USIC_CH_FDR_DM_Msk (0xc000UL) /*!< USIC_CH FDR: DM (Bitfield-Mask: 0x03) */ +#define USIC_CH_FDR_RESULT_Pos (16UL) /*!< USIC_CH FDR: RESULT (Bit 16) */ +#define USIC_CH_FDR_RESULT_Msk (0x3ff0000UL) /*!< USIC_CH FDR: RESULT (Bitfield-Mask: 0x3ff) */ + +/* --------------------------------- USIC_CH_BRG -------------------------------- */ +#define USIC_CH_BRG_CLKSEL_Pos (0UL) /*!< USIC_CH BRG: CLKSEL (Bit 0) */ +#define USIC_CH_BRG_CLKSEL_Msk (0x3UL) /*!< USIC_CH BRG: CLKSEL (Bitfield-Mask: 0x03) */ +#define USIC_CH_BRG_TMEN_Pos (3UL) /*!< USIC_CH BRG: TMEN (Bit 3) */ +#define USIC_CH_BRG_TMEN_Msk (0x8UL) /*!< USIC_CH BRG: TMEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_BRG_PPPEN_Pos (4UL) /*!< USIC_CH BRG: PPPEN (Bit 4) */ +#define USIC_CH_BRG_PPPEN_Msk (0x10UL) /*!< USIC_CH BRG: PPPEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_BRG_CTQSEL_Pos (6UL) /*!< USIC_CH BRG: CTQSEL (Bit 6) */ +#define USIC_CH_BRG_CTQSEL_Msk (0xc0UL) /*!< USIC_CH BRG: CTQSEL (Bitfield-Mask: 0x03) */ +#define USIC_CH_BRG_PCTQ_Pos (8UL) /*!< USIC_CH BRG: PCTQ (Bit 8) */ +#define USIC_CH_BRG_PCTQ_Msk (0x300UL) /*!< USIC_CH BRG: PCTQ (Bitfield-Mask: 0x03) */ +#define USIC_CH_BRG_DCTQ_Pos (10UL) /*!< USIC_CH BRG: DCTQ (Bit 10) */ +#define USIC_CH_BRG_DCTQ_Msk (0x7c00UL) /*!< USIC_CH BRG: DCTQ (Bitfield-Mask: 0x1f) */ +#define USIC_CH_BRG_PDIV_Pos (16UL) /*!< USIC_CH BRG: PDIV (Bit 16) */ +#define USIC_CH_BRG_PDIV_Msk (0x3ff0000UL) /*!< USIC_CH BRG: PDIV (Bitfield-Mask: 0x3ff) */ +#define USIC_CH_BRG_SCLKOSEL_Pos (28UL) /*!< USIC_CH BRG: SCLKOSEL (Bit 28) */ +#define USIC_CH_BRG_SCLKOSEL_Msk (0x10000000UL) /*!< USIC_CH BRG: SCLKOSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_BRG_MCLKCFG_Pos (29UL) /*!< USIC_CH BRG: MCLKCFG (Bit 29) */ +#define USIC_CH_BRG_MCLKCFG_Msk (0x20000000UL) /*!< USIC_CH BRG: MCLKCFG (Bitfield-Mask: 0x01) */ +#define USIC_CH_BRG_SCLKCFG_Pos (30UL) /*!< USIC_CH BRG: SCLKCFG (Bit 30) */ +#define USIC_CH_BRG_SCLKCFG_Msk (0xc0000000UL) /*!< USIC_CH BRG: SCLKCFG (Bitfield-Mask: 0x03) */ + +/* -------------------------------- USIC_CH_INPR -------------------------------- */ +#define USIC_CH_INPR_TSINP_Pos (0UL) /*!< USIC_CH INPR: TSINP (Bit 0) */ +#define USIC_CH_INPR_TSINP_Msk (0x7UL) /*!< USIC_CH INPR: TSINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_INPR_TBINP_Pos (4UL) /*!< USIC_CH INPR: TBINP (Bit 4) */ +#define USIC_CH_INPR_TBINP_Msk (0x70UL) /*!< USIC_CH INPR: TBINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_INPR_RINP_Pos (8UL) /*!< USIC_CH INPR: RINP (Bit 8) */ +#define USIC_CH_INPR_RINP_Msk (0x700UL) /*!< USIC_CH INPR: RINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_INPR_AINP_Pos (12UL) /*!< USIC_CH INPR: AINP (Bit 12) */ +#define USIC_CH_INPR_AINP_Msk (0x7000UL) /*!< USIC_CH INPR: AINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_INPR_PINP_Pos (16UL) /*!< USIC_CH INPR: PINP (Bit 16) */ +#define USIC_CH_INPR_PINP_Msk (0x70000UL) /*!< USIC_CH INPR: PINP (Bitfield-Mask: 0x07) */ + +/* -------------------------------- USIC_CH_DX0CR ------------------------------- */ +#define USIC_CH_DX0CR_DSEL_Pos (0UL) /*!< USIC_CH DX0CR: DSEL (Bit 0) */ +#define USIC_CH_DX0CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX0CR: DSEL (Bitfield-Mask: 0x07) */ +#define USIC_CH_DX0CR_INSW_Pos (4UL) /*!< USIC_CH DX0CR: INSW (Bit 4) */ +#define USIC_CH_DX0CR_INSW_Msk (0x10UL) /*!< USIC_CH DX0CR: INSW (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX0CR_DFEN_Pos (5UL) /*!< USIC_CH DX0CR: DFEN (Bit 5) */ +#define USIC_CH_DX0CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX0CR: DFEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX0CR_DSEN_Pos (6UL) /*!< USIC_CH DX0CR: DSEN (Bit 6) */ +#define USIC_CH_DX0CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX0CR: DSEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX0CR_DPOL_Pos (8UL) /*!< USIC_CH DX0CR: DPOL (Bit 8) */ +#define USIC_CH_DX0CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX0CR: DPOL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX0CR_SFSEL_Pos (9UL) /*!< USIC_CH DX0CR: SFSEL (Bit 9) */ +#define USIC_CH_DX0CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX0CR: SFSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX0CR_CM_Pos (10UL) /*!< USIC_CH DX0CR: CM (Bit 10) */ +#define USIC_CH_DX0CR_CM_Msk (0xc00UL) /*!< USIC_CH DX0CR: CM (Bitfield-Mask: 0x03) */ +#define USIC_CH_DX0CR_DXS_Pos (15UL) /*!< USIC_CH DX0CR: DXS (Bit 15) */ +#define USIC_CH_DX0CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX0CR: DXS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_DX1CR ------------------------------- */ +#define USIC_CH_DX1CR_DSEL_Pos (0UL) /*!< USIC_CH DX1CR: DSEL (Bit 0) */ +#define USIC_CH_DX1CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX1CR: DSEL (Bitfield-Mask: 0x07) */ +#define USIC_CH_DX1CR_DCEN_Pos (3UL) /*!< USIC_CH DX1CR: DCEN (Bit 3) */ +#define USIC_CH_DX1CR_DCEN_Msk (0x8UL) /*!< USIC_CH DX1CR: DCEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX1CR_INSW_Pos (4UL) /*!< USIC_CH DX1CR: INSW (Bit 4) */ +#define USIC_CH_DX1CR_INSW_Msk (0x10UL) /*!< USIC_CH DX1CR: INSW (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX1CR_DFEN_Pos (5UL) /*!< USIC_CH DX1CR: DFEN (Bit 5) */ +#define USIC_CH_DX1CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX1CR: DFEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX1CR_DSEN_Pos (6UL) /*!< USIC_CH DX1CR: DSEN (Bit 6) */ +#define USIC_CH_DX1CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX1CR: DSEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX1CR_DPOL_Pos (8UL) /*!< USIC_CH DX1CR: DPOL (Bit 8) */ +#define USIC_CH_DX1CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX1CR: DPOL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX1CR_SFSEL_Pos (9UL) /*!< USIC_CH DX1CR: SFSEL (Bit 9) */ +#define USIC_CH_DX1CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX1CR: SFSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX1CR_CM_Pos (10UL) /*!< USIC_CH DX1CR: CM (Bit 10) */ +#define USIC_CH_DX1CR_CM_Msk (0xc00UL) /*!< USIC_CH DX1CR: CM (Bitfield-Mask: 0x03) */ +#define USIC_CH_DX1CR_DXS_Pos (15UL) /*!< USIC_CH DX1CR: DXS (Bit 15) */ +#define USIC_CH_DX1CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX1CR: DXS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_DX2CR ------------------------------- */ +#define USIC_CH_DX2CR_DSEL_Pos (0UL) /*!< USIC_CH DX2CR: DSEL (Bit 0) */ +#define USIC_CH_DX2CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX2CR: DSEL (Bitfield-Mask: 0x07) */ +#define USIC_CH_DX2CR_INSW_Pos (4UL) /*!< USIC_CH DX2CR: INSW (Bit 4) */ +#define USIC_CH_DX2CR_INSW_Msk (0x10UL) /*!< USIC_CH DX2CR: INSW (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX2CR_DFEN_Pos (5UL) /*!< USIC_CH DX2CR: DFEN (Bit 5) */ +#define USIC_CH_DX2CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX2CR: DFEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX2CR_DSEN_Pos (6UL) /*!< USIC_CH DX2CR: DSEN (Bit 6) */ +#define USIC_CH_DX2CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX2CR: DSEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX2CR_DPOL_Pos (8UL) /*!< USIC_CH DX2CR: DPOL (Bit 8) */ +#define USIC_CH_DX2CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX2CR: DPOL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX2CR_SFSEL_Pos (9UL) /*!< USIC_CH DX2CR: SFSEL (Bit 9) */ +#define USIC_CH_DX2CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX2CR: SFSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX2CR_CM_Pos (10UL) /*!< USIC_CH DX2CR: CM (Bit 10) */ +#define USIC_CH_DX2CR_CM_Msk (0xc00UL) /*!< USIC_CH DX2CR: CM (Bitfield-Mask: 0x03) */ +#define USIC_CH_DX2CR_DXS_Pos (15UL) /*!< USIC_CH DX2CR: DXS (Bit 15) */ +#define USIC_CH_DX2CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX2CR: DXS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_DX3CR ------------------------------- */ +#define USIC_CH_DX3CR_DSEL_Pos (0UL) /*!< USIC_CH DX3CR: DSEL (Bit 0) */ +#define USIC_CH_DX3CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX3CR: DSEL (Bitfield-Mask: 0x07) */ +#define USIC_CH_DX3CR_INSW_Pos (4UL) /*!< USIC_CH DX3CR: INSW (Bit 4) */ +#define USIC_CH_DX3CR_INSW_Msk (0x10UL) /*!< USIC_CH DX3CR: INSW (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX3CR_DFEN_Pos (5UL) /*!< USIC_CH DX3CR: DFEN (Bit 5) */ +#define USIC_CH_DX3CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX3CR: DFEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX3CR_DSEN_Pos (6UL) /*!< USIC_CH DX3CR: DSEN (Bit 6) */ +#define USIC_CH_DX3CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX3CR: DSEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX3CR_DPOL_Pos (8UL) /*!< USIC_CH DX3CR: DPOL (Bit 8) */ +#define USIC_CH_DX3CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX3CR: DPOL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX3CR_SFSEL_Pos (9UL) /*!< USIC_CH DX3CR: SFSEL (Bit 9) */ +#define USIC_CH_DX3CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX3CR: SFSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX3CR_CM_Pos (10UL) /*!< USIC_CH DX3CR: CM (Bit 10) */ +#define USIC_CH_DX3CR_CM_Msk (0xc00UL) /*!< USIC_CH DX3CR: CM (Bitfield-Mask: 0x03) */ +#define USIC_CH_DX3CR_DXS_Pos (15UL) /*!< USIC_CH DX3CR: DXS (Bit 15) */ +#define USIC_CH_DX3CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX3CR: DXS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_DX4CR ------------------------------- */ +#define USIC_CH_DX4CR_DSEL_Pos (0UL) /*!< USIC_CH DX4CR: DSEL (Bit 0) */ +#define USIC_CH_DX4CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX4CR: DSEL (Bitfield-Mask: 0x07) */ +#define USIC_CH_DX4CR_INSW_Pos (4UL) /*!< USIC_CH DX4CR: INSW (Bit 4) */ +#define USIC_CH_DX4CR_INSW_Msk (0x10UL) /*!< USIC_CH DX4CR: INSW (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX4CR_DFEN_Pos (5UL) /*!< USIC_CH DX4CR: DFEN (Bit 5) */ +#define USIC_CH_DX4CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX4CR: DFEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX4CR_DSEN_Pos (6UL) /*!< USIC_CH DX4CR: DSEN (Bit 6) */ +#define USIC_CH_DX4CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX4CR: DSEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX4CR_DPOL_Pos (8UL) /*!< USIC_CH DX4CR: DPOL (Bit 8) */ +#define USIC_CH_DX4CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX4CR: DPOL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX4CR_SFSEL_Pos (9UL) /*!< USIC_CH DX4CR: SFSEL (Bit 9) */ +#define USIC_CH_DX4CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX4CR: SFSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX4CR_CM_Pos (10UL) /*!< USIC_CH DX4CR: CM (Bit 10) */ +#define USIC_CH_DX4CR_CM_Msk (0xc00UL) /*!< USIC_CH DX4CR: CM (Bitfield-Mask: 0x03) */ +#define USIC_CH_DX4CR_DXS_Pos (15UL) /*!< USIC_CH DX4CR: DXS (Bit 15) */ +#define USIC_CH_DX4CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX4CR: DXS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_DX5CR ------------------------------- */ +#define USIC_CH_DX5CR_DSEL_Pos (0UL) /*!< USIC_CH DX5CR: DSEL (Bit 0) */ +#define USIC_CH_DX5CR_DSEL_Msk (0x7UL) /*!< USIC_CH DX5CR: DSEL (Bitfield-Mask: 0x07) */ +#define USIC_CH_DX5CR_INSW_Pos (4UL) /*!< USIC_CH DX5CR: INSW (Bit 4) */ +#define USIC_CH_DX5CR_INSW_Msk (0x10UL) /*!< USIC_CH DX5CR: INSW (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX5CR_DFEN_Pos (5UL) /*!< USIC_CH DX5CR: DFEN (Bit 5) */ +#define USIC_CH_DX5CR_DFEN_Msk (0x20UL) /*!< USIC_CH DX5CR: DFEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX5CR_DSEN_Pos (6UL) /*!< USIC_CH DX5CR: DSEN (Bit 6) */ +#define USIC_CH_DX5CR_DSEN_Msk (0x40UL) /*!< USIC_CH DX5CR: DSEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX5CR_DPOL_Pos (8UL) /*!< USIC_CH DX5CR: DPOL (Bit 8) */ +#define USIC_CH_DX5CR_DPOL_Msk (0x100UL) /*!< USIC_CH DX5CR: DPOL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX5CR_SFSEL_Pos (9UL) /*!< USIC_CH DX5CR: SFSEL (Bit 9) */ +#define USIC_CH_DX5CR_SFSEL_Msk (0x200UL) /*!< USIC_CH DX5CR: SFSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_DX5CR_CM_Pos (10UL) /*!< USIC_CH DX5CR: CM (Bit 10) */ +#define USIC_CH_DX5CR_CM_Msk (0xc00UL) /*!< USIC_CH DX5CR: CM (Bitfield-Mask: 0x03) */ +#define USIC_CH_DX5CR_DXS_Pos (15UL) /*!< USIC_CH DX5CR: DXS (Bit 15) */ +#define USIC_CH_DX5CR_DXS_Msk (0x8000UL) /*!< USIC_CH DX5CR: DXS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_SCTR -------------------------------- */ +#define USIC_CH_SCTR_SDIR_Pos (0UL) /*!< USIC_CH SCTR: SDIR (Bit 0) */ +#define USIC_CH_SCTR_SDIR_Msk (0x1UL) /*!< USIC_CH SCTR: SDIR (Bitfield-Mask: 0x01) */ +#define USIC_CH_SCTR_PDL_Pos (1UL) /*!< USIC_CH SCTR: PDL (Bit 1) */ +#define USIC_CH_SCTR_PDL_Msk (0x2UL) /*!< USIC_CH SCTR: PDL (Bitfield-Mask: 0x01) */ +#define USIC_CH_SCTR_DSM_Pos (2UL) /*!< USIC_CH SCTR: DSM (Bit 2) */ +#define USIC_CH_SCTR_DSM_Msk (0xcUL) /*!< USIC_CH SCTR: DSM (Bitfield-Mask: 0x03) */ +#define USIC_CH_SCTR_HPCDIR_Pos (4UL) /*!< USIC_CH SCTR: HPCDIR (Bit 4) */ +#define USIC_CH_SCTR_HPCDIR_Msk (0x10UL) /*!< USIC_CH SCTR: HPCDIR (Bitfield-Mask: 0x01) */ +#define USIC_CH_SCTR_DOCFG_Pos (6UL) /*!< USIC_CH SCTR: DOCFG (Bit 6) */ +#define USIC_CH_SCTR_DOCFG_Msk (0xc0UL) /*!< USIC_CH SCTR: DOCFG (Bitfield-Mask: 0x03) */ +#define USIC_CH_SCTR_TRM_Pos (8UL) /*!< USIC_CH SCTR: TRM (Bit 8) */ +#define USIC_CH_SCTR_TRM_Msk (0x300UL) /*!< USIC_CH SCTR: TRM (Bitfield-Mask: 0x03) */ +#define USIC_CH_SCTR_FLE_Pos (16UL) /*!< USIC_CH SCTR: FLE (Bit 16) */ +#define USIC_CH_SCTR_FLE_Msk (0x3f0000UL) /*!< USIC_CH SCTR: FLE (Bitfield-Mask: 0x3f) */ +#define USIC_CH_SCTR_WLE_Pos (24UL) /*!< USIC_CH SCTR: WLE (Bit 24) */ +#define USIC_CH_SCTR_WLE_Msk (0xf000000UL) /*!< USIC_CH SCTR: WLE (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- USIC_CH_TCSR -------------------------------- */ +#define USIC_CH_TCSR_WLEMD_Pos (0UL) /*!< USIC_CH TCSR: WLEMD (Bit 0) */ +#define USIC_CH_TCSR_WLEMD_Msk (0x1UL) /*!< USIC_CH TCSR: WLEMD (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_SELMD_Pos (1UL) /*!< USIC_CH TCSR: SELMD (Bit 1) */ +#define USIC_CH_TCSR_SELMD_Msk (0x2UL) /*!< USIC_CH TCSR: SELMD (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_FLEMD_Pos (2UL) /*!< USIC_CH TCSR: FLEMD (Bit 2) */ +#define USIC_CH_TCSR_FLEMD_Msk (0x4UL) /*!< USIC_CH TCSR: FLEMD (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_WAMD_Pos (3UL) /*!< USIC_CH TCSR: WAMD (Bit 3) */ +#define USIC_CH_TCSR_WAMD_Msk (0x8UL) /*!< USIC_CH TCSR: WAMD (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_HPCMD_Pos (4UL) /*!< USIC_CH TCSR: HPCMD (Bit 4) */ +#define USIC_CH_TCSR_HPCMD_Msk (0x10UL) /*!< USIC_CH TCSR: HPCMD (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_SOF_Pos (5UL) /*!< USIC_CH TCSR: SOF (Bit 5) */ +#define USIC_CH_TCSR_SOF_Msk (0x20UL) /*!< USIC_CH TCSR: SOF (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_EOF_Pos (6UL) /*!< USIC_CH TCSR: EOF (Bit 6) */ +#define USIC_CH_TCSR_EOF_Msk (0x40UL) /*!< USIC_CH TCSR: EOF (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_TDV_Pos (7UL) /*!< USIC_CH TCSR: TDV (Bit 7) */ +#define USIC_CH_TCSR_TDV_Msk (0x80UL) /*!< USIC_CH TCSR: TDV (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_TDSSM_Pos (8UL) /*!< USIC_CH TCSR: TDSSM (Bit 8) */ +#define USIC_CH_TCSR_TDSSM_Msk (0x100UL) /*!< USIC_CH TCSR: TDSSM (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_TDEN_Pos (10UL) /*!< USIC_CH TCSR: TDEN (Bit 10) */ +#define USIC_CH_TCSR_TDEN_Msk (0xc00UL) /*!< USIC_CH TCSR: TDEN (Bitfield-Mask: 0x03) */ +#define USIC_CH_TCSR_TDVTR_Pos (12UL) /*!< USIC_CH TCSR: TDVTR (Bit 12) */ +#define USIC_CH_TCSR_TDVTR_Msk (0x1000UL) /*!< USIC_CH TCSR: TDVTR (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_WA_Pos (13UL) /*!< USIC_CH TCSR: WA (Bit 13) */ +#define USIC_CH_TCSR_WA_Msk (0x2000UL) /*!< USIC_CH TCSR: WA (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_TSOF_Pos (24UL) /*!< USIC_CH TCSR: TSOF (Bit 24) */ +#define USIC_CH_TCSR_TSOF_Msk (0x1000000UL) /*!< USIC_CH TCSR: TSOF (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_TV_Pos (26UL) /*!< USIC_CH TCSR: TV (Bit 26) */ +#define USIC_CH_TCSR_TV_Msk (0x4000000UL) /*!< USIC_CH TCSR: TV (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_TVC_Pos (27UL) /*!< USIC_CH TCSR: TVC (Bit 27) */ +#define USIC_CH_TCSR_TVC_Msk (0x8000000UL) /*!< USIC_CH TCSR: TVC (Bitfield-Mask: 0x01) */ +#define USIC_CH_TCSR_TE_Pos (28UL) /*!< USIC_CH TCSR: TE (Bit 28) */ +#define USIC_CH_TCSR_TE_Msk (0x10000000UL) /*!< USIC_CH TCSR: TE (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USIC_CH_PCR -------------------------------- */ +#define USIC_CH_PCR_CTR0_Pos (0UL) /*!< USIC_CH PCR: CTR0 (Bit 0) */ +#define USIC_CH_PCR_CTR0_Msk (0x1UL) /*!< USIC_CH PCR: CTR0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR1_Pos (1UL) /*!< USIC_CH PCR: CTR1 (Bit 1) */ +#define USIC_CH_PCR_CTR1_Msk (0x2UL) /*!< USIC_CH PCR: CTR1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR2_Pos (2UL) /*!< USIC_CH PCR: CTR2 (Bit 2) */ +#define USIC_CH_PCR_CTR2_Msk (0x4UL) /*!< USIC_CH PCR: CTR2 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR3_Pos (3UL) /*!< USIC_CH PCR: CTR3 (Bit 3) */ +#define USIC_CH_PCR_CTR3_Msk (0x8UL) /*!< USIC_CH PCR: CTR3 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR4_Pos (4UL) /*!< USIC_CH PCR: CTR4 (Bit 4) */ +#define USIC_CH_PCR_CTR4_Msk (0x10UL) /*!< USIC_CH PCR: CTR4 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR5_Pos (5UL) /*!< USIC_CH PCR: CTR5 (Bit 5) */ +#define USIC_CH_PCR_CTR5_Msk (0x20UL) /*!< USIC_CH PCR: CTR5 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR6_Pos (6UL) /*!< USIC_CH PCR: CTR6 (Bit 6) */ +#define USIC_CH_PCR_CTR6_Msk (0x40UL) /*!< USIC_CH PCR: CTR6 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR7_Pos (7UL) /*!< USIC_CH PCR: CTR7 (Bit 7) */ +#define USIC_CH_PCR_CTR7_Msk (0x80UL) /*!< USIC_CH PCR: CTR7 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR8_Pos (8UL) /*!< USIC_CH PCR: CTR8 (Bit 8) */ +#define USIC_CH_PCR_CTR8_Msk (0x100UL) /*!< USIC_CH PCR: CTR8 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR9_Pos (9UL) /*!< USIC_CH PCR: CTR9 (Bit 9) */ +#define USIC_CH_PCR_CTR9_Msk (0x200UL) /*!< USIC_CH PCR: CTR9 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR10_Pos (10UL) /*!< USIC_CH PCR: CTR10 (Bit 10) */ +#define USIC_CH_PCR_CTR10_Msk (0x400UL) /*!< USIC_CH PCR: CTR10 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR11_Pos (11UL) /*!< USIC_CH PCR: CTR11 (Bit 11) */ +#define USIC_CH_PCR_CTR11_Msk (0x800UL) /*!< USIC_CH PCR: CTR11 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR12_Pos (12UL) /*!< USIC_CH PCR: CTR12 (Bit 12) */ +#define USIC_CH_PCR_CTR12_Msk (0x1000UL) /*!< USIC_CH PCR: CTR12 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR13_Pos (13UL) /*!< USIC_CH PCR: CTR13 (Bit 13) */ +#define USIC_CH_PCR_CTR13_Msk (0x2000UL) /*!< USIC_CH PCR: CTR13 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR14_Pos (14UL) /*!< USIC_CH PCR: CTR14 (Bit 14) */ +#define USIC_CH_PCR_CTR14_Msk (0x4000UL) /*!< USIC_CH PCR: CTR14 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR15_Pos (15UL) /*!< USIC_CH PCR: CTR15 (Bit 15) */ +#define USIC_CH_PCR_CTR15_Msk (0x8000UL) /*!< USIC_CH PCR: CTR15 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR16_Pos (16UL) /*!< USIC_CH PCR: CTR16 (Bit 16) */ +#define USIC_CH_PCR_CTR16_Msk (0x10000UL) /*!< USIC_CH PCR: CTR16 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR17_Pos (17UL) /*!< USIC_CH PCR: CTR17 (Bit 17) */ +#define USIC_CH_PCR_CTR17_Msk (0x20000UL) /*!< USIC_CH PCR: CTR17 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR18_Pos (18UL) /*!< USIC_CH PCR: CTR18 (Bit 18) */ +#define USIC_CH_PCR_CTR18_Msk (0x40000UL) /*!< USIC_CH PCR: CTR18 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR19_Pos (19UL) /*!< USIC_CH PCR: CTR19 (Bit 19) */ +#define USIC_CH_PCR_CTR19_Msk (0x80000UL) /*!< USIC_CH PCR: CTR19 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR20_Pos (20UL) /*!< USIC_CH PCR: CTR20 (Bit 20) */ +#define USIC_CH_PCR_CTR20_Msk (0x100000UL) /*!< USIC_CH PCR: CTR20 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR21_Pos (21UL) /*!< USIC_CH PCR: CTR21 (Bit 21) */ +#define USIC_CH_PCR_CTR21_Msk (0x200000UL) /*!< USIC_CH PCR: CTR21 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR22_Pos (22UL) /*!< USIC_CH PCR: CTR22 (Bit 22) */ +#define USIC_CH_PCR_CTR22_Msk (0x400000UL) /*!< USIC_CH PCR: CTR22 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR23_Pos (23UL) /*!< USIC_CH PCR: CTR23 (Bit 23) */ +#define USIC_CH_PCR_CTR23_Msk (0x800000UL) /*!< USIC_CH PCR: CTR23 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR24_Pos (24UL) /*!< USIC_CH PCR: CTR24 (Bit 24) */ +#define USIC_CH_PCR_CTR24_Msk (0x1000000UL) /*!< USIC_CH PCR: CTR24 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR25_Pos (25UL) /*!< USIC_CH PCR: CTR25 (Bit 25) */ +#define USIC_CH_PCR_CTR25_Msk (0x2000000UL) /*!< USIC_CH PCR: CTR25 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR26_Pos (26UL) /*!< USIC_CH PCR: CTR26 (Bit 26) */ +#define USIC_CH_PCR_CTR26_Msk (0x4000000UL) /*!< USIC_CH PCR: CTR26 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR27_Pos (27UL) /*!< USIC_CH PCR: CTR27 (Bit 27) */ +#define USIC_CH_PCR_CTR27_Msk (0x8000000UL) /*!< USIC_CH PCR: CTR27 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR28_Pos (28UL) /*!< USIC_CH PCR: CTR28 (Bit 28) */ +#define USIC_CH_PCR_CTR28_Msk (0x10000000UL) /*!< USIC_CH PCR: CTR28 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR29_Pos (29UL) /*!< USIC_CH PCR: CTR29 (Bit 29) */ +#define USIC_CH_PCR_CTR29_Msk (0x20000000UL) /*!< USIC_CH PCR: CTR29 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR30_Pos (30UL) /*!< USIC_CH PCR: CTR30 (Bit 30) */ +#define USIC_CH_PCR_CTR30_Msk (0x40000000UL) /*!< USIC_CH PCR: CTR30 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_CTR31_Pos (31UL) /*!< USIC_CH PCR: CTR31 (Bit 31) */ +#define USIC_CH_PCR_CTR31_Msk (0x80000000UL) /*!< USIC_CH PCR: CTR31 (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */ +#define USIC_CH_PCR_ASCMode_SMD_Pos (0UL) /*!< USIC_CH PCR_ASCMode: SMD (Bit 0) */ +#define USIC_CH_PCR_ASCMode_SMD_Msk (0x1UL) /*!< USIC_CH PCR_ASCMode: SMD (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_STPB_Pos (1UL) /*!< USIC_CH PCR_ASCMode: STPB (Bit 1) */ +#define USIC_CH_PCR_ASCMode_STPB_Msk (0x2UL) /*!< USIC_CH PCR_ASCMode: STPB (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_IDM_Pos (2UL) /*!< USIC_CH PCR_ASCMode: IDM (Bit 2) */ +#define USIC_CH_PCR_ASCMode_IDM_Msk (0x4UL) /*!< USIC_CH PCR_ASCMode: IDM (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_SBIEN_Pos (3UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bit 3) */ +#define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x8UL) /*!< USIC_CH PCR_ASCMode: SBIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_CDEN_Pos (4UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bit 4) */ +#define USIC_CH_PCR_ASCMode_CDEN_Msk (0x10UL) /*!< USIC_CH PCR_ASCMode: CDEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_RNIEN_Pos (5UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bit 5) */ +#define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x20UL) /*!< USIC_CH PCR_ASCMode: RNIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_FEIEN_Pos (6UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bit 6) */ +#define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x40UL) /*!< USIC_CH PCR_ASCMode: FEIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_FFIEN_Pos (7UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bit 7) */ +#define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x80UL) /*!< USIC_CH PCR_ASCMode: FFIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_SP_Pos (8UL) /*!< USIC_CH PCR_ASCMode: SP (Bit 8) */ +#define USIC_CH_PCR_ASCMode_SP_Msk (0x1f00UL) /*!< USIC_CH PCR_ASCMode: SP (Bitfield-Mask: 0x1f) */ +#define USIC_CH_PCR_ASCMode_PL_Pos (13UL) /*!< USIC_CH PCR_ASCMode: PL (Bit 13) */ +#define USIC_CH_PCR_ASCMode_PL_Msk (0xe000UL) /*!< USIC_CH PCR_ASCMode: PL (Bitfield-Mask: 0x07) */ +#define USIC_CH_PCR_ASCMode_RSTEN_Pos (16UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bit 16) */ +#define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x10000UL) /*!< USIC_CH PCR_ASCMode: RSTEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_TSTEN_Pos (17UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bit 17) */ +#define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x20000UL) /*!< USIC_CH PCR_ASCMode: TSTEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_ASCMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bit 31) */ +#define USIC_CH_PCR_ASCMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_ASCMode: MCLK (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */ +#define USIC_CH_PCR_SSCMode_MSLSEN_Pos (0UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bit 0) */ +#define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x1UL) /*!< USIC_CH PCR_SSCMode: MSLSEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_SELCTR_Pos (1UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bit 1) */ +#define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x2UL) /*!< USIC_CH PCR_SSCMode: SELCTR (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_SELINV_Pos (2UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bit 2) */ +#define USIC_CH_PCR_SSCMode_SELINV_Msk (0x4UL) /*!< USIC_CH PCR_SSCMode: SELINV (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_FEM_Pos (3UL) /*!< USIC_CH PCR_SSCMode: FEM (Bit 3) */ +#define USIC_CH_PCR_SSCMode_FEM_Msk (0x8UL) /*!< USIC_CH PCR_SSCMode: FEM (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos (4UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bit 4) */ +#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x30UL) /*!< USIC_CH PCR_SSCMode: CTQSEL1 (Bitfield-Mask: 0x03) */ +#define USIC_CH_PCR_SSCMode_PCTQ1_Pos (6UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bit 6) */ +#define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0xc0UL) /*!< USIC_CH PCR_SSCMode: PCTQ1 (Bitfield-Mask: 0x03) */ +#define USIC_CH_PCR_SSCMode_DCTQ1_Pos (8UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bit 8) */ +#define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1f00UL) /*!< USIC_CH PCR_SSCMode: DCTQ1 (Bitfield-Mask: 0x1f) */ +#define USIC_CH_PCR_SSCMode_PARIEN_Pos (13UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bit 13) */ +#define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x2000UL) /*!< USIC_CH PCR_SSCMode: PARIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos (14UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bit 14) */ +#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x4000UL) /*!< USIC_CH PCR_SSCMode: MSLSIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos (15UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bit 15) */ +#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x8000UL) /*!< USIC_CH PCR_SSCMode: DX2TIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_SELO_Pos (16UL) /*!< USIC_CH PCR_SSCMode: SELO (Bit 16) */ +#define USIC_CH_PCR_SSCMode_SELO_Msk (0xff0000UL) /*!< USIC_CH PCR_SSCMode: SELO (Bitfield-Mask: 0xff) */ +#define USIC_CH_PCR_SSCMode_TIWEN_Pos (24UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bit 24) */ +#define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x1000000UL) /*!< USIC_CH PCR_SSCMode: TIWEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_SLPHSEL_Pos (25UL) /*!< USIC_CH PCR_SSCMode: SLPHSEL (Bit 25) */ +#define USIC_CH_PCR_SSCMode_SLPHSEL_Msk (0x2000000UL) /*!< USIC_CH PCR_SSCMode: SLPHSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_SSCMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bit 31) */ +#define USIC_CH_PCR_SSCMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_SSCMode: MCLK (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */ +#define USIC_CH_PCR_IICMode_SLAD_Pos (0UL) /*!< USIC_CH PCR_IICMode: SLAD (Bit 0) */ +#define USIC_CH_PCR_IICMode_SLAD_Msk (0xffffUL) /*!< USIC_CH PCR_IICMode: SLAD (Bitfield-Mask: 0xffff) */ +#define USIC_CH_PCR_IICMode_ACK00_Pos (16UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bit 16) */ +#define USIC_CH_PCR_IICMode_ACK00_Msk (0x10000UL) /*!< USIC_CH PCR_IICMode: ACK00 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_STIM_Pos (17UL) /*!< USIC_CH PCR_IICMode: STIM (Bit 17) */ +#define USIC_CH_PCR_IICMode_STIM_Msk (0x20000UL) /*!< USIC_CH PCR_IICMode: STIM (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_SCRIEN_Pos (18UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bit 18) */ +#define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x40000UL) /*!< USIC_CH PCR_IICMode: SCRIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_RSCRIEN_Pos (19UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bit 19) */ +#define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x80000UL) /*!< USIC_CH PCR_IICMode: RSCRIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_PCRIEN_Pos (20UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bit 20) */ +#define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x100000UL) /*!< USIC_CH PCR_IICMode: PCRIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_NACKIEN_Pos (21UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bit 21) */ +#define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x200000UL) /*!< USIC_CH PCR_IICMode: NACKIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_ARLIEN_Pos (22UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bit 22) */ +#define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x400000UL) /*!< USIC_CH PCR_IICMode: ARLIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_SRRIEN_Pos (23UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bit 23) */ +#define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x800000UL) /*!< USIC_CH PCR_IICMode: SRRIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_ERRIEN_Pos (24UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bit 24) */ +#define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x1000000UL) /*!< USIC_CH PCR_IICMode: ERRIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_SACKDIS_Pos (25UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bit 25) */ +#define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x2000000UL) /*!< USIC_CH PCR_IICMode: SACKDIS (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_HDEL_Pos (26UL) /*!< USIC_CH PCR_IICMode: HDEL (Bit 26) */ +#define USIC_CH_PCR_IICMode_HDEL_Msk (0x3c000000UL) /*!< USIC_CH PCR_IICMode: HDEL (Bitfield-Mask: 0x0f) */ +#define USIC_CH_PCR_IICMode_ACKIEN_Pos (30UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bit 30) */ +#define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x40000000UL) /*!< USIC_CH PCR_IICMode: ACKIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IICMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_IICMode: MCLK (Bit 31) */ +#define USIC_CH_PCR_IICMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_IICMode: MCLK (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */ +#define USIC_CH_PCR_IISMode_WAGEN_Pos (0UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bit 0) */ +#define USIC_CH_PCR_IISMode_WAGEN_Msk (0x1UL) /*!< USIC_CH PCR_IISMode: WAGEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IISMode_DTEN_Pos (1UL) /*!< USIC_CH PCR_IISMode: DTEN (Bit 1) */ +#define USIC_CH_PCR_IISMode_DTEN_Msk (0x2UL) /*!< USIC_CH PCR_IISMode: DTEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IISMode_SELINV_Pos (2UL) /*!< USIC_CH PCR_IISMode: SELINV (Bit 2) */ +#define USIC_CH_PCR_IISMode_SELINV_Msk (0x4UL) /*!< USIC_CH PCR_IISMode: SELINV (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IISMode_WAFEIEN_Pos (4UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bit 4) */ +#define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x10UL) /*!< USIC_CH PCR_IISMode: WAFEIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IISMode_WAREIEN_Pos (5UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bit 5) */ +#define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x20UL) /*!< USIC_CH PCR_IISMode: WAREIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IISMode_ENDIEN_Pos (6UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bit 6) */ +#define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x40UL) /*!< USIC_CH PCR_IISMode: ENDIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IISMode_DX2TIEN_Pos (15UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bit 15) */ +#define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x8000UL) /*!< USIC_CH PCR_IISMode: DX2TIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_PCR_IISMode_TDEL_Pos (16UL) /*!< USIC_CH PCR_IISMode: TDEL (Bit 16) */ +#define USIC_CH_PCR_IISMode_TDEL_Msk (0x3f0000UL) /*!< USIC_CH PCR_IISMode: TDEL (Bitfield-Mask: 0x3f) */ +#define USIC_CH_PCR_IISMode_MCLK_Pos (31UL) /*!< USIC_CH PCR_IISMode: MCLK (Bit 31) */ +#define USIC_CH_PCR_IISMode_MCLK_Msk (0x80000000UL) /*!< USIC_CH PCR_IISMode: MCLK (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USIC_CH_CCR -------------------------------- */ +#define USIC_CH_CCR_MODE_Pos (0UL) /*!< USIC_CH CCR: MODE (Bit 0) */ +#define USIC_CH_CCR_MODE_Msk (0xfUL) /*!< USIC_CH CCR: MODE (Bitfield-Mask: 0x0f) */ +#define USIC_CH_CCR_HPCEN_Pos (6UL) /*!< USIC_CH CCR: HPCEN (Bit 6) */ +#define USIC_CH_CCR_HPCEN_Msk (0xc0UL) /*!< USIC_CH CCR: HPCEN (Bitfield-Mask: 0x03) */ +#define USIC_CH_CCR_PM_Pos (8UL) /*!< USIC_CH CCR: PM (Bit 8) */ +#define USIC_CH_CCR_PM_Msk (0x300UL) /*!< USIC_CH CCR: PM (Bitfield-Mask: 0x03) */ +#define USIC_CH_CCR_RSIEN_Pos (10UL) /*!< USIC_CH CCR: RSIEN (Bit 10) */ +#define USIC_CH_CCR_RSIEN_Msk (0x400UL) /*!< USIC_CH CCR: RSIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCR_DLIEN_Pos (11UL) /*!< USIC_CH CCR: DLIEN (Bit 11) */ +#define USIC_CH_CCR_DLIEN_Msk (0x800UL) /*!< USIC_CH CCR: DLIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCR_TSIEN_Pos (12UL) /*!< USIC_CH CCR: TSIEN (Bit 12) */ +#define USIC_CH_CCR_TSIEN_Msk (0x1000UL) /*!< USIC_CH CCR: TSIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCR_TBIEN_Pos (13UL) /*!< USIC_CH CCR: TBIEN (Bit 13) */ +#define USIC_CH_CCR_TBIEN_Msk (0x2000UL) /*!< USIC_CH CCR: TBIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCR_RIEN_Pos (14UL) /*!< USIC_CH CCR: RIEN (Bit 14) */ +#define USIC_CH_CCR_RIEN_Msk (0x4000UL) /*!< USIC_CH CCR: RIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCR_AIEN_Pos (15UL) /*!< USIC_CH CCR: AIEN (Bit 15) */ +#define USIC_CH_CCR_AIEN_Msk (0x8000UL) /*!< USIC_CH CCR: AIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_CCR_BRGIEN_Pos (16UL) /*!< USIC_CH CCR: BRGIEN (Bit 16) */ +#define USIC_CH_CCR_BRGIEN_Msk (0x10000UL) /*!< USIC_CH CCR: BRGIEN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_CMTR -------------------------------- */ +#define USIC_CH_CMTR_CTV_Pos (0UL) /*!< USIC_CH CMTR: CTV (Bit 0) */ +#define USIC_CH_CMTR_CTV_Msk (0x3ffUL) /*!< USIC_CH CMTR: CTV (Bitfield-Mask: 0x3ff) */ + +/* --------------------------------- USIC_CH_PSR -------------------------------- */ +#define USIC_CH_PSR_ST0_Pos (0UL) /*!< USIC_CH PSR: ST0 (Bit 0) */ +#define USIC_CH_PSR_ST0_Msk (0x1UL) /*!< USIC_CH PSR: ST0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST1_Pos (1UL) /*!< USIC_CH PSR: ST1 (Bit 1) */ +#define USIC_CH_PSR_ST1_Msk (0x2UL) /*!< USIC_CH PSR: ST1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST2_Pos (2UL) /*!< USIC_CH PSR: ST2 (Bit 2) */ +#define USIC_CH_PSR_ST2_Msk (0x4UL) /*!< USIC_CH PSR: ST2 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST3_Pos (3UL) /*!< USIC_CH PSR: ST3 (Bit 3) */ +#define USIC_CH_PSR_ST3_Msk (0x8UL) /*!< USIC_CH PSR: ST3 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST4_Pos (4UL) /*!< USIC_CH PSR: ST4 (Bit 4) */ +#define USIC_CH_PSR_ST4_Msk (0x10UL) /*!< USIC_CH PSR: ST4 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST5_Pos (5UL) /*!< USIC_CH PSR: ST5 (Bit 5) */ +#define USIC_CH_PSR_ST5_Msk (0x20UL) /*!< USIC_CH PSR: ST5 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST6_Pos (6UL) /*!< USIC_CH PSR: ST6 (Bit 6) */ +#define USIC_CH_PSR_ST6_Msk (0x40UL) /*!< USIC_CH PSR: ST6 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST7_Pos (7UL) /*!< USIC_CH PSR: ST7 (Bit 7) */ +#define USIC_CH_PSR_ST7_Msk (0x80UL) /*!< USIC_CH PSR: ST7 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST8_Pos (8UL) /*!< USIC_CH PSR: ST8 (Bit 8) */ +#define USIC_CH_PSR_ST8_Msk (0x100UL) /*!< USIC_CH PSR: ST8 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ST9_Pos (9UL) /*!< USIC_CH PSR: ST9 (Bit 9) */ +#define USIC_CH_PSR_ST9_Msk (0x200UL) /*!< USIC_CH PSR: ST9 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_RSIF_Pos (10UL) /*!< USIC_CH PSR: RSIF (Bit 10) */ +#define USIC_CH_PSR_RSIF_Msk (0x400UL) /*!< USIC_CH PSR: RSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_DLIF_Pos (11UL) /*!< USIC_CH PSR: DLIF (Bit 11) */ +#define USIC_CH_PSR_DLIF_Msk (0x800UL) /*!< USIC_CH PSR: DLIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_TSIF_Pos (12UL) /*!< USIC_CH PSR: TSIF (Bit 12) */ +#define USIC_CH_PSR_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR: TSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_TBIF_Pos (13UL) /*!< USIC_CH PSR: TBIF (Bit 13) */ +#define USIC_CH_PSR_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR: TBIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_RIF_Pos (14UL) /*!< USIC_CH PSR: RIF (Bit 14) */ +#define USIC_CH_PSR_RIF_Msk (0x4000UL) /*!< USIC_CH PSR: RIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_AIF_Pos (15UL) /*!< USIC_CH PSR: AIF (Bit 15) */ +#define USIC_CH_PSR_AIF_Msk (0x8000UL) /*!< USIC_CH PSR: AIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_BRGIF_Pos (16UL) /*!< USIC_CH PSR: BRGIF (Bit 16) */ +#define USIC_CH_PSR_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR: BRGIF (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */ +#define USIC_CH_PSR_ASCMode_TXIDLE_Pos (0UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bit 0) */ +#define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x1UL) /*!< USIC_CH PSR_ASCMode: TXIDLE (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_RXIDLE_Pos (1UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bit 1) */ +#define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x2UL) /*!< USIC_CH PSR_ASCMode: RXIDLE (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_SBD_Pos (2UL) /*!< USIC_CH PSR_ASCMode: SBD (Bit 2) */ +#define USIC_CH_PSR_ASCMode_SBD_Msk (0x4UL) /*!< USIC_CH PSR_ASCMode: SBD (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_COL_Pos (3UL) /*!< USIC_CH PSR_ASCMode: COL (Bit 3) */ +#define USIC_CH_PSR_ASCMode_COL_Msk (0x8UL) /*!< USIC_CH PSR_ASCMode: COL (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_RNS_Pos (4UL) /*!< USIC_CH PSR_ASCMode: RNS (Bit 4) */ +#define USIC_CH_PSR_ASCMode_RNS_Msk (0x10UL) /*!< USIC_CH PSR_ASCMode: RNS (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_FER0_Pos (5UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bit 5) */ +#define USIC_CH_PSR_ASCMode_FER0_Msk (0x20UL) /*!< USIC_CH PSR_ASCMode: FER0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_FER1_Pos (6UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bit 6) */ +#define USIC_CH_PSR_ASCMode_FER1_Msk (0x40UL) /*!< USIC_CH PSR_ASCMode: FER1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_RFF_Pos (7UL) /*!< USIC_CH PSR_ASCMode: RFF (Bit 7) */ +#define USIC_CH_PSR_ASCMode_RFF_Msk (0x80UL) /*!< USIC_CH PSR_ASCMode: RFF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_TFF_Pos (8UL) /*!< USIC_CH PSR_ASCMode: TFF (Bit 8) */ +#define USIC_CH_PSR_ASCMode_TFF_Msk (0x100UL) /*!< USIC_CH PSR_ASCMode: TFF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_BUSY_Pos (9UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bit 9) */ +#define USIC_CH_PSR_ASCMode_BUSY_Msk (0x200UL) /*!< USIC_CH PSR_ASCMode: BUSY (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bit 10) */ +#define USIC_CH_PSR_ASCMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_ASCMode: RSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bit 11) */ +#define USIC_CH_PSR_ASCMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_ASCMode: DLIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bit 12) */ +#define USIC_CH_PSR_ASCMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_ASCMode: TSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bit 13) */ +#define USIC_CH_PSR_ASCMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_ASCMode: TBIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_RIF_Pos (14UL) /*!< USIC_CH PSR_ASCMode: RIF (Bit 14) */ +#define USIC_CH_PSR_ASCMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_ASCMode: RIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_AIF_Pos (15UL) /*!< USIC_CH PSR_ASCMode: AIF (Bit 15) */ +#define USIC_CH_PSR_ASCMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_ASCMode: AIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_ASCMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bit 16) */ +#define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_ASCMode: BRGIF (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */ +#define USIC_CH_PSR_SSCMode_MSLS_Pos (0UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bit 0) */ +#define USIC_CH_PSR_SSCMode_MSLS_Msk (0x1UL) /*!< USIC_CH PSR_SSCMode: MSLS (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_DX2S_Pos (1UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bit 1) */ +#define USIC_CH_PSR_SSCMode_DX2S_Msk (0x2UL) /*!< USIC_CH PSR_SSCMode: DX2S (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_MSLSEV_Pos (2UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bit 2) */ +#define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x4UL) /*!< USIC_CH PSR_SSCMode: MSLSEV (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_DX2TEV_Pos (3UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bit 3) */ +#define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x8UL) /*!< USIC_CH PSR_SSCMode: DX2TEV (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_PARERR_Pos (4UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bit 4) */ +#define USIC_CH_PSR_SSCMode_PARERR_Msk (0x10UL) /*!< USIC_CH PSR_SSCMode: PARERR (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bit 10) */ +#define USIC_CH_PSR_SSCMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_SSCMode: RSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bit 11) */ +#define USIC_CH_PSR_SSCMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_SSCMode: DLIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bit 12) */ +#define USIC_CH_PSR_SSCMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_SSCMode: TSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bit 13) */ +#define USIC_CH_PSR_SSCMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_SSCMode: TBIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_RIF_Pos (14UL) /*!< USIC_CH PSR_SSCMode: RIF (Bit 14) */ +#define USIC_CH_PSR_SSCMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_SSCMode: RIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_AIF_Pos (15UL) /*!< USIC_CH PSR_SSCMode: AIF (Bit 15) */ +#define USIC_CH_PSR_SSCMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_SSCMode: AIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_SSCMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bit 16) */ +#define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_SSCMode: BRGIF (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */ +#define USIC_CH_PSR_IICMode_SLSEL_Pos (0UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bit 0) */ +#define USIC_CH_PSR_IICMode_SLSEL_Msk (0x1UL) /*!< USIC_CH PSR_IICMode: SLSEL (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_WTDF_Pos (1UL) /*!< USIC_CH PSR_IICMode: WTDF (Bit 1) */ +#define USIC_CH_PSR_IICMode_WTDF_Msk (0x2UL) /*!< USIC_CH PSR_IICMode: WTDF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_SCR_Pos (2UL) /*!< USIC_CH PSR_IICMode: SCR (Bit 2) */ +#define USIC_CH_PSR_IICMode_SCR_Msk (0x4UL) /*!< USIC_CH PSR_IICMode: SCR (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_RSCR_Pos (3UL) /*!< USIC_CH PSR_IICMode: RSCR (Bit 3) */ +#define USIC_CH_PSR_IICMode_RSCR_Msk (0x8UL) /*!< USIC_CH PSR_IICMode: RSCR (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_PCR_Pos (4UL) /*!< USIC_CH PSR_IICMode: PCR (Bit 4) */ +#define USIC_CH_PSR_IICMode_PCR_Msk (0x10UL) /*!< USIC_CH PSR_IICMode: PCR (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_NACK_Pos (5UL) /*!< USIC_CH PSR_IICMode: NACK (Bit 5) */ +#define USIC_CH_PSR_IICMode_NACK_Msk (0x20UL) /*!< USIC_CH PSR_IICMode: NACK (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_ARL_Pos (6UL) /*!< USIC_CH PSR_IICMode: ARL (Bit 6) */ +#define USIC_CH_PSR_IICMode_ARL_Msk (0x40UL) /*!< USIC_CH PSR_IICMode: ARL (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_SRR_Pos (7UL) /*!< USIC_CH PSR_IICMode: SRR (Bit 7) */ +#define USIC_CH_PSR_IICMode_SRR_Msk (0x80UL) /*!< USIC_CH PSR_IICMode: SRR (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_ERR_Pos (8UL) /*!< USIC_CH PSR_IICMode: ERR (Bit 8) */ +#define USIC_CH_PSR_IICMode_ERR_Msk (0x100UL) /*!< USIC_CH PSR_IICMode: ERR (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_ACK_Pos (9UL) /*!< USIC_CH PSR_IICMode: ACK (Bit 9) */ +#define USIC_CH_PSR_IICMode_ACK_Msk (0x200UL) /*!< USIC_CH PSR_IICMode: ACK (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_IICMode: RSIF (Bit 10) */ +#define USIC_CH_PSR_IICMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_IICMode: RSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_IICMode: DLIF (Bit 11) */ +#define USIC_CH_PSR_IICMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_IICMode: DLIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_IICMode: TSIF (Bit 12) */ +#define USIC_CH_PSR_IICMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_IICMode: TSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_IICMode: TBIF (Bit 13) */ +#define USIC_CH_PSR_IICMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_IICMode: TBIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_RIF_Pos (14UL) /*!< USIC_CH PSR_IICMode: RIF (Bit 14) */ +#define USIC_CH_PSR_IICMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_IICMode: RIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_AIF_Pos (15UL) /*!< USIC_CH PSR_IICMode: AIF (Bit 15) */ +#define USIC_CH_PSR_IICMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_IICMode: AIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IICMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bit 16) */ +#define USIC_CH_PSR_IICMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_IICMode: BRGIF (Bitfield-Mask: 0x01) */ + +/* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */ +#define USIC_CH_PSR_IISMode_WA_Pos (0UL) /*!< USIC_CH PSR_IISMode: WA (Bit 0) */ +#define USIC_CH_PSR_IISMode_WA_Msk (0x1UL) /*!< USIC_CH PSR_IISMode: WA (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_DX2S_Pos (1UL) /*!< USIC_CH PSR_IISMode: DX2S (Bit 1) */ +#define USIC_CH_PSR_IISMode_DX2S_Msk (0x2UL) /*!< USIC_CH PSR_IISMode: DX2S (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_DX2TEV_Pos (3UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bit 3) */ +#define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x8UL) /*!< USIC_CH PSR_IISMode: DX2TEV (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_WAFE_Pos (4UL) /*!< USIC_CH PSR_IISMode: WAFE (Bit 4) */ +#define USIC_CH_PSR_IISMode_WAFE_Msk (0x10UL) /*!< USIC_CH PSR_IISMode: WAFE (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_WARE_Pos (5UL) /*!< USIC_CH PSR_IISMode: WARE (Bit 5) */ +#define USIC_CH_PSR_IISMode_WARE_Msk (0x20UL) /*!< USIC_CH PSR_IISMode: WARE (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_END_Pos (6UL) /*!< USIC_CH PSR_IISMode: END (Bit 6) */ +#define USIC_CH_PSR_IISMode_END_Msk (0x40UL) /*!< USIC_CH PSR_IISMode: END (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_RSIF_Pos (10UL) /*!< USIC_CH PSR_IISMode: RSIF (Bit 10) */ +#define USIC_CH_PSR_IISMode_RSIF_Msk (0x400UL) /*!< USIC_CH PSR_IISMode: RSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_DLIF_Pos (11UL) /*!< USIC_CH PSR_IISMode: DLIF (Bit 11) */ +#define USIC_CH_PSR_IISMode_DLIF_Msk (0x800UL) /*!< USIC_CH PSR_IISMode: DLIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_TSIF_Pos (12UL) /*!< USIC_CH PSR_IISMode: TSIF (Bit 12) */ +#define USIC_CH_PSR_IISMode_TSIF_Msk (0x1000UL) /*!< USIC_CH PSR_IISMode: TSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_TBIF_Pos (13UL) /*!< USIC_CH PSR_IISMode: TBIF (Bit 13) */ +#define USIC_CH_PSR_IISMode_TBIF_Msk (0x2000UL) /*!< USIC_CH PSR_IISMode: TBIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_RIF_Pos (14UL) /*!< USIC_CH PSR_IISMode: RIF (Bit 14) */ +#define USIC_CH_PSR_IISMode_RIF_Msk (0x4000UL) /*!< USIC_CH PSR_IISMode: RIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_AIF_Pos (15UL) /*!< USIC_CH PSR_IISMode: AIF (Bit 15) */ +#define USIC_CH_PSR_IISMode_AIF_Msk (0x8000UL) /*!< USIC_CH PSR_IISMode: AIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSR_IISMode_BRGIF_Pos (16UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bit 16) */ +#define USIC_CH_PSR_IISMode_BRGIF_Msk (0x10000UL) /*!< USIC_CH PSR_IISMode: BRGIF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_PSCR -------------------------------- */ +#define USIC_CH_PSCR_CST0_Pos (0UL) /*!< USIC_CH PSCR: CST0 (Bit 0) */ +#define USIC_CH_PSCR_CST0_Msk (0x1UL) /*!< USIC_CH PSCR: CST0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST1_Pos (1UL) /*!< USIC_CH PSCR: CST1 (Bit 1) */ +#define USIC_CH_PSCR_CST1_Msk (0x2UL) /*!< USIC_CH PSCR: CST1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST2_Pos (2UL) /*!< USIC_CH PSCR: CST2 (Bit 2) */ +#define USIC_CH_PSCR_CST2_Msk (0x4UL) /*!< USIC_CH PSCR: CST2 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST3_Pos (3UL) /*!< USIC_CH PSCR: CST3 (Bit 3) */ +#define USIC_CH_PSCR_CST3_Msk (0x8UL) /*!< USIC_CH PSCR: CST3 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST4_Pos (4UL) /*!< USIC_CH PSCR: CST4 (Bit 4) */ +#define USIC_CH_PSCR_CST4_Msk (0x10UL) /*!< USIC_CH PSCR: CST4 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST5_Pos (5UL) /*!< USIC_CH PSCR: CST5 (Bit 5) */ +#define USIC_CH_PSCR_CST5_Msk (0x20UL) /*!< USIC_CH PSCR: CST5 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST6_Pos (6UL) /*!< USIC_CH PSCR: CST6 (Bit 6) */ +#define USIC_CH_PSCR_CST6_Msk (0x40UL) /*!< USIC_CH PSCR: CST6 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST7_Pos (7UL) /*!< USIC_CH PSCR: CST7 (Bit 7) */ +#define USIC_CH_PSCR_CST7_Msk (0x80UL) /*!< USIC_CH PSCR: CST7 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST8_Pos (8UL) /*!< USIC_CH PSCR: CST8 (Bit 8) */ +#define USIC_CH_PSCR_CST8_Msk (0x100UL) /*!< USIC_CH PSCR: CST8 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CST9_Pos (9UL) /*!< USIC_CH PSCR: CST9 (Bit 9) */ +#define USIC_CH_PSCR_CST9_Msk (0x200UL) /*!< USIC_CH PSCR: CST9 (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CRSIF_Pos (10UL) /*!< USIC_CH PSCR: CRSIF (Bit 10) */ +#define USIC_CH_PSCR_CRSIF_Msk (0x400UL) /*!< USIC_CH PSCR: CRSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CDLIF_Pos (11UL) /*!< USIC_CH PSCR: CDLIF (Bit 11) */ +#define USIC_CH_PSCR_CDLIF_Msk (0x800UL) /*!< USIC_CH PSCR: CDLIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CTSIF_Pos (12UL) /*!< USIC_CH PSCR: CTSIF (Bit 12) */ +#define USIC_CH_PSCR_CTSIF_Msk (0x1000UL) /*!< USIC_CH PSCR: CTSIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CTBIF_Pos (13UL) /*!< USIC_CH PSCR: CTBIF (Bit 13) */ +#define USIC_CH_PSCR_CTBIF_Msk (0x2000UL) /*!< USIC_CH PSCR: CTBIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CRIF_Pos (14UL) /*!< USIC_CH PSCR: CRIF (Bit 14) */ +#define USIC_CH_PSCR_CRIF_Msk (0x4000UL) /*!< USIC_CH PSCR: CRIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CAIF_Pos (15UL) /*!< USIC_CH PSCR: CAIF (Bit 15) */ +#define USIC_CH_PSCR_CAIF_Msk (0x8000UL) /*!< USIC_CH PSCR: CAIF (Bitfield-Mask: 0x01) */ +#define USIC_CH_PSCR_CBRGIF_Pos (16UL) /*!< USIC_CH PSCR: CBRGIF (Bit 16) */ +#define USIC_CH_PSCR_CBRGIF_Msk (0x10000UL) /*!< USIC_CH PSCR: CBRGIF (Bitfield-Mask: 0x01) */ + +/* ------------------------------- USIC_CH_RBUFSR ------------------------------- */ +#define USIC_CH_RBUFSR_WLEN_Pos (0UL) /*!< USIC_CH RBUFSR: WLEN (Bit 0) */ +#define USIC_CH_RBUFSR_WLEN_Msk (0xfUL) /*!< USIC_CH RBUFSR: WLEN (Bitfield-Mask: 0x0f) */ +#define USIC_CH_RBUFSR_SOF_Pos (6UL) /*!< USIC_CH RBUFSR: SOF (Bit 6) */ +#define USIC_CH_RBUFSR_SOF_Msk (0x40UL) /*!< USIC_CH RBUFSR: SOF (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUFSR_PAR_Pos (8UL) /*!< USIC_CH RBUFSR: PAR (Bit 8) */ +#define USIC_CH_RBUFSR_PAR_Msk (0x100UL) /*!< USIC_CH RBUFSR: PAR (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUFSR_PERR_Pos (9UL) /*!< USIC_CH RBUFSR: PERR (Bit 9) */ +#define USIC_CH_RBUFSR_PERR_Msk (0x200UL) /*!< USIC_CH RBUFSR: PERR (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUFSR_RDV0_Pos (13UL) /*!< USIC_CH RBUFSR: RDV0 (Bit 13) */ +#define USIC_CH_RBUFSR_RDV0_Msk (0x2000UL) /*!< USIC_CH RBUFSR: RDV0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUFSR_RDV1_Pos (14UL) /*!< USIC_CH RBUFSR: RDV1 (Bit 14) */ +#define USIC_CH_RBUFSR_RDV1_Msk (0x4000UL) /*!< USIC_CH RBUFSR: RDV1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUFSR_DS_Pos (15UL) /*!< USIC_CH RBUFSR: DS (Bit 15) */ +#define USIC_CH_RBUFSR_DS_Msk (0x8000UL) /*!< USIC_CH RBUFSR: DS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_RBUF -------------------------------- */ +#define USIC_CH_RBUF_DSR_Pos (0UL) /*!< USIC_CH RBUF: DSR (Bit 0) */ +#define USIC_CH_RBUF_DSR_Msk (0xffffUL) /*!< USIC_CH RBUF: DSR (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USIC_CH_RBUFD ------------------------------- */ +#define USIC_CH_RBUFD_DSR_Pos (0UL) /*!< USIC_CH RBUFD: DSR (Bit 0) */ +#define USIC_CH_RBUFD_DSR_Msk (0xffffUL) /*!< USIC_CH RBUFD: DSR (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USIC_CH_RBUF0 ------------------------------- */ +#define USIC_CH_RBUF0_DSR0_Pos (0UL) /*!< USIC_CH RBUF0: DSR0 (Bit 0) */ +#define USIC_CH_RBUF0_DSR0_Msk (0xffffUL) /*!< USIC_CH RBUF0: DSR0 (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USIC_CH_RBUF1 ------------------------------- */ +#define USIC_CH_RBUF1_DSR1_Pos (0UL) /*!< USIC_CH RBUF1: DSR1 (Bit 0) */ +#define USIC_CH_RBUF1_DSR1_Msk (0xffffUL) /*!< USIC_CH RBUF1: DSR1 (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */ +#define USIC_CH_RBUF01SR_WLEN0_Pos (0UL) /*!< USIC_CH RBUF01SR: WLEN0 (Bit 0) */ +#define USIC_CH_RBUF01SR_WLEN0_Msk (0xfUL) /*!< USIC_CH RBUF01SR: WLEN0 (Bitfield-Mask: 0x0f) */ +#define USIC_CH_RBUF01SR_SOF0_Pos (6UL) /*!< USIC_CH RBUF01SR: SOF0 (Bit 6) */ +#define USIC_CH_RBUF01SR_SOF0_Msk (0x40UL) /*!< USIC_CH RBUF01SR: SOF0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_PAR0_Pos (8UL) /*!< USIC_CH RBUF01SR: PAR0 (Bit 8) */ +#define USIC_CH_RBUF01SR_PAR0_Msk (0x100UL) /*!< USIC_CH RBUF01SR: PAR0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_PERR0_Pos (9UL) /*!< USIC_CH RBUF01SR: PERR0 (Bit 9) */ +#define USIC_CH_RBUF01SR_PERR0_Msk (0x200UL) /*!< USIC_CH RBUF01SR: PERR0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_RDV00_Pos (13UL) /*!< USIC_CH RBUF01SR: RDV00 (Bit 13) */ +#define USIC_CH_RBUF01SR_RDV00_Msk (0x2000UL) /*!< USIC_CH RBUF01SR: RDV00 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_RDV01_Pos (14UL) /*!< USIC_CH RBUF01SR: RDV01 (Bit 14) */ +#define USIC_CH_RBUF01SR_RDV01_Msk (0x4000UL) /*!< USIC_CH RBUF01SR: RDV01 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_DS0_Pos (15UL) /*!< USIC_CH RBUF01SR: DS0 (Bit 15) */ +#define USIC_CH_RBUF01SR_DS0_Msk (0x8000UL) /*!< USIC_CH RBUF01SR: DS0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_WLEN1_Pos (16UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bit 16) */ +#define USIC_CH_RBUF01SR_WLEN1_Msk (0xf0000UL) /*!< USIC_CH RBUF01SR: WLEN1 (Bitfield-Mask: 0x0f) */ +#define USIC_CH_RBUF01SR_SOF1_Pos (22UL) /*!< USIC_CH RBUF01SR: SOF1 (Bit 22) */ +#define USIC_CH_RBUF01SR_SOF1_Msk (0x400000UL) /*!< USIC_CH RBUF01SR: SOF1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_PAR1_Pos (24UL) /*!< USIC_CH RBUF01SR: PAR1 (Bit 24) */ +#define USIC_CH_RBUF01SR_PAR1_Msk (0x1000000UL) /*!< USIC_CH RBUF01SR: PAR1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_PERR1_Pos (25UL) /*!< USIC_CH RBUF01SR: PERR1 (Bit 25) */ +#define USIC_CH_RBUF01SR_PERR1_Msk (0x2000000UL) /*!< USIC_CH RBUF01SR: PERR1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_RDV10_Pos (29UL) /*!< USIC_CH RBUF01SR: RDV10 (Bit 29) */ +#define USIC_CH_RBUF01SR_RDV10_Msk (0x20000000UL) /*!< USIC_CH RBUF01SR: RDV10 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_RDV11_Pos (30UL) /*!< USIC_CH RBUF01SR: RDV11 (Bit 30) */ +#define USIC_CH_RBUF01SR_RDV11_Msk (0x40000000UL) /*!< USIC_CH RBUF01SR: RDV11 (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBUF01SR_DS1_Pos (31UL) /*!< USIC_CH RBUF01SR: DS1 (Bit 31) */ +#define USIC_CH_RBUF01SR_DS1_Msk (0x80000000UL) /*!< USIC_CH RBUF01SR: DS1 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- USIC_CH_FMR -------------------------------- */ +#define USIC_CH_FMR_MTDV_Pos (0UL) /*!< USIC_CH FMR: MTDV (Bit 0) */ +#define USIC_CH_FMR_MTDV_Msk (0x3UL) /*!< USIC_CH FMR: MTDV (Bitfield-Mask: 0x03) */ +#define USIC_CH_FMR_ATVC_Pos (4UL) /*!< USIC_CH FMR: ATVC (Bit 4) */ +#define USIC_CH_FMR_ATVC_Msk (0x10UL) /*!< USIC_CH FMR: ATVC (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_CRDV0_Pos (14UL) /*!< USIC_CH FMR: CRDV0 (Bit 14) */ +#define USIC_CH_FMR_CRDV0_Msk (0x4000UL) /*!< USIC_CH FMR: CRDV0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_CRDV1_Pos (15UL) /*!< USIC_CH FMR: CRDV1 (Bit 15) */ +#define USIC_CH_FMR_CRDV1_Msk (0x8000UL) /*!< USIC_CH FMR: CRDV1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_SIO0_Pos (16UL) /*!< USIC_CH FMR: SIO0 (Bit 16) */ +#define USIC_CH_FMR_SIO0_Msk (0x10000UL) /*!< USIC_CH FMR: SIO0 (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_SIO1_Pos (17UL) /*!< USIC_CH FMR: SIO1 (Bit 17) */ +#define USIC_CH_FMR_SIO1_Msk (0x20000UL) /*!< USIC_CH FMR: SIO1 (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_SIO2_Pos (18UL) /*!< USIC_CH FMR: SIO2 (Bit 18) */ +#define USIC_CH_FMR_SIO2_Msk (0x40000UL) /*!< USIC_CH FMR: SIO2 (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_SIO3_Pos (19UL) /*!< USIC_CH FMR: SIO3 (Bit 19) */ +#define USIC_CH_FMR_SIO3_Msk (0x80000UL) /*!< USIC_CH FMR: SIO3 (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_SIO4_Pos (20UL) /*!< USIC_CH FMR: SIO4 (Bit 20) */ +#define USIC_CH_FMR_SIO4_Msk (0x100000UL) /*!< USIC_CH FMR: SIO4 (Bitfield-Mask: 0x01) */ +#define USIC_CH_FMR_SIO5_Pos (21UL) /*!< USIC_CH FMR: SIO5 (Bit 21) */ +#define USIC_CH_FMR_SIO5_Msk (0x200000UL) /*!< USIC_CH FMR: SIO5 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_TBUF -------------------------------- */ +#define USIC_CH_TBUF_TDATA_Pos (0UL) /*!< USIC_CH TBUF: TDATA (Bit 0) */ +#define USIC_CH_TBUF_TDATA_Msk (0xffffUL) /*!< USIC_CH TBUF: TDATA (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- USIC_CH_BYP -------------------------------- */ +#define USIC_CH_BYP_BDATA_Pos (0UL) /*!< USIC_CH BYP: BDATA (Bit 0) */ +#define USIC_CH_BYP_BDATA_Msk (0xffffUL) /*!< USIC_CH BYP: BDATA (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- USIC_CH_BYPCR ------------------------------- */ +#define USIC_CH_BYPCR_BWLE_Pos (0UL) /*!< USIC_CH BYPCR: BWLE (Bit 0) */ +#define USIC_CH_BYPCR_BWLE_Msk (0xfUL) /*!< USIC_CH BYPCR: BWLE (Bitfield-Mask: 0x0f) */ +#define USIC_CH_BYPCR_BDSSM_Pos (8UL) /*!< USIC_CH BYPCR: BDSSM (Bit 8) */ +#define USIC_CH_BYPCR_BDSSM_Msk (0x100UL) /*!< USIC_CH BYPCR: BDSSM (Bitfield-Mask: 0x01) */ +#define USIC_CH_BYPCR_BDEN_Pos (10UL) /*!< USIC_CH BYPCR: BDEN (Bit 10) */ +#define USIC_CH_BYPCR_BDEN_Msk (0xc00UL) /*!< USIC_CH BYPCR: BDEN (Bitfield-Mask: 0x03) */ +#define USIC_CH_BYPCR_BDVTR_Pos (12UL) /*!< USIC_CH BYPCR: BDVTR (Bit 12) */ +#define USIC_CH_BYPCR_BDVTR_Msk (0x1000UL) /*!< USIC_CH BYPCR: BDVTR (Bitfield-Mask: 0x01) */ +#define USIC_CH_BYPCR_BPRIO_Pos (13UL) /*!< USIC_CH BYPCR: BPRIO (Bit 13) */ +#define USIC_CH_BYPCR_BPRIO_Msk (0x2000UL) /*!< USIC_CH BYPCR: BPRIO (Bitfield-Mask: 0x01) */ +#define USIC_CH_BYPCR_BDV_Pos (15UL) /*!< USIC_CH BYPCR: BDV (Bit 15) */ +#define USIC_CH_BYPCR_BDV_Msk (0x8000UL) /*!< USIC_CH BYPCR: BDV (Bitfield-Mask: 0x01) */ +#define USIC_CH_BYPCR_BSELO_Pos (16UL) /*!< USIC_CH BYPCR: BSELO (Bit 16) */ +#define USIC_CH_BYPCR_BSELO_Msk (0x1f0000UL) /*!< USIC_CH BYPCR: BSELO (Bitfield-Mask: 0x1f) */ +#define USIC_CH_BYPCR_BHPC_Pos (21UL) /*!< USIC_CH BYPCR: BHPC (Bit 21) */ +#define USIC_CH_BYPCR_BHPC_Msk (0xe00000UL) /*!< USIC_CH BYPCR: BHPC (Bitfield-Mask: 0x07) */ + +/* -------------------------------- USIC_CH_TBCTR ------------------------------- */ +#define USIC_CH_TBCTR_DPTR_Pos (0UL) /*!< USIC_CH TBCTR: DPTR (Bit 0) */ +#define USIC_CH_TBCTR_DPTR_Msk (0x3fUL) /*!< USIC_CH TBCTR: DPTR (Bitfield-Mask: 0x3f) */ +#define USIC_CH_TBCTR_LIMIT_Pos (8UL) /*!< USIC_CH TBCTR: LIMIT (Bit 8) */ +#define USIC_CH_TBCTR_LIMIT_Msk (0x3f00UL) /*!< USIC_CH TBCTR: LIMIT (Bitfield-Mask: 0x3f) */ +#define USIC_CH_TBCTR_STBTM_Pos (14UL) /*!< USIC_CH TBCTR: STBTM (Bit 14) */ +#define USIC_CH_TBCTR_STBTM_Msk (0x4000UL) /*!< USIC_CH TBCTR: STBTM (Bitfield-Mask: 0x01) */ +#define USIC_CH_TBCTR_STBTEN_Pos (15UL) /*!< USIC_CH TBCTR: STBTEN (Bit 15) */ +#define USIC_CH_TBCTR_STBTEN_Msk (0x8000UL) /*!< USIC_CH TBCTR: STBTEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_TBCTR_STBINP_Pos (16UL) /*!< USIC_CH TBCTR: STBINP (Bit 16) */ +#define USIC_CH_TBCTR_STBINP_Msk (0x70000UL) /*!< USIC_CH TBCTR: STBINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_TBCTR_ATBINP_Pos (19UL) /*!< USIC_CH TBCTR: ATBINP (Bit 19) */ +#define USIC_CH_TBCTR_ATBINP_Msk (0x380000UL) /*!< USIC_CH TBCTR: ATBINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_TBCTR_SIZE_Pos (24UL) /*!< USIC_CH TBCTR: SIZE (Bit 24) */ +#define USIC_CH_TBCTR_SIZE_Msk (0x7000000UL) /*!< USIC_CH TBCTR: SIZE (Bitfield-Mask: 0x07) */ +#define USIC_CH_TBCTR_LOF_Pos (28UL) /*!< USIC_CH TBCTR: LOF (Bit 28) */ +#define USIC_CH_TBCTR_LOF_Msk (0x10000000UL) /*!< USIC_CH TBCTR: LOF (Bitfield-Mask: 0x01) */ +#define USIC_CH_TBCTR_STBIEN_Pos (30UL) /*!< USIC_CH TBCTR: STBIEN (Bit 30) */ +#define USIC_CH_TBCTR_STBIEN_Msk (0x40000000UL) /*!< USIC_CH TBCTR: STBIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_TBCTR_TBERIEN_Pos (31UL) /*!< USIC_CH TBCTR: TBERIEN (Bit 31) */ +#define USIC_CH_TBCTR_TBERIEN_Msk (0x80000000UL) /*!< USIC_CH TBCTR: TBERIEN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_RBCTR ------------------------------- */ +#define USIC_CH_RBCTR_DPTR_Pos (0UL) /*!< USIC_CH RBCTR: DPTR (Bit 0) */ +#define USIC_CH_RBCTR_DPTR_Msk (0x3fUL) /*!< USIC_CH RBCTR: DPTR (Bitfield-Mask: 0x3f) */ +#define USIC_CH_RBCTR_LIMIT_Pos (8UL) /*!< USIC_CH RBCTR: LIMIT (Bit 8) */ +#define USIC_CH_RBCTR_LIMIT_Msk (0x3f00UL) /*!< USIC_CH RBCTR: LIMIT (Bitfield-Mask: 0x3f) */ +#define USIC_CH_RBCTR_SRBTM_Pos (14UL) /*!< USIC_CH RBCTR: SRBTM (Bit 14) */ +#define USIC_CH_RBCTR_SRBTM_Msk (0x4000UL) /*!< USIC_CH RBCTR: SRBTM (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBCTR_SRBTEN_Pos (15UL) /*!< USIC_CH RBCTR: SRBTEN (Bit 15) */ +#define USIC_CH_RBCTR_SRBTEN_Msk (0x8000UL) /*!< USIC_CH RBCTR: SRBTEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBCTR_SRBINP_Pos (16UL) /*!< USIC_CH RBCTR: SRBINP (Bit 16) */ +#define USIC_CH_RBCTR_SRBINP_Msk (0x70000UL) /*!< USIC_CH RBCTR: SRBINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_RBCTR_ARBINP_Pos (19UL) /*!< USIC_CH RBCTR: ARBINP (Bit 19) */ +#define USIC_CH_RBCTR_ARBINP_Msk (0x380000UL) /*!< USIC_CH RBCTR: ARBINP (Bitfield-Mask: 0x07) */ +#define USIC_CH_RBCTR_RCIM_Pos (22UL) /*!< USIC_CH RBCTR: RCIM (Bit 22) */ +#define USIC_CH_RBCTR_RCIM_Msk (0xc00000UL) /*!< USIC_CH RBCTR: RCIM (Bitfield-Mask: 0x03) */ +#define USIC_CH_RBCTR_SIZE_Pos (24UL) /*!< USIC_CH RBCTR: SIZE (Bit 24) */ +#define USIC_CH_RBCTR_SIZE_Msk (0x7000000UL) /*!< USIC_CH RBCTR: SIZE (Bitfield-Mask: 0x07) */ +#define USIC_CH_RBCTR_RNM_Pos (27UL) /*!< USIC_CH RBCTR: RNM (Bit 27) */ +#define USIC_CH_RBCTR_RNM_Msk (0x8000000UL) /*!< USIC_CH RBCTR: RNM (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBCTR_LOF_Pos (28UL) /*!< USIC_CH RBCTR: LOF (Bit 28) */ +#define USIC_CH_RBCTR_LOF_Msk (0x10000000UL) /*!< USIC_CH RBCTR: LOF (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBCTR_ARBIEN_Pos (29UL) /*!< USIC_CH RBCTR: ARBIEN (Bit 29) */ +#define USIC_CH_RBCTR_ARBIEN_Msk (0x20000000UL) /*!< USIC_CH RBCTR: ARBIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBCTR_SRBIEN_Pos (30UL) /*!< USIC_CH RBCTR: SRBIEN (Bit 30) */ +#define USIC_CH_RBCTR_SRBIEN_Msk (0x40000000UL) /*!< USIC_CH RBCTR: SRBIEN (Bitfield-Mask: 0x01) */ +#define USIC_CH_RBCTR_RBERIEN_Pos (31UL) /*!< USIC_CH RBCTR: RBERIEN (Bit 31) */ +#define USIC_CH_RBCTR_RBERIEN_Msk (0x80000000UL) /*!< USIC_CH RBCTR: RBERIEN (Bitfield-Mask: 0x01) */ + +/* ------------------------------- USIC_CH_TRBPTR ------------------------------- */ +#define USIC_CH_TRBPTR_TDIPTR_Pos (0UL) /*!< USIC_CH TRBPTR: TDIPTR (Bit 0) */ +#define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL) /*!< USIC_CH TRBPTR: TDIPTR (Bitfield-Mask: 0x3f) */ +#define USIC_CH_TRBPTR_TDOPTR_Pos (8UL) /*!< USIC_CH TRBPTR: TDOPTR (Bit 8) */ +#define USIC_CH_TRBPTR_TDOPTR_Msk (0x3f00UL) /*!< USIC_CH TRBPTR: TDOPTR (Bitfield-Mask: 0x3f) */ +#define USIC_CH_TRBPTR_RDIPTR_Pos (16UL) /*!< USIC_CH TRBPTR: RDIPTR (Bit 16) */ +#define USIC_CH_TRBPTR_RDIPTR_Msk (0x3f0000UL) /*!< USIC_CH TRBPTR: RDIPTR (Bitfield-Mask: 0x3f) */ +#define USIC_CH_TRBPTR_RDOPTR_Pos (24UL) /*!< USIC_CH TRBPTR: RDOPTR (Bit 24) */ +#define USIC_CH_TRBPTR_RDOPTR_Msk (0x3f000000UL) /*!< USIC_CH TRBPTR: RDOPTR (Bitfield-Mask: 0x3f) */ + +/* -------------------------------- USIC_CH_TRBSR ------------------------------- */ +#define USIC_CH_TRBSR_SRBI_Pos (0UL) /*!< USIC_CH TRBSR: SRBI (Bit 0) */ +#define USIC_CH_TRBSR_SRBI_Msk (0x1UL) /*!< USIC_CH TRBSR: SRBI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_RBERI_Pos (1UL) /*!< USIC_CH TRBSR: RBERI (Bit 1) */ +#define USIC_CH_TRBSR_RBERI_Msk (0x2UL) /*!< USIC_CH TRBSR: RBERI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_ARBI_Pos (2UL) /*!< USIC_CH TRBSR: ARBI (Bit 2) */ +#define USIC_CH_TRBSR_ARBI_Msk (0x4UL) /*!< USIC_CH TRBSR: ARBI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_REMPTY_Pos (3UL) /*!< USIC_CH TRBSR: REMPTY (Bit 3) */ +#define USIC_CH_TRBSR_REMPTY_Msk (0x8UL) /*!< USIC_CH TRBSR: REMPTY (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_RFULL_Pos (4UL) /*!< USIC_CH TRBSR: RFULL (Bit 4) */ +#define USIC_CH_TRBSR_RFULL_Msk (0x10UL) /*!< USIC_CH TRBSR: RFULL (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_RBUS_Pos (5UL) /*!< USIC_CH TRBSR: RBUS (Bit 5) */ +#define USIC_CH_TRBSR_RBUS_Msk (0x20UL) /*!< USIC_CH TRBSR: RBUS (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_SRBT_Pos (6UL) /*!< USIC_CH TRBSR: SRBT (Bit 6) */ +#define USIC_CH_TRBSR_SRBT_Msk (0x40UL) /*!< USIC_CH TRBSR: SRBT (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_STBI_Pos (8UL) /*!< USIC_CH TRBSR: STBI (Bit 8) */ +#define USIC_CH_TRBSR_STBI_Msk (0x100UL) /*!< USIC_CH TRBSR: STBI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_TBERI_Pos (9UL) /*!< USIC_CH TRBSR: TBERI (Bit 9) */ +#define USIC_CH_TRBSR_TBERI_Msk (0x200UL) /*!< USIC_CH TRBSR: TBERI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_TEMPTY_Pos (11UL) /*!< USIC_CH TRBSR: TEMPTY (Bit 11) */ +#define USIC_CH_TRBSR_TEMPTY_Msk (0x800UL) /*!< USIC_CH TRBSR: TEMPTY (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_TFULL_Pos (12UL) /*!< USIC_CH TRBSR: TFULL (Bit 12) */ +#define USIC_CH_TRBSR_TFULL_Msk (0x1000UL) /*!< USIC_CH TRBSR: TFULL (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_TBUS_Pos (13UL) /*!< USIC_CH TRBSR: TBUS (Bit 13) */ +#define USIC_CH_TRBSR_TBUS_Msk (0x2000UL) /*!< USIC_CH TRBSR: TBUS (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_STBT_Pos (14UL) /*!< USIC_CH TRBSR: STBT (Bit 14) */ +#define USIC_CH_TRBSR_STBT_Msk (0x4000UL) /*!< USIC_CH TRBSR: STBT (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSR_RBFLVL_Pos (16UL) /*!< USIC_CH TRBSR: RBFLVL (Bit 16) */ +#define USIC_CH_TRBSR_RBFLVL_Msk (0x7f0000UL) /*!< USIC_CH TRBSR: RBFLVL (Bitfield-Mask: 0x7f) */ +#define USIC_CH_TRBSR_TBFLVL_Pos (24UL) /*!< USIC_CH TRBSR: TBFLVL (Bit 24) */ +#define USIC_CH_TRBSR_TBFLVL_Msk (0x7f000000UL) /*!< USIC_CH TRBSR: TBFLVL (Bitfield-Mask: 0x7f) */ + +/* ------------------------------- USIC_CH_TRBSCR ------------------------------- */ +#define USIC_CH_TRBSCR_CSRBI_Pos (0UL) /*!< USIC_CH TRBSCR: CSRBI (Bit 0) */ +#define USIC_CH_TRBSCR_CSRBI_Msk (0x1UL) /*!< USIC_CH TRBSCR: CSRBI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSCR_CRBERI_Pos (1UL) /*!< USIC_CH TRBSCR: CRBERI (Bit 1) */ +#define USIC_CH_TRBSCR_CRBERI_Msk (0x2UL) /*!< USIC_CH TRBSCR: CRBERI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSCR_CARBI_Pos (2UL) /*!< USIC_CH TRBSCR: CARBI (Bit 2) */ +#define USIC_CH_TRBSCR_CARBI_Msk (0x4UL) /*!< USIC_CH TRBSCR: CARBI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSCR_CSTBI_Pos (8UL) /*!< USIC_CH TRBSCR: CSTBI (Bit 8) */ +#define USIC_CH_TRBSCR_CSTBI_Msk (0x100UL) /*!< USIC_CH TRBSCR: CSTBI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSCR_CTBERI_Pos (9UL) /*!< USIC_CH TRBSCR: CTBERI (Bit 9) */ +#define USIC_CH_TRBSCR_CTBERI_Msk (0x200UL) /*!< USIC_CH TRBSCR: CTBERI (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSCR_CBDV_Pos (10UL) /*!< USIC_CH TRBSCR: CBDV (Bit 10) */ +#define USIC_CH_TRBSCR_CBDV_Msk (0x400UL) /*!< USIC_CH TRBSCR: CBDV (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSCR_FLUSHRB_Pos (14UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bit 14) */ +#define USIC_CH_TRBSCR_FLUSHRB_Msk (0x4000UL) /*!< USIC_CH TRBSCR: FLUSHRB (Bitfield-Mask: 0x01) */ +#define USIC_CH_TRBSCR_FLUSHTB_Pos (15UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bit 15) */ +#define USIC_CH_TRBSCR_FLUSHTB_Msk (0x8000UL) /*!< USIC_CH TRBSCR: FLUSHTB (Bitfield-Mask: 0x01) */ + +/* -------------------------------- USIC_CH_OUTR -------------------------------- */ +#define USIC_CH_OUTR_DSR_Pos (0UL) /*!< USIC_CH OUTR: DSR (Bit 0) */ +#define USIC_CH_OUTR_DSR_Msk (0xffffUL) /*!< USIC_CH OUTR: DSR (Bitfield-Mask: 0xffff) */ +#define USIC_CH_OUTR_RCI_Pos (16UL) /*!< USIC_CH OUTR: RCI (Bit 16) */ +#define USIC_CH_OUTR_RCI_Msk (0x1f0000UL) /*!< USIC_CH OUTR: RCI (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- USIC_CH_OUTDR ------------------------------- */ +#define USIC_CH_OUTDR_DSR_Pos (0UL) /*!< USIC_CH OUTDR: DSR (Bit 0) */ +#define USIC_CH_OUTDR_DSR_Msk (0xffffUL) /*!< USIC_CH OUTDR: DSR (Bitfield-Mask: 0xffff) */ +#define USIC_CH_OUTDR_RCI_Pos (16UL) /*!< USIC_CH OUTDR: RCI (Bit 16) */ +#define USIC_CH_OUTDR_RCI_Msk (0x1f0000UL) /*!< USIC_CH OUTDR: RCI (Bitfield-Mask: 0x1f) */ + +/* --------------------------------- USIC_CH_IN --------------------------------- */ +#define USIC_CH_IN_TDATA_Pos (0UL) /*!< USIC_CH IN: TDATA (Bit 0) */ +#define USIC_CH_IN_TDATA_Msk (0xffffUL) /*!< USIC_CH IN: TDATA (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ struct 'CAN' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- CAN_CLC ---------------------------------- */ +#define CAN_CLC_DISR_Pos (0UL) /*!< CAN CLC: DISR (Bit 0) */ +#define CAN_CLC_DISR_Msk (0x1UL) /*!< CAN CLC: DISR (Bitfield-Mask: 0x01) */ +#define CAN_CLC_DISS_Pos (1UL) /*!< CAN CLC: DISS (Bit 1) */ +#define CAN_CLC_DISS_Msk (0x2UL) /*!< CAN CLC: DISS (Bitfield-Mask: 0x01) */ +#define CAN_CLC_EDIS_Pos (3UL) /*!< CAN CLC: EDIS (Bit 3) */ +#define CAN_CLC_EDIS_Msk (0x8UL) /*!< CAN CLC: EDIS (Bitfield-Mask: 0x01) */ +#define CAN_CLC_SBWE_Pos (4UL) /*!< CAN CLC: SBWE (Bit 4) */ +#define CAN_CLC_SBWE_Msk (0x10UL) /*!< CAN CLC: SBWE (Bitfield-Mask: 0x01) */ + +/* ----------------------------------- CAN_ID ----------------------------------- */ +#define CAN_ID_MOD_REV_Pos (0UL) /*!< CAN ID: MOD_REV (Bit 0) */ +#define CAN_ID_MOD_REV_Msk (0xffUL) /*!< CAN ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define CAN_ID_MOD_TYPE_Pos (8UL) /*!< CAN ID: MOD_TYPE (Bit 8) */ +#define CAN_ID_MOD_TYPE_Msk (0xff00UL) /*!< CAN ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define CAN_ID_MOD_NUMBER_Pos (16UL) /*!< CAN ID: MOD_NUMBER (Bit 16) */ +#define CAN_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< CAN ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* ----------------------------------- CAN_FDR ---------------------------------- */ +#define CAN_FDR_STEP_Pos (0UL) /*!< CAN FDR: STEP (Bit 0) */ +#define CAN_FDR_STEP_Msk (0x3ffUL) /*!< CAN FDR: STEP (Bitfield-Mask: 0x3ff) */ +#define CAN_FDR_SM_Pos (11UL) /*!< CAN FDR: SM (Bit 11) */ +#define CAN_FDR_SM_Msk (0x800UL) /*!< CAN FDR: SM (Bitfield-Mask: 0x01) */ +#define CAN_FDR_SC_Pos (12UL) /*!< CAN FDR: SC (Bit 12) */ +#define CAN_FDR_SC_Msk (0x3000UL) /*!< CAN FDR: SC (Bitfield-Mask: 0x03) */ +#define CAN_FDR_DM_Pos (14UL) /*!< CAN FDR: DM (Bit 14) */ +#define CAN_FDR_DM_Msk (0xc000UL) /*!< CAN FDR: DM (Bitfield-Mask: 0x03) */ +#define CAN_FDR_RESULT_Pos (16UL) /*!< CAN FDR: RESULT (Bit 16) */ +#define CAN_FDR_RESULT_Msk (0x3ff0000UL) /*!< CAN FDR: RESULT (Bitfield-Mask: 0x3ff) */ +#define CAN_FDR_SUSACK_Pos (28UL) /*!< CAN FDR: SUSACK (Bit 28) */ +#define CAN_FDR_SUSACK_Msk (0x10000000UL) /*!< CAN FDR: SUSACK (Bitfield-Mask: 0x01) */ +#define CAN_FDR_SUSREQ_Pos (29UL) /*!< CAN FDR: SUSREQ (Bit 29) */ +#define CAN_FDR_SUSREQ_Msk (0x20000000UL) /*!< CAN FDR: SUSREQ (Bitfield-Mask: 0x01) */ +#define CAN_FDR_ENHW_Pos (30UL) /*!< CAN FDR: ENHW (Bit 30) */ +#define CAN_FDR_ENHW_Msk (0x40000000UL) /*!< CAN FDR: ENHW (Bitfield-Mask: 0x01) */ +#define CAN_FDR_DISCLK_Pos (31UL) /*!< CAN FDR: DISCLK (Bit 31) */ +#define CAN_FDR_DISCLK_Msk (0x80000000UL) /*!< CAN FDR: DISCLK (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CAN_LIST ---------------------------------- */ +#define CAN_LIST_BEGIN_Pos (0UL) /*!< CAN LIST: BEGIN (Bit 0) */ +#define CAN_LIST_BEGIN_Msk (0xffUL) /*!< CAN LIST: BEGIN (Bitfield-Mask: 0xff) */ +#define CAN_LIST_END_Pos (8UL) /*!< CAN LIST: END (Bit 8) */ +#define CAN_LIST_END_Msk (0xff00UL) /*!< CAN LIST: END (Bitfield-Mask: 0xff) */ +#define CAN_LIST_SIZE_Pos (16UL) /*!< CAN LIST: SIZE (Bit 16) */ +#define CAN_LIST_SIZE_Msk (0xff0000UL) /*!< CAN LIST: SIZE (Bitfield-Mask: 0xff) */ +#define CAN_LIST_EMPTY_Pos (24UL) /*!< CAN LIST: EMPTY (Bit 24) */ +#define CAN_LIST_EMPTY_Msk (0x1000000UL) /*!< CAN LIST: EMPTY (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CAN_MSPND --------------------------------- */ +#define CAN_MSPND_PND_Pos (0UL) /*!< CAN MSPND: PND (Bit 0) */ +#define CAN_MSPND_PND_Msk (0xffffffffUL) /*!< CAN MSPND: PND (Bitfield-Mask: 0xffffffff) */ + +/* ---------------------------------- CAN_MSID ---------------------------------- */ +#define CAN_MSID_INDEX_Pos (0UL) /*!< CAN MSID: INDEX (Bit 0) */ +#define CAN_MSID_INDEX_Msk (0x3fUL) /*!< CAN MSID: INDEX (Bitfield-Mask: 0x3f) */ + +/* --------------------------------- CAN_MSIMASK -------------------------------- */ +#define CAN_MSIMASK_IM_Pos (0UL) /*!< CAN MSIMASK: IM (Bit 0) */ +#define CAN_MSIMASK_IM_Msk (0xffffffffUL) /*!< CAN MSIMASK: IM (Bitfield-Mask: 0xffffffff) */ + +/* --------------------------------- CAN_PANCTR --------------------------------- */ +#define CAN_PANCTR_PANCMD_Pos (0UL) /*!< CAN PANCTR: PANCMD (Bit 0) */ +#define CAN_PANCTR_PANCMD_Msk (0xffUL) /*!< CAN PANCTR: PANCMD (Bitfield-Mask: 0xff) */ +#define CAN_PANCTR_BUSY_Pos (8UL) /*!< CAN PANCTR: BUSY (Bit 8) */ +#define CAN_PANCTR_BUSY_Msk (0x100UL) /*!< CAN PANCTR: BUSY (Bitfield-Mask: 0x01) */ +#define CAN_PANCTR_RBUSY_Pos (9UL) /*!< CAN PANCTR: RBUSY (Bit 9) */ +#define CAN_PANCTR_RBUSY_Msk (0x200UL) /*!< CAN PANCTR: RBUSY (Bitfield-Mask: 0x01) */ +#define CAN_PANCTR_PANAR1_Pos (16UL) /*!< CAN PANCTR: PANAR1 (Bit 16) */ +#define CAN_PANCTR_PANAR1_Msk (0xff0000UL) /*!< CAN PANCTR: PANAR1 (Bitfield-Mask: 0xff) */ +#define CAN_PANCTR_PANAR2_Pos (24UL) /*!< CAN PANCTR: PANAR2 (Bit 24) */ +#define CAN_PANCTR_PANAR2_Msk (0xff000000UL) /*!< CAN PANCTR: PANAR2 (Bitfield-Mask: 0xff) */ + +/* ----------------------------------- CAN_MCR ---------------------------------- */ +#define CAN_MCR_MPSEL_Pos (12UL) /*!< CAN MCR: MPSEL (Bit 12) */ +#define CAN_MCR_MPSEL_Msk (0xf000UL) /*!< CAN MCR: MPSEL (Bitfield-Mask: 0x0f) */ + +/* ---------------------------------- CAN_MITR ---------------------------------- */ +#define CAN_MITR_IT_Pos (0UL) /*!< CAN MITR: IT (Bit 0) */ +#define CAN_MITR_IT_Msk (0xffUL) /*!< CAN MITR: IT (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ Group 'CAN_NODE' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- CAN_NODE_NCR -------------------------------- */ +#define CAN_NODE_NCR_INIT_Pos (0UL) /*!< CAN_NODE NCR: INIT (Bit 0) */ +#define CAN_NODE_NCR_INIT_Msk (0x1UL) /*!< CAN_NODE NCR: INIT (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NCR_TRIE_Pos (1UL) /*!< CAN_NODE NCR: TRIE (Bit 1) */ +#define CAN_NODE_NCR_TRIE_Msk (0x2UL) /*!< CAN_NODE NCR: TRIE (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NCR_LECIE_Pos (2UL) /*!< CAN_NODE NCR: LECIE (Bit 2) */ +#define CAN_NODE_NCR_LECIE_Msk (0x4UL) /*!< CAN_NODE NCR: LECIE (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NCR_ALIE_Pos (3UL) /*!< CAN_NODE NCR: ALIE (Bit 3) */ +#define CAN_NODE_NCR_ALIE_Msk (0x8UL) /*!< CAN_NODE NCR: ALIE (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NCR_CANDIS_Pos (4UL) /*!< CAN_NODE NCR: CANDIS (Bit 4) */ +#define CAN_NODE_NCR_CANDIS_Msk (0x10UL) /*!< CAN_NODE NCR: CANDIS (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NCR_CCE_Pos (6UL) /*!< CAN_NODE NCR: CCE (Bit 6) */ +#define CAN_NODE_NCR_CCE_Msk (0x40UL) /*!< CAN_NODE NCR: CCE (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NCR_CALM_Pos (7UL) /*!< CAN_NODE NCR: CALM (Bit 7) */ +#define CAN_NODE_NCR_CALM_Msk (0x80UL) /*!< CAN_NODE NCR: CALM (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NCR_SUSEN_Pos (8UL) /*!< CAN_NODE NCR: SUSEN (Bit 8) */ +#define CAN_NODE_NCR_SUSEN_Msk (0x100UL) /*!< CAN_NODE NCR: SUSEN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CAN_NODE_NSR -------------------------------- */ +#define CAN_NODE_NSR_LEC_Pos (0UL) /*!< CAN_NODE NSR: LEC (Bit 0) */ +#define CAN_NODE_NSR_LEC_Msk (0x7UL) /*!< CAN_NODE NSR: LEC (Bitfield-Mask: 0x07) */ +#define CAN_NODE_NSR_TXOK_Pos (3UL) /*!< CAN_NODE NSR: TXOK (Bit 3) */ +#define CAN_NODE_NSR_TXOK_Msk (0x8UL) /*!< CAN_NODE NSR: TXOK (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NSR_RXOK_Pos (4UL) /*!< CAN_NODE NSR: RXOK (Bit 4) */ +#define CAN_NODE_NSR_RXOK_Msk (0x10UL) /*!< CAN_NODE NSR: RXOK (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NSR_ALERT_Pos (5UL) /*!< CAN_NODE NSR: ALERT (Bit 5) */ +#define CAN_NODE_NSR_ALERT_Msk (0x20UL) /*!< CAN_NODE NSR: ALERT (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NSR_EWRN_Pos (6UL) /*!< CAN_NODE NSR: EWRN (Bit 6) */ +#define CAN_NODE_NSR_EWRN_Msk (0x40UL) /*!< CAN_NODE NSR: EWRN (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NSR_BOFF_Pos (7UL) /*!< CAN_NODE NSR: BOFF (Bit 7) */ +#define CAN_NODE_NSR_BOFF_Msk (0x80UL) /*!< CAN_NODE NSR: BOFF (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NSR_LLE_Pos (8UL) /*!< CAN_NODE NSR: LLE (Bit 8) */ +#define CAN_NODE_NSR_LLE_Msk (0x100UL) /*!< CAN_NODE NSR: LLE (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NSR_LOE_Pos (9UL) /*!< CAN_NODE NSR: LOE (Bit 9) */ +#define CAN_NODE_NSR_LOE_Msk (0x200UL) /*!< CAN_NODE NSR: LOE (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NSR_SUSACK_Pos (10UL) /*!< CAN_NODE NSR: SUSACK (Bit 10) */ +#define CAN_NODE_NSR_SUSACK_Msk (0x400UL) /*!< CAN_NODE NSR: SUSACK (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CAN_NODE_NIPR ------------------------------- */ +#define CAN_NODE_NIPR_ALINP_Pos (0UL) /*!< CAN_NODE NIPR: ALINP (Bit 0) */ +#define CAN_NODE_NIPR_ALINP_Msk (0x7UL) /*!< CAN_NODE NIPR: ALINP (Bitfield-Mask: 0x07) */ +#define CAN_NODE_NIPR_LECINP_Pos (4UL) /*!< CAN_NODE NIPR: LECINP (Bit 4) */ +#define CAN_NODE_NIPR_LECINP_Msk (0x70UL) /*!< CAN_NODE NIPR: LECINP (Bitfield-Mask: 0x07) */ +#define CAN_NODE_NIPR_TRINP_Pos (8UL) /*!< CAN_NODE NIPR: TRINP (Bit 8) */ +#define CAN_NODE_NIPR_TRINP_Msk (0x700UL) /*!< CAN_NODE NIPR: TRINP (Bitfield-Mask: 0x07) */ +#define CAN_NODE_NIPR_CFCINP_Pos (12UL) /*!< CAN_NODE NIPR: CFCINP (Bit 12) */ +#define CAN_NODE_NIPR_CFCINP_Msk (0x7000UL) /*!< CAN_NODE NIPR: CFCINP (Bitfield-Mask: 0x07) */ + +/* -------------------------------- CAN_NODE_NPCR ------------------------------- */ +#define CAN_NODE_NPCR_RXSEL_Pos (0UL) /*!< CAN_NODE NPCR: RXSEL (Bit 0) */ +#define CAN_NODE_NPCR_RXSEL_Msk (0x7UL) /*!< CAN_NODE NPCR: RXSEL (Bitfield-Mask: 0x07) */ +#define CAN_NODE_NPCR_LBM_Pos (8UL) /*!< CAN_NODE NPCR: LBM (Bit 8) */ +#define CAN_NODE_NPCR_LBM_Msk (0x100UL) /*!< CAN_NODE NPCR: LBM (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CAN_NODE_NBTR ------------------------------- */ +#define CAN_NODE_NBTR_BRP_Pos (0UL) /*!< CAN_NODE NBTR: BRP (Bit 0) */ +#define CAN_NODE_NBTR_BRP_Msk (0x3fUL) /*!< CAN_NODE NBTR: BRP (Bitfield-Mask: 0x3f) */ +#define CAN_NODE_NBTR_SJW_Pos (6UL) /*!< CAN_NODE NBTR: SJW (Bit 6) */ +#define CAN_NODE_NBTR_SJW_Msk (0xc0UL) /*!< CAN_NODE NBTR: SJW (Bitfield-Mask: 0x03) */ +#define CAN_NODE_NBTR_TSEG1_Pos (8UL) /*!< CAN_NODE NBTR: TSEG1 (Bit 8) */ +#define CAN_NODE_NBTR_TSEG1_Msk (0xf00UL) /*!< CAN_NODE NBTR: TSEG1 (Bitfield-Mask: 0x0f) */ +#define CAN_NODE_NBTR_TSEG2_Pos (12UL) /*!< CAN_NODE NBTR: TSEG2 (Bit 12) */ +#define CAN_NODE_NBTR_TSEG2_Msk (0x7000UL) /*!< CAN_NODE NBTR: TSEG2 (Bitfield-Mask: 0x07) */ +#define CAN_NODE_NBTR_DIV8_Pos (15UL) /*!< CAN_NODE NBTR: DIV8 (Bit 15) */ +#define CAN_NODE_NBTR_DIV8_Msk (0x8000UL) /*!< CAN_NODE NBTR: DIV8 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- CAN_NODE_NECNT ------------------------------- */ +#define CAN_NODE_NECNT_REC_Pos (0UL) /*!< CAN_NODE NECNT: REC (Bit 0) */ +#define CAN_NODE_NECNT_REC_Msk (0xffUL) /*!< CAN_NODE NECNT: REC (Bitfield-Mask: 0xff) */ +#define CAN_NODE_NECNT_TEC_Pos (8UL) /*!< CAN_NODE NECNT: TEC (Bit 8) */ +#define CAN_NODE_NECNT_TEC_Msk (0xff00UL) /*!< CAN_NODE NECNT: TEC (Bitfield-Mask: 0xff) */ +#define CAN_NODE_NECNT_EWRNLVL_Pos (16UL) /*!< CAN_NODE NECNT: EWRNLVL (Bit 16) */ +#define CAN_NODE_NECNT_EWRNLVL_Msk (0xff0000UL) /*!< CAN_NODE NECNT: EWRNLVL (Bitfield-Mask: 0xff) */ +#define CAN_NODE_NECNT_LETD_Pos (24UL) /*!< CAN_NODE NECNT: LETD (Bit 24) */ +#define CAN_NODE_NECNT_LETD_Msk (0x1000000UL) /*!< CAN_NODE NECNT: LETD (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NECNT_LEINC_Pos (25UL) /*!< CAN_NODE NECNT: LEINC (Bit 25) */ +#define CAN_NODE_NECNT_LEINC_Msk (0x2000000UL) /*!< CAN_NODE NECNT: LEINC (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CAN_NODE_NFCR ------------------------------- */ +#define CAN_NODE_NFCR_CFC_Pos (0UL) /*!< CAN_NODE NFCR: CFC (Bit 0) */ +#define CAN_NODE_NFCR_CFC_Msk (0xffffUL) /*!< CAN_NODE NFCR: CFC (Bitfield-Mask: 0xffff) */ +#define CAN_NODE_NFCR_CFSEL_Pos (16UL) /*!< CAN_NODE NFCR: CFSEL (Bit 16) */ +#define CAN_NODE_NFCR_CFSEL_Msk (0x70000UL) /*!< CAN_NODE NFCR: CFSEL (Bitfield-Mask: 0x07) */ +#define CAN_NODE_NFCR_CFMOD_Pos (19UL) /*!< CAN_NODE NFCR: CFMOD (Bit 19) */ +#define CAN_NODE_NFCR_CFMOD_Msk (0x180000UL) /*!< CAN_NODE NFCR: CFMOD (Bitfield-Mask: 0x03) */ +#define CAN_NODE_NFCR_CFCIE_Pos (22UL) /*!< CAN_NODE NFCR: CFCIE (Bit 22) */ +#define CAN_NODE_NFCR_CFCIE_Msk (0x400000UL) /*!< CAN_NODE NFCR: CFCIE (Bitfield-Mask: 0x01) */ +#define CAN_NODE_NFCR_CFCOV_Pos (23UL) /*!< CAN_NODE NFCR: CFCOV (Bit 23) */ +#define CAN_NODE_NFCR_CFCOV_Msk (0x800000UL) /*!< CAN_NODE NFCR: CFCOV (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'CAN_MO' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- CAN_MO_MOFCR -------------------------------- */ +#define CAN_MO_MOFCR_MMC_Pos (0UL) /*!< CAN_MO MOFCR: MMC (Bit 0) */ +#define CAN_MO_MOFCR_MMC_Msk (0xfUL) /*!< CAN_MO MOFCR: MMC (Bitfield-Mask: 0x0f) */ +#define CAN_MO_MOFCR_GDFS_Pos (8UL) /*!< CAN_MO MOFCR: GDFS (Bit 8) */ +#define CAN_MO_MOFCR_GDFS_Msk (0x100UL) /*!< CAN_MO MOFCR: GDFS (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_IDC_Pos (9UL) /*!< CAN_MO MOFCR: IDC (Bit 9) */ +#define CAN_MO_MOFCR_IDC_Msk (0x200UL) /*!< CAN_MO MOFCR: IDC (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_DLCC_Pos (10UL) /*!< CAN_MO MOFCR: DLCC (Bit 10) */ +#define CAN_MO_MOFCR_DLCC_Msk (0x400UL) /*!< CAN_MO MOFCR: DLCC (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_DATC_Pos (11UL) /*!< CAN_MO MOFCR: DATC (Bit 11) */ +#define CAN_MO_MOFCR_DATC_Msk (0x800UL) /*!< CAN_MO MOFCR: DATC (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_RXIE_Pos (16UL) /*!< CAN_MO MOFCR: RXIE (Bit 16) */ +#define CAN_MO_MOFCR_RXIE_Msk (0x10000UL) /*!< CAN_MO MOFCR: RXIE (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_TXIE_Pos (17UL) /*!< CAN_MO MOFCR: TXIE (Bit 17) */ +#define CAN_MO_MOFCR_TXIE_Msk (0x20000UL) /*!< CAN_MO MOFCR: TXIE (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_OVIE_Pos (18UL) /*!< CAN_MO MOFCR: OVIE (Bit 18) */ +#define CAN_MO_MOFCR_OVIE_Msk (0x40000UL) /*!< CAN_MO MOFCR: OVIE (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_FRREN_Pos (20UL) /*!< CAN_MO MOFCR: FRREN (Bit 20) */ +#define CAN_MO_MOFCR_FRREN_Msk (0x100000UL) /*!< CAN_MO MOFCR: FRREN (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_RMM_Pos (21UL) /*!< CAN_MO MOFCR: RMM (Bit 21) */ +#define CAN_MO_MOFCR_RMM_Msk (0x200000UL) /*!< CAN_MO MOFCR: RMM (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_SDT_Pos (22UL) /*!< CAN_MO MOFCR: SDT (Bit 22) */ +#define CAN_MO_MOFCR_SDT_Msk (0x400000UL) /*!< CAN_MO MOFCR: SDT (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_STT_Pos (23UL) /*!< CAN_MO MOFCR: STT (Bit 23) */ +#define CAN_MO_MOFCR_STT_Msk (0x800000UL) /*!< CAN_MO MOFCR: STT (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOFCR_DLC_Pos (24UL) /*!< CAN_MO MOFCR: DLC (Bit 24) */ +#define CAN_MO_MOFCR_DLC_Msk (0xf000000UL) /*!< CAN_MO MOFCR: DLC (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CAN_MO_MOFGPR ------------------------------- */ +#define CAN_MO_MOFGPR_BOT_Pos (0UL) /*!< CAN_MO MOFGPR: BOT (Bit 0) */ +#define CAN_MO_MOFGPR_BOT_Msk (0xffUL) /*!< CAN_MO MOFGPR: BOT (Bitfield-Mask: 0xff) */ +#define CAN_MO_MOFGPR_TOP_Pos (8UL) /*!< CAN_MO MOFGPR: TOP (Bit 8) */ +#define CAN_MO_MOFGPR_TOP_Msk (0xff00UL) /*!< CAN_MO MOFGPR: TOP (Bitfield-Mask: 0xff) */ +#define CAN_MO_MOFGPR_CUR_Pos (16UL) /*!< CAN_MO MOFGPR: CUR (Bit 16) */ +#define CAN_MO_MOFGPR_CUR_Msk (0xff0000UL) /*!< CAN_MO MOFGPR: CUR (Bitfield-Mask: 0xff) */ +#define CAN_MO_MOFGPR_SEL_Pos (24UL) /*!< CAN_MO MOFGPR: SEL (Bit 24) */ +#define CAN_MO_MOFGPR_SEL_Msk (0xff000000UL) /*!< CAN_MO MOFGPR: SEL (Bitfield-Mask: 0xff) */ + +/* -------------------------------- CAN_MO_MOIPR -------------------------------- */ +#define CAN_MO_MOIPR_RXINP_Pos (0UL) /*!< CAN_MO MOIPR: RXINP (Bit 0) */ +#define CAN_MO_MOIPR_RXINP_Msk (0x7UL) /*!< CAN_MO MOIPR: RXINP (Bitfield-Mask: 0x07) */ +#define CAN_MO_MOIPR_TXINP_Pos (4UL) /*!< CAN_MO MOIPR: TXINP (Bit 4) */ +#define CAN_MO_MOIPR_TXINP_Msk (0x70UL) /*!< CAN_MO MOIPR: TXINP (Bitfield-Mask: 0x07) */ +#define CAN_MO_MOIPR_MPN_Pos (8UL) /*!< CAN_MO MOIPR: MPN (Bit 8) */ +#define CAN_MO_MOIPR_MPN_Msk (0xff00UL) /*!< CAN_MO MOIPR: MPN (Bitfield-Mask: 0xff) */ +#define CAN_MO_MOIPR_CFCVAL_Pos (16UL) /*!< CAN_MO MOIPR: CFCVAL (Bit 16) */ +#define CAN_MO_MOIPR_CFCVAL_Msk (0xffff0000UL) /*!< CAN_MO MOIPR: CFCVAL (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CAN_MO_MOAMR -------------------------------- */ +#define CAN_MO_MOAMR_AM_Pos (0UL) /*!< CAN_MO MOAMR: AM (Bit 0) */ +#define CAN_MO_MOAMR_AM_Msk (0x1fffffffUL) /*!< CAN_MO MOAMR: AM (Bitfield-Mask: 0x1fffffff) */ +#define CAN_MO_MOAMR_MIDE_Pos (29UL) /*!< CAN_MO MOAMR: MIDE (Bit 29) */ +#define CAN_MO_MOAMR_MIDE_Msk (0x20000000UL) /*!< CAN_MO MOAMR: MIDE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- CAN_MO_MODATAL ------------------------------- */ +#define CAN_MO_MODATAL_DB0_Pos (0UL) /*!< CAN_MO MODATAL: DB0 (Bit 0) */ +#define CAN_MO_MODATAL_DB0_Msk (0xffUL) /*!< CAN_MO MODATAL: DB0 (Bitfield-Mask: 0xff) */ +#define CAN_MO_MODATAL_DB1_Pos (8UL) /*!< CAN_MO MODATAL: DB1 (Bit 8) */ +#define CAN_MO_MODATAL_DB1_Msk (0xff00UL) /*!< CAN_MO MODATAL: DB1 (Bitfield-Mask: 0xff) */ +#define CAN_MO_MODATAL_DB2_Pos (16UL) /*!< CAN_MO MODATAL: DB2 (Bit 16) */ +#define CAN_MO_MODATAL_DB2_Msk (0xff0000UL) /*!< CAN_MO MODATAL: DB2 (Bitfield-Mask: 0xff) */ +#define CAN_MO_MODATAL_DB3_Pos (24UL) /*!< CAN_MO MODATAL: DB3 (Bit 24) */ +#define CAN_MO_MODATAL_DB3_Msk (0xff000000UL) /*!< CAN_MO MODATAL: DB3 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- CAN_MO_MODATAH ------------------------------- */ +#define CAN_MO_MODATAH_DB4_Pos (0UL) /*!< CAN_MO MODATAH: DB4 (Bit 0) */ +#define CAN_MO_MODATAH_DB4_Msk (0xffUL) /*!< CAN_MO MODATAH: DB4 (Bitfield-Mask: 0xff) */ +#define CAN_MO_MODATAH_DB5_Pos (8UL) /*!< CAN_MO MODATAH: DB5 (Bit 8) */ +#define CAN_MO_MODATAH_DB5_Msk (0xff00UL) /*!< CAN_MO MODATAH: DB5 (Bitfield-Mask: 0xff) */ +#define CAN_MO_MODATAH_DB6_Pos (16UL) /*!< CAN_MO MODATAH: DB6 (Bit 16) */ +#define CAN_MO_MODATAH_DB6_Msk (0xff0000UL) /*!< CAN_MO MODATAH: DB6 (Bitfield-Mask: 0xff) */ +#define CAN_MO_MODATAH_DB7_Pos (24UL) /*!< CAN_MO MODATAH: DB7 (Bit 24) */ +#define CAN_MO_MODATAH_DB7_Msk (0xff000000UL) /*!< CAN_MO MODATAH: DB7 (Bitfield-Mask: 0xff) */ + +/* --------------------------------- CAN_MO_MOAR -------------------------------- */ +#define CAN_MO_MOAR_ID_Pos (0UL) /*!< CAN_MO MOAR: ID (Bit 0) */ +#define CAN_MO_MOAR_ID_Msk (0x1fffffffUL) /*!< CAN_MO MOAR: ID (Bitfield-Mask: 0x1fffffff) */ +#define CAN_MO_MOAR_IDE_Pos (29UL) /*!< CAN_MO MOAR: IDE (Bit 29) */ +#define CAN_MO_MOAR_IDE_Msk (0x20000000UL) /*!< CAN_MO MOAR: IDE (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOAR_PRI_Pos (30UL) /*!< CAN_MO MOAR: PRI (Bit 30) */ +#define CAN_MO_MOAR_PRI_Msk (0xc0000000UL) /*!< CAN_MO MOAR: PRI (Bitfield-Mask: 0x03) */ + +/* -------------------------------- CAN_MO_MOCTR -------------------------------- */ +#define CAN_MO_MOCTR_RESRXPND_Pos (0UL) /*!< CAN_MO MOCTR: RESRXPND (Bit 0) */ +#define CAN_MO_MOCTR_RESRXPND_Msk (0x1UL) /*!< CAN_MO MOCTR: RESRXPND (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESTXPND_Pos (1UL) /*!< CAN_MO MOCTR: RESTXPND (Bit 1) */ +#define CAN_MO_MOCTR_RESTXPND_Msk (0x2UL) /*!< CAN_MO MOCTR: RESTXPND (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESRXUPD_Pos (2UL) /*!< CAN_MO MOCTR: RESRXUPD (Bit 2) */ +#define CAN_MO_MOCTR_RESRXUPD_Msk (0x4UL) /*!< CAN_MO MOCTR: RESRXUPD (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESNEWDAT_Pos (3UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bit 3) */ +#define CAN_MO_MOCTR_RESNEWDAT_Msk (0x8UL) /*!< CAN_MO MOCTR: RESNEWDAT (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESMSGLST_Pos (4UL) /*!< CAN_MO MOCTR: RESMSGLST (Bit 4) */ +#define CAN_MO_MOCTR_RESMSGLST_Msk (0x10UL) /*!< CAN_MO MOCTR: RESMSGLST (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESMSGVAL_Pos (5UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bit 5) */ +#define CAN_MO_MOCTR_RESMSGVAL_Msk (0x20UL) /*!< CAN_MO MOCTR: RESMSGVAL (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESRTSEL_Pos (6UL) /*!< CAN_MO MOCTR: RESRTSEL (Bit 6) */ +#define CAN_MO_MOCTR_RESRTSEL_Msk (0x40UL) /*!< CAN_MO MOCTR: RESRTSEL (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESRXEN_Pos (7UL) /*!< CAN_MO MOCTR: RESRXEN (Bit 7) */ +#define CAN_MO_MOCTR_RESRXEN_Msk (0x80UL) /*!< CAN_MO MOCTR: RESRXEN (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESTXRQ_Pos (8UL) /*!< CAN_MO MOCTR: RESTXRQ (Bit 8) */ +#define CAN_MO_MOCTR_RESTXRQ_Msk (0x100UL) /*!< CAN_MO MOCTR: RESTXRQ (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESTXEN0_Pos (9UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bit 9) */ +#define CAN_MO_MOCTR_RESTXEN0_Msk (0x200UL) /*!< CAN_MO MOCTR: RESTXEN0 (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESTXEN1_Pos (10UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bit 10) */ +#define CAN_MO_MOCTR_RESTXEN1_Msk (0x400UL) /*!< CAN_MO MOCTR: RESTXEN1 (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_RESDIR_Pos (11UL) /*!< CAN_MO MOCTR: RESDIR (Bit 11) */ +#define CAN_MO_MOCTR_RESDIR_Msk (0x800UL) /*!< CAN_MO MOCTR: RESDIR (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETRXPND_Pos (16UL) /*!< CAN_MO MOCTR: SETRXPND (Bit 16) */ +#define CAN_MO_MOCTR_SETRXPND_Msk (0x10000UL) /*!< CAN_MO MOCTR: SETRXPND (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETTXPND_Pos (17UL) /*!< CAN_MO MOCTR: SETTXPND (Bit 17) */ +#define CAN_MO_MOCTR_SETTXPND_Msk (0x20000UL) /*!< CAN_MO MOCTR: SETTXPND (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETRXUPD_Pos (18UL) /*!< CAN_MO MOCTR: SETRXUPD (Bit 18) */ +#define CAN_MO_MOCTR_SETRXUPD_Msk (0x40000UL) /*!< CAN_MO MOCTR: SETRXUPD (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETNEWDAT_Pos (19UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bit 19) */ +#define CAN_MO_MOCTR_SETNEWDAT_Msk (0x80000UL) /*!< CAN_MO MOCTR: SETNEWDAT (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETMSGLST_Pos (20UL) /*!< CAN_MO MOCTR: SETMSGLST (Bit 20) */ +#define CAN_MO_MOCTR_SETMSGLST_Msk (0x100000UL) /*!< CAN_MO MOCTR: SETMSGLST (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETMSGVAL_Pos (21UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bit 21) */ +#define CAN_MO_MOCTR_SETMSGVAL_Msk (0x200000UL) /*!< CAN_MO MOCTR: SETMSGVAL (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETRTSEL_Pos (22UL) /*!< CAN_MO MOCTR: SETRTSEL (Bit 22) */ +#define CAN_MO_MOCTR_SETRTSEL_Msk (0x400000UL) /*!< CAN_MO MOCTR: SETRTSEL (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETRXEN_Pos (23UL) /*!< CAN_MO MOCTR: SETRXEN (Bit 23) */ +#define CAN_MO_MOCTR_SETRXEN_Msk (0x800000UL) /*!< CAN_MO MOCTR: SETRXEN (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETTXRQ_Pos (24UL) /*!< CAN_MO MOCTR: SETTXRQ (Bit 24) */ +#define CAN_MO_MOCTR_SETTXRQ_Msk (0x1000000UL) /*!< CAN_MO MOCTR: SETTXRQ (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETTXEN0_Pos (25UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bit 25) */ +#define CAN_MO_MOCTR_SETTXEN0_Msk (0x2000000UL) /*!< CAN_MO MOCTR: SETTXEN0 (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETTXEN1_Pos (26UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bit 26) */ +#define CAN_MO_MOCTR_SETTXEN1_Msk (0x4000000UL) /*!< CAN_MO MOCTR: SETTXEN1 (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOCTR_SETDIR_Pos (27UL) /*!< CAN_MO MOCTR: SETDIR (Bit 27) */ +#define CAN_MO_MOCTR_SETDIR_Msk (0x8000000UL) /*!< CAN_MO MOCTR: SETDIR (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CAN_MO_MOSTAT ------------------------------- */ +#define CAN_MO_MOSTAT_RXPND_Pos (0UL) /*!< CAN_MO MOSTAT: RXPND (Bit 0) */ +#define CAN_MO_MOSTAT_RXPND_Msk (0x1UL) /*!< CAN_MO MOSTAT: RXPND (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_TXPND_Pos (1UL) /*!< CAN_MO MOSTAT: TXPND (Bit 1) */ +#define CAN_MO_MOSTAT_TXPND_Msk (0x2UL) /*!< CAN_MO MOSTAT: TXPND (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_RXUPD_Pos (2UL) /*!< CAN_MO MOSTAT: RXUPD (Bit 2) */ +#define CAN_MO_MOSTAT_RXUPD_Msk (0x4UL) /*!< CAN_MO MOSTAT: RXUPD (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_NEWDAT_Pos (3UL) /*!< CAN_MO MOSTAT: NEWDAT (Bit 3) */ +#define CAN_MO_MOSTAT_NEWDAT_Msk (0x8UL) /*!< CAN_MO MOSTAT: NEWDAT (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_MSGLST_Pos (4UL) /*!< CAN_MO MOSTAT: MSGLST (Bit 4) */ +#define CAN_MO_MOSTAT_MSGLST_Msk (0x10UL) /*!< CAN_MO MOSTAT: MSGLST (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_MSGVAL_Pos (5UL) /*!< CAN_MO MOSTAT: MSGVAL (Bit 5) */ +#define CAN_MO_MOSTAT_MSGVAL_Msk (0x20UL) /*!< CAN_MO MOSTAT: MSGVAL (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_RTSEL_Pos (6UL) /*!< CAN_MO MOSTAT: RTSEL (Bit 6) */ +#define CAN_MO_MOSTAT_RTSEL_Msk (0x40UL) /*!< CAN_MO MOSTAT: RTSEL (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_RXEN_Pos (7UL) /*!< CAN_MO MOSTAT: RXEN (Bit 7) */ +#define CAN_MO_MOSTAT_RXEN_Msk (0x80UL) /*!< CAN_MO MOSTAT: RXEN (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_TXRQ_Pos (8UL) /*!< CAN_MO MOSTAT: TXRQ (Bit 8) */ +#define CAN_MO_MOSTAT_TXRQ_Msk (0x100UL) /*!< CAN_MO MOSTAT: TXRQ (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_TXEN0_Pos (9UL) /*!< CAN_MO MOSTAT: TXEN0 (Bit 9) */ +#define CAN_MO_MOSTAT_TXEN0_Msk (0x200UL) /*!< CAN_MO MOSTAT: TXEN0 (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_TXEN1_Pos (10UL) /*!< CAN_MO MOSTAT: TXEN1 (Bit 10) */ +#define CAN_MO_MOSTAT_TXEN1_Msk (0x400UL) /*!< CAN_MO MOSTAT: TXEN1 (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_DIR_Pos (11UL) /*!< CAN_MO MOSTAT: DIR (Bit 11) */ +#define CAN_MO_MOSTAT_DIR_Msk (0x800UL) /*!< CAN_MO MOSTAT: DIR (Bitfield-Mask: 0x01) */ +#define CAN_MO_MOSTAT_LIST_Pos (12UL) /*!< CAN_MO MOSTAT: LIST (Bit 12) */ +#define CAN_MO_MOSTAT_LIST_Msk (0xf000UL) /*!< CAN_MO MOSTAT: LIST (Bitfield-Mask: 0x0f) */ +#define CAN_MO_MOSTAT_PPREV_Pos (16UL) /*!< CAN_MO MOSTAT: PPREV (Bit 16) */ +#define CAN_MO_MOSTAT_PPREV_Msk (0xff0000UL) /*!< CAN_MO MOSTAT: PPREV (Bitfield-Mask: 0xff) */ +#define CAN_MO_MOSTAT_PNEXT_Pos (24UL) /*!< CAN_MO MOSTAT: PNEXT (Bit 24) */ +#define CAN_MO_MOSTAT_PNEXT_Msk (0xff000000UL) /*!< CAN_MO MOSTAT: PNEXT (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'VADC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- VADC_CLC ---------------------------------- */ +#define VADC_CLC_DISR_Pos (0UL) /*!< VADC CLC: DISR (Bit 0) */ +#define VADC_CLC_DISR_Msk (0x1UL) /*!< VADC CLC: DISR (Bitfield-Mask: 0x01) */ +#define VADC_CLC_DISS_Pos (1UL) /*!< VADC CLC: DISS (Bit 1) */ +#define VADC_CLC_DISS_Msk (0x2UL) /*!< VADC CLC: DISS (Bitfield-Mask: 0x01) */ +#define VADC_CLC_EDIS_Pos (3UL) /*!< VADC CLC: EDIS (Bit 3) */ +#define VADC_CLC_EDIS_Msk (0x8UL) /*!< VADC CLC: EDIS (Bitfield-Mask: 0x01) */ + +/* ----------------------------------- VADC_ID ---------------------------------- */ +#define VADC_ID_MOD_REV_Pos (0UL) /*!< VADC ID: MOD_REV (Bit 0) */ +#define VADC_ID_MOD_REV_Msk (0xffUL) /*!< VADC ID: MOD_REV (Bitfield-Mask: 0xff) */ +#define VADC_ID_MOD_TYPE_Pos (8UL) /*!< VADC ID: MOD_TYPE (Bit 8) */ +#define VADC_ID_MOD_TYPE_Msk (0xff00UL) /*!< VADC ID: MOD_TYPE (Bitfield-Mask: 0xff) */ +#define VADC_ID_MOD_NUMBER_Pos (16UL) /*!< VADC ID: MOD_NUMBER (Bit 16) */ +#define VADC_ID_MOD_NUMBER_Msk (0xffff0000UL) /*!< VADC ID: MOD_NUMBER (Bitfield-Mask: 0xffff) */ + +/* ---------------------------------- VADC_OCS ---------------------------------- */ +#define VADC_OCS_TGS_Pos (0UL) /*!< VADC OCS: TGS (Bit 0) */ +#define VADC_OCS_TGS_Msk (0x3UL) /*!< VADC OCS: TGS (Bitfield-Mask: 0x03) */ +#define VADC_OCS_TGB_Pos (2UL) /*!< VADC OCS: TGB (Bit 2) */ +#define VADC_OCS_TGB_Msk (0x4UL) /*!< VADC OCS: TGB (Bitfield-Mask: 0x01) */ +#define VADC_OCS_TG_P_Pos (3UL) /*!< VADC OCS: TG_P (Bit 3) */ +#define VADC_OCS_TG_P_Msk (0x8UL) /*!< VADC OCS: TG_P (Bitfield-Mask: 0x01) */ +#define VADC_OCS_SUS_Pos (24UL) /*!< VADC OCS: SUS (Bit 24) */ +#define VADC_OCS_SUS_Msk (0xf000000UL) /*!< VADC OCS: SUS (Bitfield-Mask: 0x0f) */ +#define VADC_OCS_SUS_P_Pos (28UL) /*!< VADC OCS: SUS_P (Bit 28) */ +#define VADC_OCS_SUS_P_Msk (0x10000000UL) /*!< VADC OCS: SUS_P (Bitfield-Mask: 0x01) */ +#define VADC_OCS_SUSSTA_Pos (29UL) /*!< VADC OCS: SUSSTA (Bit 29) */ +#define VADC_OCS_SUSSTA_Msk (0x20000000UL) /*!< VADC OCS: SUSSTA (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_GLOBCFG -------------------------------- */ +#define VADC_GLOBCFG_DIVA_Pos (0UL) /*!< VADC GLOBCFG: DIVA (Bit 0) */ +#define VADC_GLOBCFG_DIVA_Msk (0x1fUL) /*!< VADC GLOBCFG: DIVA (Bitfield-Mask: 0x1f) */ +#define VADC_GLOBCFG_DCMSB_Pos (7UL) /*!< VADC GLOBCFG: DCMSB (Bit 7) */ +#define VADC_GLOBCFG_DCMSB_Msk (0x80UL) /*!< VADC GLOBCFG: DCMSB (Bitfield-Mask: 0x01) */ +#define VADC_GLOBCFG_DIVD_Pos (8UL) /*!< VADC GLOBCFG: DIVD (Bit 8) */ +#define VADC_GLOBCFG_DIVD_Msk (0x300UL) /*!< VADC GLOBCFG: DIVD (Bitfield-Mask: 0x03) */ +#define VADC_GLOBCFG_DIVWC_Pos (15UL) /*!< VADC GLOBCFG: DIVWC (Bit 15) */ +#define VADC_GLOBCFG_DIVWC_Msk (0x8000UL) /*!< VADC GLOBCFG: DIVWC (Bitfield-Mask: 0x01) */ +#define VADC_GLOBCFG_DPCAL0_Pos (16UL) /*!< VADC GLOBCFG: DPCAL0 (Bit 16) */ +#define VADC_GLOBCFG_DPCAL0_Msk (0x10000UL) /*!< VADC GLOBCFG: DPCAL0 (Bitfield-Mask: 0x01) */ +#define VADC_GLOBCFG_DPCAL1_Pos (17UL) /*!< VADC GLOBCFG: DPCAL1 (Bit 17) */ +#define VADC_GLOBCFG_DPCAL1_Msk (0x20000UL) /*!< VADC GLOBCFG: DPCAL1 (Bitfield-Mask: 0x01) */ +#define VADC_GLOBCFG_DPCAL2_Pos (18UL) /*!< VADC GLOBCFG: DPCAL2 (Bit 18) */ +#define VADC_GLOBCFG_DPCAL2_Msk (0x40000UL) /*!< VADC GLOBCFG: DPCAL2 (Bitfield-Mask: 0x01) */ +#define VADC_GLOBCFG_DPCAL3_Pos (19UL) /*!< VADC GLOBCFG: DPCAL3 (Bit 19) */ +#define VADC_GLOBCFG_DPCAL3_Msk (0x80000UL) /*!< VADC GLOBCFG: DPCAL3 (Bitfield-Mask: 0x01) */ +#define VADC_GLOBCFG_SUCAL_Pos (31UL) /*!< VADC GLOBCFG: SUCAL (Bit 31) */ +#define VADC_GLOBCFG_SUCAL_Msk (0x80000000UL) /*!< VADC GLOBCFG: SUCAL (Bitfield-Mask: 0x01) */ + +/* ------------------------------- VADC_GLOBICLASS ------------------------------ */ +#define VADC_GLOBICLASS_STCS_Pos (0UL) /*!< VADC GLOBICLASS: STCS (Bit 0) */ +#define VADC_GLOBICLASS_STCS_Msk (0x1fUL) /*!< VADC GLOBICLASS: STCS (Bitfield-Mask: 0x1f) */ +#define VADC_GLOBICLASS_CMS_Pos (8UL) /*!< VADC GLOBICLASS: CMS (Bit 8) */ +#define VADC_GLOBICLASS_CMS_Msk (0x700UL) /*!< VADC GLOBICLASS: CMS (Bitfield-Mask: 0x07) */ +#define VADC_GLOBICLASS_STCE_Pos (16UL) /*!< VADC GLOBICLASS: STCE (Bit 16) */ +#define VADC_GLOBICLASS_STCE_Msk (0x1f0000UL) /*!< VADC GLOBICLASS: STCE (Bitfield-Mask: 0x1f) */ +#define VADC_GLOBICLASS_CME_Pos (24UL) /*!< VADC GLOBICLASS: CME (Bit 24) */ +#define VADC_GLOBICLASS_CME_Msk (0x7000000UL) /*!< VADC GLOBICLASS: CME (Bitfield-Mask: 0x07) */ + +/* ------------------------------- VADC_GLOBBOUND ------------------------------- */ +#define VADC_GLOBBOUND_BOUNDARY0_Pos (0UL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bit 0) */ +#define VADC_GLOBBOUND_BOUNDARY0_Msk (0xfffUL) /*!< VADC GLOBBOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ +#define VADC_GLOBBOUND_BOUNDARY1_Pos (16UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bit 16) */ +#define VADC_GLOBBOUND_BOUNDARY1_Msk (0xfff0000UL) /*!< VADC GLOBBOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ + +/* ------------------------------- VADC_GLOBEFLAG ------------------------------- */ +#define VADC_GLOBEFLAG_SEVGLB_Pos (0UL) /*!< VADC GLOBEFLAG: SEVGLB (Bit 0) */ +#define VADC_GLOBEFLAG_SEVGLB_Msk (0x1UL) /*!< VADC GLOBEFLAG: SEVGLB (Bitfield-Mask: 0x01) */ +#define VADC_GLOBEFLAG_REVGLB_Pos (8UL) /*!< VADC GLOBEFLAG: REVGLB (Bit 8) */ +#define VADC_GLOBEFLAG_REVGLB_Msk (0x100UL) /*!< VADC GLOBEFLAG: REVGLB (Bitfield-Mask: 0x01) */ +#define VADC_GLOBEFLAG_SEVGLBCLR_Pos (16UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bit 16) */ +#define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x10000UL) /*!< VADC GLOBEFLAG: SEVGLBCLR (Bitfield-Mask: 0x01) */ +#define VADC_GLOBEFLAG_REVGLBCLR_Pos (24UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bit 24) */ +#define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x1000000UL) /*!< VADC GLOBEFLAG: REVGLBCLR (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_GLOBEVNP ------------------------------- */ +#define VADC_GLOBEVNP_SEV0NP_Pos (0UL) /*!< VADC GLOBEVNP: SEV0NP (Bit 0) */ +#define VADC_GLOBEVNP_SEV0NP_Msk (0xfUL) /*!< VADC GLOBEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ +#define VADC_GLOBEVNP_REV0NP_Pos (16UL) /*!< VADC GLOBEVNP: REV0NP (Bit 16) */ +#define VADC_GLOBEVNP_REV0NP_Msk (0xf0000UL) /*!< VADC GLOBEVNP: REV0NP (Bitfield-Mask: 0x0f) */ + +/* --------------------------------- VADC_GLOBTF -------------------------------- */ +#define VADC_GLOBTF_CDGR_Pos (4UL) /*!< VADC GLOBTF: CDGR (Bit 4) */ +#define VADC_GLOBTF_CDGR_Msk (0xf0UL) /*!< VADC GLOBTF: CDGR (Bitfield-Mask: 0x0f) */ +#define VADC_GLOBTF_CDEN_Pos (8UL) /*!< VADC GLOBTF: CDEN (Bit 8) */ +#define VADC_GLOBTF_CDEN_Msk (0x100UL) /*!< VADC GLOBTF: CDEN (Bitfield-Mask: 0x01) */ +#define VADC_GLOBTF_CDSEL_Pos (9UL) /*!< VADC GLOBTF: CDSEL (Bit 9) */ +#define VADC_GLOBTF_CDSEL_Msk (0x600UL) /*!< VADC GLOBTF: CDSEL (Bitfield-Mask: 0x03) */ +#define VADC_GLOBTF_CDWC_Pos (15UL) /*!< VADC GLOBTF: CDWC (Bit 15) */ +#define VADC_GLOBTF_CDWC_Msk (0x8000UL) /*!< VADC GLOBTF: CDWC (Bitfield-Mask: 0x01) */ +#define VADC_GLOBTF_PDD_Pos (16UL) /*!< VADC GLOBTF: PDD (Bit 16) */ +#define VADC_GLOBTF_PDD_Msk (0x10000UL) /*!< VADC GLOBTF: PDD (Bitfield-Mask: 0x01) */ +#define VADC_GLOBTF_MDWC_Pos (23UL) /*!< VADC GLOBTF: MDWC (Bit 23) */ +#define VADC_GLOBTF_MDWC_Msk (0x800000UL) /*!< VADC GLOBTF: MDWC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_BRSSEL -------------------------------- */ +#define VADC_BRSSEL_CHSELG0_Pos (0UL) /*!< VADC BRSSEL: CHSELG0 (Bit 0) */ +#define VADC_BRSSEL_CHSELG0_Msk (0x1UL) /*!< VADC BRSSEL: CHSELG0 (Bitfield-Mask: 0x01) */ +#define VADC_BRSSEL_CHSELG1_Pos (1UL) /*!< VADC BRSSEL: CHSELG1 (Bit 1) */ +#define VADC_BRSSEL_CHSELG1_Msk (0x2UL) /*!< VADC BRSSEL: CHSELG1 (Bitfield-Mask: 0x01) */ +#define VADC_BRSSEL_CHSELG2_Pos (2UL) /*!< VADC BRSSEL: CHSELG2 (Bit 2) */ +#define VADC_BRSSEL_CHSELG2_Msk (0x4UL) /*!< VADC BRSSEL: CHSELG2 (Bitfield-Mask: 0x01) */ +#define VADC_BRSSEL_CHSELG3_Pos (3UL) /*!< VADC BRSSEL: CHSELG3 (Bit 3) */ +#define VADC_BRSSEL_CHSELG3_Msk (0x8UL) /*!< VADC BRSSEL: CHSELG3 (Bitfield-Mask: 0x01) */ +#define VADC_BRSSEL_CHSELG4_Pos (4UL) /*!< VADC BRSSEL: CHSELG4 (Bit 4) */ +#define VADC_BRSSEL_CHSELG4_Msk (0x10UL) /*!< VADC BRSSEL: CHSELG4 (Bitfield-Mask: 0x01) */ +#define VADC_BRSSEL_CHSELG5_Pos (5UL) /*!< VADC BRSSEL: CHSELG5 (Bit 5) */ +#define VADC_BRSSEL_CHSELG5_Msk (0x20UL) /*!< VADC BRSSEL: CHSELG5 (Bitfield-Mask: 0x01) */ +#define VADC_BRSSEL_CHSELG6_Pos (6UL) /*!< VADC BRSSEL: CHSELG6 (Bit 6) */ +#define VADC_BRSSEL_CHSELG6_Msk (0x40UL) /*!< VADC BRSSEL: CHSELG6 (Bitfield-Mask: 0x01) */ +#define VADC_BRSSEL_CHSELG7_Pos (7UL) /*!< VADC BRSSEL: CHSELG7 (Bit 7) */ +#define VADC_BRSSEL_CHSELG7_Msk (0x80UL) /*!< VADC BRSSEL: CHSELG7 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_BRSPND -------------------------------- */ +#define VADC_BRSPND_CHPNDG0_Pos (0UL) /*!< VADC BRSPND: CHPNDG0 (Bit 0) */ +#define VADC_BRSPND_CHPNDG0_Msk (0x1UL) /*!< VADC BRSPND: CHPNDG0 (Bitfield-Mask: 0x01) */ +#define VADC_BRSPND_CHPNDG1_Pos (1UL) /*!< VADC BRSPND: CHPNDG1 (Bit 1) */ +#define VADC_BRSPND_CHPNDG1_Msk (0x2UL) /*!< VADC BRSPND: CHPNDG1 (Bitfield-Mask: 0x01) */ +#define VADC_BRSPND_CHPNDG2_Pos (2UL) /*!< VADC BRSPND: CHPNDG2 (Bit 2) */ +#define VADC_BRSPND_CHPNDG2_Msk (0x4UL) /*!< VADC BRSPND: CHPNDG2 (Bitfield-Mask: 0x01) */ +#define VADC_BRSPND_CHPNDG3_Pos (3UL) /*!< VADC BRSPND: CHPNDG3 (Bit 3) */ +#define VADC_BRSPND_CHPNDG3_Msk (0x8UL) /*!< VADC BRSPND: CHPNDG3 (Bitfield-Mask: 0x01) */ +#define VADC_BRSPND_CHPNDG4_Pos (4UL) /*!< VADC BRSPND: CHPNDG4 (Bit 4) */ +#define VADC_BRSPND_CHPNDG4_Msk (0x10UL) /*!< VADC BRSPND: CHPNDG4 (Bitfield-Mask: 0x01) */ +#define VADC_BRSPND_CHPNDG5_Pos (5UL) /*!< VADC BRSPND: CHPNDG5 (Bit 5) */ +#define VADC_BRSPND_CHPNDG5_Msk (0x20UL) /*!< VADC BRSPND: CHPNDG5 (Bitfield-Mask: 0x01) */ +#define VADC_BRSPND_CHPNDG6_Pos (6UL) /*!< VADC BRSPND: CHPNDG6 (Bit 6) */ +#define VADC_BRSPND_CHPNDG6_Msk (0x40UL) /*!< VADC BRSPND: CHPNDG6 (Bitfield-Mask: 0x01) */ +#define VADC_BRSPND_CHPNDG7_Pos (7UL) /*!< VADC BRSPND: CHPNDG7 (Bit 7) */ +#define VADC_BRSPND_CHPNDG7_Msk (0x80UL) /*!< VADC BRSPND: CHPNDG7 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_BRSCTRL -------------------------------- */ +#define VADC_BRSCTRL_SRCRESREG_Pos (0UL) /*!< VADC BRSCTRL: SRCRESREG (Bit 0) */ +#define VADC_BRSCTRL_SRCRESREG_Msk (0xfUL) /*!< VADC BRSCTRL: SRCRESREG (Bitfield-Mask: 0x0f) */ +#define VADC_BRSCTRL_XTSEL_Pos (8UL) /*!< VADC BRSCTRL: XTSEL (Bit 8) */ +#define VADC_BRSCTRL_XTSEL_Msk (0xf00UL) /*!< VADC BRSCTRL: XTSEL (Bitfield-Mask: 0x0f) */ +#define VADC_BRSCTRL_XTLVL_Pos (12UL) /*!< VADC BRSCTRL: XTLVL (Bit 12) */ +#define VADC_BRSCTRL_XTLVL_Msk (0x1000UL) /*!< VADC BRSCTRL: XTLVL (Bitfield-Mask: 0x01) */ +#define VADC_BRSCTRL_XTMODE_Pos (13UL) /*!< VADC BRSCTRL: XTMODE (Bit 13) */ +#define VADC_BRSCTRL_XTMODE_Msk (0x6000UL) /*!< VADC BRSCTRL: XTMODE (Bitfield-Mask: 0x03) */ +#define VADC_BRSCTRL_XTWC_Pos (15UL) /*!< VADC BRSCTRL: XTWC (Bit 15) */ +#define VADC_BRSCTRL_XTWC_Msk (0x8000UL) /*!< VADC BRSCTRL: XTWC (Bitfield-Mask: 0x01) */ +#define VADC_BRSCTRL_GTSEL_Pos (16UL) /*!< VADC BRSCTRL: GTSEL (Bit 16) */ +#define VADC_BRSCTRL_GTSEL_Msk (0xf0000UL) /*!< VADC BRSCTRL: GTSEL (Bitfield-Mask: 0x0f) */ +#define VADC_BRSCTRL_GTLVL_Pos (20UL) /*!< VADC BRSCTRL: GTLVL (Bit 20) */ +#define VADC_BRSCTRL_GTLVL_Msk (0x100000UL) /*!< VADC BRSCTRL: GTLVL (Bitfield-Mask: 0x01) */ +#define VADC_BRSCTRL_GTWC_Pos (23UL) /*!< VADC BRSCTRL: GTWC (Bit 23) */ +#define VADC_BRSCTRL_GTWC_Msk (0x800000UL) /*!< VADC BRSCTRL: GTWC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_BRSMR --------------------------------- */ +#define VADC_BRSMR_ENGT_Pos (0UL) /*!< VADC BRSMR: ENGT (Bit 0) */ +#define VADC_BRSMR_ENGT_Msk (0x3UL) /*!< VADC BRSMR: ENGT (Bitfield-Mask: 0x03) */ +#define VADC_BRSMR_ENTR_Pos (2UL) /*!< VADC BRSMR: ENTR (Bit 2) */ +#define VADC_BRSMR_ENTR_Msk (0x4UL) /*!< VADC BRSMR: ENTR (Bitfield-Mask: 0x01) */ +#define VADC_BRSMR_ENSI_Pos (3UL) /*!< VADC BRSMR: ENSI (Bit 3) */ +#define VADC_BRSMR_ENSI_Msk (0x8UL) /*!< VADC BRSMR: ENSI (Bitfield-Mask: 0x01) */ +#define VADC_BRSMR_SCAN_Pos (4UL) /*!< VADC BRSMR: SCAN (Bit 4) */ +#define VADC_BRSMR_SCAN_Msk (0x10UL) /*!< VADC BRSMR: SCAN (Bitfield-Mask: 0x01) */ +#define VADC_BRSMR_LDM_Pos (5UL) /*!< VADC BRSMR: LDM (Bit 5) */ +#define VADC_BRSMR_LDM_Msk (0x20UL) /*!< VADC BRSMR: LDM (Bitfield-Mask: 0x01) */ +#define VADC_BRSMR_REQGT_Pos (7UL) /*!< VADC BRSMR: REQGT (Bit 7) */ +#define VADC_BRSMR_REQGT_Msk (0x80UL) /*!< VADC BRSMR: REQGT (Bitfield-Mask: 0x01) */ +#define VADC_BRSMR_CLRPND_Pos (8UL) /*!< VADC BRSMR: CLRPND (Bit 8) */ +#define VADC_BRSMR_CLRPND_Msk (0x100UL) /*!< VADC BRSMR: CLRPND (Bitfield-Mask: 0x01) */ +#define VADC_BRSMR_LDEV_Pos (9UL) /*!< VADC BRSMR: LDEV (Bit 9) */ +#define VADC_BRSMR_LDEV_Msk (0x200UL) /*!< VADC BRSMR: LDEV (Bitfield-Mask: 0x01) */ +#define VADC_BRSMR_RPTDIS_Pos (16UL) /*!< VADC BRSMR: RPTDIS (Bit 16) */ +#define VADC_BRSMR_RPTDIS_Msk (0x10000UL) /*!< VADC BRSMR: RPTDIS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_GLOBRCR -------------------------------- */ +#define VADC_GLOBRCR_DRCTR_Pos (16UL) /*!< VADC GLOBRCR: DRCTR (Bit 16) */ +#define VADC_GLOBRCR_DRCTR_Msk (0xf0000UL) /*!< VADC GLOBRCR: DRCTR (Bitfield-Mask: 0x0f) */ +#define VADC_GLOBRCR_WFR_Pos (24UL) /*!< VADC GLOBRCR: WFR (Bit 24) */ +#define VADC_GLOBRCR_WFR_Msk (0x1000000UL) /*!< VADC GLOBRCR: WFR (Bitfield-Mask: 0x01) */ +#define VADC_GLOBRCR_SRGEN_Pos (31UL) /*!< VADC GLOBRCR: SRGEN (Bit 31) */ +#define VADC_GLOBRCR_SRGEN_Msk (0x80000000UL) /*!< VADC GLOBRCR: SRGEN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_GLOBRES -------------------------------- */ +#define VADC_GLOBRES_RESULT_Pos (0UL) /*!< VADC GLOBRES: RESULT (Bit 0) */ +#define VADC_GLOBRES_RESULT_Msk (0xffffUL) /*!< VADC GLOBRES: RESULT (Bitfield-Mask: 0xffff) */ +#define VADC_GLOBRES_GNR_Pos (16UL) /*!< VADC GLOBRES: GNR (Bit 16) */ +#define VADC_GLOBRES_GNR_Msk (0xf0000UL) /*!< VADC GLOBRES: GNR (Bitfield-Mask: 0x0f) */ +#define VADC_GLOBRES_CHNR_Pos (20UL) /*!< VADC GLOBRES: CHNR (Bit 20) */ +#define VADC_GLOBRES_CHNR_Msk (0x1f00000UL) /*!< VADC GLOBRES: CHNR (Bitfield-Mask: 0x1f) */ +#define VADC_GLOBRES_EMUX_Pos (25UL) /*!< VADC GLOBRES: EMUX (Bit 25) */ +#define VADC_GLOBRES_EMUX_Msk (0xe000000UL) /*!< VADC GLOBRES: EMUX (Bitfield-Mask: 0x07) */ +#define VADC_GLOBRES_CRS_Pos (28UL) /*!< VADC GLOBRES: CRS (Bit 28) */ +#define VADC_GLOBRES_CRS_Msk (0x30000000UL) /*!< VADC GLOBRES: CRS (Bitfield-Mask: 0x03) */ +#define VADC_GLOBRES_FCR_Pos (30UL) /*!< VADC GLOBRES: FCR (Bit 30) */ +#define VADC_GLOBRES_FCR_Msk (0x40000000UL) /*!< VADC GLOBRES: FCR (Bitfield-Mask: 0x01) */ +#define VADC_GLOBRES_VF_Pos (31UL) /*!< VADC GLOBRES: VF (Bit 31) */ +#define VADC_GLOBRES_VF_Msk (0x80000000UL) /*!< VADC GLOBRES: VF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_GLOBRESD ------------------------------- */ +#define VADC_GLOBRESD_RESULT_Pos (0UL) /*!< VADC GLOBRESD: RESULT (Bit 0) */ +#define VADC_GLOBRESD_RESULT_Msk (0xffffUL) /*!< VADC GLOBRESD: RESULT (Bitfield-Mask: 0xffff) */ +#define VADC_GLOBRESD_GNR_Pos (16UL) /*!< VADC GLOBRESD: GNR (Bit 16) */ +#define VADC_GLOBRESD_GNR_Msk (0xf0000UL) /*!< VADC GLOBRESD: GNR (Bitfield-Mask: 0x0f) */ +#define VADC_GLOBRESD_CHNR_Pos (20UL) /*!< VADC GLOBRESD: CHNR (Bit 20) */ +#define VADC_GLOBRESD_CHNR_Msk (0x1f00000UL) /*!< VADC GLOBRESD: CHNR (Bitfield-Mask: 0x1f) */ +#define VADC_GLOBRESD_EMUX_Pos (25UL) /*!< VADC GLOBRESD: EMUX (Bit 25) */ +#define VADC_GLOBRESD_EMUX_Msk (0xe000000UL) /*!< VADC GLOBRESD: EMUX (Bitfield-Mask: 0x07) */ +#define VADC_GLOBRESD_CRS_Pos (28UL) /*!< VADC GLOBRESD: CRS (Bit 28) */ +#define VADC_GLOBRESD_CRS_Msk (0x30000000UL) /*!< VADC GLOBRESD: CRS (Bitfield-Mask: 0x03) */ +#define VADC_GLOBRESD_FCR_Pos (30UL) /*!< VADC GLOBRESD: FCR (Bit 30) */ +#define VADC_GLOBRESD_FCR_Msk (0x40000000UL) /*!< VADC GLOBRESD: FCR (Bitfield-Mask: 0x01) */ +#define VADC_GLOBRESD_VF_Pos (31UL) /*!< VADC GLOBRESD: VF (Bit 31) */ +#define VADC_GLOBRESD_VF_Msk (0x80000000UL) /*!< VADC GLOBRESD: VF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_EMUXSEL -------------------------------- */ +#define VADC_EMUXSEL_EMUXGRP0_Pos (0UL) /*!< VADC EMUXSEL: EMUXGRP0 (Bit 0) */ +#define VADC_EMUXSEL_EMUXGRP0_Msk (0xfUL) /*!< VADC EMUXSEL: EMUXGRP0 (Bitfield-Mask: 0x0f) */ +#define VADC_EMUXSEL_EMUXGRP1_Pos (4UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bit 4) */ +#define VADC_EMUXSEL_EMUXGRP1_Msk (0xf0UL) /*!< VADC EMUXSEL: EMUXGRP1 (Bitfield-Mask: 0x0f) */ + + +/* ================================================================================ */ +/* ================ Group 'VADC_G' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- VADC_G_ARBCFG ------------------------------- */ +#define VADC_G_ARBCFG_ANONC_Pos (0UL) /*!< VADC_G ARBCFG: ANONC (Bit 0) */ +#define VADC_G_ARBCFG_ANONC_Msk (0x3UL) /*!< VADC_G ARBCFG: ANONC (Bitfield-Mask: 0x03) */ +#define VADC_G_ARBCFG_ARBRND_Pos (4UL) /*!< VADC_G ARBCFG: ARBRND (Bit 4) */ +#define VADC_G_ARBCFG_ARBRND_Msk (0x30UL) /*!< VADC_G ARBCFG: ARBRND (Bitfield-Mask: 0x03) */ +#define VADC_G_ARBCFG_ARBM_Pos (7UL) /*!< VADC_G ARBCFG: ARBM (Bit 7) */ +#define VADC_G_ARBCFG_ARBM_Msk (0x80UL) /*!< VADC_G ARBCFG: ARBM (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBCFG_ANONS_Pos (16UL) /*!< VADC_G ARBCFG: ANONS (Bit 16) */ +#define VADC_G_ARBCFG_ANONS_Msk (0x30000UL) /*!< VADC_G ARBCFG: ANONS (Bitfield-Mask: 0x03) */ +#define VADC_G_ARBCFG_CAL_Pos (28UL) /*!< VADC_G ARBCFG: CAL (Bit 28) */ +#define VADC_G_ARBCFG_CAL_Msk (0x10000000UL) /*!< VADC_G ARBCFG: CAL (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBCFG_BUSY_Pos (30UL) /*!< VADC_G ARBCFG: BUSY (Bit 30) */ +#define VADC_G_ARBCFG_BUSY_Msk (0x40000000UL) /*!< VADC_G ARBCFG: BUSY (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBCFG_SAMPLE_Pos (31UL) /*!< VADC_G ARBCFG: SAMPLE (Bit 31) */ +#define VADC_G_ARBCFG_SAMPLE_Msk (0x80000000UL) /*!< VADC_G ARBCFG: SAMPLE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_ARBPR -------------------------------- */ +#define VADC_G_ARBPR_PRIO0_Pos (0UL) /*!< VADC_G ARBPR: PRIO0 (Bit 0) */ +#define VADC_G_ARBPR_PRIO0_Msk (0x3UL) /*!< VADC_G ARBPR: PRIO0 (Bitfield-Mask: 0x03) */ +#define VADC_G_ARBPR_CSM0_Pos (3UL) /*!< VADC_G ARBPR: CSM0 (Bit 3) */ +#define VADC_G_ARBPR_CSM0_Msk (0x8UL) /*!< VADC_G ARBPR: CSM0 (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBPR_PRIO1_Pos (4UL) /*!< VADC_G ARBPR: PRIO1 (Bit 4) */ +#define VADC_G_ARBPR_PRIO1_Msk (0x30UL) /*!< VADC_G ARBPR: PRIO1 (Bitfield-Mask: 0x03) */ +#define VADC_G_ARBPR_CSM1_Pos (7UL) /*!< VADC_G ARBPR: CSM1 (Bit 7) */ +#define VADC_G_ARBPR_CSM1_Msk (0x80UL) /*!< VADC_G ARBPR: CSM1 (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBPR_PRIO2_Pos (8UL) /*!< VADC_G ARBPR: PRIO2 (Bit 8) */ +#define VADC_G_ARBPR_PRIO2_Msk (0x300UL) /*!< VADC_G ARBPR: PRIO2 (Bitfield-Mask: 0x03) */ +#define VADC_G_ARBPR_CSM2_Pos (11UL) /*!< VADC_G ARBPR: CSM2 (Bit 11) */ +#define VADC_G_ARBPR_CSM2_Msk (0x800UL) /*!< VADC_G ARBPR: CSM2 (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBPR_ASEN0_Pos (24UL) /*!< VADC_G ARBPR: ASEN0 (Bit 24) */ +#define VADC_G_ARBPR_ASEN0_Msk (0x1000000UL) /*!< VADC_G ARBPR: ASEN0 (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBPR_ASEN1_Pos (25UL) /*!< VADC_G ARBPR: ASEN1 (Bit 25) */ +#define VADC_G_ARBPR_ASEN1_Msk (0x2000000UL) /*!< VADC_G ARBPR: ASEN1 (Bitfield-Mask: 0x01) */ +#define VADC_G_ARBPR_ASEN2_Pos (26UL) /*!< VADC_G ARBPR: ASEN2 (Bit 26) */ +#define VADC_G_ARBPR_ASEN2_Msk (0x4000000UL) /*!< VADC_G ARBPR: ASEN2 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_CHASS -------------------------------- */ +#define VADC_G_CHASS_ASSCH0_Pos (0UL) /*!< VADC_G CHASS: ASSCH0 (Bit 0) */ +#define VADC_G_CHASS_ASSCH0_Msk (0x1UL) /*!< VADC_G CHASS: ASSCH0 (Bitfield-Mask: 0x01) */ +#define VADC_G_CHASS_ASSCH1_Pos (1UL) /*!< VADC_G CHASS: ASSCH1 (Bit 1) */ +#define VADC_G_CHASS_ASSCH1_Msk (0x2UL) /*!< VADC_G CHASS: ASSCH1 (Bitfield-Mask: 0x01) */ +#define VADC_G_CHASS_ASSCH2_Pos (2UL) /*!< VADC_G CHASS: ASSCH2 (Bit 2) */ +#define VADC_G_CHASS_ASSCH2_Msk (0x4UL) /*!< VADC_G CHASS: ASSCH2 (Bitfield-Mask: 0x01) */ +#define VADC_G_CHASS_ASSCH3_Pos (3UL) /*!< VADC_G CHASS: ASSCH3 (Bit 3) */ +#define VADC_G_CHASS_ASSCH3_Msk (0x8UL) /*!< VADC_G CHASS: ASSCH3 (Bitfield-Mask: 0x01) */ +#define VADC_G_CHASS_ASSCH4_Pos (4UL) /*!< VADC_G CHASS: ASSCH4 (Bit 4) */ +#define VADC_G_CHASS_ASSCH4_Msk (0x10UL) /*!< VADC_G CHASS: ASSCH4 (Bitfield-Mask: 0x01) */ +#define VADC_G_CHASS_ASSCH5_Pos (5UL) /*!< VADC_G CHASS: ASSCH5 (Bit 5) */ +#define VADC_G_CHASS_ASSCH5_Msk (0x20UL) /*!< VADC_G CHASS: ASSCH5 (Bitfield-Mask: 0x01) */ +#define VADC_G_CHASS_ASSCH6_Pos (6UL) /*!< VADC_G CHASS: ASSCH6 (Bit 6) */ +#define VADC_G_CHASS_ASSCH6_Msk (0x40UL) /*!< VADC_G CHASS: ASSCH6 (Bitfield-Mask: 0x01) */ +#define VADC_G_CHASS_ASSCH7_Pos (7UL) /*!< VADC_G CHASS: ASSCH7 (Bit 7) */ +#define VADC_G_CHASS_ASSCH7_Msk (0x80UL) /*!< VADC_G CHASS: ASSCH7 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_ICLASS ------------------------------- */ +#define VADC_G_ICLASS_STCS_Pos (0UL) /*!< VADC_G ICLASS: STCS (Bit 0) */ +#define VADC_G_ICLASS_STCS_Msk (0x1fUL) /*!< VADC_G ICLASS: STCS (Bitfield-Mask: 0x1f) */ +#define VADC_G_ICLASS_CMS_Pos (8UL) /*!< VADC_G ICLASS: CMS (Bit 8) */ +#define VADC_G_ICLASS_CMS_Msk (0x700UL) /*!< VADC_G ICLASS: CMS (Bitfield-Mask: 0x07) */ +#define VADC_G_ICLASS_STCE_Pos (16UL) /*!< VADC_G ICLASS: STCE (Bit 16) */ +#define VADC_G_ICLASS_STCE_Msk (0x1f0000UL) /*!< VADC_G ICLASS: STCE (Bitfield-Mask: 0x1f) */ +#define VADC_G_ICLASS_CME_Pos (24UL) /*!< VADC_G ICLASS: CME (Bit 24) */ +#define VADC_G_ICLASS_CME_Msk (0x7000000UL) /*!< VADC_G ICLASS: CME (Bitfield-Mask: 0x07) */ + +/* -------------------------------- VADC_G_ALIAS -------------------------------- */ +#define VADC_G_ALIAS_ALIAS0_Pos (0UL) /*!< VADC_G ALIAS: ALIAS0 (Bit 0) */ +#define VADC_G_ALIAS_ALIAS0_Msk (0x1fUL) /*!< VADC_G ALIAS: ALIAS0 (Bitfield-Mask: 0x1f) */ +#define VADC_G_ALIAS_ALIAS1_Pos (8UL) /*!< VADC_G ALIAS: ALIAS1 (Bit 8) */ +#define VADC_G_ALIAS_ALIAS1_Msk (0x1f00UL) /*!< VADC_G ALIAS: ALIAS1 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- VADC_G_BOUND -------------------------------- */ +#define VADC_G_BOUND_BOUNDARY0_Pos (0UL) /*!< VADC_G BOUND: BOUNDARY0 (Bit 0) */ +#define VADC_G_BOUND_BOUNDARY0_Msk (0xfffUL) /*!< VADC_G BOUND: BOUNDARY0 (Bitfield-Mask: 0xfff) */ +#define VADC_G_BOUND_BOUNDARY1_Pos (16UL) /*!< VADC_G BOUND: BOUNDARY1 (Bit 16) */ +#define VADC_G_BOUND_BOUNDARY1_Msk (0xfff0000UL) /*!< VADC_G BOUND: BOUNDARY1 (Bitfield-Mask: 0xfff) */ + +/* -------------------------------- VADC_G_SYNCTR ------------------------------- */ +#define VADC_G_SYNCTR_STSEL_Pos (0UL) /*!< VADC_G SYNCTR: STSEL (Bit 0) */ +#define VADC_G_SYNCTR_STSEL_Msk (0x3UL) /*!< VADC_G SYNCTR: STSEL (Bitfield-Mask: 0x03) */ +#define VADC_G_SYNCTR_EVALR1_Pos (4UL) /*!< VADC_G SYNCTR: EVALR1 (Bit 4) */ +#define VADC_G_SYNCTR_EVALR1_Msk (0x10UL) /*!< VADC_G SYNCTR: EVALR1 (Bitfield-Mask: 0x01) */ +#define VADC_G_SYNCTR_EVALR2_Pos (5UL) /*!< VADC_G SYNCTR: EVALR2 (Bit 5) */ +#define VADC_G_SYNCTR_EVALR2_Msk (0x20UL) /*!< VADC_G SYNCTR: EVALR2 (Bitfield-Mask: 0x01) */ +#define VADC_G_SYNCTR_EVALR3_Pos (6UL) /*!< VADC_G SYNCTR: EVALR3 (Bit 6) */ +#define VADC_G_SYNCTR_EVALR3_Msk (0x40UL) /*!< VADC_G SYNCTR: EVALR3 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_BFL --------------------------------- */ +#define VADC_G_BFL_BFL0_Pos (0UL) /*!< VADC_G BFL: BFL0 (Bit 0) */ +#define VADC_G_BFL_BFL0_Msk (0x1UL) /*!< VADC_G BFL: BFL0 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFL1_Pos (1UL) /*!< VADC_G BFL: BFL1 (Bit 1) */ +#define VADC_G_BFL_BFL1_Msk (0x2UL) /*!< VADC_G BFL: BFL1 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFL2_Pos (2UL) /*!< VADC_G BFL: BFL2 (Bit 2) */ +#define VADC_G_BFL_BFL2_Msk (0x4UL) /*!< VADC_G BFL: BFL2 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFL3_Pos (3UL) /*!< VADC_G BFL: BFL3 (Bit 3) */ +#define VADC_G_BFL_BFL3_Msk (0x8UL) /*!< VADC_G BFL: BFL3 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFA0_Pos (8UL) /*!< VADC_G BFL: BFA0 (Bit 8) */ +#define VADC_G_BFL_BFA0_Msk (0x100UL) /*!< VADC_G BFL: BFA0 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFA1_Pos (9UL) /*!< VADC_G BFL: BFA1 (Bit 9) */ +#define VADC_G_BFL_BFA1_Msk (0x200UL) /*!< VADC_G BFL: BFA1 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFA2_Pos (10UL) /*!< VADC_G BFL: BFA2 (Bit 10) */ +#define VADC_G_BFL_BFA2_Msk (0x400UL) /*!< VADC_G BFL: BFA2 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFA3_Pos (11UL) /*!< VADC_G BFL: BFA3 (Bit 11) */ +#define VADC_G_BFL_BFA3_Msk (0x800UL) /*!< VADC_G BFL: BFA3 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFI0_Pos (16UL) /*!< VADC_G BFL: BFI0 (Bit 16) */ +#define VADC_G_BFL_BFI0_Msk (0x10000UL) /*!< VADC_G BFL: BFI0 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFI1_Pos (17UL) /*!< VADC_G BFL: BFI1 (Bit 17) */ +#define VADC_G_BFL_BFI1_Msk (0x20000UL) /*!< VADC_G BFL: BFI1 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFI2_Pos (18UL) /*!< VADC_G BFL: BFI2 (Bit 18) */ +#define VADC_G_BFL_BFI2_Msk (0x40000UL) /*!< VADC_G BFL: BFI2 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFL_BFI3_Pos (19UL) /*!< VADC_G BFL: BFI3 (Bit 19) */ +#define VADC_G_BFL_BFI3_Msk (0x80000UL) /*!< VADC_G BFL: BFI3 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_BFLS -------------------------------- */ +#define VADC_G_BFLS_BFC0_Pos (0UL) /*!< VADC_G BFLS: BFC0 (Bit 0) */ +#define VADC_G_BFLS_BFC0_Msk (0x1UL) /*!< VADC_G BFLS: BFC0 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFLS_BFC1_Pos (1UL) /*!< VADC_G BFLS: BFC1 (Bit 1) */ +#define VADC_G_BFLS_BFC1_Msk (0x2UL) /*!< VADC_G BFLS: BFC1 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFLS_BFC2_Pos (2UL) /*!< VADC_G BFLS: BFC2 (Bit 2) */ +#define VADC_G_BFLS_BFC2_Msk (0x4UL) /*!< VADC_G BFLS: BFC2 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFLS_BFC3_Pos (3UL) /*!< VADC_G BFLS: BFC3 (Bit 3) */ +#define VADC_G_BFLS_BFC3_Msk (0x8UL) /*!< VADC_G BFLS: BFC3 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFLS_BFS0_Pos (16UL) /*!< VADC_G BFLS: BFS0 (Bit 16) */ +#define VADC_G_BFLS_BFS0_Msk (0x10000UL) /*!< VADC_G BFLS: BFS0 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFLS_BFS1_Pos (17UL) /*!< VADC_G BFLS: BFS1 (Bit 17) */ +#define VADC_G_BFLS_BFS1_Msk (0x20000UL) /*!< VADC_G BFLS: BFS1 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFLS_BFS2_Pos (18UL) /*!< VADC_G BFLS: BFS2 (Bit 18) */ +#define VADC_G_BFLS_BFS2_Msk (0x40000UL) /*!< VADC_G BFLS: BFS2 (Bitfield-Mask: 0x01) */ +#define VADC_G_BFLS_BFS3_Pos (19UL) /*!< VADC_G BFLS: BFS3 (Bit 19) */ +#define VADC_G_BFLS_BFS3_Msk (0x80000UL) /*!< VADC_G BFLS: BFS3 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_BFLC -------------------------------- */ +#define VADC_G_BFLC_BFM0_Pos (0UL) /*!< VADC_G BFLC: BFM0 (Bit 0) */ +#define VADC_G_BFLC_BFM0_Msk (0xfUL) /*!< VADC_G BFLC: BFM0 (Bitfield-Mask: 0x0f) */ +#define VADC_G_BFLC_BFM1_Pos (4UL) /*!< VADC_G BFLC: BFM1 (Bit 4) */ +#define VADC_G_BFLC_BFM1_Msk (0xf0UL) /*!< VADC_G BFLC: BFM1 (Bitfield-Mask: 0x0f) */ +#define VADC_G_BFLC_BFM2_Pos (8UL) /*!< VADC_G BFLC: BFM2 (Bit 8) */ +#define VADC_G_BFLC_BFM2_Msk (0xf00UL) /*!< VADC_G BFLC: BFM2 (Bitfield-Mask: 0x0f) */ +#define VADC_G_BFLC_BFM3_Pos (12UL) /*!< VADC_G BFLC: BFM3 (Bit 12) */ +#define VADC_G_BFLC_BFM3_Msk (0xf000UL) /*!< VADC_G BFLC: BFM3 (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- VADC_G_BFLNP -------------------------------- */ +#define VADC_G_BFLNP_BFL0NP_Pos (0UL) /*!< VADC_G BFLNP: BFL0NP (Bit 0) */ +#define VADC_G_BFLNP_BFL0NP_Msk (0xfUL) /*!< VADC_G BFLNP: BFL0NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_BFLNP_BFL1NP_Pos (4UL) /*!< VADC_G BFLNP: BFL1NP (Bit 4) */ +#define VADC_G_BFLNP_BFL1NP_Msk (0xf0UL) /*!< VADC_G BFLNP: BFL1NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_BFLNP_BFL2NP_Pos (8UL) /*!< VADC_G BFLNP: BFL2NP (Bit 8) */ +#define VADC_G_BFLNP_BFL2NP_Msk (0xf00UL) /*!< VADC_G BFLNP: BFL2NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_BFLNP_BFL3NP_Pos (12UL) /*!< VADC_G BFLNP: BFL3NP (Bit 12) */ +#define VADC_G_BFLNP_BFL3NP_Msk (0xf000UL) /*!< VADC_G BFLNP: BFL3NP (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- VADC_G_QCTRL0 ------------------------------- */ +#define VADC_G_QCTRL0_SRCRESREG_Pos (0UL) /*!< VADC_G QCTRL0: SRCRESREG (Bit 0) */ +#define VADC_G_QCTRL0_SRCRESREG_Msk (0xfUL) /*!< VADC_G QCTRL0: SRCRESREG (Bitfield-Mask: 0x0f) */ +#define VADC_G_QCTRL0_XTSEL_Pos (8UL) /*!< VADC_G QCTRL0: XTSEL (Bit 8) */ +#define VADC_G_QCTRL0_XTSEL_Msk (0xf00UL) /*!< VADC_G QCTRL0: XTSEL (Bitfield-Mask: 0x0f) */ +#define VADC_G_QCTRL0_XTLVL_Pos (12UL) /*!< VADC_G QCTRL0: XTLVL (Bit 12) */ +#define VADC_G_QCTRL0_XTLVL_Msk (0x1000UL) /*!< VADC_G QCTRL0: XTLVL (Bitfield-Mask: 0x01) */ +#define VADC_G_QCTRL0_XTMODE_Pos (13UL) /*!< VADC_G QCTRL0: XTMODE (Bit 13) */ +#define VADC_G_QCTRL0_XTMODE_Msk (0x6000UL) /*!< VADC_G QCTRL0: XTMODE (Bitfield-Mask: 0x03) */ +#define VADC_G_QCTRL0_XTWC_Pos (15UL) /*!< VADC_G QCTRL0: XTWC (Bit 15) */ +#define VADC_G_QCTRL0_XTWC_Msk (0x8000UL) /*!< VADC_G QCTRL0: XTWC (Bitfield-Mask: 0x01) */ +#define VADC_G_QCTRL0_GTSEL_Pos (16UL) /*!< VADC_G QCTRL0: GTSEL (Bit 16) */ +#define VADC_G_QCTRL0_GTSEL_Msk (0xf0000UL) /*!< VADC_G QCTRL0: GTSEL (Bitfield-Mask: 0x0f) */ +#define VADC_G_QCTRL0_GTLVL_Pos (20UL) /*!< VADC_G QCTRL0: GTLVL (Bit 20) */ +#define VADC_G_QCTRL0_GTLVL_Msk (0x100000UL) /*!< VADC_G QCTRL0: GTLVL (Bitfield-Mask: 0x01) */ +#define VADC_G_QCTRL0_GTWC_Pos (23UL) /*!< VADC_G QCTRL0: GTWC (Bit 23) */ +#define VADC_G_QCTRL0_GTWC_Msk (0x800000UL) /*!< VADC_G QCTRL0: GTWC (Bitfield-Mask: 0x01) */ +#define VADC_G_QCTRL0_TMEN_Pos (28UL) /*!< VADC_G QCTRL0: TMEN (Bit 28) */ +#define VADC_G_QCTRL0_TMEN_Msk (0x10000000UL) /*!< VADC_G QCTRL0: TMEN (Bitfield-Mask: 0x01) */ +#define VADC_G_QCTRL0_TMWC_Pos (31UL) /*!< VADC_G QCTRL0: TMWC (Bit 31) */ +#define VADC_G_QCTRL0_TMWC_Msk (0x80000000UL) /*!< VADC_G QCTRL0: TMWC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_QMR0 -------------------------------- */ +#define VADC_G_QMR0_ENGT_Pos (0UL) /*!< VADC_G QMR0: ENGT (Bit 0) */ +#define VADC_G_QMR0_ENGT_Msk (0x3UL) /*!< VADC_G QMR0: ENGT (Bitfield-Mask: 0x03) */ +#define VADC_G_QMR0_ENTR_Pos (2UL) /*!< VADC_G QMR0: ENTR (Bit 2) */ +#define VADC_G_QMR0_ENTR_Msk (0x4UL) /*!< VADC_G QMR0: ENTR (Bitfield-Mask: 0x01) */ +#define VADC_G_QMR0_CLRV_Pos (8UL) /*!< VADC_G QMR0: CLRV (Bit 8) */ +#define VADC_G_QMR0_CLRV_Msk (0x100UL) /*!< VADC_G QMR0: CLRV (Bitfield-Mask: 0x01) */ +#define VADC_G_QMR0_TREV_Pos (9UL) /*!< VADC_G QMR0: TREV (Bit 9) */ +#define VADC_G_QMR0_TREV_Msk (0x200UL) /*!< VADC_G QMR0: TREV (Bitfield-Mask: 0x01) */ +#define VADC_G_QMR0_FLUSH_Pos (10UL) /*!< VADC_G QMR0: FLUSH (Bit 10) */ +#define VADC_G_QMR0_FLUSH_Msk (0x400UL) /*!< VADC_G QMR0: FLUSH (Bitfield-Mask: 0x01) */ +#define VADC_G_QMR0_CEV_Pos (11UL) /*!< VADC_G QMR0: CEV (Bit 11) */ +#define VADC_G_QMR0_CEV_Msk (0x800UL) /*!< VADC_G QMR0: CEV (Bitfield-Mask: 0x01) */ +#define VADC_G_QMR0_RPTDIS_Pos (16UL) /*!< VADC_G QMR0: RPTDIS (Bit 16) */ +#define VADC_G_QMR0_RPTDIS_Msk (0x10000UL) /*!< VADC_G QMR0: RPTDIS (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_QSR0 -------------------------------- */ +#define VADC_G_QSR0_FILL_Pos (0UL) /*!< VADC_G QSR0: FILL (Bit 0) */ +#define VADC_G_QSR0_FILL_Msk (0xfUL) /*!< VADC_G QSR0: FILL (Bitfield-Mask: 0x0f) */ +#define VADC_G_QSR0_EMPTY_Pos (5UL) /*!< VADC_G QSR0: EMPTY (Bit 5) */ +#define VADC_G_QSR0_EMPTY_Msk (0x20UL) /*!< VADC_G QSR0: EMPTY (Bitfield-Mask: 0x01) */ +#define VADC_G_QSR0_REQGT_Pos (7UL) /*!< VADC_G QSR0: REQGT (Bit 7) */ +#define VADC_G_QSR0_REQGT_Msk (0x80UL) /*!< VADC_G QSR0: REQGT (Bitfield-Mask: 0x01) */ +#define VADC_G_QSR0_EV_Pos (8UL) /*!< VADC_G QSR0: EV (Bit 8) */ +#define VADC_G_QSR0_EV_Msk (0x100UL) /*!< VADC_G QSR0: EV (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_Q0R0 -------------------------------- */ +#define VADC_G_Q0R0_REQCHNR_Pos (0UL) /*!< VADC_G Q0R0: REQCHNR (Bit 0) */ +#define VADC_G_Q0R0_REQCHNR_Msk (0x1fUL) /*!< VADC_G Q0R0: REQCHNR (Bitfield-Mask: 0x1f) */ +#define VADC_G_Q0R0_RF_Pos (5UL) /*!< VADC_G Q0R0: RF (Bit 5) */ +#define VADC_G_Q0R0_RF_Msk (0x20UL) /*!< VADC_G Q0R0: RF (Bitfield-Mask: 0x01) */ +#define VADC_G_Q0R0_ENSI_Pos (6UL) /*!< VADC_G Q0R0: ENSI (Bit 6) */ +#define VADC_G_Q0R0_ENSI_Msk (0x40UL) /*!< VADC_G Q0R0: ENSI (Bitfield-Mask: 0x01) */ +#define VADC_G_Q0R0_EXTR_Pos (7UL) /*!< VADC_G Q0R0: EXTR (Bit 7) */ +#define VADC_G_Q0R0_EXTR_Msk (0x80UL) /*!< VADC_G Q0R0: EXTR (Bitfield-Mask: 0x01) */ +#define VADC_G_Q0R0_V_Pos (8UL) /*!< VADC_G Q0R0: V (Bit 8) */ +#define VADC_G_Q0R0_V_Msk (0x100UL) /*!< VADC_G Q0R0: V (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_QINR0 -------------------------------- */ +#define VADC_G_QINR0_REQCHNR_Pos (0UL) /*!< VADC_G QINR0: REQCHNR (Bit 0) */ +#define VADC_G_QINR0_REQCHNR_Msk (0x1fUL) /*!< VADC_G QINR0: REQCHNR (Bitfield-Mask: 0x1f) */ +#define VADC_G_QINR0_RF_Pos (5UL) /*!< VADC_G QINR0: RF (Bit 5) */ +#define VADC_G_QINR0_RF_Msk (0x20UL) /*!< VADC_G QINR0: RF (Bitfield-Mask: 0x01) */ +#define VADC_G_QINR0_ENSI_Pos (6UL) /*!< VADC_G QINR0: ENSI (Bit 6) */ +#define VADC_G_QINR0_ENSI_Msk (0x40UL) /*!< VADC_G QINR0: ENSI (Bitfield-Mask: 0x01) */ +#define VADC_G_QINR0_EXTR_Pos (7UL) /*!< VADC_G QINR0: EXTR (Bit 7) */ +#define VADC_G_QINR0_EXTR_Msk (0x80UL) /*!< VADC_G QINR0: EXTR (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_QBUR0 -------------------------------- */ +#define VADC_G_QBUR0_REQCHNR_Pos (0UL) /*!< VADC_G QBUR0: REQCHNR (Bit 0) */ +#define VADC_G_QBUR0_REQCHNR_Msk (0x1fUL) /*!< VADC_G QBUR0: REQCHNR (Bitfield-Mask: 0x1f) */ +#define VADC_G_QBUR0_RF_Pos (5UL) /*!< VADC_G QBUR0: RF (Bit 5) */ +#define VADC_G_QBUR0_RF_Msk (0x20UL) /*!< VADC_G QBUR0: RF (Bitfield-Mask: 0x01) */ +#define VADC_G_QBUR0_ENSI_Pos (6UL) /*!< VADC_G QBUR0: ENSI (Bit 6) */ +#define VADC_G_QBUR0_ENSI_Msk (0x40UL) /*!< VADC_G QBUR0: ENSI (Bitfield-Mask: 0x01) */ +#define VADC_G_QBUR0_EXTR_Pos (7UL) /*!< VADC_G QBUR0: EXTR (Bit 7) */ +#define VADC_G_QBUR0_EXTR_Msk (0x80UL) /*!< VADC_G QBUR0: EXTR (Bitfield-Mask: 0x01) */ +#define VADC_G_QBUR0_V_Pos (8UL) /*!< VADC_G QBUR0: V (Bit 8) */ +#define VADC_G_QBUR0_V_Msk (0x100UL) /*!< VADC_G QBUR0: V (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_ASCTRL ------------------------------- */ +#define VADC_G_ASCTRL_SRCRESREG_Pos (0UL) /*!< VADC_G ASCTRL: SRCRESREG (Bit 0) */ +#define VADC_G_ASCTRL_SRCRESREG_Msk (0xfUL) /*!< VADC_G ASCTRL: SRCRESREG (Bitfield-Mask: 0x0f) */ +#define VADC_G_ASCTRL_XTSEL_Pos (8UL) /*!< VADC_G ASCTRL: XTSEL (Bit 8) */ +#define VADC_G_ASCTRL_XTSEL_Msk (0xf00UL) /*!< VADC_G ASCTRL: XTSEL (Bitfield-Mask: 0x0f) */ +#define VADC_G_ASCTRL_XTLVL_Pos (12UL) /*!< VADC_G ASCTRL: XTLVL (Bit 12) */ +#define VADC_G_ASCTRL_XTLVL_Msk (0x1000UL) /*!< VADC_G ASCTRL: XTLVL (Bitfield-Mask: 0x01) */ +#define VADC_G_ASCTRL_XTMODE_Pos (13UL) /*!< VADC_G ASCTRL: XTMODE (Bit 13) */ +#define VADC_G_ASCTRL_XTMODE_Msk (0x6000UL) /*!< VADC_G ASCTRL: XTMODE (Bitfield-Mask: 0x03) */ +#define VADC_G_ASCTRL_XTWC_Pos (15UL) /*!< VADC_G ASCTRL: XTWC (Bit 15) */ +#define VADC_G_ASCTRL_XTWC_Msk (0x8000UL) /*!< VADC_G ASCTRL: XTWC (Bitfield-Mask: 0x01) */ +#define VADC_G_ASCTRL_GTSEL_Pos (16UL) /*!< VADC_G ASCTRL: GTSEL (Bit 16) */ +#define VADC_G_ASCTRL_GTSEL_Msk (0xf0000UL) /*!< VADC_G ASCTRL: GTSEL (Bitfield-Mask: 0x0f) */ +#define VADC_G_ASCTRL_GTLVL_Pos (20UL) /*!< VADC_G ASCTRL: GTLVL (Bit 20) */ +#define VADC_G_ASCTRL_GTLVL_Msk (0x100000UL) /*!< VADC_G ASCTRL: GTLVL (Bitfield-Mask: 0x01) */ +#define VADC_G_ASCTRL_GTWC_Pos (23UL) /*!< VADC_G ASCTRL: GTWC (Bit 23) */ +#define VADC_G_ASCTRL_GTWC_Msk (0x800000UL) /*!< VADC_G ASCTRL: GTWC (Bitfield-Mask: 0x01) */ +#define VADC_G_ASCTRL_TMEN_Pos (28UL) /*!< VADC_G ASCTRL: TMEN (Bit 28) */ +#define VADC_G_ASCTRL_TMEN_Msk (0x10000000UL) /*!< VADC_G ASCTRL: TMEN (Bitfield-Mask: 0x01) */ +#define VADC_G_ASCTRL_TMWC_Pos (31UL) /*!< VADC_G ASCTRL: TMWC (Bit 31) */ +#define VADC_G_ASCTRL_TMWC_Msk (0x80000000UL) /*!< VADC_G ASCTRL: TMWC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_ASMR -------------------------------- */ +#define VADC_G_ASMR_ENGT_Pos (0UL) /*!< VADC_G ASMR: ENGT (Bit 0) */ +#define VADC_G_ASMR_ENGT_Msk (0x3UL) /*!< VADC_G ASMR: ENGT (Bitfield-Mask: 0x03) */ +#define VADC_G_ASMR_ENTR_Pos (2UL) /*!< VADC_G ASMR: ENTR (Bit 2) */ +#define VADC_G_ASMR_ENTR_Msk (0x4UL) /*!< VADC_G ASMR: ENTR (Bitfield-Mask: 0x01) */ +#define VADC_G_ASMR_ENSI_Pos (3UL) /*!< VADC_G ASMR: ENSI (Bit 3) */ +#define VADC_G_ASMR_ENSI_Msk (0x8UL) /*!< VADC_G ASMR: ENSI (Bitfield-Mask: 0x01) */ +#define VADC_G_ASMR_SCAN_Pos (4UL) /*!< VADC_G ASMR: SCAN (Bit 4) */ +#define VADC_G_ASMR_SCAN_Msk (0x10UL) /*!< VADC_G ASMR: SCAN (Bitfield-Mask: 0x01) */ +#define VADC_G_ASMR_LDM_Pos (5UL) /*!< VADC_G ASMR: LDM (Bit 5) */ +#define VADC_G_ASMR_LDM_Msk (0x20UL) /*!< VADC_G ASMR: LDM (Bitfield-Mask: 0x01) */ +#define VADC_G_ASMR_REQGT_Pos (7UL) /*!< VADC_G ASMR: REQGT (Bit 7) */ +#define VADC_G_ASMR_REQGT_Msk (0x80UL) /*!< VADC_G ASMR: REQGT (Bitfield-Mask: 0x01) */ +#define VADC_G_ASMR_CLRPND_Pos (8UL) /*!< VADC_G ASMR: CLRPND (Bit 8) */ +#define VADC_G_ASMR_CLRPND_Msk (0x100UL) /*!< VADC_G ASMR: CLRPND (Bitfield-Mask: 0x01) */ +#define VADC_G_ASMR_LDEV_Pos (9UL) /*!< VADC_G ASMR: LDEV (Bit 9) */ +#define VADC_G_ASMR_LDEV_Msk (0x200UL) /*!< VADC_G ASMR: LDEV (Bitfield-Mask: 0x01) */ +#define VADC_G_ASMR_RPTDIS_Pos (16UL) /*!< VADC_G ASMR: RPTDIS (Bit 16) */ +#define VADC_G_ASMR_RPTDIS_Msk (0x10000UL) /*!< VADC_G ASMR: RPTDIS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_ASSEL -------------------------------- */ +#define VADC_G_ASSEL_CHSEL0_Pos (0UL) /*!< VADC_G ASSEL: CHSEL0 (Bit 0) */ +#define VADC_G_ASSEL_CHSEL0_Msk (0x1UL) /*!< VADC_G ASSEL: CHSEL0 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASSEL_CHSEL1_Pos (1UL) /*!< VADC_G ASSEL: CHSEL1 (Bit 1) */ +#define VADC_G_ASSEL_CHSEL1_Msk (0x2UL) /*!< VADC_G ASSEL: CHSEL1 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASSEL_CHSEL2_Pos (2UL) /*!< VADC_G ASSEL: CHSEL2 (Bit 2) */ +#define VADC_G_ASSEL_CHSEL2_Msk (0x4UL) /*!< VADC_G ASSEL: CHSEL2 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASSEL_CHSEL3_Pos (3UL) /*!< VADC_G ASSEL: CHSEL3 (Bit 3) */ +#define VADC_G_ASSEL_CHSEL3_Msk (0x8UL) /*!< VADC_G ASSEL: CHSEL3 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASSEL_CHSEL4_Pos (4UL) /*!< VADC_G ASSEL: CHSEL4 (Bit 4) */ +#define VADC_G_ASSEL_CHSEL4_Msk (0x10UL) /*!< VADC_G ASSEL: CHSEL4 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASSEL_CHSEL5_Pos (5UL) /*!< VADC_G ASSEL: CHSEL5 (Bit 5) */ +#define VADC_G_ASSEL_CHSEL5_Msk (0x20UL) /*!< VADC_G ASSEL: CHSEL5 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASSEL_CHSEL6_Pos (6UL) /*!< VADC_G ASSEL: CHSEL6 (Bit 6) */ +#define VADC_G_ASSEL_CHSEL6_Msk (0x40UL) /*!< VADC_G ASSEL: CHSEL6 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASSEL_CHSEL7_Pos (7UL) /*!< VADC_G ASSEL: CHSEL7 (Bit 7) */ +#define VADC_G_ASSEL_CHSEL7_Msk (0x80UL) /*!< VADC_G ASSEL: CHSEL7 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_ASPND -------------------------------- */ +#define VADC_G_ASPND_CHPND0_Pos (0UL) /*!< VADC_G ASPND: CHPND0 (Bit 0) */ +#define VADC_G_ASPND_CHPND0_Msk (0x1UL) /*!< VADC_G ASPND: CHPND0 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASPND_CHPND1_Pos (1UL) /*!< VADC_G ASPND: CHPND1 (Bit 1) */ +#define VADC_G_ASPND_CHPND1_Msk (0x2UL) /*!< VADC_G ASPND: CHPND1 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASPND_CHPND2_Pos (2UL) /*!< VADC_G ASPND: CHPND2 (Bit 2) */ +#define VADC_G_ASPND_CHPND2_Msk (0x4UL) /*!< VADC_G ASPND: CHPND2 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASPND_CHPND3_Pos (3UL) /*!< VADC_G ASPND: CHPND3 (Bit 3) */ +#define VADC_G_ASPND_CHPND3_Msk (0x8UL) /*!< VADC_G ASPND: CHPND3 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASPND_CHPND4_Pos (4UL) /*!< VADC_G ASPND: CHPND4 (Bit 4) */ +#define VADC_G_ASPND_CHPND4_Msk (0x10UL) /*!< VADC_G ASPND: CHPND4 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASPND_CHPND5_Pos (5UL) /*!< VADC_G ASPND: CHPND5 (Bit 5) */ +#define VADC_G_ASPND_CHPND5_Msk (0x20UL) /*!< VADC_G ASPND: CHPND5 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASPND_CHPND6_Pos (6UL) /*!< VADC_G ASPND: CHPND6 (Bit 6) */ +#define VADC_G_ASPND_CHPND6_Msk (0x40UL) /*!< VADC_G ASPND: CHPND6 (Bitfield-Mask: 0x01) */ +#define VADC_G_ASPND_CHPND7_Pos (7UL) /*!< VADC_G ASPND: CHPND7 (Bit 7) */ +#define VADC_G_ASPND_CHPND7_Msk (0x80UL) /*!< VADC_G ASPND: CHPND7 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_CEFLAG ------------------------------- */ +#define VADC_G_CEFLAG_CEV0_Pos (0UL) /*!< VADC_G CEFLAG: CEV0 (Bit 0) */ +#define VADC_G_CEFLAG_CEV0_Msk (0x1UL) /*!< VADC_G CEFLAG: CEV0 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFLAG_CEV1_Pos (1UL) /*!< VADC_G CEFLAG: CEV1 (Bit 1) */ +#define VADC_G_CEFLAG_CEV1_Msk (0x2UL) /*!< VADC_G CEFLAG: CEV1 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFLAG_CEV2_Pos (2UL) /*!< VADC_G CEFLAG: CEV2 (Bit 2) */ +#define VADC_G_CEFLAG_CEV2_Msk (0x4UL) /*!< VADC_G CEFLAG: CEV2 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFLAG_CEV3_Pos (3UL) /*!< VADC_G CEFLAG: CEV3 (Bit 3) */ +#define VADC_G_CEFLAG_CEV3_Msk (0x8UL) /*!< VADC_G CEFLAG: CEV3 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFLAG_CEV4_Pos (4UL) /*!< VADC_G CEFLAG: CEV4 (Bit 4) */ +#define VADC_G_CEFLAG_CEV4_Msk (0x10UL) /*!< VADC_G CEFLAG: CEV4 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFLAG_CEV5_Pos (5UL) /*!< VADC_G CEFLAG: CEV5 (Bit 5) */ +#define VADC_G_CEFLAG_CEV5_Msk (0x20UL) /*!< VADC_G CEFLAG: CEV5 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFLAG_CEV6_Pos (6UL) /*!< VADC_G CEFLAG: CEV6 (Bit 6) */ +#define VADC_G_CEFLAG_CEV6_Msk (0x40UL) /*!< VADC_G CEFLAG: CEV6 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFLAG_CEV7_Pos (7UL) /*!< VADC_G CEFLAG: CEV7 (Bit 7) */ +#define VADC_G_CEFLAG_CEV7_Msk (0x80UL) /*!< VADC_G CEFLAG: CEV7 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_REFLAG ------------------------------- */ +#define VADC_G_REFLAG_REV0_Pos (0UL) /*!< VADC_G REFLAG: REV0 (Bit 0) */ +#define VADC_G_REFLAG_REV0_Msk (0x1UL) /*!< VADC_G REFLAG: REV0 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV1_Pos (1UL) /*!< VADC_G REFLAG: REV1 (Bit 1) */ +#define VADC_G_REFLAG_REV1_Msk (0x2UL) /*!< VADC_G REFLAG: REV1 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV2_Pos (2UL) /*!< VADC_G REFLAG: REV2 (Bit 2) */ +#define VADC_G_REFLAG_REV2_Msk (0x4UL) /*!< VADC_G REFLAG: REV2 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV3_Pos (3UL) /*!< VADC_G REFLAG: REV3 (Bit 3) */ +#define VADC_G_REFLAG_REV3_Msk (0x8UL) /*!< VADC_G REFLAG: REV3 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV4_Pos (4UL) /*!< VADC_G REFLAG: REV4 (Bit 4) */ +#define VADC_G_REFLAG_REV4_Msk (0x10UL) /*!< VADC_G REFLAG: REV4 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV5_Pos (5UL) /*!< VADC_G REFLAG: REV5 (Bit 5) */ +#define VADC_G_REFLAG_REV5_Msk (0x20UL) /*!< VADC_G REFLAG: REV5 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV6_Pos (6UL) /*!< VADC_G REFLAG: REV6 (Bit 6) */ +#define VADC_G_REFLAG_REV6_Msk (0x40UL) /*!< VADC_G REFLAG: REV6 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV7_Pos (7UL) /*!< VADC_G REFLAG: REV7 (Bit 7) */ +#define VADC_G_REFLAG_REV7_Msk (0x80UL) /*!< VADC_G REFLAG: REV7 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV8_Pos (8UL) /*!< VADC_G REFLAG: REV8 (Bit 8) */ +#define VADC_G_REFLAG_REV8_Msk (0x100UL) /*!< VADC_G REFLAG: REV8 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV9_Pos (9UL) /*!< VADC_G REFLAG: REV9 (Bit 9) */ +#define VADC_G_REFLAG_REV9_Msk (0x200UL) /*!< VADC_G REFLAG: REV9 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV10_Pos (10UL) /*!< VADC_G REFLAG: REV10 (Bit 10) */ +#define VADC_G_REFLAG_REV10_Msk (0x400UL) /*!< VADC_G REFLAG: REV10 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV11_Pos (11UL) /*!< VADC_G REFLAG: REV11 (Bit 11) */ +#define VADC_G_REFLAG_REV11_Msk (0x800UL) /*!< VADC_G REFLAG: REV11 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV12_Pos (12UL) /*!< VADC_G REFLAG: REV12 (Bit 12) */ +#define VADC_G_REFLAG_REV12_Msk (0x1000UL) /*!< VADC_G REFLAG: REV12 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV13_Pos (13UL) /*!< VADC_G REFLAG: REV13 (Bit 13) */ +#define VADC_G_REFLAG_REV13_Msk (0x2000UL) /*!< VADC_G REFLAG: REV13 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV14_Pos (14UL) /*!< VADC_G REFLAG: REV14 (Bit 14) */ +#define VADC_G_REFLAG_REV14_Msk (0x4000UL) /*!< VADC_G REFLAG: REV14 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFLAG_REV15_Pos (15UL) /*!< VADC_G REFLAG: REV15 (Bit 15) */ +#define VADC_G_REFLAG_REV15_Msk (0x8000UL) /*!< VADC_G REFLAG: REV15 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_SEFLAG ------------------------------- */ +#define VADC_G_SEFLAG_SEV0_Pos (0UL) /*!< VADC_G SEFLAG: SEV0 (Bit 0) */ +#define VADC_G_SEFLAG_SEV0_Msk (0x1UL) /*!< VADC_G SEFLAG: SEV0 (Bitfield-Mask: 0x01) */ +#define VADC_G_SEFLAG_SEV1_Pos (1UL) /*!< VADC_G SEFLAG: SEV1 (Bit 1) */ +#define VADC_G_SEFLAG_SEV1_Msk (0x2UL) /*!< VADC_G SEFLAG: SEV1 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_CEFCLR ------------------------------- */ +#define VADC_G_CEFCLR_CEV0_Pos (0UL) /*!< VADC_G CEFCLR: CEV0 (Bit 0) */ +#define VADC_G_CEFCLR_CEV0_Msk (0x1UL) /*!< VADC_G CEFCLR: CEV0 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFCLR_CEV1_Pos (1UL) /*!< VADC_G CEFCLR: CEV1 (Bit 1) */ +#define VADC_G_CEFCLR_CEV1_Msk (0x2UL) /*!< VADC_G CEFCLR: CEV1 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFCLR_CEV2_Pos (2UL) /*!< VADC_G CEFCLR: CEV2 (Bit 2) */ +#define VADC_G_CEFCLR_CEV2_Msk (0x4UL) /*!< VADC_G CEFCLR: CEV2 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFCLR_CEV3_Pos (3UL) /*!< VADC_G CEFCLR: CEV3 (Bit 3) */ +#define VADC_G_CEFCLR_CEV3_Msk (0x8UL) /*!< VADC_G CEFCLR: CEV3 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFCLR_CEV4_Pos (4UL) /*!< VADC_G CEFCLR: CEV4 (Bit 4) */ +#define VADC_G_CEFCLR_CEV4_Msk (0x10UL) /*!< VADC_G CEFCLR: CEV4 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFCLR_CEV5_Pos (5UL) /*!< VADC_G CEFCLR: CEV5 (Bit 5) */ +#define VADC_G_CEFCLR_CEV5_Msk (0x20UL) /*!< VADC_G CEFCLR: CEV5 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFCLR_CEV6_Pos (6UL) /*!< VADC_G CEFCLR: CEV6 (Bit 6) */ +#define VADC_G_CEFCLR_CEV6_Msk (0x40UL) /*!< VADC_G CEFCLR: CEV6 (Bitfield-Mask: 0x01) */ +#define VADC_G_CEFCLR_CEV7_Pos (7UL) /*!< VADC_G CEFCLR: CEV7 (Bit 7) */ +#define VADC_G_CEFCLR_CEV7_Msk (0x80UL) /*!< VADC_G CEFCLR: CEV7 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_REFCLR ------------------------------- */ +#define VADC_G_REFCLR_REV0_Pos (0UL) /*!< VADC_G REFCLR: REV0 (Bit 0) */ +#define VADC_G_REFCLR_REV0_Msk (0x1UL) /*!< VADC_G REFCLR: REV0 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV1_Pos (1UL) /*!< VADC_G REFCLR: REV1 (Bit 1) */ +#define VADC_G_REFCLR_REV1_Msk (0x2UL) /*!< VADC_G REFCLR: REV1 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV2_Pos (2UL) /*!< VADC_G REFCLR: REV2 (Bit 2) */ +#define VADC_G_REFCLR_REV2_Msk (0x4UL) /*!< VADC_G REFCLR: REV2 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV3_Pos (3UL) /*!< VADC_G REFCLR: REV3 (Bit 3) */ +#define VADC_G_REFCLR_REV3_Msk (0x8UL) /*!< VADC_G REFCLR: REV3 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV4_Pos (4UL) /*!< VADC_G REFCLR: REV4 (Bit 4) */ +#define VADC_G_REFCLR_REV4_Msk (0x10UL) /*!< VADC_G REFCLR: REV4 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV5_Pos (5UL) /*!< VADC_G REFCLR: REV5 (Bit 5) */ +#define VADC_G_REFCLR_REV5_Msk (0x20UL) /*!< VADC_G REFCLR: REV5 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV6_Pos (6UL) /*!< VADC_G REFCLR: REV6 (Bit 6) */ +#define VADC_G_REFCLR_REV6_Msk (0x40UL) /*!< VADC_G REFCLR: REV6 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV7_Pos (7UL) /*!< VADC_G REFCLR: REV7 (Bit 7) */ +#define VADC_G_REFCLR_REV7_Msk (0x80UL) /*!< VADC_G REFCLR: REV7 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV8_Pos (8UL) /*!< VADC_G REFCLR: REV8 (Bit 8) */ +#define VADC_G_REFCLR_REV8_Msk (0x100UL) /*!< VADC_G REFCLR: REV8 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV9_Pos (9UL) /*!< VADC_G REFCLR: REV9 (Bit 9) */ +#define VADC_G_REFCLR_REV9_Msk (0x200UL) /*!< VADC_G REFCLR: REV9 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV10_Pos (10UL) /*!< VADC_G REFCLR: REV10 (Bit 10) */ +#define VADC_G_REFCLR_REV10_Msk (0x400UL) /*!< VADC_G REFCLR: REV10 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV11_Pos (11UL) /*!< VADC_G REFCLR: REV11 (Bit 11) */ +#define VADC_G_REFCLR_REV11_Msk (0x800UL) /*!< VADC_G REFCLR: REV11 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV12_Pos (12UL) /*!< VADC_G REFCLR: REV12 (Bit 12) */ +#define VADC_G_REFCLR_REV12_Msk (0x1000UL) /*!< VADC_G REFCLR: REV12 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV13_Pos (13UL) /*!< VADC_G REFCLR: REV13 (Bit 13) */ +#define VADC_G_REFCLR_REV13_Msk (0x2000UL) /*!< VADC_G REFCLR: REV13 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV14_Pos (14UL) /*!< VADC_G REFCLR: REV14 (Bit 14) */ +#define VADC_G_REFCLR_REV14_Msk (0x4000UL) /*!< VADC_G REFCLR: REV14 (Bitfield-Mask: 0x01) */ +#define VADC_G_REFCLR_REV15_Pos (15UL) /*!< VADC_G REFCLR: REV15 (Bit 15) */ +#define VADC_G_REFCLR_REV15_Msk (0x8000UL) /*!< VADC_G REFCLR: REV15 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_SEFCLR ------------------------------- */ +#define VADC_G_SEFCLR_SEV0_Pos (0UL) /*!< VADC_G SEFCLR: SEV0 (Bit 0) */ +#define VADC_G_SEFCLR_SEV0_Msk (0x1UL) /*!< VADC_G SEFCLR: SEV0 (Bitfield-Mask: 0x01) */ +#define VADC_G_SEFCLR_SEV1_Pos (1UL) /*!< VADC_G SEFCLR: SEV1 (Bit 1) */ +#define VADC_G_SEFCLR_SEV1_Msk (0x2UL) /*!< VADC_G SEFCLR: SEV1 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_CEVNP0 ------------------------------- */ +#define VADC_G_CEVNP0_CEV0NP_Pos (0UL) /*!< VADC_G CEVNP0: CEV0NP (Bit 0) */ +#define VADC_G_CEVNP0_CEV0NP_Msk (0xfUL) /*!< VADC_G CEVNP0: CEV0NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_CEVNP0_CEV1NP_Pos (4UL) /*!< VADC_G CEVNP0: CEV1NP (Bit 4) */ +#define VADC_G_CEVNP0_CEV1NP_Msk (0xf0UL) /*!< VADC_G CEVNP0: CEV1NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_CEVNP0_CEV2NP_Pos (8UL) /*!< VADC_G CEVNP0: CEV2NP (Bit 8) */ +#define VADC_G_CEVNP0_CEV2NP_Msk (0xf00UL) /*!< VADC_G CEVNP0: CEV2NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_CEVNP0_CEV3NP_Pos (12UL) /*!< VADC_G CEVNP0: CEV3NP (Bit 12) */ +#define VADC_G_CEVNP0_CEV3NP_Msk (0xf000UL) /*!< VADC_G CEVNP0: CEV3NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_CEVNP0_CEV4NP_Pos (16UL) /*!< VADC_G CEVNP0: CEV4NP (Bit 16) */ +#define VADC_G_CEVNP0_CEV4NP_Msk (0xf0000UL) /*!< VADC_G CEVNP0: CEV4NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_CEVNP0_CEV5NP_Pos (20UL) /*!< VADC_G CEVNP0: CEV5NP (Bit 20) */ +#define VADC_G_CEVNP0_CEV5NP_Msk (0xf00000UL) /*!< VADC_G CEVNP0: CEV5NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_CEVNP0_CEV6NP_Pos (24UL) /*!< VADC_G CEVNP0: CEV6NP (Bit 24) */ +#define VADC_G_CEVNP0_CEV6NP_Msk (0xf000000UL) /*!< VADC_G CEVNP0: CEV6NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_CEVNP0_CEV7NP_Pos (28UL) /*!< VADC_G CEVNP0: CEV7NP (Bit 28) */ +#define VADC_G_CEVNP0_CEV7NP_Msk (0xf0000000UL) /*!< VADC_G CEVNP0: CEV7NP (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- VADC_G_REVNP0 ------------------------------- */ +#define VADC_G_REVNP0_REV0NP_Pos (0UL) /*!< VADC_G REVNP0: REV0NP (Bit 0) */ +#define VADC_G_REVNP0_REV0NP_Msk (0xfUL) /*!< VADC_G REVNP0: REV0NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP0_REV1NP_Pos (4UL) /*!< VADC_G REVNP0: REV1NP (Bit 4) */ +#define VADC_G_REVNP0_REV1NP_Msk (0xf0UL) /*!< VADC_G REVNP0: REV1NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP0_REV2NP_Pos (8UL) /*!< VADC_G REVNP0: REV2NP (Bit 8) */ +#define VADC_G_REVNP0_REV2NP_Msk (0xf00UL) /*!< VADC_G REVNP0: REV2NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP0_REV3NP_Pos (12UL) /*!< VADC_G REVNP0: REV3NP (Bit 12) */ +#define VADC_G_REVNP0_REV3NP_Msk (0xf000UL) /*!< VADC_G REVNP0: REV3NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP0_REV4NP_Pos (16UL) /*!< VADC_G REVNP0: REV4NP (Bit 16) */ +#define VADC_G_REVNP0_REV4NP_Msk (0xf0000UL) /*!< VADC_G REVNP0: REV4NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP0_REV5NP_Pos (20UL) /*!< VADC_G REVNP0: REV5NP (Bit 20) */ +#define VADC_G_REVNP0_REV5NP_Msk (0xf00000UL) /*!< VADC_G REVNP0: REV5NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP0_REV6NP_Pos (24UL) /*!< VADC_G REVNP0: REV6NP (Bit 24) */ +#define VADC_G_REVNP0_REV6NP_Msk (0xf000000UL) /*!< VADC_G REVNP0: REV6NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP0_REV7NP_Pos (28UL) /*!< VADC_G REVNP0: REV7NP (Bit 28) */ +#define VADC_G_REVNP0_REV7NP_Msk (0xf0000000UL) /*!< VADC_G REVNP0: REV7NP (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- VADC_G_REVNP1 ------------------------------- */ +#define VADC_G_REVNP1_REV8NP_Pos (0UL) /*!< VADC_G REVNP1: REV8NP (Bit 0) */ +#define VADC_G_REVNP1_REV8NP_Msk (0xfUL) /*!< VADC_G REVNP1: REV8NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP1_REV9NP_Pos (4UL) /*!< VADC_G REVNP1: REV9NP (Bit 4) */ +#define VADC_G_REVNP1_REV9NP_Msk (0xf0UL) /*!< VADC_G REVNP1: REV9NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP1_REV10NP_Pos (8UL) /*!< VADC_G REVNP1: REV10NP (Bit 8) */ +#define VADC_G_REVNP1_REV10NP_Msk (0xf00UL) /*!< VADC_G REVNP1: REV10NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP1_REV11NP_Pos (12UL) /*!< VADC_G REVNP1: REV11NP (Bit 12) */ +#define VADC_G_REVNP1_REV11NP_Msk (0xf000UL) /*!< VADC_G REVNP1: REV11NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP1_REV12NP_Pos (16UL) /*!< VADC_G REVNP1: REV12NP (Bit 16) */ +#define VADC_G_REVNP1_REV12NP_Msk (0xf0000UL) /*!< VADC_G REVNP1: REV12NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP1_REV13NP_Pos (20UL) /*!< VADC_G REVNP1: REV13NP (Bit 20) */ +#define VADC_G_REVNP1_REV13NP_Msk (0xf00000UL) /*!< VADC_G REVNP1: REV13NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP1_REV14NP_Pos (24UL) /*!< VADC_G REVNP1: REV14NP (Bit 24) */ +#define VADC_G_REVNP1_REV14NP_Msk (0xf000000UL) /*!< VADC_G REVNP1: REV14NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_REVNP1_REV15NP_Pos (28UL) /*!< VADC_G REVNP1: REV15NP (Bit 28) */ +#define VADC_G_REVNP1_REV15NP_Msk (0xf0000000UL) /*!< VADC_G REVNP1: REV15NP (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- VADC_G_SEVNP -------------------------------- */ +#define VADC_G_SEVNP_SEV0NP_Pos (0UL) /*!< VADC_G SEVNP: SEV0NP (Bit 0) */ +#define VADC_G_SEVNP_SEV0NP_Msk (0xfUL) /*!< VADC_G SEVNP: SEV0NP (Bitfield-Mask: 0x0f) */ +#define VADC_G_SEVNP_SEV1NP_Pos (4UL) /*!< VADC_G SEVNP: SEV1NP (Bit 4) */ +#define VADC_G_SEVNP_SEV1NP_Msk (0xf0UL) /*!< VADC_G SEVNP: SEV1NP (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- VADC_G_SRACT -------------------------------- */ +#define VADC_G_SRACT_AGSR0_Pos (0UL) /*!< VADC_G SRACT: AGSR0 (Bit 0) */ +#define VADC_G_SRACT_AGSR0_Msk (0x1UL) /*!< VADC_G SRACT: AGSR0 (Bitfield-Mask: 0x01) */ +#define VADC_G_SRACT_AGSR1_Pos (1UL) /*!< VADC_G SRACT: AGSR1 (Bit 1) */ +#define VADC_G_SRACT_AGSR1_Msk (0x2UL) /*!< VADC_G SRACT: AGSR1 (Bitfield-Mask: 0x01) */ +#define VADC_G_SRACT_AGSR2_Pos (2UL) /*!< VADC_G SRACT: AGSR2 (Bit 2) */ +#define VADC_G_SRACT_AGSR2_Msk (0x4UL) /*!< VADC_G SRACT: AGSR2 (Bitfield-Mask: 0x01) */ +#define VADC_G_SRACT_AGSR3_Pos (3UL) /*!< VADC_G SRACT: AGSR3 (Bit 3) */ +#define VADC_G_SRACT_AGSR3_Msk (0x8UL) /*!< VADC_G SRACT: AGSR3 (Bitfield-Mask: 0x01) */ +#define VADC_G_SRACT_ASSR0_Pos (8UL) /*!< VADC_G SRACT: ASSR0 (Bit 8) */ +#define VADC_G_SRACT_ASSR0_Msk (0x100UL) /*!< VADC_G SRACT: ASSR0 (Bitfield-Mask: 0x01) */ +#define VADC_G_SRACT_ASSR1_Pos (9UL) /*!< VADC_G SRACT: ASSR1 (Bit 9) */ +#define VADC_G_SRACT_ASSR1_Msk (0x200UL) /*!< VADC_G SRACT: ASSR1 (Bitfield-Mask: 0x01) */ +#define VADC_G_SRACT_ASSR2_Pos (10UL) /*!< VADC_G SRACT: ASSR2 (Bit 10) */ +#define VADC_G_SRACT_ASSR2_Msk (0x400UL) /*!< VADC_G SRACT: ASSR2 (Bitfield-Mask: 0x01) */ +#define VADC_G_SRACT_ASSR3_Pos (11UL) /*!< VADC_G SRACT: ASSR3 (Bit 11) */ +#define VADC_G_SRACT_ASSR3_Msk (0x800UL) /*!< VADC_G SRACT: ASSR3 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- VADC_G_EMUXCTR ------------------------------- */ +#define VADC_G_EMUXCTR_EMUXSET_Pos (0UL) /*!< VADC_G EMUXCTR: EMUXSET (Bit 0) */ +#define VADC_G_EMUXCTR_EMUXSET_Msk (0x7UL) /*!< VADC_G EMUXCTR: EMUXSET (Bitfield-Mask: 0x07) */ +#define VADC_G_EMUXCTR_EMUXACT_Pos (8UL) /*!< VADC_G EMUXCTR: EMUXACT (Bit 8) */ +#define VADC_G_EMUXCTR_EMUXACT_Msk (0x700UL) /*!< VADC_G EMUXCTR: EMUXACT (Bitfield-Mask: 0x07) */ +#define VADC_G_EMUXCTR_EMUXCH_Pos (16UL) /*!< VADC_G EMUXCTR: EMUXCH (Bit 16) */ +#define VADC_G_EMUXCTR_EMUXCH_Msk (0x3ff0000UL) /*!< VADC_G EMUXCTR: EMUXCH (Bitfield-Mask: 0x3ff) */ +#define VADC_G_EMUXCTR_EMUXMODE_Pos (26UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bit 26) */ +#define VADC_G_EMUXCTR_EMUXMODE_Msk (0xc000000UL) /*!< VADC_G EMUXCTR: EMUXMODE (Bitfield-Mask: 0x03) */ +#define VADC_G_EMUXCTR_EMXCOD_Pos (28UL) /*!< VADC_G EMUXCTR: EMXCOD (Bit 28) */ +#define VADC_G_EMUXCTR_EMXCOD_Msk (0x10000000UL) /*!< VADC_G EMUXCTR: EMXCOD (Bitfield-Mask: 0x01) */ +#define VADC_G_EMUXCTR_EMXST_Pos (29UL) /*!< VADC_G EMUXCTR: EMXST (Bit 29) */ +#define VADC_G_EMUXCTR_EMXST_Msk (0x20000000UL) /*!< VADC_G EMUXCTR: EMXST (Bitfield-Mask: 0x01) */ +#define VADC_G_EMUXCTR_EMXCSS_Pos (30UL) /*!< VADC_G EMUXCTR: EMXCSS (Bit 30) */ +#define VADC_G_EMUXCTR_EMXCSS_Msk (0x40000000UL) /*!< VADC_G EMUXCTR: EMXCSS (Bitfield-Mask: 0x01) */ +#define VADC_G_EMUXCTR_EMXWC_Pos (31UL) /*!< VADC_G EMUXCTR: EMXWC (Bit 31) */ +#define VADC_G_EMUXCTR_EMXWC_Msk (0x80000000UL) /*!< VADC_G EMUXCTR: EMXWC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_VFR --------------------------------- */ +#define VADC_G_VFR_VF0_Pos (0UL) /*!< VADC_G VFR: VF0 (Bit 0) */ +#define VADC_G_VFR_VF0_Msk (0x1UL) /*!< VADC_G VFR: VF0 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF1_Pos (1UL) /*!< VADC_G VFR: VF1 (Bit 1) */ +#define VADC_G_VFR_VF1_Msk (0x2UL) /*!< VADC_G VFR: VF1 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF2_Pos (2UL) /*!< VADC_G VFR: VF2 (Bit 2) */ +#define VADC_G_VFR_VF2_Msk (0x4UL) /*!< VADC_G VFR: VF2 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF3_Pos (3UL) /*!< VADC_G VFR: VF3 (Bit 3) */ +#define VADC_G_VFR_VF3_Msk (0x8UL) /*!< VADC_G VFR: VF3 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF4_Pos (4UL) /*!< VADC_G VFR: VF4 (Bit 4) */ +#define VADC_G_VFR_VF4_Msk (0x10UL) /*!< VADC_G VFR: VF4 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF5_Pos (5UL) /*!< VADC_G VFR: VF5 (Bit 5) */ +#define VADC_G_VFR_VF5_Msk (0x20UL) /*!< VADC_G VFR: VF5 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF6_Pos (6UL) /*!< VADC_G VFR: VF6 (Bit 6) */ +#define VADC_G_VFR_VF6_Msk (0x40UL) /*!< VADC_G VFR: VF6 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF7_Pos (7UL) /*!< VADC_G VFR: VF7 (Bit 7) */ +#define VADC_G_VFR_VF7_Msk (0x80UL) /*!< VADC_G VFR: VF7 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF8_Pos (8UL) /*!< VADC_G VFR: VF8 (Bit 8) */ +#define VADC_G_VFR_VF8_Msk (0x100UL) /*!< VADC_G VFR: VF8 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF9_Pos (9UL) /*!< VADC_G VFR: VF9 (Bit 9) */ +#define VADC_G_VFR_VF9_Msk (0x200UL) /*!< VADC_G VFR: VF9 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF10_Pos (10UL) /*!< VADC_G VFR: VF10 (Bit 10) */ +#define VADC_G_VFR_VF10_Msk (0x400UL) /*!< VADC_G VFR: VF10 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF11_Pos (11UL) /*!< VADC_G VFR: VF11 (Bit 11) */ +#define VADC_G_VFR_VF11_Msk (0x800UL) /*!< VADC_G VFR: VF11 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF12_Pos (12UL) /*!< VADC_G VFR: VF12 (Bit 12) */ +#define VADC_G_VFR_VF12_Msk (0x1000UL) /*!< VADC_G VFR: VF12 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF13_Pos (13UL) /*!< VADC_G VFR: VF13 (Bit 13) */ +#define VADC_G_VFR_VF13_Msk (0x2000UL) /*!< VADC_G VFR: VF13 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF14_Pos (14UL) /*!< VADC_G VFR: VF14 (Bit 14) */ +#define VADC_G_VFR_VF14_Msk (0x4000UL) /*!< VADC_G VFR: VF14 (Bitfield-Mask: 0x01) */ +#define VADC_G_VFR_VF15_Pos (15UL) /*!< VADC_G VFR: VF15 (Bit 15) */ +#define VADC_G_VFR_VF15_Msk (0x8000UL) /*!< VADC_G VFR: VF15 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- VADC_G_CHCTR -------------------------------- */ +#define VADC_G_CHCTR_ICLSEL_Pos (0UL) /*!< VADC_G CHCTR: ICLSEL (Bit 0) */ +#define VADC_G_CHCTR_ICLSEL_Msk (0x3UL) /*!< VADC_G CHCTR: ICLSEL (Bitfield-Mask: 0x03) */ +#define VADC_G_CHCTR_BNDSELL_Pos (4UL) /*!< VADC_G CHCTR: BNDSELL (Bit 4) */ +#define VADC_G_CHCTR_BNDSELL_Msk (0x30UL) /*!< VADC_G CHCTR: BNDSELL (Bitfield-Mask: 0x03) */ +#define VADC_G_CHCTR_BNDSELU_Pos (6UL) /*!< VADC_G CHCTR: BNDSELU (Bit 6) */ +#define VADC_G_CHCTR_BNDSELU_Msk (0xc0UL) /*!< VADC_G CHCTR: BNDSELU (Bitfield-Mask: 0x03) */ +#define VADC_G_CHCTR_CHEVMODE_Pos (8UL) /*!< VADC_G CHCTR: CHEVMODE (Bit 8) */ +#define VADC_G_CHCTR_CHEVMODE_Msk (0x300UL) /*!< VADC_G CHCTR: CHEVMODE (Bitfield-Mask: 0x03) */ +#define VADC_G_CHCTR_SYNC_Pos (10UL) /*!< VADC_G CHCTR: SYNC (Bit 10) */ +#define VADC_G_CHCTR_SYNC_Msk (0x400UL) /*!< VADC_G CHCTR: SYNC (Bitfield-Mask: 0x01) */ +#define VADC_G_CHCTR_REFSEL_Pos (11UL) /*!< VADC_G CHCTR: REFSEL (Bit 11) */ +#define VADC_G_CHCTR_REFSEL_Msk (0x800UL) /*!< VADC_G CHCTR: REFSEL (Bitfield-Mask: 0x01) */ +#define VADC_G_CHCTR_RESREG_Pos (16UL) /*!< VADC_G CHCTR: RESREG (Bit 16) */ +#define VADC_G_CHCTR_RESREG_Msk (0xf0000UL) /*!< VADC_G CHCTR: RESREG (Bitfield-Mask: 0x0f) */ +#define VADC_G_CHCTR_RESTBS_Pos (20UL) /*!< VADC_G CHCTR: RESTBS (Bit 20) */ +#define VADC_G_CHCTR_RESTBS_Msk (0x100000UL) /*!< VADC_G CHCTR: RESTBS (Bitfield-Mask: 0x01) */ +#define VADC_G_CHCTR_RESPOS_Pos (21UL) /*!< VADC_G CHCTR: RESPOS (Bit 21) */ +#define VADC_G_CHCTR_RESPOS_Msk (0x200000UL) /*!< VADC_G CHCTR: RESPOS (Bitfield-Mask: 0x01) */ +#define VADC_G_CHCTR_BWDCH_Pos (28UL) /*!< VADC_G CHCTR: BWDCH (Bit 28) */ +#define VADC_G_CHCTR_BWDCH_Msk (0x30000000UL) /*!< VADC_G CHCTR: BWDCH (Bitfield-Mask: 0x03) */ +#define VADC_G_CHCTR_BWDEN_Pos (30UL) /*!< VADC_G CHCTR: BWDEN (Bit 30) */ +#define VADC_G_CHCTR_BWDEN_Msk (0x40000000UL) /*!< VADC_G CHCTR: BWDEN (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_RCR --------------------------------- */ +#define VADC_G_RCR_DRCTR_Pos (16UL) /*!< VADC_G RCR: DRCTR (Bit 16) */ +#define VADC_G_RCR_DRCTR_Msk (0xf0000UL) /*!< VADC_G RCR: DRCTR (Bitfield-Mask: 0x0f) */ +#define VADC_G_RCR_DMM_Pos (20UL) /*!< VADC_G RCR: DMM (Bit 20) */ +#define VADC_G_RCR_DMM_Msk (0x300000UL) /*!< VADC_G RCR: DMM (Bitfield-Mask: 0x03) */ +#define VADC_G_RCR_WFR_Pos (24UL) /*!< VADC_G RCR: WFR (Bit 24) */ +#define VADC_G_RCR_WFR_Msk (0x1000000UL) /*!< VADC_G RCR: WFR (Bitfield-Mask: 0x01) */ +#define VADC_G_RCR_FEN_Pos (25UL) /*!< VADC_G RCR: FEN (Bit 25) */ +#define VADC_G_RCR_FEN_Msk (0x6000000UL) /*!< VADC_G RCR: FEN (Bitfield-Mask: 0x03) */ +#define VADC_G_RCR_SRGEN_Pos (31UL) /*!< VADC_G RCR: SRGEN (Bit 31) */ +#define VADC_G_RCR_SRGEN_Msk (0x80000000UL) /*!< VADC_G RCR: SRGEN (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_RES --------------------------------- */ +#define VADC_G_RES_RESULT_Pos (0UL) /*!< VADC_G RES: RESULT (Bit 0) */ +#define VADC_G_RES_RESULT_Msk (0xffffUL) /*!< VADC_G RES: RESULT (Bitfield-Mask: 0xffff) */ +#define VADC_G_RES_DRC_Pos (16UL) /*!< VADC_G RES: DRC (Bit 16) */ +#define VADC_G_RES_DRC_Msk (0xf0000UL) /*!< VADC_G RES: DRC (Bitfield-Mask: 0x0f) */ +#define VADC_G_RES_CHNR_Pos (20UL) /*!< VADC_G RES: CHNR (Bit 20) */ +#define VADC_G_RES_CHNR_Msk (0x1f00000UL) /*!< VADC_G RES: CHNR (Bitfield-Mask: 0x1f) */ +#define VADC_G_RES_EMUX_Pos (25UL) /*!< VADC_G RES: EMUX (Bit 25) */ +#define VADC_G_RES_EMUX_Msk (0xe000000UL) /*!< VADC_G RES: EMUX (Bitfield-Mask: 0x07) */ +#define VADC_G_RES_CRS_Pos (28UL) /*!< VADC_G RES: CRS (Bit 28) */ +#define VADC_G_RES_CRS_Msk (0x30000000UL) /*!< VADC_G RES: CRS (Bitfield-Mask: 0x03) */ +#define VADC_G_RES_FCR_Pos (30UL) /*!< VADC_G RES: FCR (Bit 30) */ +#define VADC_G_RES_FCR_Msk (0x40000000UL) /*!< VADC_G RES: FCR (Bitfield-Mask: 0x01) */ +#define VADC_G_RES_VF_Pos (31UL) /*!< VADC_G RES: VF (Bit 31) */ +#define VADC_G_RES_VF_Msk (0x80000000UL) /*!< VADC_G RES: VF (Bitfield-Mask: 0x01) */ + +/* --------------------------------- VADC_G_RESD -------------------------------- */ +#define VADC_G_RESD_RESULT_Pos (0UL) /*!< VADC_G RESD: RESULT (Bit 0) */ +#define VADC_G_RESD_RESULT_Msk (0xffffUL) /*!< VADC_G RESD: RESULT (Bitfield-Mask: 0xffff) */ +#define VADC_G_RESD_DRC_Pos (16UL) /*!< VADC_G RESD: DRC (Bit 16) */ +#define VADC_G_RESD_DRC_Msk (0xf0000UL) /*!< VADC_G RESD: DRC (Bitfield-Mask: 0x0f) */ +#define VADC_G_RESD_CHNR_Pos (20UL) /*!< VADC_G RESD: CHNR (Bit 20) */ +#define VADC_G_RESD_CHNR_Msk (0x1f00000UL) /*!< VADC_G RESD: CHNR (Bitfield-Mask: 0x1f) */ +#define VADC_G_RESD_EMUX_Pos (25UL) /*!< VADC_G RESD: EMUX (Bit 25) */ +#define VADC_G_RESD_EMUX_Msk (0xe000000UL) /*!< VADC_G RESD: EMUX (Bitfield-Mask: 0x07) */ +#define VADC_G_RESD_CRS_Pos (28UL) /*!< VADC_G RESD: CRS (Bit 28) */ +#define VADC_G_RESD_CRS_Msk (0x30000000UL) /*!< VADC_G RESD: CRS (Bitfield-Mask: 0x03) */ +#define VADC_G_RESD_FCR_Pos (30UL) /*!< VADC_G RESD: FCR (Bit 30) */ +#define VADC_G_RESD_FCR_Msk (0x40000000UL) /*!< VADC_G RESD: FCR (Bitfield-Mask: 0x01) */ +#define VADC_G_RESD_VF_Pos (31UL) /*!< VADC_G RESD: VF (Bit 31) */ +#define VADC_G_RESD_VF_Msk (0x80000000UL) /*!< VADC_G RESD: VF (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'DAC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ----------------------------------- DAC_ID ----------------------------------- */ +#define DAC_ID_MODR_Pos (0UL) /*!< DAC ID: MODR (Bit 0) */ +#define DAC_ID_MODR_Msk (0xffUL) /*!< DAC ID: MODR (Bitfield-Mask: 0xff) */ +#define DAC_ID_MODT_Pos (8UL) /*!< DAC ID: MODT (Bit 8) */ +#define DAC_ID_MODT_Msk (0xff00UL) /*!< DAC ID: MODT (Bitfield-Mask: 0xff) */ +#define DAC_ID_MODN_Pos (16UL) /*!< DAC ID: MODN (Bit 16) */ +#define DAC_ID_MODN_Msk (0xffff0000UL) /*!< DAC ID: MODN (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- DAC_DAC0CFG0 -------------------------------- */ +#define DAC_DAC0CFG0_FREQ_Pos (0UL) /*!< DAC DAC0CFG0: FREQ (Bit 0) */ +#define DAC_DAC0CFG0_FREQ_Msk (0xfffffUL) /*!< DAC DAC0CFG0: FREQ (Bitfield-Mask: 0xfffff) */ +#define DAC_DAC0CFG0_MODE_Pos (20UL) /*!< DAC DAC0CFG0: MODE (Bit 20) */ +#define DAC_DAC0CFG0_MODE_Msk (0x700000UL) /*!< DAC DAC0CFG0: MODE (Bitfield-Mask: 0x07) */ +#define DAC_DAC0CFG0_SIGN_Pos (23UL) /*!< DAC DAC0CFG0: SIGN (Bit 23) */ +#define DAC_DAC0CFG0_SIGN_Msk (0x800000UL) /*!< DAC DAC0CFG0: SIGN (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG0_FIFOIND_Pos (24UL) /*!< DAC DAC0CFG0: FIFOIND (Bit 24) */ +#define DAC_DAC0CFG0_FIFOIND_Msk (0x3000000UL) /*!< DAC DAC0CFG0: FIFOIND (Bitfield-Mask: 0x03) */ +#define DAC_DAC0CFG0_FIFOEMP_Pos (26UL) /*!< DAC DAC0CFG0: FIFOEMP (Bit 26) */ +#define DAC_DAC0CFG0_FIFOEMP_Msk (0x4000000UL) /*!< DAC DAC0CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG0_FIFOFUL_Pos (27UL) /*!< DAC DAC0CFG0: FIFOFUL (Bit 27) */ +#define DAC_DAC0CFG0_FIFOFUL_Msk (0x8000000UL) /*!< DAC DAC0CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG0_NEGATE_Pos (28UL) /*!< DAC DAC0CFG0: NEGATE (Bit 28) */ +#define DAC_DAC0CFG0_NEGATE_Msk (0x10000000UL) /*!< DAC DAC0CFG0: NEGATE (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG0_SIGNEN_Pos (29UL) /*!< DAC DAC0CFG0: SIGNEN (Bit 29) */ +#define DAC_DAC0CFG0_SIGNEN_Msk (0x20000000UL) /*!< DAC DAC0CFG0: SIGNEN (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG0_SREN_Pos (30UL) /*!< DAC DAC0CFG0: SREN (Bit 30) */ +#define DAC_DAC0CFG0_SREN_Msk (0x40000000UL) /*!< DAC DAC0CFG0: SREN (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG0_RUN_Pos (31UL) /*!< DAC DAC0CFG0: RUN (Bit 31) */ +#define DAC_DAC0CFG0_RUN_Msk (0x80000000UL) /*!< DAC DAC0CFG0: RUN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- DAC_DAC0CFG1 -------------------------------- */ +#define DAC_DAC0CFG1_SCALE_Pos (0UL) /*!< DAC DAC0CFG1: SCALE (Bit 0) */ +#define DAC_DAC0CFG1_SCALE_Msk (0x7UL) /*!< DAC DAC0CFG1: SCALE (Bitfield-Mask: 0x07) */ +#define DAC_DAC0CFG1_MULDIV_Pos (3UL) /*!< DAC DAC0CFG1: MULDIV (Bit 3) */ +#define DAC_DAC0CFG1_MULDIV_Msk (0x8UL) /*!< DAC DAC0CFG1: MULDIV (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG1_OFFS_Pos (4UL) /*!< DAC DAC0CFG1: OFFS (Bit 4) */ +#define DAC_DAC0CFG1_OFFS_Msk (0xff0UL) /*!< DAC DAC0CFG1: OFFS (Bitfield-Mask: 0xff) */ +#define DAC_DAC0CFG1_TRIGSEL_Pos (12UL) /*!< DAC DAC0CFG1: TRIGSEL (Bit 12) */ +#define DAC_DAC0CFG1_TRIGSEL_Msk (0x7000UL) /*!< DAC DAC0CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ +#define DAC_DAC0CFG1_DATMOD_Pos (15UL) /*!< DAC DAC0CFG1: DATMOD (Bit 15) */ +#define DAC_DAC0CFG1_DATMOD_Msk (0x8000UL) /*!< DAC DAC0CFG1: DATMOD (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG1_SWTRIG_Pos (16UL) /*!< DAC DAC0CFG1: SWTRIG (Bit 16) */ +#define DAC_DAC0CFG1_SWTRIG_Msk (0x10000UL) /*!< DAC DAC0CFG1: SWTRIG (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG1_TRIGMOD_Pos (17UL) /*!< DAC DAC0CFG1: TRIGMOD (Bit 17) */ +#define DAC_DAC0CFG1_TRIGMOD_Msk (0x60000UL) /*!< DAC DAC0CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ +#define DAC_DAC0CFG1_ANACFG_Pos (19UL) /*!< DAC DAC0CFG1: ANACFG (Bit 19) */ +#define DAC_DAC0CFG1_ANACFG_Msk (0xf80000UL) /*!< DAC DAC0CFG1: ANACFG (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0CFG1_ANAEN_Pos (24UL) /*!< DAC DAC0CFG1: ANAEN (Bit 24) */ +#define DAC_DAC0CFG1_ANAEN_Msk (0x1000000UL) /*!< DAC DAC0CFG1: ANAEN (Bitfield-Mask: 0x01) */ +#define DAC_DAC0CFG1_REFCFGL_Pos (28UL) /*!< DAC DAC0CFG1: REFCFGL (Bit 28) */ +#define DAC_DAC0CFG1_REFCFGL_Msk (0xf0000000UL) /*!< DAC DAC0CFG1: REFCFGL (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- DAC_DAC1CFG0 -------------------------------- */ +#define DAC_DAC1CFG0_FREQ_Pos (0UL) /*!< DAC DAC1CFG0: FREQ (Bit 0) */ +#define DAC_DAC1CFG0_FREQ_Msk (0xfffffUL) /*!< DAC DAC1CFG0: FREQ (Bitfield-Mask: 0xfffff) */ +#define DAC_DAC1CFG0_MODE_Pos (20UL) /*!< DAC DAC1CFG0: MODE (Bit 20) */ +#define DAC_DAC1CFG0_MODE_Msk (0x700000UL) /*!< DAC DAC1CFG0: MODE (Bitfield-Mask: 0x07) */ +#define DAC_DAC1CFG0_SIGN_Pos (23UL) /*!< DAC DAC1CFG0: SIGN (Bit 23) */ +#define DAC_DAC1CFG0_SIGN_Msk (0x800000UL) /*!< DAC DAC1CFG0: SIGN (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG0_FIFOIND_Pos (24UL) /*!< DAC DAC1CFG0: FIFOIND (Bit 24) */ +#define DAC_DAC1CFG0_FIFOIND_Msk (0x3000000UL) /*!< DAC DAC1CFG0: FIFOIND (Bitfield-Mask: 0x03) */ +#define DAC_DAC1CFG0_FIFOEMP_Pos (26UL) /*!< DAC DAC1CFG0: FIFOEMP (Bit 26) */ +#define DAC_DAC1CFG0_FIFOEMP_Msk (0x4000000UL) /*!< DAC DAC1CFG0: FIFOEMP (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG0_FIFOFUL_Pos (27UL) /*!< DAC DAC1CFG0: FIFOFUL (Bit 27) */ +#define DAC_DAC1CFG0_FIFOFUL_Msk (0x8000000UL) /*!< DAC DAC1CFG0: FIFOFUL (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG0_NEGATE_Pos (28UL) /*!< DAC DAC1CFG0: NEGATE (Bit 28) */ +#define DAC_DAC1CFG0_NEGATE_Msk (0x10000000UL) /*!< DAC DAC1CFG0: NEGATE (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG0_SIGNEN_Pos (29UL) /*!< DAC DAC1CFG0: SIGNEN (Bit 29) */ +#define DAC_DAC1CFG0_SIGNEN_Msk (0x20000000UL) /*!< DAC DAC1CFG0: SIGNEN (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG0_SREN_Pos (30UL) /*!< DAC DAC1CFG0: SREN (Bit 30) */ +#define DAC_DAC1CFG0_SREN_Msk (0x40000000UL) /*!< DAC DAC1CFG0: SREN (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG0_RUN_Pos (31UL) /*!< DAC DAC1CFG0: RUN (Bit 31) */ +#define DAC_DAC1CFG0_RUN_Msk (0x80000000UL) /*!< DAC DAC1CFG0: RUN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- DAC_DAC1CFG1 -------------------------------- */ +#define DAC_DAC1CFG1_SCALE_Pos (0UL) /*!< DAC DAC1CFG1: SCALE (Bit 0) */ +#define DAC_DAC1CFG1_SCALE_Msk (0x7UL) /*!< DAC DAC1CFG1: SCALE (Bitfield-Mask: 0x07) */ +#define DAC_DAC1CFG1_MULDIV_Pos (3UL) /*!< DAC DAC1CFG1: MULDIV (Bit 3) */ +#define DAC_DAC1CFG1_MULDIV_Msk (0x8UL) /*!< DAC DAC1CFG1: MULDIV (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG1_OFFS_Pos (4UL) /*!< DAC DAC1CFG1: OFFS (Bit 4) */ +#define DAC_DAC1CFG1_OFFS_Msk (0xff0UL) /*!< DAC DAC1CFG1: OFFS (Bitfield-Mask: 0xff) */ +#define DAC_DAC1CFG1_TRIGSEL_Pos (12UL) /*!< DAC DAC1CFG1: TRIGSEL (Bit 12) */ +#define DAC_DAC1CFG1_TRIGSEL_Msk (0x7000UL) /*!< DAC DAC1CFG1: TRIGSEL (Bitfield-Mask: 0x07) */ +#define DAC_DAC1CFG1_SWTRIG_Pos (16UL) /*!< DAC DAC1CFG1: SWTRIG (Bit 16) */ +#define DAC_DAC1CFG1_SWTRIG_Msk (0x10000UL) /*!< DAC DAC1CFG1: SWTRIG (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG1_TRIGMOD_Pos (17UL) /*!< DAC DAC1CFG1: TRIGMOD (Bit 17) */ +#define DAC_DAC1CFG1_TRIGMOD_Msk (0x60000UL) /*!< DAC DAC1CFG1: TRIGMOD (Bitfield-Mask: 0x03) */ +#define DAC_DAC1CFG1_ANACFG_Pos (19UL) /*!< DAC DAC1CFG1: ANACFG (Bit 19) */ +#define DAC_DAC1CFG1_ANACFG_Msk (0xf80000UL) /*!< DAC DAC1CFG1: ANACFG (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1CFG1_ANAEN_Pos (24UL) /*!< DAC DAC1CFG1: ANAEN (Bit 24) */ +#define DAC_DAC1CFG1_ANAEN_Msk (0x1000000UL) /*!< DAC DAC1CFG1: ANAEN (Bitfield-Mask: 0x01) */ +#define DAC_DAC1CFG1_REFCFGH_Pos (28UL) /*!< DAC DAC1CFG1: REFCFGH (Bit 28) */ +#define DAC_DAC1CFG1_REFCFGH_Msk (0xf0000000UL) /*!< DAC DAC1CFG1: REFCFGH (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- DAC_DAC0DATA -------------------------------- */ +#define DAC_DAC0DATA_DATA0_Pos (0UL) /*!< DAC DAC0DATA: DATA0 (Bit 0) */ +#define DAC_DAC0DATA_DATA0_Msk (0xfffUL) /*!< DAC DAC0DATA: DATA0 (Bitfield-Mask: 0xfff) */ + +/* -------------------------------- DAC_DAC1DATA -------------------------------- */ +#define DAC_DAC1DATA_DATA1_Pos (0UL) /*!< DAC DAC1DATA: DATA1 (Bit 0) */ +#define DAC_DAC1DATA_DATA1_Msk (0xfffUL) /*!< DAC DAC1DATA: DATA1 (Bitfield-Mask: 0xfff) */ + +/* -------------------------------- DAC_DAC01DATA ------------------------------- */ +#define DAC_DAC01DATA_DATA0_Pos (0UL) /*!< DAC DAC01DATA: DATA0 (Bit 0) */ +#define DAC_DAC01DATA_DATA0_Msk (0xfffUL) /*!< DAC DAC01DATA: DATA0 (Bitfield-Mask: 0xfff) */ +#define DAC_DAC01DATA_DATA1_Pos (16UL) /*!< DAC DAC01DATA: DATA1 (Bit 16) */ +#define DAC_DAC01DATA_DATA1_Msk (0xfff0000UL) /*!< DAC DAC01DATA: DATA1 (Bitfield-Mask: 0xfff) */ + +/* -------------------------------- DAC_DAC0PATL -------------------------------- */ +#define DAC_DAC0PATL_PAT0_Pos (0UL) /*!< DAC DAC0PATL: PAT0 (Bit 0) */ +#define DAC_DAC0PATL_PAT0_Msk (0x1fUL) /*!< DAC DAC0PATL: PAT0 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0PATL_PAT1_Pos (5UL) /*!< DAC DAC0PATL: PAT1 (Bit 5) */ +#define DAC_DAC0PATL_PAT1_Msk (0x3e0UL) /*!< DAC DAC0PATL: PAT1 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0PATL_PAT2_Pos (10UL) /*!< DAC DAC0PATL: PAT2 (Bit 10) */ +#define DAC_DAC0PATL_PAT2_Msk (0x7c00UL) /*!< DAC DAC0PATL: PAT2 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0PATL_PAT3_Pos (15UL) /*!< DAC DAC0PATL: PAT3 (Bit 15) */ +#define DAC_DAC0PATL_PAT3_Msk (0xf8000UL) /*!< DAC DAC0PATL: PAT3 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0PATL_PAT4_Pos (20UL) /*!< DAC DAC0PATL: PAT4 (Bit 20) */ +#define DAC_DAC0PATL_PAT4_Msk (0x1f00000UL) /*!< DAC DAC0PATL: PAT4 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0PATL_PAT5_Pos (25UL) /*!< DAC DAC0PATL: PAT5 (Bit 25) */ +#define DAC_DAC0PATL_PAT5_Msk (0x3e000000UL) /*!< DAC DAC0PATL: PAT5 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- DAC_DAC0PATH -------------------------------- */ +#define DAC_DAC0PATH_PAT6_Pos (0UL) /*!< DAC DAC0PATH: PAT6 (Bit 0) */ +#define DAC_DAC0PATH_PAT6_Msk (0x1fUL) /*!< DAC DAC0PATH: PAT6 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0PATH_PAT7_Pos (5UL) /*!< DAC DAC0PATH: PAT7 (Bit 5) */ +#define DAC_DAC0PATH_PAT7_Msk (0x3e0UL) /*!< DAC DAC0PATH: PAT7 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC0PATH_PAT8_Pos (10UL) /*!< DAC DAC0PATH: PAT8 (Bit 10) */ +#define DAC_DAC0PATH_PAT8_Msk (0x7c00UL) /*!< DAC DAC0PATH: PAT8 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- DAC_DAC1PATL -------------------------------- */ +#define DAC_DAC1PATL_PAT0_Pos (0UL) /*!< DAC DAC1PATL: PAT0 (Bit 0) */ +#define DAC_DAC1PATL_PAT0_Msk (0x1fUL) /*!< DAC DAC1PATL: PAT0 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1PATL_PAT1_Pos (5UL) /*!< DAC DAC1PATL: PAT1 (Bit 5) */ +#define DAC_DAC1PATL_PAT1_Msk (0x3e0UL) /*!< DAC DAC1PATL: PAT1 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1PATL_PAT2_Pos (10UL) /*!< DAC DAC1PATL: PAT2 (Bit 10) */ +#define DAC_DAC1PATL_PAT2_Msk (0x7c00UL) /*!< DAC DAC1PATL: PAT2 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1PATL_PAT3_Pos (15UL) /*!< DAC DAC1PATL: PAT3 (Bit 15) */ +#define DAC_DAC1PATL_PAT3_Msk (0xf8000UL) /*!< DAC DAC1PATL: PAT3 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1PATL_PAT4_Pos (20UL) /*!< DAC DAC1PATL: PAT4 (Bit 20) */ +#define DAC_DAC1PATL_PAT4_Msk (0x1f00000UL) /*!< DAC DAC1PATL: PAT4 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1PATL_PAT5_Pos (25UL) /*!< DAC DAC1PATL: PAT5 (Bit 25) */ +#define DAC_DAC1PATL_PAT5_Msk (0x3e000000UL) /*!< DAC DAC1PATL: PAT5 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- DAC_DAC1PATH -------------------------------- */ +#define DAC_DAC1PATH_PAT6_Pos (0UL) /*!< DAC DAC1PATH: PAT6 (Bit 0) */ +#define DAC_DAC1PATH_PAT6_Msk (0x1fUL) /*!< DAC DAC1PATH: PAT6 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1PATH_PAT7_Pos (5UL) /*!< DAC DAC1PATH: PAT7 (Bit 5) */ +#define DAC_DAC1PATH_PAT7_Msk (0x3e0UL) /*!< DAC DAC1PATH: PAT7 (Bitfield-Mask: 0x1f) */ +#define DAC_DAC1PATH_PAT8_Pos (10UL) /*!< DAC DAC1PATH: PAT8 (Bit 10) */ +#define DAC_DAC1PATH_PAT8_Msk (0x7c00UL) /*!< DAC DAC1PATH: PAT8 (Bitfield-Mask: 0x1f) */ + + +/* ================================================================================ */ +/* ================ Group 'CCU4' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- CCU4_GCTRL --------------------------------- */ +#define CCU4_GCTRL_PRBC_Pos (0UL) /*!< CCU4 GCTRL: PRBC (Bit 0) */ +#define CCU4_GCTRL_PRBC_Msk (0x7UL) /*!< CCU4 GCTRL: PRBC (Bitfield-Mask: 0x07) */ +#define CCU4_GCTRL_PCIS_Pos (4UL) /*!< CCU4 GCTRL: PCIS (Bit 4) */ +#define CCU4_GCTRL_PCIS_Msk (0x30UL) /*!< CCU4 GCTRL: PCIS (Bitfield-Mask: 0x03) */ +#define CCU4_GCTRL_SUSCFG_Pos (8UL) /*!< CCU4 GCTRL: SUSCFG (Bit 8) */ +#define CCU4_GCTRL_SUSCFG_Msk (0x300UL) /*!< CCU4 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ +#define CCU4_GCTRL_MSE0_Pos (10UL) /*!< CCU4 GCTRL: MSE0 (Bit 10) */ +#define CCU4_GCTRL_MSE0_Msk (0x400UL) /*!< CCU4 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ +#define CCU4_GCTRL_MSE1_Pos (11UL) /*!< CCU4 GCTRL: MSE1 (Bit 11) */ +#define CCU4_GCTRL_MSE1_Msk (0x800UL) /*!< CCU4 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ +#define CCU4_GCTRL_MSE2_Pos (12UL) /*!< CCU4 GCTRL: MSE2 (Bit 12) */ +#define CCU4_GCTRL_MSE2_Msk (0x1000UL) /*!< CCU4 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ +#define CCU4_GCTRL_MSE3_Pos (13UL) /*!< CCU4 GCTRL: MSE3 (Bit 13) */ +#define CCU4_GCTRL_MSE3_Msk (0x2000UL) /*!< CCU4 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ +#define CCU4_GCTRL_MSDE_Pos (14UL) /*!< CCU4 GCTRL: MSDE (Bit 14) */ +#define CCU4_GCTRL_MSDE_Msk (0xc000UL) /*!< CCU4 GCTRL: MSDE (Bitfield-Mask: 0x03) */ + +/* --------------------------------- CCU4_GSTAT --------------------------------- */ +#define CCU4_GSTAT_S0I_Pos (0UL) /*!< CCU4 GSTAT: S0I (Bit 0) */ +#define CCU4_GSTAT_S0I_Msk (0x1UL) /*!< CCU4 GSTAT: S0I (Bitfield-Mask: 0x01) */ +#define CCU4_GSTAT_S1I_Pos (1UL) /*!< CCU4 GSTAT: S1I (Bit 1) */ +#define CCU4_GSTAT_S1I_Msk (0x2UL) /*!< CCU4 GSTAT: S1I (Bitfield-Mask: 0x01) */ +#define CCU4_GSTAT_S2I_Pos (2UL) /*!< CCU4 GSTAT: S2I (Bit 2) */ +#define CCU4_GSTAT_S2I_Msk (0x4UL) /*!< CCU4 GSTAT: S2I (Bitfield-Mask: 0x01) */ +#define CCU4_GSTAT_S3I_Pos (3UL) /*!< CCU4 GSTAT: S3I (Bit 3) */ +#define CCU4_GSTAT_S3I_Msk (0x8UL) /*!< CCU4 GSTAT: S3I (Bitfield-Mask: 0x01) */ +#define CCU4_GSTAT_PRB_Pos (8UL) /*!< CCU4 GSTAT: PRB (Bit 8) */ +#define CCU4_GSTAT_PRB_Msk (0x100UL) /*!< CCU4 GSTAT: PRB (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CCU4_GIDLS --------------------------------- */ +#define CCU4_GIDLS_SS0I_Pos (0UL) /*!< CCU4 GIDLS: SS0I (Bit 0) */ +#define CCU4_GIDLS_SS0I_Msk (0x1UL) /*!< CCU4 GIDLS: SS0I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLS_SS1I_Pos (1UL) /*!< CCU4 GIDLS: SS1I (Bit 1) */ +#define CCU4_GIDLS_SS1I_Msk (0x2UL) /*!< CCU4 GIDLS: SS1I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLS_SS2I_Pos (2UL) /*!< CCU4 GIDLS: SS2I (Bit 2) */ +#define CCU4_GIDLS_SS2I_Msk (0x4UL) /*!< CCU4 GIDLS: SS2I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLS_SS3I_Pos (3UL) /*!< CCU4 GIDLS: SS3I (Bit 3) */ +#define CCU4_GIDLS_SS3I_Msk (0x8UL) /*!< CCU4 GIDLS: SS3I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLS_CPRB_Pos (8UL) /*!< CCU4 GIDLS: CPRB (Bit 8) */ +#define CCU4_GIDLS_CPRB_Msk (0x100UL) /*!< CCU4 GIDLS: CPRB (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLS_PSIC_Pos (9UL) /*!< CCU4 GIDLS: PSIC (Bit 9) */ +#define CCU4_GIDLS_PSIC_Msk (0x200UL) /*!< CCU4 GIDLS: PSIC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CCU4_GIDLC --------------------------------- */ +#define CCU4_GIDLC_CS0I_Pos (0UL) /*!< CCU4 GIDLC: CS0I (Bit 0) */ +#define CCU4_GIDLC_CS0I_Msk (0x1UL) /*!< CCU4 GIDLC: CS0I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLC_CS1I_Pos (1UL) /*!< CCU4 GIDLC: CS1I (Bit 1) */ +#define CCU4_GIDLC_CS1I_Msk (0x2UL) /*!< CCU4 GIDLC: CS1I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLC_CS2I_Pos (2UL) /*!< CCU4 GIDLC: CS2I (Bit 2) */ +#define CCU4_GIDLC_CS2I_Msk (0x4UL) /*!< CCU4 GIDLC: CS2I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLC_CS3I_Pos (3UL) /*!< CCU4 GIDLC: CS3I (Bit 3) */ +#define CCU4_GIDLC_CS3I_Msk (0x8UL) /*!< CCU4 GIDLC: CS3I (Bitfield-Mask: 0x01) */ +#define CCU4_GIDLC_SPRB_Pos (8UL) /*!< CCU4 GIDLC: SPRB (Bit 8) */ +#define CCU4_GIDLC_SPRB_Msk (0x100UL) /*!< CCU4 GIDLC: SPRB (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU4_GCSS --------------------------------- */ +#define CCU4_GCSS_S0SE_Pos (0UL) /*!< CCU4 GCSS: S0SE (Bit 0) */ +#define CCU4_GCSS_S0SE_Msk (0x1UL) /*!< CCU4 GCSS: S0SE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S0DSE_Pos (1UL) /*!< CCU4 GCSS: S0DSE (Bit 1) */ +#define CCU4_GCSS_S0DSE_Msk (0x2UL) /*!< CCU4 GCSS: S0DSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S0PSE_Pos (2UL) /*!< CCU4 GCSS: S0PSE (Bit 2) */ +#define CCU4_GCSS_S0PSE_Msk (0x4UL) /*!< CCU4 GCSS: S0PSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S1SE_Pos (4UL) /*!< CCU4 GCSS: S1SE (Bit 4) */ +#define CCU4_GCSS_S1SE_Msk (0x10UL) /*!< CCU4 GCSS: S1SE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S1DSE_Pos (5UL) /*!< CCU4 GCSS: S1DSE (Bit 5) */ +#define CCU4_GCSS_S1DSE_Msk (0x20UL) /*!< CCU4 GCSS: S1DSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S1PSE_Pos (6UL) /*!< CCU4 GCSS: S1PSE (Bit 6) */ +#define CCU4_GCSS_S1PSE_Msk (0x40UL) /*!< CCU4 GCSS: S1PSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S2SE_Pos (8UL) /*!< CCU4 GCSS: S2SE (Bit 8) */ +#define CCU4_GCSS_S2SE_Msk (0x100UL) /*!< CCU4 GCSS: S2SE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S2DSE_Pos (9UL) /*!< CCU4 GCSS: S2DSE (Bit 9) */ +#define CCU4_GCSS_S2DSE_Msk (0x200UL) /*!< CCU4 GCSS: S2DSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S2PSE_Pos (10UL) /*!< CCU4 GCSS: S2PSE (Bit 10) */ +#define CCU4_GCSS_S2PSE_Msk (0x400UL) /*!< CCU4 GCSS: S2PSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S3SE_Pos (12UL) /*!< CCU4 GCSS: S3SE (Bit 12) */ +#define CCU4_GCSS_S3SE_Msk (0x1000UL) /*!< CCU4 GCSS: S3SE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S3DSE_Pos (13UL) /*!< CCU4 GCSS: S3DSE (Bit 13) */ +#define CCU4_GCSS_S3DSE_Msk (0x2000UL) /*!< CCU4 GCSS: S3DSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S3PSE_Pos (14UL) /*!< CCU4 GCSS: S3PSE (Bit 14) */ +#define CCU4_GCSS_S3PSE_Msk (0x4000UL) /*!< CCU4 GCSS: S3PSE (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S0STS_Pos (16UL) /*!< CCU4 GCSS: S0STS (Bit 16) */ +#define CCU4_GCSS_S0STS_Msk (0x10000UL) /*!< CCU4 GCSS: S0STS (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S1STS_Pos (17UL) /*!< CCU4 GCSS: S1STS (Bit 17) */ +#define CCU4_GCSS_S1STS_Msk (0x20000UL) /*!< CCU4 GCSS: S1STS (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S2STS_Pos (18UL) /*!< CCU4 GCSS: S2STS (Bit 18) */ +#define CCU4_GCSS_S2STS_Msk (0x40000UL) /*!< CCU4 GCSS: S2STS (Bitfield-Mask: 0x01) */ +#define CCU4_GCSS_S3STS_Pos (19UL) /*!< CCU4 GCSS: S3STS (Bit 19) */ +#define CCU4_GCSS_S3STS_Msk (0x80000UL) /*!< CCU4 GCSS: S3STS (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU4_GCSC --------------------------------- */ +#define CCU4_GCSC_S0SC_Pos (0UL) /*!< CCU4 GCSC: S0SC (Bit 0) */ +#define CCU4_GCSC_S0SC_Msk (0x1UL) /*!< CCU4 GCSC: S0SC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S0DSC_Pos (1UL) /*!< CCU4 GCSC: S0DSC (Bit 1) */ +#define CCU4_GCSC_S0DSC_Msk (0x2UL) /*!< CCU4 GCSC: S0DSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S0PSC_Pos (2UL) /*!< CCU4 GCSC: S0PSC (Bit 2) */ +#define CCU4_GCSC_S0PSC_Msk (0x4UL) /*!< CCU4 GCSC: S0PSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S1SC_Pos (4UL) /*!< CCU4 GCSC: S1SC (Bit 4) */ +#define CCU4_GCSC_S1SC_Msk (0x10UL) /*!< CCU4 GCSC: S1SC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S1DSC_Pos (5UL) /*!< CCU4 GCSC: S1DSC (Bit 5) */ +#define CCU4_GCSC_S1DSC_Msk (0x20UL) /*!< CCU4 GCSC: S1DSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S1PSC_Pos (6UL) /*!< CCU4 GCSC: S1PSC (Bit 6) */ +#define CCU4_GCSC_S1PSC_Msk (0x40UL) /*!< CCU4 GCSC: S1PSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S2SC_Pos (8UL) /*!< CCU4 GCSC: S2SC (Bit 8) */ +#define CCU4_GCSC_S2SC_Msk (0x100UL) /*!< CCU4 GCSC: S2SC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S2DSC_Pos (9UL) /*!< CCU4 GCSC: S2DSC (Bit 9) */ +#define CCU4_GCSC_S2DSC_Msk (0x200UL) /*!< CCU4 GCSC: S2DSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S2PSC_Pos (10UL) /*!< CCU4 GCSC: S2PSC (Bit 10) */ +#define CCU4_GCSC_S2PSC_Msk (0x400UL) /*!< CCU4 GCSC: S2PSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S3SC_Pos (12UL) /*!< CCU4 GCSC: S3SC (Bit 12) */ +#define CCU4_GCSC_S3SC_Msk (0x1000UL) /*!< CCU4 GCSC: S3SC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S3DSC_Pos (13UL) /*!< CCU4 GCSC: S3DSC (Bit 13) */ +#define CCU4_GCSC_S3DSC_Msk (0x2000UL) /*!< CCU4 GCSC: S3DSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S3PSC_Pos (14UL) /*!< CCU4 GCSC: S3PSC (Bit 14) */ +#define CCU4_GCSC_S3PSC_Msk (0x4000UL) /*!< CCU4 GCSC: S3PSC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S0STC_Pos (16UL) /*!< CCU4 GCSC: S0STC (Bit 16) */ +#define CCU4_GCSC_S0STC_Msk (0x10000UL) /*!< CCU4 GCSC: S0STC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S1STC_Pos (17UL) /*!< CCU4 GCSC: S1STC (Bit 17) */ +#define CCU4_GCSC_S1STC_Msk (0x20000UL) /*!< CCU4 GCSC: S1STC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S2STC_Pos (18UL) /*!< CCU4 GCSC: S2STC (Bit 18) */ +#define CCU4_GCSC_S2STC_Msk (0x40000UL) /*!< CCU4 GCSC: S2STC (Bitfield-Mask: 0x01) */ +#define CCU4_GCSC_S3STC_Pos (19UL) /*!< CCU4 GCSC: S3STC (Bit 19) */ +#define CCU4_GCSC_S3STC_Msk (0x80000UL) /*!< CCU4 GCSC: S3STC (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU4_GCST --------------------------------- */ +#define CCU4_GCST_S0SS_Pos (0UL) /*!< CCU4 GCST: S0SS (Bit 0) */ +#define CCU4_GCST_S0SS_Msk (0x1UL) /*!< CCU4 GCST: S0SS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S0DSS_Pos (1UL) /*!< CCU4 GCST: S0DSS (Bit 1) */ +#define CCU4_GCST_S0DSS_Msk (0x2UL) /*!< CCU4 GCST: S0DSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S0PSS_Pos (2UL) /*!< CCU4 GCST: S0PSS (Bit 2) */ +#define CCU4_GCST_S0PSS_Msk (0x4UL) /*!< CCU4 GCST: S0PSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S1SS_Pos (4UL) /*!< CCU4 GCST: S1SS (Bit 4) */ +#define CCU4_GCST_S1SS_Msk (0x10UL) /*!< CCU4 GCST: S1SS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S1DSS_Pos (5UL) /*!< CCU4 GCST: S1DSS (Bit 5) */ +#define CCU4_GCST_S1DSS_Msk (0x20UL) /*!< CCU4 GCST: S1DSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S1PSS_Pos (6UL) /*!< CCU4 GCST: S1PSS (Bit 6) */ +#define CCU4_GCST_S1PSS_Msk (0x40UL) /*!< CCU4 GCST: S1PSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S2SS_Pos (8UL) /*!< CCU4 GCST: S2SS (Bit 8) */ +#define CCU4_GCST_S2SS_Msk (0x100UL) /*!< CCU4 GCST: S2SS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S2DSS_Pos (9UL) /*!< CCU4 GCST: S2DSS (Bit 9) */ +#define CCU4_GCST_S2DSS_Msk (0x200UL) /*!< CCU4 GCST: S2DSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S2PSS_Pos (10UL) /*!< CCU4 GCST: S2PSS (Bit 10) */ +#define CCU4_GCST_S2PSS_Msk (0x400UL) /*!< CCU4 GCST: S2PSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S3SS_Pos (12UL) /*!< CCU4 GCST: S3SS (Bit 12) */ +#define CCU4_GCST_S3SS_Msk (0x1000UL) /*!< CCU4 GCST: S3SS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S3DSS_Pos (13UL) /*!< CCU4 GCST: S3DSS (Bit 13) */ +#define CCU4_GCST_S3DSS_Msk (0x2000UL) /*!< CCU4 GCST: S3DSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_S3PSS_Pos (14UL) /*!< CCU4 GCST: S3PSS (Bit 14) */ +#define CCU4_GCST_S3PSS_Msk (0x4000UL) /*!< CCU4 GCST: S3PSS (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_CC40ST_Pos (16UL) /*!< CCU4 GCST: CC40ST (Bit 16) */ +#define CCU4_GCST_CC40ST_Msk (0x10000UL) /*!< CCU4 GCST: CC40ST (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_CC41ST_Pos (17UL) /*!< CCU4 GCST: CC41ST (Bit 17) */ +#define CCU4_GCST_CC41ST_Msk (0x20000UL) /*!< CCU4 GCST: CC41ST (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_CC42ST_Pos (18UL) /*!< CCU4 GCST: CC42ST (Bit 18) */ +#define CCU4_GCST_CC42ST_Msk (0x40000UL) /*!< CCU4 GCST: CC42ST (Bitfield-Mask: 0x01) */ +#define CCU4_GCST_CC43ST_Pos (19UL) /*!< CCU4 GCST: CC43ST (Bit 19) */ +#define CCU4_GCST_CC43ST_Msk (0x80000UL) /*!< CCU4 GCST: CC43ST (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU4_ECRD --------------------------------- */ +#define CCU4_ECRD_CAPV_Pos (0UL) /*!< CCU4 ECRD: CAPV (Bit 0) */ +#define CCU4_ECRD_CAPV_Msk (0xffffUL) /*!< CCU4 ECRD: CAPV (Bitfield-Mask: 0xffff) */ +#define CCU4_ECRD_FPCV_Pos (16UL) /*!< CCU4 ECRD: FPCV (Bit 16) */ +#define CCU4_ECRD_FPCV_Msk (0xf0000UL) /*!< CCU4 ECRD: FPCV (Bitfield-Mask: 0x0f) */ +#define CCU4_ECRD_SPTR_Pos (20UL) /*!< CCU4 ECRD: SPTR (Bit 20) */ +#define CCU4_ECRD_SPTR_Msk (0x300000UL) /*!< CCU4 ECRD: SPTR (Bitfield-Mask: 0x03) */ +#define CCU4_ECRD_VPTR_Pos (22UL) /*!< CCU4 ECRD: VPTR (Bit 22) */ +#define CCU4_ECRD_VPTR_Msk (0xc00000UL) /*!< CCU4 ECRD: VPTR (Bitfield-Mask: 0x03) */ +#define CCU4_ECRD_FFL_Pos (24UL) /*!< CCU4 ECRD: FFL (Bit 24) */ +#define CCU4_ECRD_FFL_Msk (0x1000000UL) /*!< CCU4 ECRD: FFL (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU4_MIDR --------------------------------- */ +#define CCU4_MIDR_MODR_Pos (0UL) /*!< CCU4 MIDR: MODR (Bit 0) */ +#define CCU4_MIDR_MODR_Msk (0xffUL) /*!< CCU4 MIDR: MODR (Bitfield-Mask: 0xff) */ +#define CCU4_MIDR_MODT_Pos (8UL) /*!< CCU4 MIDR: MODT (Bit 8) */ +#define CCU4_MIDR_MODT_Msk (0xff00UL) /*!< CCU4 MIDR: MODT (Bitfield-Mask: 0xff) */ +#define CCU4_MIDR_MODN_Pos (16UL) /*!< CCU4 MIDR: MODN (Bit 16) */ +#define CCU4_MIDR_MODN_Msk (0xffff0000UL) /*!< CCU4 MIDR: MODN (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ Group 'CCU4_CC4' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- CCU4_CC4_INS -------------------------------- */ +#define CCU4_CC4_INS_EV0IS_Pos (0UL) /*!< CCU4_CC4 INS: EV0IS (Bit 0) */ +#define CCU4_CC4_INS_EV0IS_Msk (0xfUL) /*!< CCU4_CC4 INS: EV0IS (Bitfield-Mask: 0x0f) */ +#define CCU4_CC4_INS_EV1IS_Pos (4UL) /*!< CCU4_CC4 INS: EV1IS (Bit 4) */ +#define CCU4_CC4_INS_EV1IS_Msk (0xf0UL) /*!< CCU4_CC4 INS: EV1IS (Bitfield-Mask: 0x0f) */ +#define CCU4_CC4_INS_EV2IS_Pos (8UL) /*!< CCU4_CC4 INS: EV2IS (Bit 8) */ +#define CCU4_CC4_INS_EV2IS_Msk (0xf00UL) /*!< CCU4_CC4 INS: EV2IS (Bitfield-Mask: 0x0f) */ +#define CCU4_CC4_INS_EV0EM_Pos (16UL) /*!< CCU4_CC4 INS: EV0EM (Bit 16) */ +#define CCU4_CC4_INS_EV0EM_Msk (0x30000UL) /*!< CCU4_CC4 INS: EV0EM (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_INS_EV1EM_Pos (18UL) /*!< CCU4_CC4 INS: EV1EM (Bit 18) */ +#define CCU4_CC4_INS_EV1EM_Msk (0xc0000UL) /*!< CCU4_CC4 INS: EV1EM (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_INS_EV2EM_Pos (20UL) /*!< CCU4_CC4 INS: EV2EM (Bit 20) */ +#define CCU4_CC4_INS_EV2EM_Msk (0x300000UL) /*!< CCU4_CC4 INS: EV2EM (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_INS_EV0LM_Pos (22UL) /*!< CCU4_CC4 INS: EV0LM (Bit 22) */ +#define CCU4_CC4_INS_EV0LM_Msk (0x400000UL) /*!< CCU4_CC4 INS: EV0LM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INS_EV1LM_Pos (23UL) /*!< CCU4_CC4 INS: EV1LM (Bit 23) */ +#define CCU4_CC4_INS_EV1LM_Msk (0x800000UL) /*!< CCU4_CC4 INS: EV1LM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INS_EV2LM_Pos (24UL) /*!< CCU4_CC4 INS: EV2LM (Bit 24) */ +#define CCU4_CC4_INS_EV2LM_Msk (0x1000000UL) /*!< CCU4_CC4 INS: EV2LM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INS_LPF0M_Pos (25UL) /*!< CCU4_CC4 INS: LPF0M (Bit 25) */ +#define CCU4_CC4_INS_LPF0M_Msk (0x6000000UL) /*!< CCU4_CC4 INS: LPF0M (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_INS_LPF1M_Pos (27UL) /*!< CCU4_CC4 INS: LPF1M (Bit 27) */ +#define CCU4_CC4_INS_LPF1M_Msk (0x18000000UL) /*!< CCU4_CC4 INS: LPF1M (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_INS_LPF2M_Pos (29UL) /*!< CCU4_CC4 INS: LPF2M (Bit 29) */ +#define CCU4_CC4_INS_LPF2M_Msk (0x60000000UL) /*!< CCU4_CC4 INS: LPF2M (Bitfield-Mask: 0x03) */ + +/* -------------------------------- CCU4_CC4_CMC -------------------------------- */ +#define CCU4_CC4_CMC_STRTS_Pos (0UL) /*!< CCU4_CC4 CMC: STRTS (Bit 0) */ +#define CCU4_CC4_CMC_STRTS_Msk (0x3UL) /*!< CCU4_CC4 CMC: STRTS (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_ENDS_Pos (2UL) /*!< CCU4_CC4 CMC: ENDS (Bit 2) */ +#define CCU4_CC4_CMC_ENDS_Msk (0xcUL) /*!< CCU4_CC4 CMC: ENDS (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_CAP0S_Pos (4UL) /*!< CCU4_CC4 CMC: CAP0S (Bit 4) */ +#define CCU4_CC4_CMC_CAP0S_Msk (0x30UL) /*!< CCU4_CC4 CMC: CAP0S (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_CAP1S_Pos (6UL) /*!< CCU4_CC4 CMC: CAP1S (Bit 6) */ +#define CCU4_CC4_CMC_CAP1S_Msk (0xc0UL) /*!< CCU4_CC4 CMC: CAP1S (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_GATES_Pos (8UL) /*!< CCU4_CC4 CMC: GATES (Bit 8) */ +#define CCU4_CC4_CMC_GATES_Msk (0x300UL) /*!< CCU4_CC4 CMC: GATES (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_UDS_Pos (10UL) /*!< CCU4_CC4 CMC: UDS (Bit 10) */ +#define CCU4_CC4_CMC_UDS_Msk (0xc00UL) /*!< CCU4_CC4 CMC: UDS (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_LDS_Pos (12UL) /*!< CCU4_CC4 CMC: LDS (Bit 12) */ +#define CCU4_CC4_CMC_LDS_Msk (0x3000UL) /*!< CCU4_CC4 CMC: LDS (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_CNTS_Pos (14UL) /*!< CCU4_CC4 CMC: CNTS (Bit 14) */ +#define CCU4_CC4_CMC_CNTS_Msk (0xc000UL) /*!< CCU4_CC4 CMC: CNTS (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_OFS_Pos (16UL) /*!< CCU4_CC4 CMC: OFS (Bit 16) */ +#define CCU4_CC4_CMC_OFS_Msk (0x10000UL) /*!< CCU4_CC4 CMC: OFS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_CMC_TS_Pos (17UL) /*!< CCU4_CC4 CMC: TS (Bit 17) */ +#define CCU4_CC4_CMC_TS_Msk (0x20000UL) /*!< CCU4_CC4 CMC: TS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_CMC_MOS_Pos (18UL) /*!< CCU4_CC4 CMC: MOS (Bit 18) */ +#define CCU4_CC4_CMC_MOS_Msk (0xc0000UL) /*!< CCU4_CC4 CMC: MOS (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_CMC_TCE_Pos (20UL) /*!< CCU4_CC4 CMC: TCE (Bit 20) */ +#define CCU4_CC4_CMC_TCE_Msk (0x100000UL) /*!< CCU4_CC4 CMC: TCE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU4_CC4_TCST ------------------------------- */ +#define CCU4_CC4_TCST_TRB_Pos (0UL) /*!< CCU4_CC4 TCST: TRB (Bit 0) */ +#define CCU4_CC4_TCST_TRB_Msk (0x1UL) /*!< CCU4_CC4 TCST: TRB (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TCST_CDIR_Pos (1UL) /*!< CCU4_CC4 TCST: CDIR (Bit 1) */ +#define CCU4_CC4_TCST_CDIR_Msk (0x2UL) /*!< CCU4_CC4 TCST: CDIR (Bitfield-Mask: 0x01) */ + +/* ------------------------------- CCU4_CC4_TCSET ------------------------------- */ +#define CCU4_CC4_TCSET_TRBS_Pos (0UL) /*!< CCU4_CC4 TCSET: TRBS (Bit 0) */ +#define CCU4_CC4_TCSET_TRBS_Msk (0x1UL) /*!< CCU4_CC4 TCSET: TRBS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */ +#define CCU4_CC4_TCCLR_TRBC_Pos (0UL) /*!< CCU4_CC4 TCCLR: TRBC (Bit 0) */ +#define CCU4_CC4_TCCLR_TRBC_Msk (0x1UL) /*!< CCU4_CC4 TCCLR: TRBC (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TCCLR_TCC_Pos (1UL) /*!< CCU4_CC4 TCCLR: TCC (Bit 1) */ +#define CCU4_CC4_TCCLR_TCC_Msk (0x2UL) /*!< CCU4_CC4 TCCLR: TCC (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TCCLR_DITC_Pos (2UL) /*!< CCU4_CC4 TCCLR: DITC (Bit 2) */ +#define CCU4_CC4_TCCLR_DITC_Msk (0x4UL) /*!< CCU4_CC4 TCCLR: DITC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CCU4_CC4_TC -------------------------------- */ +#define CCU4_CC4_TC_TCM_Pos (0UL) /*!< CCU4_CC4 TC: TCM (Bit 0) */ +#define CCU4_CC4_TC_TCM_Msk (0x1UL) /*!< CCU4_CC4 TC: TCM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_TSSM_Pos (1UL) /*!< CCU4_CC4 TC: TSSM (Bit 1) */ +#define CCU4_CC4_TC_TSSM_Msk (0x2UL) /*!< CCU4_CC4 TC: TSSM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_CLST_Pos (2UL) /*!< CCU4_CC4 TC: CLST (Bit 2) */ +#define CCU4_CC4_TC_CLST_Msk (0x4UL) /*!< CCU4_CC4 TC: CLST (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_CMOD_Pos (3UL) /*!< CCU4_CC4 TC: CMOD (Bit 3) */ +#define CCU4_CC4_TC_CMOD_Msk (0x8UL) /*!< CCU4_CC4 TC: CMOD (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_ECM_Pos (4UL) /*!< CCU4_CC4 TC: ECM (Bit 4) */ +#define CCU4_CC4_TC_ECM_Msk (0x10UL) /*!< CCU4_CC4 TC: ECM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_CAPC_Pos (5UL) /*!< CCU4_CC4 TC: CAPC (Bit 5) */ +#define CCU4_CC4_TC_CAPC_Msk (0x60UL) /*!< CCU4_CC4 TC: CAPC (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_TC_ENDM_Pos (8UL) /*!< CCU4_CC4 TC: ENDM (Bit 8) */ +#define CCU4_CC4_TC_ENDM_Msk (0x300UL) /*!< CCU4_CC4 TC: ENDM (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_TC_STRM_Pos (10UL) /*!< CCU4_CC4 TC: STRM (Bit 10) */ +#define CCU4_CC4_TC_STRM_Msk (0x400UL) /*!< CCU4_CC4 TC: STRM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_SCE_Pos (11UL) /*!< CCU4_CC4 TC: SCE (Bit 11) */ +#define CCU4_CC4_TC_SCE_Msk (0x800UL) /*!< CCU4_CC4 TC: SCE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_CCS_Pos (12UL) /*!< CCU4_CC4 TC: CCS (Bit 12) */ +#define CCU4_CC4_TC_CCS_Msk (0x1000UL) /*!< CCU4_CC4 TC: CCS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_DITHE_Pos (13UL) /*!< CCU4_CC4 TC: DITHE (Bit 13) */ +#define CCU4_CC4_TC_DITHE_Msk (0x6000UL) /*!< CCU4_CC4 TC: DITHE (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_TC_DIM_Pos (15UL) /*!< CCU4_CC4 TC: DIM (Bit 15) */ +#define CCU4_CC4_TC_DIM_Msk (0x8000UL) /*!< CCU4_CC4 TC: DIM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_FPE_Pos (16UL) /*!< CCU4_CC4 TC: FPE (Bit 16) */ +#define CCU4_CC4_TC_FPE_Msk (0x10000UL) /*!< CCU4_CC4 TC: FPE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_TRAPE_Pos (17UL) /*!< CCU4_CC4 TC: TRAPE (Bit 17) */ +#define CCU4_CC4_TC_TRAPE_Msk (0x20000UL) /*!< CCU4_CC4 TC: TRAPE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_TRPSE_Pos (21UL) /*!< CCU4_CC4 TC: TRPSE (Bit 21) */ +#define CCU4_CC4_TC_TRPSE_Msk (0x200000UL) /*!< CCU4_CC4 TC: TRPSE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_TRPSW_Pos (22UL) /*!< CCU4_CC4 TC: TRPSW (Bit 22) */ +#define CCU4_CC4_TC_TRPSW_Msk (0x400000UL) /*!< CCU4_CC4 TC: TRPSW (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_EMS_Pos (23UL) /*!< CCU4_CC4 TC: EMS (Bit 23) */ +#define CCU4_CC4_TC_EMS_Msk (0x800000UL) /*!< CCU4_CC4 TC: EMS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_EMT_Pos (24UL) /*!< CCU4_CC4 TC: EMT (Bit 24) */ +#define CCU4_CC4_TC_EMT_Msk (0x1000000UL) /*!< CCU4_CC4 TC: EMT (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_TC_MCME_Pos (25UL) /*!< CCU4_CC4 TC: MCME (Bit 25) */ +#define CCU4_CC4_TC_MCME_Msk (0x2000000UL) /*!< CCU4_CC4 TC: MCME (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU4_CC4_PSL -------------------------------- */ +#define CCU4_CC4_PSL_PSL_Pos (0UL) /*!< CCU4_CC4 PSL: PSL (Bit 0) */ +#define CCU4_CC4_PSL_PSL_Msk (0x1UL) /*!< CCU4_CC4 PSL: PSL (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU4_CC4_DIT -------------------------------- */ +#define CCU4_CC4_DIT_DCV_Pos (0UL) /*!< CCU4_CC4 DIT: DCV (Bit 0) */ +#define CCU4_CC4_DIT_DCV_Msk (0xfUL) /*!< CCU4_CC4 DIT: DCV (Bitfield-Mask: 0x0f) */ +#define CCU4_CC4_DIT_DCNT_Pos (8UL) /*!< CCU4_CC4 DIT: DCNT (Bit 8) */ +#define CCU4_CC4_DIT_DCNT_Msk (0xf00UL) /*!< CCU4_CC4 DIT: DCNT (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU4_CC4_DITS ------------------------------- */ +#define CCU4_CC4_DITS_DCVS_Pos (0UL) /*!< CCU4_CC4 DITS: DCVS (Bit 0) */ +#define CCU4_CC4_DITS_DCVS_Msk (0xfUL) /*!< CCU4_CC4 DITS: DCVS (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU4_CC4_PSC -------------------------------- */ +#define CCU4_CC4_PSC_PSIV_Pos (0UL) /*!< CCU4_CC4 PSC: PSIV (Bit 0) */ +#define CCU4_CC4_PSC_PSIV_Msk (0xfUL) /*!< CCU4_CC4 PSC: PSIV (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU4_CC4_FPC -------------------------------- */ +#define CCU4_CC4_FPC_PCMP_Pos (0UL) /*!< CCU4_CC4 FPC: PCMP (Bit 0) */ +#define CCU4_CC4_FPC_PCMP_Msk (0xfUL) /*!< CCU4_CC4 FPC: PCMP (Bitfield-Mask: 0x0f) */ +#define CCU4_CC4_FPC_PVAL_Pos (8UL) /*!< CCU4_CC4 FPC: PVAL (Bit 8) */ +#define CCU4_CC4_FPC_PVAL_Msk (0xf00UL) /*!< CCU4_CC4 FPC: PVAL (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU4_CC4_FPCS ------------------------------- */ +#define CCU4_CC4_FPCS_PCMP_Pos (0UL) /*!< CCU4_CC4 FPCS: PCMP (Bit 0) */ +#define CCU4_CC4_FPCS_PCMP_Msk (0xfUL) /*!< CCU4_CC4 FPCS: PCMP (Bitfield-Mask: 0x0f) */ + +/* --------------------------------- CCU4_CC4_PR -------------------------------- */ +#define CCU4_CC4_PR_PR_Pos (0UL) /*!< CCU4_CC4 PR: PR (Bit 0) */ +#define CCU4_CC4_PR_PR_Msk (0xffffUL) /*!< CCU4_CC4 PR: PR (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU4_CC4_PRS -------------------------------- */ +#define CCU4_CC4_PRS_PRS_Pos (0UL) /*!< CCU4_CC4 PRS: PRS (Bit 0) */ +#define CCU4_CC4_PRS_PRS_Msk (0xffffUL) /*!< CCU4_CC4 PRS: PRS (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- CCU4_CC4_CR -------------------------------- */ +#define CCU4_CC4_CR_CR_Pos (0UL) /*!< CCU4_CC4 CR: CR (Bit 0) */ +#define CCU4_CC4_CR_CR_Msk (0xffffUL) /*!< CCU4_CC4 CR: CR (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU4_CC4_CRS -------------------------------- */ +#define CCU4_CC4_CRS_CRS_Pos (0UL) /*!< CCU4_CC4 CRS: CRS (Bit 0) */ +#define CCU4_CC4_CRS_CRS_Msk (0xffffUL) /*!< CCU4_CC4 CRS: CRS (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- CCU4_CC4_TIMER ------------------------------- */ +#define CCU4_CC4_TIMER_TVAL_Pos (0UL) /*!< CCU4_CC4 TIMER: TVAL (Bit 0) */ +#define CCU4_CC4_TIMER_TVAL_Msk (0xffffUL) /*!< CCU4_CC4 TIMER: TVAL (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- CCU4_CC4_CV -------------------------------- */ +#define CCU4_CC4_CV_CAPTV_Pos (0UL) /*!< CCU4_CC4 CV: CAPTV (Bit 0) */ +#define CCU4_CC4_CV_CAPTV_Msk (0xffffUL) /*!< CCU4_CC4 CV: CAPTV (Bitfield-Mask: 0xffff) */ +#define CCU4_CC4_CV_FPCV_Pos (16UL) /*!< CCU4_CC4 CV: FPCV (Bit 16) */ +#define CCU4_CC4_CV_FPCV_Msk (0xf0000UL) /*!< CCU4_CC4 CV: FPCV (Bitfield-Mask: 0x0f) */ +#define CCU4_CC4_CV_FFL_Pos (20UL) /*!< CCU4_CC4 CV: FFL (Bit 20) */ +#define CCU4_CC4_CV_FFL_Msk (0x100000UL) /*!< CCU4_CC4 CV: FFL (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU4_CC4_INTS ------------------------------- */ +#define CCU4_CC4_INTS_PMUS_Pos (0UL) /*!< CCU4_CC4 INTS: PMUS (Bit 0) */ +#define CCU4_CC4_INTS_PMUS_Msk (0x1UL) /*!< CCU4_CC4 INTS: PMUS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTS_OMDS_Pos (1UL) /*!< CCU4_CC4 INTS: OMDS (Bit 1) */ +#define CCU4_CC4_INTS_OMDS_Msk (0x2UL) /*!< CCU4_CC4 INTS: OMDS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTS_CMUS_Pos (2UL) /*!< CCU4_CC4 INTS: CMUS (Bit 2) */ +#define CCU4_CC4_INTS_CMUS_Msk (0x4UL) /*!< CCU4_CC4 INTS: CMUS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTS_CMDS_Pos (3UL) /*!< CCU4_CC4 INTS: CMDS (Bit 3) */ +#define CCU4_CC4_INTS_CMDS_Msk (0x8UL) /*!< CCU4_CC4 INTS: CMDS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTS_E0AS_Pos (8UL) /*!< CCU4_CC4 INTS: E0AS (Bit 8) */ +#define CCU4_CC4_INTS_E0AS_Msk (0x100UL) /*!< CCU4_CC4 INTS: E0AS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTS_E1AS_Pos (9UL) /*!< CCU4_CC4 INTS: E1AS (Bit 9) */ +#define CCU4_CC4_INTS_E1AS_Msk (0x200UL) /*!< CCU4_CC4 INTS: E1AS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTS_E2AS_Pos (10UL) /*!< CCU4_CC4 INTS: E2AS (Bit 10) */ +#define CCU4_CC4_INTS_E2AS_Msk (0x400UL) /*!< CCU4_CC4 INTS: E2AS (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTS_TRPF_Pos (11UL) /*!< CCU4_CC4 INTS: TRPF (Bit 11) */ +#define CCU4_CC4_INTS_TRPF_Msk (0x800UL) /*!< CCU4_CC4 INTS: TRPF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU4_CC4_INTE ------------------------------- */ +#define CCU4_CC4_INTE_PME_Pos (0UL) /*!< CCU4_CC4 INTE: PME (Bit 0) */ +#define CCU4_CC4_INTE_PME_Msk (0x1UL) /*!< CCU4_CC4 INTE: PME (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTE_OME_Pos (1UL) /*!< CCU4_CC4 INTE: OME (Bit 1) */ +#define CCU4_CC4_INTE_OME_Msk (0x2UL) /*!< CCU4_CC4 INTE: OME (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTE_CMUE_Pos (2UL) /*!< CCU4_CC4 INTE: CMUE (Bit 2) */ +#define CCU4_CC4_INTE_CMUE_Msk (0x4UL) /*!< CCU4_CC4 INTE: CMUE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTE_CMDE_Pos (3UL) /*!< CCU4_CC4 INTE: CMDE (Bit 3) */ +#define CCU4_CC4_INTE_CMDE_Msk (0x8UL) /*!< CCU4_CC4 INTE: CMDE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTE_E0AE_Pos (8UL) /*!< CCU4_CC4 INTE: E0AE (Bit 8) */ +#define CCU4_CC4_INTE_E0AE_Msk (0x100UL) /*!< CCU4_CC4 INTE: E0AE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTE_E1AE_Pos (9UL) /*!< CCU4_CC4 INTE: E1AE (Bit 9) */ +#define CCU4_CC4_INTE_E1AE_Msk (0x200UL) /*!< CCU4_CC4 INTE: E1AE (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_INTE_E2AE_Pos (10UL) /*!< CCU4_CC4 INTE: E2AE (Bit 10) */ +#define CCU4_CC4_INTE_E2AE_Msk (0x400UL) /*!< CCU4_CC4 INTE: E2AE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU4_CC4_SRS -------------------------------- */ +#define CCU4_CC4_SRS_POSR_Pos (0UL) /*!< CCU4_CC4 SRS: POSR (Bit 0) */ +#define CCU4_CC4_SRS_POSR_Msk (0x3UL) /*!< CCU4_CC4 SRS: POSR (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_SRS_CMSR_Pos (2UL) /*!< CCU4_CC4 SRS: CMSR (Bit 2) */ +#define CCU4_CC4_SRS_CMSR_Msk (0xcUL) /*!< CCU4_CC4 SRS: CMSR (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_SRS_E0SR_Pos (8UL) /*!< CCU4_CC4 SRS: E0SR (Bit 8) */ +#define CCU4_CC4_SRS_E0SR_Msk (0x300UL) /*!< CCU4_CC4 SRS: E0SR (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_SRS_E1SR_Pos (10UL) /*!< CCU4_CC4 SRS: E1SR (Bit 10) */ +#define CCU4_CC4_SRS_E1SR_Msk (0xc00UL) /*!< CCU4_CC4 SRS: E1SR (Bitfield-Mask: 0x03) */ +#define CCU4_CC4_SRS_E2SR_Pos (12UL) /*!< CCU4_CC4 SRS: E2SR (Bit 12) */ +#define CCU4_CC4_SRS_E2SR_Msk (0x3000UL) /*!< CCU4_CC4 SRS: E2SR (Bitfield-Mask: 0x03) */ + +/* -------------------------------- CCU4_CC4_SWS -------------------------------- */ +#define CCU4_CC4_SWS_SPM_Pos (0UL) /*!< CCU4_CC4 SWS: SPM (Bit 0) */ +#define CCU4_CC4_SWS_SPM_Msk (0x1UL) /*!< CCU4_CC4 SWS: SPM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWS_SOM_Pos (1UL) /*!< CCU4_CC4 SWS: SOM (Bit 1) */ +#define CCU4_CC4_SWS_SOM_Msk (0x2UL) /*!< CCU4_CC4 SWS: SOM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWS_SCMU_Pos (2UL) /*!< CCU4_CC4 SWS: SCMU (Bit 2) */ +#define CCU4_CC4_SWS_SCMU_Msk (0x4UL) /*!< CCU4_CC4 SWS: SCMU (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWS_SCMD_Pos (3UL) /*!< CCU4_CC4 SWS: SCMD (Bit 3) */ +#define CCU4_CC4_SWS_SCMD_Msk (0x8UL) /*!< CCU4_CC4 SWS: SCMD (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWS_SE0A_Pos (8UL) /*!< CCU4_CC4 SWS: SE0A (Bit 8) */ +#define CCU4_CC4_SWS_SE0A_Msk (0x100UL) /*!< CCU4_CC4 SWS: SE0A (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWS_SE1A_Pos (9UL) /*!< CCU4_CC4 SWS: SE1A (Bit 9) */ +#define CCU4_CC4_SWS_SE1A_Msk (0x200UL) /*!< CCU4_CC4 SWS: SE1A (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWS_SE2A_Pos (10UL) /*!< CCU4_CC4 SWS: SE2A (Bit 10) */ +#define CCU4_CC4_SWS_SE2A_Msk (0x400UL) /*!< CCU4_CC4 SWS: SE2A (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWS_STRPF_Pos (11UL) /*!< CCU4_CC4 SWS: STRPF (Bit 11) */ +#define CCU4_CC4_SWS_STRPF_Msk (0x800UL) /*!< CCU4_CC4 SWS: STRPF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU4_CC4_SWR -------------------------------- */ +#define CCU4_CC4_SWR_RPM_Pos (0UL) /*!< CCU4_CC4 SWR: RPM (Bit 0) */ +#define CCU4_CC4_SWR_RPM_Msk (0x1UL) /*!< CCU4_CC4 SWR: RPM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWR_ROM_Pos (1UL) /*!< CCU4_CC4 SWR: ROM (Bit 1) */ +#define CCU4_CC4_SWR_ROM_Msk (0x2UL) /*!< CCU4_CC4 SWR: ROM (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWR_RCMU_Pos (2UL) /*!< CCU4_CC4 SWR: RCMU (Bit 2) */ +#define CCU4_CC4_SWR_RCMU_Msk (0x4UL) /*!< CCU4_CC4 SWR: RCMU (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWR_RCMD_Pos (3UL) /*!< CCU4_CC4 SWR: RCMD (Bit 3) */ +#define CCU4_CC4_SWR_RCMD_Msk (0x8UL) /*!< CCU4_CC4 SWR: RCMD (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWR_RE0A_Pos (8UL) /*!< CCU4_CC4 SWR: RE0A (Bit 8) */ +#define CCU4_CC4_SWR_RE0A_Msk (0x100UL) /*!< CCU4_CC4 SWR: RE0A (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWR_RE1A_Pos (9UL) /*!< CCU4_CC4 SWR: RE1A (Bit 9) */ +#define CCU4_CC4_SWR_RE1A_Msk (0x200UL) /*!< CCU4_CC4 SWR: RE1A (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWR_RE2A_Pos (10UL) /*!< CCU4_CC4 SWR: RE2A (Bit 10) */ +#define CCU4_CC4_SWR_RE2A_Msk (0x400UL) /*!< CCU4_CC4 SWR: RE2A (Bitfield-Mask: 0x01) */ +#define CCU4_CC4_SWR_RTRPF_Pos (11UL) /*!< CCU4_CC4 SWR: RTRPF (Bit 11) */ +#define CCU4_CC4_SWR_RTRPF_Msk (0x800UL) /*!< CCU4_CC4 SWR: RTRPF (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'CCU8' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- CCU8_GCTRL --------------------------------- */ +#define CCU8_GCTRL_PRBC_Pos (0UL) /*!< CCU8 GCTRL: PRBC (Bit 0) */ +#define CCU8_GCTRL_PRBC_Msk (0x7UL) /*!< CCU8 GCTRL: PRBC (Bitfield-Mask: 0x07) */ +#define CCU8_GCTRL_PCIS_Pos (4UL) /*!< CCU8 GCTRL: PCIS (Bit 4) */ +#define CCU8_GCTRL_PCIS_Msk (0x30UL) /*!< CCU8 GCTRL: PCIS (Bitfield-Mask: 0x03) */ +#define CCU8_GCTRL_SUSCFG_Pos (8UL) /*!< CCU8 GCTRL: SUSCFG (Bit 8) */ +#define CCU8_GCTRL_SUSCFG_Msk (0x300UL) /*!< CCU8 GCTRL: SUSCFG (Bitfield-Mask: 0x03) */ +#define CCU8_GCTRL_MSE0_Pos (10UL) /*!< CCU8 GCTRL: MSE0 (Bit 10) */ +#define CCU8_GCTRL_MSE0_Msk (0x400UL) /*!< CCU8 GCTRL: MSE0 (Bitfield-Mask: 0x01) */ +#define CCU8_GCTRL_MSE1_Pos (11UL) /*!< CCU8 GCTRL: MSE1 (Bit 11) */ +#define CCU8_GCTRL_MSE1_Msk (0x800UL) /*!< CCU8 GCTRL: MSE1 (Bitfield-Mask: 0x01) */ +#define CCU8_GCTRL_MSE2_Pos (12UL) /*!< CCU8 GCTRL: MSE2 (Bit 12) */ +#define CCU8_GCTRL_MSE2_Msk (0x1000UL) /*!< CCU8 GCTRL: MSE2 (Bitfield-Mask: 0x01) */ +#define CCU8_GCTRL_MSE3_Pos (13UL) /*!< CCU8 GCTRL: MSE3 (Bit 13) */ +#define CCU8_GCTRL_MSE3_Msk (0x2000UL) /*!< CCU8 GCTRL: MSE3 (Bitfield-Mask: 0x01) */ +#define CCU8_GCTRL_MSDE_Pos (14UL) /*!< CCU8 GCTRL: MSDE (Bit 14) */ +#define CCU8_GCTRL_MSDE_Msk (0xc000UL) /*!< CCU8 GCTRL: MSDE (Bitfield-Mask: 0x03) */ + +/* --------------------------------- CCU8_GSTAT --------------------------------- */ +#define CCU8_GSTAT_S0I_Pos (0UL) /*!< CCU8 GSTAT: S0I (Bit 0) */ +#define CCU8_GSTAT_S0I_Msk (0x1UL) /*!< CCU8 GSTAT: S0I (Bitfield-Mask: 0x01) */ +#define CCU8_GSTAT_S1I_Pos (1UL) /*!< CCU8 GSTAT: S1I (Bit 1) */ +#define CCU8_GSTAT_S1I_Msk (0x2UL) /*!< CCU8 GSTAT: S1I (Bitfield-Mask: 0x01) */ +#define CCU8_GSTAT_S2I_Pos (2UL) /*!< CCU8 GSTAT: S2I (Bit 2) */ +#define CCU8_GSTAT_S2I_Msk (0x4UL) /*!< CCU8 GSTAT: S2I (Bitfield-Mask: 0x01) */ +#define CCU8_GSTAT_S3I_Pos (3UL) /*!< CCU8 GSTAT: S3I (Bit 3) */ +#define CCU8_GSTAT_S3I_Msk (0x8UL) /*!< CCU8 GSTAT: S3I (Bitfield-Mask: 0x01) */ +#define CCU8_GSTAT_PRB_Pos (8UL) /*!< CCU8 GSTAT: PRB (Bit 8) */ +#define CCU8_GSTAT_PRB_Msk (0x100UL) /*!< CCU8 GSTAT: PRB (Bitfield-Mask: 0x01) */ +#define CCU8_GSTAT_PCRB_Pos (10UL) /*!< CCU8 GSTAT: PCRB (Bit 10) */ +#define CCU8_GSTAT_PCRB_Msk (0x400UL) /*!< CCU8 GSTAT: PCRB (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CCU8_GIDLS --------------------------------- */ +#define CCU8_GIDLS_SS0I_Pos (0UL) /*!< CCU8 GIDLS: SS0I (Bit 0) */ +#define CCU8_GIDLS_SS0I_Msk (0x1UL) /*!< CCU8 GIDLS: SS0I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLS_SS1I_Pos (1UL) /*!< CCU8 GIDLS: SS1I (Bit 1) */ +#define CCU8_GIDLS_SS1I_Msk (0x2UL) /*!< CCU8 GIDLS: SS1I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLS_SS2I_Pos (2UL) /*!< CCU8 GIDLS: SS2I (Bit 2) */ +#define CCU8_GIDLS_SS2I_Msk (0x4UL) /*!< CCU8 GIDLS: SS2I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLS_SS3I_Pos (3UL) /*!< CCU8 GIDLS: SS3I (Bit 3) */ +#define CCU8_GIDLS_SS3I_Msk (0x8UL) /*!< CCU8 GIDLS: SS3I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLS_CPRB_Pos (8UL) /*!< CCU8 GIDLS: CPRB (Bit 8) */ +#define CCU8_GIDLS_CPRB_Msk (0x100UL) /*!< CCU8 GIDLS: CPRB (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLS_PSIC_Pos (9UL) /*!< CCU8 GIDLS: PSIC (Bit 9) */ +#define CCU8_GIDLS_PSIC_Msk (0x200UL) /*!< CCU8 GIDLS: PSIC (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLS_CPCH_Pos (10UL) /*!< CCU8 GIDLS: CPCH (Bit 10) */ +#define CCU8_GIDLS_CPCH_Msk (0x400UL) /*!< CCU8 GIDLS: CPCH (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CCU8_GIDLC --------------------------------- */ +#define CCU8_GIDLC_CS0I_Pos (0UL) /*!< CCU8 GIDLC: CS0I (Bit 0) */ +#define CCU8_GIDLC_CS0I_Msk (0x1UL) /*!< CCU8 GIDLC: CS0I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLC_CS1I_Pos (1UL) /*!< CCU8 GIDLC: CS1I (Bit 1) */ +#define CCU8_GIDLC_CS1I_Msk (0x2UL) /*!< CCU8 GIDLC: CS1I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLC_CS2I_Pos (2UL) /*!< CCU8 GIDLC: CS2I (Bit 2) */ +#define CCU8_GIDLC_CS2I_Msk (0x4UL) /*!< CCU8 GIDLC: CS2I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLC_CS3I_Pos (3UL) /*!< CCU8 GIDLC: CS3I (Bit 3) */ +#define CCU8_GIDLC_CS3I_Msk (0x8UL) /*!< CCU8 GIDLC: CS3I (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLC_SPRB_Pos (8UL) /*!< CCU8 GIDLC: SPRB (Bit 8) */ +#define CCU8_GIDLC_SPRB_Msk (0x100UL) /*!< CCU8 GIDLC: SPRB (Bitfield-Mask: 0x01) */ +#define CCU8_GIDLC_SPCH_Pos (10UL) /*!< CCU8 GIDLC: SPCH (Bit 10) */ +#define CCU8_GIDLC_SPCH_Msk (0x400UL) /*!< CCU8 GIDLC: SPCH (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU8_GCSS --------------------------------- */ +#define CCU8_GCSS_S0SE_Pos (0UL) /*!< CCU8 GCSS: S0SE (Bit 0) */ +#define CCU8_GCSS_S0SE_Msk (0x1UL) /*!< CCU8 GCSS: S0SE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S0DSE_Pos (1UL) /*!< CCU8 GCSS: S0DSE (Bit 1) */ +#define CCU8_GCSS_S0DSE_Msk (0x2UL) /*!< CCU8 GCSS: S0DSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S0PSE_Pos (2UL) /*!< CCU8 GCSS: S0PSE (Bit 2) */ +#define CCU8_GCSS_S0PSE_Msk (0x4UL) /*!< CCU8 GCSS: S0PSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S1SE_Pos (4UL) /*!< CCU8 GCSS: S1SE (Bit 4) */ +#define CCU8_GCSS_S1SE_Msk (0x10UL) /*!< CCU8 GCSS: S1SE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S1DSE_Pos (5UL) /*!< CCU8 GCSS: S1DSE (Bit 5) */ +#define CCU8_GCSS_S1DSE_Msk (0x20UL) /*!< CCU8 GCSS: S1DSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S1PSE_Pos (6UL) /*!< CCU8 GCSS: S1PSE (Bit 6) */ +#define CCU8_GCSS_S1PSE_Msk (0x40UL) /*!< CCU8 GCSS: S1PSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S2SE_Pos (8UL) /*!< CCU8 GCSS: S2SE (Bit 8) */ +#define CCU8_GCSS_S2SE_Msk (0x100UL) /*!< CCU8 GCSS: S2SE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S2DSE_Pos (9UL) /*!< CCU8 GCSS: S2DSE (Bit 9) */ +#define CCU8_GCSS_S2DSE_Msk (0x200UL) /*!< CCU8 GCSS: S2DSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S2PSE_Pos (10UL) /*!< CCU8 GCSS: S2PSE (Bit 10) */ +#define CCU8_GCSS_S2PSE_Msk (0x400UL) /*!< CCU8 GCSS: S2PSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S3SE_Pos (12UL) /*!< CCU8 GCSS: S3SE (Bit 12) */ +#define CCU8_GCSS_S3SE_Msk (0x1000UL) /*!< CCU8 GCSS: S3SE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S3DSE_Pos (13UL) /*!< CCU8 GCSS: S3DSE (Bit 13) */ +#define CCU8_GCSS_S3DSE_Msk (0x2000UL) /*!< CCU8 GCSS: S3DSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S3PSE_Pos (14UL) /*!< CCU8 GCSS: S3PSE (Bit 14) */ +#define CCU8_GCSS_S3PSE_Msk (0x4000UL) /*!< CCU8 GCSS: S3PSE (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S0ST1S_Pos (16UL) /*!< CCU8 GCSS: S0ST1S (Bit 16) */ +#define CCU8_GCSS_S0ST1S_Msk (0x10000UL) /*!< CCU8 GCSS: S0ST1S (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S1ST1S_Pos (17UL) /*!< CCU8 GCSS: S1ST1S (Bit 17) */ +#define CCU8_GCSS_S1ST1S_Msk (0x20000UL) /*!< CCU8 GCSS: S1ST1S (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S2ST1S_Pos (18UL) /*!< CCU8 GCSS: S2ST1S (Bit 18) */ +#define CCU8_GCSS_S2ST1S_Msk (0x40000UL) /*!< CCU8 GCSS: S2ST1S (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S3ST1S_Pos (19UL) /*!< CCU8 GCSS: S3ST1S (Bit 19) */ +#define CCU8_GCSS_S3ST1S_Msk (0x80000UL) /*!< CCU8 GCSS: S3ST1S (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S0ST2S_Pos (20UL) /*!< CCU8 GCSS: S0ST2S (Bit 20) */ +#define CCU8_GCSS_S0ST2S_Msk (0x100000UL) /*!< CCU8 GCSS: S0ST2S (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S1ST2S_Pos (21UL) /*!< CCU8 GCSS: S1ST2S (Bit 21) */ +#define CCU8_GCSS_S1ST2S_Msk (0x200000UL) /*!< CCU8 GCSS: S1ST2S (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S2ST2S_Pos (22UL) /*!< CCU8 GCSS: S2ST2S (Bit 22) */ +#define CCU8_GCSS_S2ST2S_Msk (0x400000UL) /*!< CCU8 GCSS: S2ST2S (Bitfield-Mask: 0x01) */ +#define CCU8_GCSS_S3ST2S_Pos (23UL) /*!< CCU8 GCSS: S3ST2S (Bit 23) */ +#define CCU8_GCSS_S3ST2S_Msk (0x800000UL) /*!< CCU8 GCSS: S3ST2S (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU8_GCSC --------------------------------- */ +#define CCU8_GCSC_S0SC_Pos (0UL) /*!< CCU8 GCSC: S0SC (Bit 0) */ +#define CCU8_GCSC_S0SC_Msk (0x1UL) /*!< CCU8 GCSC: S0SC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S0DSC_Pos (1UL) /*!< CCU8 GCSC: S0DSC (Bit 1) */ +#define CCU8_GCSC_S0DSC_Msk (0x2UL) /*!< CCU8 GCSC: S0DSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S0PSC_Pos (2UL) /*!< CCU8 GCSC: S0PSC (Bit 2) */ +#define CCU8_GCSC_S0PSC_Msk (0x4UL) /*!< CCU8 GCSC: S0PSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S1SC_Pos (4UL) /*!< CCU8 GCSC: S1SC (Bit 4) */ +#define CCU8_GCSC_S1SC_Msk (0x10UL) /*!< CCU8 GCSC: S1SC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S1DSC_Pos (5UL) /*!< CCU8 GCSC: S1DSC (Bit 5) */ +#define CCU8_GCSC_S1DSC_Msk (0x20UL) /*!< CCU8 GCSC: S1DSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S1PSC_Pos (6UL) /*!< CCU8 GCSC: S1PSC (Bit 6) */ +#define CCU8_GCSC_S1PSC_Msk (0x40UL) /*!< CCU8 GCSC: S1PSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S2SC_Pos (8UL) /*!< CCU8 GCSC: S2SC (Bit 8) */ +#define CCU8_GCSC_S2SC_Msk (0x100UL) /*!< CCU8 GCSC: S2SC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S2DSC_Pos (9UL) /*!< CCU8 GCSC: S2DSC (Bit 9) */ +#define CCU8_GCSC_S2DSC_Msk (0x200UL) /*!< CCU8 GCSC: S2DSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S2PSC_Pos (10UL) /*!< CCU8 GCSC: S2PSC (Bit 10) */ +#define CCU8_GCSC_S2PSC_Msk (0x400UL) /*!< CCU8 GCSC: S2PSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S3SC_Pos (12UL) /*!< CCU8 GCSC: S3SC (Bit 12) */ +#define CCU8_GCSC_S3SC_Msk (0x1000UL) /*!< CCU8 GCSC: S3SC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S3DSC_Pos (13UL) /*!< CCU8 GCSC: S3DSC (Bit 13) */ +#define CCU8_GCSC_S3DSC_Msk (0x2000UL) /*!< CCU8 GCSC: S3DSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S3PSC_Pos (14UL) /*!< CCU8 GCSC: S3PSC (Bit 14) */ +#define CCU8_GCSC_S3PSC_Msk (0x4000UL) /*!< CCU8 GCSC: S3PSC (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S0ST1C_Pos (16UL) /*!< CCU8 GCSC: S0ST1C (Bit 16) */ +#define CCU8_GCSC_S0ST1C_Msk (0x10000UL) /*!< CCU8 GCSC: S0ST1C (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S1ST1C_Pos (17UL) /*!< CCU8 GCSC: S1ST1C (Bit 17) */ +#define CCU8_GCSC_S1ST1C_Msk (0x20000UL) /*!< CCU8 GCSC: S1ST1C (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S2ST1C_Pos (18UL) /*!< CCU8 GCSC: S2ST1C (Bit 18) */ +#define CCU8_GCSC_S2ST1C_Msk (0x40000UL) /*!< CCU8 GCSC: S2ST1C (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S3ST1C_Pos (19UL) /*!< CCU8 GCSC: S3ST1C (Bit 19) */ +#define CCU8_GCSC_S3ST1C_Msk (0x80000UL) /*!< CCU8 GCSC: S3ST1C (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S0ST2C_Pos (20UL) /*!< CCU8 GCSC: S0ST2C (Bit 20) */ +#define CCU8_GCSC_S0ST2C_Msk (0x100000UL) /*!< CCU8 GCSC: S0ST2C (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S1ST2C_Pos (21UL) /*!< CCU8 GCSC: S1ST2C (Bit 21) */ +#define CCU8_GCSC_S1ST2C_Msk (0x200000UL) /*!< CCU8 GCSC: S1ST2C (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S2ST2C_Pos (22UL) /*!< CCU8 GCSC: S2ST2C (Bit 22) */ +#define CCU8_GCSC_S2ST2C_Msk (0x400000UL) /*!< CCU8 GCSC: S2ST2C (Bitfield-Mask: 0x01) */ +#define CCU8_GCSC_S3ST2C_Pos (23UL) /*!< CCU8 GCSC: S3ST2C (Bit 23) */ +#define CCU8_GCSC_S3ST2C_Msk (0x800000UL) /*!< CCU8 GCSC: S3ST2C (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU8_GCST --------------------------------- */ +#define CCU8_GCST_S0SS_Pos (0UL) /*!< CCU8 GCST: S0SS (Bit 0) */ +#define CCU8_GCST_S0SS_Msk (0x1UL) /*!< CCU8 GCST: S0SS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S0DSS_Pos (1UL) /*!< CCU8 GCST: S0DSS (Bit 1) */ +#define CCU8_GCST_S0DSS_Msk (0x2UL) /*!< CCU8 GCST: S0DSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S0PSS_Pos (2UL) /*!< CCU8 GCST: S0PSS (Bit 2) */ +#define CCU8_GCST_S0PSS_Msk (0x4UL) /*!< CCU8 GCST: S0PSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S1SS_Pos (4UL) /*!< CCU8 GCST: S1SS (Bit 4) */ +#define CCU8_GCST_S1SS_Msk (0x10UL) /*!< CCU8 GCST: S1SS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S1DSS_Pos (5UL) /*!< CCU8 GCST: S1DSS (Bit 5) */ +#define CCU8_GCST_S1DSS_Msk (0x20UL) /*!< CCU8 GCST: S1DSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S1PSS_Pos (6UL) /*!< CCU8 GCST: S1PSS (Bit 6) */ +#define CCU8_GCST_S1PSS_Msk (0x40UL) /*!< CCU8 GCST: S1PSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S2SS_Pos (8UL) /*!< CCU8 GCST: S2SS (Bit 8) */ +#define CCU8_GCST_S2SS_Msk (0x100UL) /*!< CCU8 GCST: S2SS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S2DSS_Pos (9UL) /*!< CCU8 GCST: S2DSS (Bit 9) */ +#define CCU8_GCST_S2DSS_Msk (0x200UL) /*!< CCU8 GCST: S2DSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S2PSS_Pos (10UL) /*!< CCU8 GCST: S2PSS (Bit 10) */ +#define CCU8_GCST_S2PSS_Msk (0x400UL) /*!< CCU8 GCST: S2PSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S3SS_Pos (12UL) /*!< CCU8 GCST: S3SS (Bit 12) */ +#define CCU8_GCST_S3SS_Msk (0x1000UL) /*!< CCU8 GCST: S3SS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S3DSS_Pos (13UL) /*!< CCU8 GCST: S3DSS (Bit 13) */ +#define CCU8_GCST_S3DSS_Msk (0x2000UL) /*!< CCU8 GCST: S3DSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_S3PSS_Pos (14UL) /*!< CCU8 GCST: S3PSS (Bit 14) */ +#define CCU8_GCST_S3PSS_Msk (0x4000UL) /*!< CCU8 GCST: S3PSS (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC80ST1_Pos (16UL) /*!< CCU8 GCST: CC80ST1 (Bit 16) */ +#define CCU8_GCST_CC80ST1_Msk (0x10000UL) /*!< CCU8 GCST: CC80ST1 (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC81ST1_Pos (17UL) /*!< CCU8 GCST: CC81ST1 (Bit 17) */ +#define CCU8_GCST_CC81ST1_Msk (0x20000UL) /*!< CCU8 GCST: CC81ST1 (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC82ST1_Pos (18UL) /*!< CCU8 GCST: CC82ST1 (Bit 18) */ +#define CCU8_GCST_CC82ST1_Msk (0x40000UL) /*!< CCU8 GCST: CC82ST1 (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC83ST1_Pos (19UL) /*!< CCU8 GCST: CC83ST1 (Bit 19) */ +#define CCU8_GCST_CC83ST1_Msk (0x80000UL) /*!< CCU8 GCST: CC83ST1 (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC80ST2_Pos (20UL) /*!< CCU8 GCST: CC80ST2 (Bit 20) */ +#define CCU8_GCST_CC80ST2_Msk (0x100000UL) /*!< CCU8 GCST: CC80ST2 (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC81ST2_Pos (21UL) /*!< CCU8 GCST: CC81ST2 (Bit 21) */ +#define CCU8_GCST_CC81ST2_Msk (0x200000UL) /*!< CCU8 GCST: CC81ST2 (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC82ST2_Pos (22UL) /*!< CCU8 GCST: CC82ST2 (Bit 22) */ +#define CCU8_GCST_CC82ST2_Msk (0x400000UL) /*!< CCU8 GCST: CC82ST2 (Bitfield-Mask: 0x01) */ +#define CCU8_GCST_CC83ST2_Pos (23UL) /*!< CCU8 GCST: CC83ST2 (Bit 23) */ +#define CCU8_GCST_CC83ST2_Msk (0x800000UL) /*!< CCU8 GCST: CC83ST2 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CCU8_GPCHK --------------------------------- */ +#define CCU8_GPCHK_PASE_Pos (0UL) /*!< CCU8 GPCHK: PASE (Bit 0) */ +#define CCU8_GPCHK_PASE_Msk (0x1UL) /*!< CCU8 GPCHK: PASE (Bitfield-Mask: 0x01) */ +#define CCU8_GPCHK_PACS_Pos (1UL) /*!< CCU8 GPCHK: PACS (Bit 1) */ +#define CCU8_GPCHK_PACS_Msk (0x6UL) /*!< CCU8 GPCHK: PACS (Bitfield-Mask: 0x03) */ +#define CCU8_GPCHK_PISEL_Pos (3UL) /*!< CCU8 GPCHK: PISEL (Bit 3) */ +#define CCU8_GPCHK_PISEL_Msk (0x18UL) /*!< CCU8 GPCHK: PISEL (Bitfield-Mask: 0x03) */ +#define CCU8_GPCHK_PCDS_Pos (5UL) /*!< CCU8 GPCHK: PCDS (Bit 5) */ +#define CCU8_GPCHK_PCDS_Msk (0x60UL) /*!< CCU8 GPCHK: PCDS (Bitfield-Mask: 0x03) */ +#define CCU8_GPCHK_PCTS_Pos (7UL) /*!< CCU8 GPCHK: PCTS (Bit 7) */ +#define CCU8_GPCHK_PCTS_Msk (0x80UL) /*!< CCU8 GPCHK: PCTS (Bitfield-Mask: 0x01) */ +#define CCU8_GPCHK_PCST_Pos (15UL) /*!< CCU8 GPCHK: PCST (Bit 15) */ +#define CCU8_GPCHK_PCST_Msk (0x8000UL) /*!< CCU8 GPCHK: PCST (Bitfield-Mask: 0x01) */ +#define CCU8_GPCHK_PCSEL0_Pos (16UL) /*!< CCU8 GPCHK: PCSEL0 (Bit 16) */ +#define CCU8_GPCHK_PCSEL0_Msk (0xf0000UL) /*!< CCU8 GPCHK: PCSEL0 (Bitfield-Mask: 0x0f) */ +#define CCU8_GPCHK_PCSEL1_Pos (20UL) /*!< CCU8 GPCHK: PCSEL1 (Bit 20) */ +#define CCU8_GPCHK_PCSEL1_Msk (0xf00000UL) /*!< CCU8 GPCHK: PCSEL1 (Bitfield-Mask: 0x0f) */ +#define CCU8_GPCHK_PCSEL2_Pos (24UL) /*!< CCU8 GPCHK: PCSEL2 (Bit 24) */ +#define CCU8_GPCHK_PCSEL2_Msk (0xf000000UL) /*!< CCU8 GPCHK: PCSEL2 (Bitfield-Mask: 0x0f) */ +#define CCU8_GPCHK_PCSEL3_Pos (28UL) /*!< CCU8 GPCHK: PCSEL3 (Bit 28) */ +#define CCU8_GPCHK_PCSEL3_Msk (0xf0000000UL) /*!< CCU8 GPCHK: PCSEL3 (Bitfield-Mask: 0x0f) */ + +/* ---------------------------------- CCU8_ECRD --------------------------------- */ +#define CCU8_ECRD_CAPV_Pos (0UL) /*!< CCU8 ECRD: CAPV (Bit 0) */ +#define CCU8_ECRD_CAPV_Msk (0xffffUL) /*!< CCU8 ECRD: CAPV (Bitfield-Mask: 0xffff) */ +#define CCU8_ECRD_FPCV_Pos (16UL) /*!< CCU8 ECRD: FPCV (Bit 16) */ +#define CCU8_ECRD_FPCV_Msk (0xf0000UL) /*!< CCU8 ECRD: FPCV (Bitfield-Mask: 0x0f) */ +#define CCU8_ECRD_SPTR_Pos (20UL) /*!< CCU8 ECRD: SPTR (Bit 20) */ +#define CCU8_ECRD_SPTR_Msk (0x300000UL) /*!< CCU8 ECRD: SPTR (Bitfield-Mask: 0x03) */ +#define CCU8_ECRD_VPTR_Pos (22UL) /*!< CCU8 ECRD: VPTR (Bit 22) */ +#define CCU8_ECRD_VPTR_Msk (0xc00000UL) /*!< CCU8 ECRD: VPTR (Bitfield-Mask: 0x03) */ +#define CCU8_ECRD_FFL_Pos (24UL) /*!< CCU8 ECRD: FFL (Bit 24) */ +#define CCU8_ECRD_FFL_Msk (0x1000000UL) /*!< CCU8 ECRD: FFL (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- CCU8_MIDR --------------------------------- */ +#define CCU8_MIDR_MODR_Pos (0UL) /*!< CCU8 MIDR: MODR (Bit 0) */ +#define CCU8_MIDR_MODR_Msk (0xffUL) /*!< CCU8 MIDR: MODR (Bitfield-Mask: 0xff) */ +#define CCU8_MIDR_MODT_Pos (8UL) /*!< CCU8 MIDR: MODT (Bit 8) */ +#define CCU8_MIDR_MODT_Msk (0xff00UL) /*!< CCU8 MIDR: MODT (Bitfield-Mask: 0xff) */ +#define CCU8_MIDR_MODN_Pos (16UL) /*!< CCU8 MIDR: MODN (Bit 16) */ +#define CCU8_MIDR_MODN_Msk (0xffff0000UL) /*!< CCU8 MIDR: MODN (Bitfield-Mask: 0xffff) */ + + +/* ================================================================================ */ +/* ================ Group 'CCU8_CC8' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- CCU8_CC8_INS -------------------------------- */ +#define CCU8_CC8_INS_EV0IS_Pos (0UL) /*!< CCU8_CC8 INS: EV0IS (Bit 0) */ +#define CCU8_CC8_INS_EV0IS_Msk (0xfUL) /*!< CCU8_CC8 INS: EV0IS (Bitfield-Mask: 0x0f) */ +#define CCU8_CC8_INS_EV1IS_Pos (4UL) /*!< CCU8_CC8 INS: EV1IS (Bit 4) */ +#define CCU8_CC8_INS_EV1IS_Msk (0xf0UL) /*!< CCU8_CC8 INS: EV1IS (Bitfield-Mask: 0x0f) */ +#define CCU8_CC8_INS_EV2IS_Pos (8UL) /*!< CCU8_CC8 INS: EV2IS (Bit 8) */ +#define CCU8_CC8_INS_EV2IS_Msk (0xf00UL) /*!< CCU8_CC8 INS: EV2IS (Bitfield-Mask: 0x0f) */ +#define CCU8_CC8_INS_EV0EM_Pos (16UL) /*!< CCU8_CC8 INS: EV0EM (Bit 16) */ +#define CCU8_CC8_INS_EV0EM_Msk (0x30000UL) /*!< CCU8_CC8 INS: EV0EM (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_INS_EV1EM_Pos (18UL) /*!< CCU8_CC8 INS: EV1EM (Bit 18) */ +#define CCU8_CC8_INS_EV1EM_Msk (0xc0000UL) /*!< CCU8_CC8 INS: EV1EM (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_INS_EV2EM_Pos (20UL) /*!< CCU8_CC8 INS: EV2EM (Bit 20) */ +#define CCU8_CC8_INS_EV2EM_Msk (0x300000UL) /*!< CCU8_CC8 INS: EV2EM (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_INS_EV0LM_Pos (22UL) /*!< CCU8_CC8 INS: EV0LM (Bit 22) */ +#define CCU8_CC8_INS_EV0LM_Msk (0x400000UL) /*!< CCU8_CC8 INS: EV0LM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INS_EV1LM_Pos (23UL) /*!< CCU8_CC8 INS: EV1LM (Bit 23) */ +#define CCU8_CC8_INS_EV1LM_Msk (0x800000UL) /*!< CCU8_CC8 INS: EV1LM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INS_EV2LM_Pos (24UL) /*!< CCU8_CC8 INS: EV2LM (Bit 24) */ +#define CCU8_CC8_INS_EV2LM_Msk (0x1000000UL) /*!< CCU8_CC8 INS: EV2LM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INS_LPF0M_Pos (25UL) /*!< CCU8_CC8 INS: LPF0M (Bit 25) */ +#define CCU8_CC8_INS_LPF0M_Msk (0x6000000UL) /*!< CCU8_CC8 INS: LPF0M (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_INS_LPF1M_Pos (27UL) /*!< CCU8_CC8 INS: LPF1M (Bit 27) */ +#define CCU8_CC8_INS_LPF1M_Msk (0x18000000UL) /*!< CCU8_CC8 INS: LPF1M (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_INS_LPF2M_Pos (29UL) /*!< CCU8_CC8 INS: LPF2M (Bit 29) */ +#define CCU8_CC8_INS_LPF2M_Msk (0x60000000UL) /*!< CCU8_CC8 INS: LPF2M (Bitfield-Mask: 0x03) */ + +/* -------------------------------- CCU8_CC8_CMC -------------------------------- */ +#define CCU8_CC8_CMC_STRTS_Pos (0UL) /*!< CCU8_CC8 CMC: STRTS (Bit 0) */ +#define CCU8_CC8_CMC_STRTS_Msk (0x3UL) /*!< CCU8_CC8 CMC: STRTS (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_ENDS_Pos (2UL) /*!< CCU8_CC8 CMC: ENDS (Bit 2) */ +#define CCU8_CC8_CMC_ENDS_Msk (0xcUL) /*!< CCU8_CC8 CMC: ENDS (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_CAP0S_Pos (4UL) /*!< CCU8_CC8 CMC: CAP0S (Bit 4) */ +#define CCU8_CC8_CMC_CAP0S_Msk (0x30UL) /*!< CCU8_CC8 CMC: CAP0S (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_CAP1S_Pos (6UL) /*!< CCU8_CC8 CMC: CAP1S (Bit 6) */ +#define CCU8_CC8_CMC_CAP1S_Msk (0xc0UL) /*!< CCU8_CC8 CMC: CAP1S (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_GATES_Pos (8UL) /*!< CCU8_CC8 CMC: GATES (Bit 8) */ +#define CCU8_CC8_CMC_GATES_Msk (0x300UL) /*!< CCU8_CC8 CMC: GATES (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_UDS_Pos (10UL) /*!< CCU8_CC8 CMC: UDS (Bit 10) */ +#define CCU8_CC8_CMC_UDS_Msk (0xc00UL) /*!< CCU8_CC8 CMC: UDS (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_LDS_Pos (12UL) /*!< CCU8_CC8 CMC: LDS (Bit 12) */ +#define CCU8_CC8_CMC_LDS_Msk (0x3000UL) /*!< CCU8_CC8 CMC: LDS (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_CNTS_Pos (14UL) /*!< CCU8_CC8 CMC: CNTS (Bit 14) */ +#define CCU8_CC8_CMC_CNTS_Msk (0xc000UL) /*!< CCU8_CC8 CMC: CNTS (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_OFS_Pos (16UL) /*!< CCU8_CC8 CMC: OFS (Bit 16) */ +#define CCU8_CC8_CMC_OFS_Msk (0x10000UL) /*!< CCU8_CC8 CMC: OFS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_CMC_TS_Pos (17UL) /*!< CCU8_CC8 CMC: TS (Bit 17) */ +#define CCU8_CC8_CMC_TS_Msk (0x20000UL) /*!< CCU8_CC8 CMC: TS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_CMC_MOS_Pos (18UL) /*!< CCU8_CC8 CMC: MOS (Bit 18) */ +#define CCU8_CC8_CMC_MOS_Msk (0xc0000UL) /*!< CCU8_CC8 CMC: MOS (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_CMC_TCE_Pos (20UL) /*!< CCU8_CC8 CMC: TCE (Bit 20) */ +#define CCU8_CC8_CMC_TCE_Msk (0x100000UL) /*!< CCU8_CC8 CMC: TCE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_TCST ------------------------------- */ +#define CCU8_CC8_TCST_TRB_Pos (0UL) /*!< CCU8_CC8 TCST: TRB (Bit 0) */ +#define CCU8_CC8_TCST_TRB_Msk (0x1UL) /*!< CCU8_CC8 TCST: TRB (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TCST_CDIR_Pos (1UL) /*!< CCU8_CC8 TCST: CDIR (Bit 1) */ +#define CCU8_CC8_TCST_CDIR_Msk (0x2UL) /*!< CCU8_CC8 TCST: CDIR (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TCST_DTR1_Pos (3UL) /*!< CCU8_CC8 TCST: DTR1 (Bit 3) */ +#define CCU8_CC8_TCST_DTR1_Msk (0x8UL) /*!< CCU8_CC8 TCST: DTR1 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TCST_DTR2_Pos (4UL) /*!< CCU8_CC8 TCST: DTR2 (Bit 4) */ +#define CCU8_CC8_TCST_DTR2_Msk (0x10UL) /*!< CCU8_CC8 TCST: DTR2 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- CCU8_CC8_TCSET ------------------------------- */ +#define CCU8_CC8_TCSET_TRBS_Pos (0UL) /*!< CCU8_CC8 TCSET: TRBS (Bit 0) */ +#define CCU8_CC8_TCSET_TRBS_Msk (0x1UL) /*!< CCU8_CC8 TCSET: TRBS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- CCU8_CC8_TCCLR ------------------------------- */ +#define CCU8_CC8_TCCLR_TRBC_Pos (0UL) /*!< CCU8_CC8 TCCLR: TRBC (Bit 0) */ +#define CCU8_CC8_TCCLR_TRBC_Msk (0x1UL) /*!< CCU8_CC8 TCCLR: TRBC (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TCCLR_TCC_Pos (1UL) /*!< CCU8_CC8 TCCLR: TCC (Bit 1) */ +#define CCU8_CC8_TCCLR_TCC_Msk (0x2UL) /*!< CCU8_CC8 TCCLR: TCC (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TCCLR_DITC_Pos (2UL) /*!< CCU8_CC8 TCCLR: DITC (Bit 2) */ +#define CCU8_CC8_TCCLR_DITC_Msk (0x4UL) /*!< CCU8_CC8 TCCLR: DITC (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TCCLR_DTC1C_Pos (3UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bit 3) */ +#define CCU8_CC8_TCCLR_DTC1C_Msk (0x8UL) /*!< CCU8_CC8 TCCLR: DTC1C (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TCCLR_DTC2C_Pos (4UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bit 4) */ +#define CCU8_CC8_TCCLR_DTC2C_Msk (0x10UL) /*!< CCU8_CC8 TCCLR: DTC2C (Bitfield-Mask: 0x01) */ + +/* --------------------------------- CCU8_CC8_TC -------------------------------- */ +#define CCU8_CC8_TC_TCM_Pos (0UL) /*!< CCU8_CC8 TC: TCM (Bit 0) */ +#define CCU8_CC8_TC_TCM_Msk (0x1UL) /*!< CCU8_CC8 TC: TCM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_TSSM_Pos (1UL) /*!< CCU8_CC8 TC: TSSM (Bit 1) */ +#define CCU8_CC8_TC_TSSM_Msk (0x2UL) /*!< CCU8_CC8 TC: TSSM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_CLST_Pos (2UL) /*!< CCU8_CC8 TC: CLST (Bit 2) */ +#define CCU8_CC8_TC_CLST_Msk (0x4UL) /*!< CCU8_CC8 TC: CLST (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_CMOD_Pos (3UL) /*!< CCU8_CC8 TC: CMOD (Bit 3) */ +#define CCU8_CC8_TC_CMOD_Msk (0x8UL) /*!< CCU8_CC8 TC: CMOD (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_ECM_Pos (4UL) /*!< CCU8_CC8 TC: ECM (Bit 4) */ +#define CCU8_CC8_TC_ECM_Msk (0x10UL) /*!< CCU8_CC8 TC: ECM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_CAPC_Pos (5UL) /*!< CCU8_CC8 TC: CAPC (Bit 5) */ +#define CCU8_CC8_TC_CAPC_Msk (0x60UL) /*!< CCU8_CC8 TC: CAPC (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_TC_TLS_Pos (7UL) /*!< CCU8_CC8 TC: TLS (Bit 7) */ +#define CCU8_CC8_TC_TLS_Msk (0x80UL) /*!< CCU8_CC8 TC: TLS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_ENDM_Pos (8UL) /*!< CCU8_CC8 TC: ENDM (Bit 8) */ +#define CCU8_CC8_TC_ENDM_Msk (0x300UL) /*!< CCU8_CC8 TC: ENDM (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_TC_STRM_Pos (10UL) /*!< CCU8_CC8 TC: STRM (Bit 10) */ +#define CCU8_CC8_TC_STRM_Msk (0x400UL) /*!< CCU8_CC8 TC: STRM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_SCE_Pos (11UL) /*!< CCU8_CC8 TC: SCE (Bit 11) */ +#define CCU8_CC8_TC_SCE_Msk (0x800UL) /*!< CCU8_CC8 TC: SCE (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_CCS_Pos (12UL) /*!< CCU8_CC8 TC: CCS (Bit 12) */ +#define CCU8_CC8_TC_CCS_Msk (0x1000UL) /*!< CCU8_CC8 TC: CCS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_DITHE_Pos (13UL) /*!< CCU8_CC8 TC: DITHE (Bit 13) */ +#define CCU8_CC8_TC_DITHE_Msk (0x6000UL) /*!< CCU8_CC8 TC: DITHE (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_TC_DIM_Pos (15UL) /*!< CCU8_CC8 TC: DIM (Bit 15) */ +#define CCU8_CC8_TC_DIM_Msk (0x8000UL) /*!< CCU8_CC8 TC: DIM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_FPE_Pos (16UL) /*!< CCU8_CC8 TC: FPE (Bit 16) */ +#define CCU8_CC8_TC_FPE_Msk (0x10000UL) /*!< CCU8_CC8 TC: FPE (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_TRAPE0_Pos (17UL) /*!< CCU8_CC8 TC: TRAPE0 (Bit 17) */ +#define CCU8_CC8_TC_TRAPE0_Msk (0x20000UL) /*!< CCU8_CC8 TC: TRAPE0 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_TRAPE1_Pos (18UL) /*!< CCU8_CC8 TC: TRAPE1 (Bit 18) */ +#define CCU8_CC8_TC_TRAPE1_Msk (0x40000UL) /*!< CCU8_CC8 TC: TRAPE1 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_TRAPE2_Pos (19UL) /*!< CCU8_CC8 TC: TRAPE2 (Bit 19) */ +#define CCU8_CC8_TC_TRAPE2_Msk (0x80000UL) /*!< CCU8_CC8 TC: TRAPE2 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_TRAPE3_Pos (20UL) /*!< CCU8_CC8 TC: TRAPE3 (Bit 20) */ +#define CCU8_CC8_TC_TRAPE3_Msk (0x100000UL) /*!< CCU8_CC8 TC: TRAPE3 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_TRPSE_Pos (21UL) /*!< CCU8_CC8 TC: TRPSE (Bit 21) */ +#define CCU8_CC8_TC_TRPSE_Msk (0x200000UL) /*!< CCU8_CC8 TC: TRPSE (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_TRPSW_Pos (22UL) /*!< CCU8_CC8 TC: TRPSW (Bit 22) */ +#define CCU8_CC8_TC_TRPSW_Msk (0x400000UL) /*!< CCU8_CC8 TC: TRPSW (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_EMS_Pos (23UL) /*!< CCU8_CC8 TC: EMS (Bit 23) */ +#define CCU8_CC8_TC_EMS_Msk (0x800000UL) /*!< CCU8_CC8 TC: EMS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_EMT_Pos (24UL) /*!< CCU8_CC8 TC: EMT (Bit 24) */ +#define CCU8_CC8_TC_EMT_Msk (0x1000000UL) /*!< CCU8_CC8 TC: EMT (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_MCME1_Pos (25UL) /*!< CCU8_CC8 TC: MCME1 (Bit 25) */ +#define CCU8_CC8_TC_MCME1_Msk (0x2000000UL) /*!< CCU8_CC8 TC: MCME1 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_MCME2_Pos (26UL) /*!< CCU8_CC8 TC: MCME2 (Bit 26) */ +#define CCU8_CC8_TC_MCME2_Msk (0x4000000UL) /*!< CCU8_CC8 TC: MCME2 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_TC_EME_Pos (27UL) /*!< CCU8_CC8 TC: EME (Bit 27) */ +#define CCU8_CC8_TC_EME_Msk (0x18000000UL) /*!< CCU8_CC8 TC: EME (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_TC_STOS_Pos (29UL) /*!< CCU8_CC8 TC: STOS (Bit 29) */ +#define CCU8_CC8_TC_STOS_Msk (0x60000000UL) /*!< CCU8_CC8 TC: STOS (Bitfield-Mask: 0x03) */ + +/* -------------------------------- CCU8_CC8_PSL -------------------------------- */ +#define CCU8_CC8_PSL_PSL11_Pos (0UL) /*!< CCU8_CC8 PSL: PSL11 (Bit 0) */ +#define CCU8_CC8_PSL_PSL11_Msk (0x1UL) /*!< CCU8_CC8 PSL: PSL11 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_PSL_PSL12_Pos (1UL) /*!< CCU8_CC8 PSL: PSL12 (Bit 1) */ +#define CCU8_CC8_PSL_PSL12_Msk (0x2UL) /*!< CCU8_CC8 PSL: PSL12 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_PSL_PSL21_Pos (2UL) /*!< CCU8_CC8 PSL: PSL21 (Bit 2) */ +#define CCU8_CC8_PSL_PSL21_Msk (0x4UL) /*!< CCU8_CC8 PSL: PSL21 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_PSL_PSL22_Pos (3UL) /*!< CCU8_CC8 PSL: PSL22 (Bit 3) */ +#define CCU8_CC8_PSL_PSL22_Msk (0x8UL) /*!< CCU8_CC8 PSL: PSL22 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_DIT -------------------------------- */ +#define CCU8_CC8_DIT_DCV_Pos (0UL) /*!< CCU8_CC8 DIT: DCV (Bit 0) */ +#define CCU8_CC8_DIT_DCV_Msk (0xfUL) /*!< CCU8_CC8 DIT: DCV (Bitfield-Mask: 0x0f) */ +#define CCU8_CC8_DIT_DCNT_Pos (8UL) /*!< CCU8_CC8 DIT: DCNT (Bit 8) */ +#define CCU8_CC8_DIT_DCNT_Msk (0xf00UL) /*!< CCU8_CC8 DIT: DCNT (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU8_CC8_DITS ------------------------------- */ +#define CCU8_CC8_DITS_DCVS_Pos (0UL) /*!< CCU8_CC8 DITS: DCVS (Bit 0) */ +#define CCU8_CC8_DITS_DCVS_Msk (0xfUL) /*!< CCU8_CC8 DITS: DCVS (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU8_CC8_PSC -------------------------------- */ +#define CCU8_CC8_PSC_PSIV_Pos (0UL) /*!< CCU8_CC8 PSC: PSIV (Bit 0) */ +#define CCU8_CC8_PSC_PSIV_Msk (0xfUL) /*!< CCU8_CC8 PSC: PSIV (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU8_CC8_FPC -------------------------------- */ +#define CCU8_CC8_FPC_PCMP_Pos (0UL) /*!< CCU8_CC8 FPC: PCMP (Bit 0) */ +#define CCU8_CC8_FPC_PCMP_Msk (0xfUL) /*!< CCU8_CC8 FPC: PCMP (Bitfield-Mask: 0x0f) */ +#define CCU8_CC8_FPC_PVAL_Pos (8UL) /*!< CCU8_CC8 FPC: PVAL (Bit 8) */ +#define CCU8_CC8_FPC_PVAL_Msk (0xf00UL) /*!< CCU8_CC8 FPC: PVAL (Bitfield-Mask: 0x0f) */ + +/* -------------------------------- CCU8_CC8_FPCS ------------------------------- */ +#define CCU8_CC8_FPCS_PCMP_Pos (0UL) /*!< CCU8_CC8 FPCS: PCMP (Bit 0) */ +#define CCU8_CC8_FPCS_PCMP_Msk (0xfUL) /*!< CCU8_CC8 FPCS: PCMP (Bitfield-Mask: 0x0f) */ + +/* --------------------------------- CCU8_CC8_PR -------------------------------- */ +#define CCU8_CC8_PR_PR_Pos (0UL) /*!< CCU8_CC8 PR: PR (Bit 0) */ +#define CCU8_CC8_PR_PR_Msk (0xffffUL) /*!< CCU8_CC8 PR: PR (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU8_CC8_PRS -------------------------------- */ +#define CCU8_CC8_PRS_PRS_Pos (0UL) /*!< CCU8_CC8 PRS: PRS (Bit 0) */ +#define CCU8_CC8_PRS_PRS_Msk (0xffffUL) /*!< CCU8_CC8 PRS: PRS (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU8_CC8_CR1 -------------------------------- */ +#define CCU8_CC8_CR1_CR1_Pos (0UL) /*!< CCU8_CC8 CR1: CR1 (Bit 0) */ +#define CCU8_CC8_CR1_CR1_Msk (0xffffUL) /*!< CCU8_CC8 CR1: CR1 (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU8_CC8_CR1S ------------------------------- */ +#define CCU8_CC8_CR1S_CR1S_Pos (0UL) /*!< CCU8_CC8 CR1S: CR1S (Bit 0) */ +#define CCU8_CC8_CR1S_CR1S_Msk (0xffffUL) /*!< CCU8_CC8 CR1S: CR1S (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU8_CC8_CR2 -------------------------------- */ +#define CCU8_CC8_CR2_CR2_Pos (0UL) /*!< CCU8_CC8 CR2: CR2 (Bit 0) */ +#define CCU8_CC8_CR2_CR2_Msk (0xffffUL) /*!< CCU8_CC8 CR2: CR2 (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU8_CC8_CR2S ------------------------------- */ +#define CCU8_CC8_CR2S_CR2S_Pos (0UL) /*!< CCU8_CC8 CR2S: CR2S (Bit 0) */ +#define CCU8_CC8_CR2S_CR2S_Msk (0xffffUL) /*!< CCU8_CC8 CR2S: CR2S (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- CCU8_CC8_CHC -------------------------------- */ +#define CCU8_CC8_CHC_ASE_Pos (0UL) /*!< CCU8_CC8 CHC: ASE (Bit 0) */ +#define CCU8_CC8_CHC_ASE_Msk (0x1UL) /*!< CCU8_CC8 CHC: ASE (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_CHC_OCS1_Pos (1UL) /*!< CCU8_CC8 CHC: OCS1 (Bit 1) */ +#define CCU8_CC8_CHC_OCS1_Msk (0x2UL) /*!< CCU8_CC8 CHC: OCS1 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_CHC_OCS2_Pos (2UL) /*!< CCU8_CC8 CHC: OCS2 (Bit 2) */ +#define CCU8_CC8_CHC_OCS2_Msk (0x4UL) /*!< CCU8_CC8 CHC: OCS2 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_CHC_OCS3_Pos (3UL) /*!< CCU8_CC8 CHC: OCS3 (Bit 3) */ +#define CCU8_CC8_CHC_OCS3_Msk (0x8UL) /*!< CCU8_CC8 CHC: OCS3 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_CHC_OCS4_Pos (4UL) /*!< CCU8_CC8 CHC: OCS4 (Bit 4) */ +#define CCU8_CC8_CHC_OCS4_Msk (0x10UL) /*!< CCU8_CC8 CHC: OCS4 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_DTC -------------------------------- */ +#define CCU8_CC8_DTC_DTE1_Pos (0UL) /*!< CCU8_CC8 DTC: DTE1 (Bit 0) */ +#define CCU8_CC8_DTC_DTE1_Msk (0x1UL) /*!< CCU8_CC8 DTC: DTE1 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_DTC_DTE2_Pos (1UL) /*!< CCU8_CC8 DTC: DTE2 (Bit 1) */ +#define CCU8_CC8_DTC_DTE2_Msk (0x2UL) /*!< CCU8_CC8 DTC: DTE2 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_DTC_DCEN1_Pos (2UL) /*!< CCU8_CC8 DTC: DCEN1 (Bit 2) */ +#define CCU8_CC8_DTC_DCEN1_Msk (0x4UL) /*!< CCU8_CC8 DTC: DCEN1 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_DTC_DCEN2_Pos (3UL) /*!< CCU8_CC8 DTC: DCEN2 (Bit 3) */ +#define CCU8_CC8_DTC_DCEN2_Msk (0x8UL) /*!< CCU8_CC8 DTC: DCEN2 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_DTC_DCEN3_Pos (4UL) /*!< CCU8_CC8 DTC: DCEN3 (Bit 4) */ +#define CCU8_CC8_DTC_DCEN3_Msk (0x10UL) /*!< CCU8_CC8 DTC: DCEN3 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_DTC_DCEN4_Pos (5UL) /*!< CCU8_CC8 DTC: DCEN4 (Bit 5) */ +#define CCU8_CC8_DTC_DCEN4_Msk (0x20UL) /*!< CCU8_CC8 DTC: DCEN4 (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_DTC_DTCC_Pos (6UL) /*!< CCU8_CC8 DTC: DTCC (Bit 6) */ +#define CCU8_CC8_DTC_DTCC_Msk (0xc0UL) /*!< CCU8_CC8 DTC: DTCC (Bitfield-Mask: 0x03) */ + +/* -------------------------------- CCU8_CC8_DC1R ------------------------------- */ +#define CCU8_CC8_DC1R_DT1R_Pos (0UL) /*!< CCU8_CC8 DC1R: DT1R (Bit 0) */ +#define CCU8_CC8_DC1R_DT1R_Msk (0xffUL) /*!< CCU8_CC8 DC1R: DT1R (Bitfield-Mask: 0xff) */ +#define CCU8_CC8_DC1R_DT1F_Pos (8UL) /*!< CCU8_CC8 DC1R: DT1F (Bit 8) */ +#define CCU8_CC8_DC1R_DT1F_Msk (0xff00UL) /*!< CCU8_CC8 DC1R: DT1F (Bitfield-Mask: 0xff) */ + +/* -------------------------------- CCU8_CC8_DC2R ------------------------------- */ +#define CCU8_CC8_DC2R_DT2R_Pos (0UL) /*!< CCU8_CC8 DC2R: DT2R (Bit 0) */ +#define CCU8_CC8_DC2R_DT2R_Msk (0xffUL) /*!< CCU8_CC8 DC2R: DT2R (Bitfield-Mask: 0xff) */ +#define CCU8_CC8_DC2R_DT2F_Pos (8UL) /*!< CCU8_CC8 DC2R: DT2F (Bit 8) */ +#define CCU8_CC8_DC2R_DT2F_Msk (0xff00UL) /*!< CCU8_CC8 DC2R: DT2F (Bitfield-Mask: 0xff) */ + +/* ------------------------------- CCU8_CC8_TIMER ------------------------------- */ +#define CCU8_CC8_TIMER_TVAL_Pos (0UL) /*!< CCU8_CC8 TIMER: TVAL (Bit 0) */ +#define CCU8_CC8_TIMER_TVAL_Msk (0xffffUL) /*!< CCU8_CC8 TIMER: TVAL (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- CCU8_CC8_CV -------------------------------- */ +#define CCU8_CC8_CV_CAPTV_Pos (0UL) /*!< CCU8_CC8 CV: CAPTV (Bit 0) */ +#define CCU8_CC8_CV_CAPTV_Msk (0xffffUL) /*!< CCU8_CC8 CV: CAPTV (Bitfield-Mask: 0xffff) */ +#define CCU8_CC8_CV_FPCV_Pos (16UL) /*!< CCU8_CC8 CV: FPCV (Bit 16) */ +#define CCU8_CC8_CV_FPCV_Msk (0xf0000UL) /*!< CCU8_CC8 CV: FPCV (Bitfield-Mask: 0x0f) */ +#define CCU8_CC8_CV_FFL_Pos (20UL) /*!< CCU8_CC8 CV: FFL (Bit 20) */ +#define CCU8_CC8_CV_FFL_Msk (0x100000UL) /*!< CCU8_CC8 CV: FFL (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_INTS ------------------------------- */ +#define CCU8_CC8_INTS_PMUS_Pos (0UL) /*!< CCU8_CC8 INTS: PMUS (Bit 0) */ +#define CCU8_CC8_INTS_PMUS_Msk (0x1UL) /*!< CCU8_CC8 INTS: PMUS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_OMDS_Pos (1UL) /*!< CCU8_CC8 INTS: OMDS (Bit 1) */ +#define CCU8_CC8_INTS_OMDS_Msk (0x2UL) /*!< CCU8_CC8 INTS: OMDS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_CMU1S_Pos (2UL) /*!< CCU8_CC8 INTS: CMU1S (Bit 2) */ +#define CCU8_CC8_INTS_CMU1S_Msk (0x4UL) /*!< CCU8_CC8 INTS: CMU1S (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_CMD1S_Pos (3UL) /*!< CCU8_CC8 INTS: CMD1S (Bit 3) */ +#define CCU8_CC8_INTS_CMD1S_Msk (0x8UL) /*!< CCU8_CC8 INTS: CMD1S (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_CMU2S_Pos (4UL) /*!< CCU8_CC8 INTS: CMU2S (Bit 4) */ +#define CCU8_CC8_INTS_CMU2S_Msk (0x10UL) /*!< CCU8_CC8 INTS: CMU2S (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_CMD2S_Pos (5UL) /*!< CCU8_CC8 INTS: CMD2S (Bit 5) */ +#define CCU8_CC8_INTS_CMD2S_Msk (0x20UL) /*!< CCU8_CC8 INTS: CMD2S (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_E0AS_Pos (8UL) /*!< CCU8_CC8 INTS: E0AS (Bit 8) */ +#define CCU8_CC8_INTS_E0AS_Msk (0x100UL) /*!< CCU8_CC8 INTS: E0AS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_E1AS_Pos (9UL) /*!< CCU8_CC8 INTS: E1AS (Bit 9) */ +#define CCU8_CC8_INTS_E1AS_Msk (0x200UL) /*!< CCU8_CC8 INTS: E1AS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_E2AS_Pos (10UL) /*!< CCU8_CC8 INTS: E2AS (Bit 10) */ +#define CCU8_CC8_INTS_E2AS_Msk (0x400UL) /*!< CCU8_CC8 INTS: E2AS (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTS_TRPF_Pos (11UL) /*!< CCU8_CC8 INTS: TRPF (Bit 11) */ +#define CCU8_CC8_INTS_TRPF_Msk (0x800UL) /*!< CCU8_CC8 INTS: TRPF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_INTE ------------------------------- */ +#define CCU8_CC8_INTE_PME_Pos (0UL) /*!< CCU8_CC8 INTE: PME (Bit 0) */ +#define CCU8_CC8_INTE_PME_Msk (0x1UL) /*!< CCU8_CC8 INTE: PME (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_OME_Pos (1UL) /*!< CCU8_CC8 INTE: OME (Bit 1) */ +#define CCU8_CC8_INTE_OME_Msk (0x2UL) /*!< CCU8_CC8 INTE: OME (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_CMU1E_Pos (2UL) /*!< CCU8_CC8 INTE: CMU1E (Bit 2) */ +#define CCU8_CC8_INTE_CMU1E_Msk (0x4UL) /*!< CCU8_CC8 INTE: CMU1E (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_CMD1E_Pos (3UL) /*!< CCU8_CC8 INTE: CMD1E (Bit 3) */ +#define CCU8_CC8_INTE_CMD1E_Msk (0x8UL) /*!< CCU8_CC8 INTE: CMD1E (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_CMU2E_Pos (4UL) /*!< CCU8_CC8 INTE: CMU2E (Bit 4) */ +#define CCU8_CC8_INTE_CMU2E_Msk (0x10UL) /*!< CCU8_CC8 INTE: CMU2E (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_CMD2E_Pos (5UL) /*!< CCU8_CC8 INTE: CMD2E (Bit 5) */ +#define CCU8_CC8_INTE_CMD2E_Msk (0x20UL) /*!< CCU8_CC8 INTE: CMD2E (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_E0AE_Pos (8UL) /*!< CCU8_CC8 INTE: E0AE (Bit 8) */ +#define CCU8_CC8_INTE_E0AE_Msk (0x100UL) /*!< CCU8_CC8 INTE: E0AE (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_E1AE_Pos (9UL) /*!< CCU8_CC8 INTE: E1AE (Bit 9) */ +#define CCU8_CC8_INTE_E1AE_Msk (0x200UL) /*!< CCU8_CC8 INTE: E1AE (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_INTE_E2AE_Pos (10UL) /*!< CCU8_CC8 INTE: E2AE (Bit 10) */ +#define CCU8_CC8_INTE_E2AE_Msk (0x400UL) /*!< CCU8_CC8 INTE: E2AE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_SRS -------------------------------- */ +#define CCU8_CC8_SRS_POSR_Pos (0UL) /*!< CCU8_CC8 SRS: POSR (Bit 0) */ +#define CCU8_CC8_SRS_POSR_Msk (0x3UL) /*!< CCU8_CC8 SRS: POSR (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_SRS_CM1SR_Pos (2UL) /*!< CCU8_CC8 SRS: CM1SR (Bit 2) */ +#define CCU8_CC8_SRS_CM1SR_Msk (0xcUL) /*!< CCU8_CC8 SRS: CM1SR (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_SRS_CM2SR_Pos (4UL) /*!< CCU8_CC8 SRS: CM2SR (Bit 4) */ +#define CCU8_CC8_SRS_CM2SR_Msk (0x30UL) /*!< CCU8_CC8 SRS: CM2SR (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_SRS_E0SR_Pos (8UL) /*!< CCU8_CC8 SRS: E0SR (Bit 8) */ +#define CCU8_CC8_SRS_E0SR_Msk (0x300UL) /*!< CCU8_CC8 SRS: E0SR (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_SRS_E1SR_Pos (10UL) /*!< CCU8_CC8 SRS: E1SR (Bit 10) */ +#define CCU8_CC8_SRS_E1SR_Msk (0xc00UL) /*!< CCU8_CC8 SRS: E1SR (Bitfield-Mask: 0x03) */ +#define CCU8_CC8_SRS_E2SR_Pos (12UL) /*!< CCU8_CC8 SRS: E2SR (Bit 12) */ +#define CCU8_CC8_SRS_E2SR_Msk (0x3000UL) /*!< CCU8_CC8 SRS: E2SR (Bitfield-Mask: 0x03) */ + +/* -------------------------------- CCU8_CC8_SWS -------------------------------- */ +#define CCU8_CC8_SWS_SPM_Pos (0UL) /*!< CCU8_CC8 SWS: SPM (Bit 0) */ +#define CCU8_CC8_SWS_SPM_Msk (0x1UL) /*!< CCU8_CC8 SWS: SPM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SOM_Pos (1UL) /*!< CCU8_CC8 SWS: SOM (Bit 1) */ +#define CCU8_CC8_SWS_SOM_Msk (0x2UL) /*!< CCU8_CC8 SWS: SOM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SCM1U_Pos (2UL) /*!< CCU8_CC8 SWS: SCM1U (Bit 2) */ +#define CCU8_CC8_SWS_SCM1U_Msk (0x4UL) /*!< CCU8_CC8 SWS: SCM1U (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SCM1D_Pos (3UL) /*!< CCU8_CC8 SWS: SCM1D (Bit 3) */ +#define CCU8_CC8_SWS_SCM1D_Msk (0x8UL) /*!< CCU8_CC8 SWS: SCM1D (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SCM2U_Pos (4UL) /*!< CCU8_CC8 SWS: SCM2U (Bit 4) */ +#define CCU8_CC8_SWS_SCM2U_Msk (0x10UL) /*!< CCU8_CC8 SWS: SCM2U (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SCM2D_Pos (5UL) /*!< CCU8_CC8 SWS: SCM2D (Bit 5) */ +#define CCU8_CC8_SWS_SCM2D_Msk (0x20UL) /*!< CCU8_CC8 SWS: SCM2D (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SE0A_Pos (8UL) /*!< CCU8_CC8 SWS: SE0A (Bit 8) */ +#define CCU8_CC8_SWS_SE0A_Msk (0x100UL) /*!< CCU8_CC8 SWS: SE0A (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SE1A_Pos (9UL) /*!< CCU8_CC8 SWS: SE1A (Bit 9) */ +#define CCU8_CC8_SWS_SE1A_Msk (0x200UL) /*!< CCU8_CC8 SWS: SE1A (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_SE2A_Pos (10UL) /*!< CCU8_CC8 SWS: SE2A (Bit 10) */ +#define CCU8_CC8_SWS_SE2A_Msk (0x400UL) /*!< CCU8_CC8 SWS: SE2A (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWS_STRPF_Pos (11UL) /*!< CCU8_CC8 SWS: STRPF (Bit 11) */ +#define CCU8_CC8_SWS_STRPF_Msk (0x800UL) /*!< CCU8_CC8 SWS: STRPF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_SWR -------------------------------- */ +#define CCU8_CC8_SWR_RPM_Pos (0UL) /*!< CCU8_CC8 SWR: RPM (Bit 0) */ +#define CCU8_CC8_SWR_RPM_Msk (0x1UL) /*!< CCU8_CC8 SWR: RPM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_ROM_Pos (1UL) /*!< CCU8_CC8 SWR: ROM (Bit 1) */ +#define CCU8_CC8_SWR_ROM_Msk (0x2UL) /*!< CCU8_CC8 SWR: ROM (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RCM1U_Pos (2UL) /*!< CCU8_CC8 SWR: RCM1U (Bit 2) */ +#define CCU8_CC8_SWR_RCM1U_Msk (0x4UL) /*!< CCU8_CC8 SWR: RCM1U (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RCM1D_Pos (3UL) /*!< CCU8_CC8 SWR: RCM1D (Bit 3) */ +#define CCU8_CC8_SWR_RCM1D_Msk (0x8UL) /*!< CCU8_CC8 SWR: RCM1D (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RCM2U_Pos (4UL) /*!< CCU8_CC8 SWR: RCM2U (Bit 4) */ +#define CCU8_CC8_SWR_RCM2U_Msk (0x10UL) /*!< CCU8_CC8 SWR: RCM2U (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RCM2D_Pos (5UL) /*!< CCU8_CC8 SWR: RCM2D (Bit 5) */ +#define CCU8_CC8_SWR_RCM2D_Msk (0x20UL) /*!< CCU8_CC8 SWR: RCM2D (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RE0A_Pos (8UL) /*!< CCU8_CC8 SWR: RE0A (Bit 8) */ +#define CCU8_CC8_SWR_RE0A_Msk (0x100UL) /*!< CCU8_CC8 SWR: RE0A (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RE1A_Pos (9UL) /*!< CCU8_CC8 SWR: RE1A (Bit 9) */ +#define CCU8_CC8_SWR_RE1A_Msk (0x200UL) /*!< CCU8_CC8 SWR: RE1A (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RE2A_Pos (10UL) /*!< CCU8_CC8 SWR: RE2A (Bit 10) */ +#define CCU8_CC8_SWR_RE2A_Msk (0x400UL) /*!< CCU8_CC8 SWR: RE2A (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_SWR_RTRPF_Pos (11UL) /*!< CCU8_CC8 SWR: RTRPF (Bit 11) */ +#define CCU8_CC8_SWR_RTRPF_Msk (0x800UL) /*!< CCU8_CC8 SWR: RTRPF (Bitfield-Mask: 0x01) */ + +/* -------------------------------- CCU8_CC8_STC -------------------------------- */ +#define CCU8_CC8_STC_CSE_Pos (0UL) /*!< CCU8_CC8 STC: CSE (Bit 0) */ +#define CCU8_CC8_STC_CSE_Msk (0x1UL) /*!< CCU8_CC8 STC: CSE (Bitfield-Mask: 0x01) */ +#define CCU8_CC8_STC_STM_Pos (1UL) /*!< CCU8_CC8 STC: STM (Bit 1) */ +#define CCU8_CC8_STC_STM_Msk (0x6UL) /*!< CCU8_CC8 STC: STM (Bitfield-Mask: 0x03) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- HRPWM0_HRBSC -------------------------------- */ +#define HRPWM0_HRBSC_SUSCFG_Pos (0UL) /*!< HRPWM0 HRBSC: SUSCFG (Bit 0) */ +#define HRPWM0_HRBSC_SUSCFG_Msk (0x7UL) /*!< HRPWM0 HRBSC: SUSCFG (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRBSC_HRBE_Pos (8UL) /*!< HRPWM0 HRBSC: HRBE (Bit 8) */ +#define HRPWM0_HRBSC_HRBE_Msk (0x100UL) /*!< HRPWM0 HRBSC: HRBE (Bitfield-Mask: 0x01) */ + +/* --------------------------------- HRPWM0_MIDR -------------------------------- */ +#define HRPWM0_MIDR_MODR_Pos (0UL) /*!< HRPWM0 MIDR: MODR (Bit 0) */ +#define HRPWM0_MIDR_MODR_Msk (0xffUL) /*!< HRPWM0 MIDR: MODR (Bitfield-Mask: 0xff) */ +#define HRPWM0_MIDR_MODT_Pos (8UL) /*!< HRPWM0 MIDR: MODT (Bit 8) */ +#define HRPWM0_MIDR_MODT_Msk (0xff00UL) /*!< HRPWM0 MIDR: MODT (Bitfield-Mask: 0xff) */ +#define HRPWM0_MIDR_MODN_Pos (16UL) /*!< HRPWM0 MIDR: MODN (Bit 16) */ +#define HRPWM0_MIDR_MODN_Msk (0xffff0000UL) /*!< HRPWM0 MIDR: MODN (Bitfield-Mask: 0xffff) */ + +/* -------------------------------- HRPWM0_GLBANA ------------------------------- */ +#define HRPWM0_GLBANA_SLDLY_Pos (0UL) /*!< HRPWM0 GLBANA: SLDLY (Bit 0) */ +#define HRPWM0_GLBANA_SLDLY_Msk (0x3UL) /*!< HRPWM0 GLBANA: SLDLY (Bitfield-Mask: 0x03) */ +#define HRPWM0_GLBANA_FUP_Pos (2UL) /*!< HRPWM0 GLBANA: FUP (Bit 2) */ +#define HRPWM0_GLBANA_FUP_Msk (0x4UL) /*!< HRPWM0 GLBANA: FUP (Bitfield-Mask: 0x01) */ +#define HRPWM0_GLBANA_FDN_Pos (3UL) /*!< HRPWM0 GLBANA: FDN (Bit 3) */ +#define HRPWM0_GLBANA_FDN_Msk (0x8UL) /*!< HRPWM0 GLBANA: FDN (Bitfield-Mask: 0x01) */ +#define HRPWM0_GLBANA_SLCP_Pos (6UL) /*!< HRPWM0 GLBANA: SLCP (Bit 6) */ +#define HRPWM0_GLBANA_SLCP_Msk (0x1c0UL) /*!< HRPWM0 GLBANA: SLCP (Bitfield-Mask: 0x07) */ +#define HRPWM0_GLBANA_SLIBLDO_Pos (9UL) /*!< HRPWM0 GLBANA: SLIBLDO (Bit 9) */ +#define HRPWM0_GLBANA_SLIBLDO_Msk (0x600UL) /*!< HRPWM0 GLBANA: SLIBLDO (Bitfield-Mask: 0x03) */ +#define HRPWM0_GLBANA_SLIBLF_Pos (11UL) /*!< HRPWM0 GLBANA: SLIBLF (Bit 11) */ +#define HRPWM0_GLBANA_SLIBLF_Msk (0x1800UL) /*!< HRPWM0 GLBANA: SLIBLF (Bitfield-Mask: 0x03) */ +#define HRPWM0_GLBANA_SLVREF_Pos (13UL) /*!< HRPWM0 GLBANA: SLVREF (Bit 13) */ +#define HRPWM0_GLBANA_SLVREF_Msk (0xe000UL) /*!< HRPWM0 GLBANA: SLVREF (Bitfield-Mask: 0x07) */ +#define HRPWM0_GLBANA_TRIBIAS_Pos (16UL) /*!< HRPWM0 GLBANA: TRIBIAS (Bit 16) */ +#define HRPWM0_GLBANA_TRIBIAS_Msk (0x30000UL) /*!< HRPWM0 GLBANA: TRIBIAS (Bitfield-Mask: 0x03) */ +#define HRPWM0_GLBANA_GHREN_Pos (18UL) /*!< HRPWM0 GLBANA: GHREN (Bit 18) */ +#define HRPWM0_GLBANA_GHREN_Msk (0x40000UL) /*!< HRPWM0 GLBANA: GHREN (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_CSGCFG ------------------------------- */ +#define HRPWM0_CSGCFG_C0PM_Pos (0UL) /*!< HRPWM0 CSGCFG: C0PM (Bit 0) */ +#define HRPWM0_CSGCFG_C0PM_Msk (0x3UL) /*!< HRPWM0 CSGCFG: C0PM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSGCFG_C1PM_Pos (2UL) /*!< HRPWM0 CSGCFG: C1PM (Bit 2) */ +#define HRPWM0_CSGCFG_C1PM_Msk (0xcUL) /*!< HRPWM0 CSGCFG: C1PM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSGCFG_C2PM_Pos (4UL) /*!< HRPWM0 CSGCFG: C2PM (Bit 4) */ +#define HRPWM0_CSGCFG_C2PM_Msk (0x30UL) /*!< HRPWM0 CSGCFG: C2PM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSGCFG_C0CD_Pos (16UL) /*!< HRPWM0 CSGCFG: C0CD (Bit 16) */ +#define HRPWM0_CSGCFG_C0CD_Msk (0x10000UL) /*!< HRPWM0 CSGCFG: C0CD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCFG_C1CD_Pos (17UL) /*!< HRPWM0 CSGCFG: C1CD (Bit 17) */ +#define HRPWM0_CSGCFG_C1CD_Msk (0x20000UL) /*!< HRPWM0 CSGCFG: C1CD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCFG_C2CD_Pos (18UL) /*!< HRPWM0 CSGCFG: C2CD (Bit 18) */ +#define HRPWM0_CSGCFG_C2CD_Msk (0x40000UL) /*!< HRPWM0 CSGCFG: C2CD (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSGSETG ------------------------------- */ +#define HRPWM0_CSGSETG_SD0R_Pos (0UL) /*!< HRPWM0 CSGSETG: SD0R (Bit 0) */ +#define HRPWM0_CSGSETG_SD0R_Msk (0x1UL) /*!< HRPWM0 CSGSETG: SD0R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SC0R_Pos (1UL) /*!< HRPWM0 CSGSETG: SC0R (Bit 1) */ +#define HRPWM0_CSGSETG_SC0R_Msk (0x2UL) /*!< HRPWM0 CSGSETG: SC0R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SC0P_Pos (2UL) /*!< HRPWM0 CSGSETG: SC0P (Bit 2) */ +#define HRPWM0_CSGSETG_SC0P_Msk (0x4UL) /*!< HRPWM0 CSGSETG: SC0P (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SD1R_Pos (4UL) /*!< HRPWM0 CSGSETG: SD1R (Bit 4) */ +#define HRPWM0_CSGSETG_SD1R_Msk (0x10UL) /*!< HRPWM0 CSGSETG: SD1R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SC1R_Pos (5UL) /*!< HRPWM0 CSGSETG: SC1R (Bit 5) */ +#define HRPWM0_CSGSETG_SC1R_Msk (0x20UL) /*!< HRPWM0 CSGSETG: SC1R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SC1P_Pos (6UL) /*!< HRPWM0 CSGSETG: SC1P (Bit 6) */ +#define HRPWM0_CSGSETG_SC1P_Msk (0x40UL) /*!< HRPWM0 CSGSETG: SC1P (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SD2R_Pos (8UL) /*!< HRPWM0 CSGSETG: SD2R (Bit 8) */ +#define HRPWM0_CSGSETG_SD2R_Msk (0x100UL) /*!< HRPWM0 CSGSETG: SD2R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SC2R_Pos (9UL) /*!< HRPWM0 CSGSETG: SC2R (Bit 9) */ +#define HRPWM0_CSGSETG_SC2R_Msk (0x200UL) /*!< HRPWM0 CSGSETG: SC2R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSETG_SC2P_Pos (10UL) /*!< HRPWM0 CSGSETG: SC2P (Bit 10) */ +#define HRPWM0_CSGSETG_SC2P_Msk (0x400UL) /*!< HRPWM0 CSGSETG: SC2P (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSGCLRG ------------------------------- */ +#define HRPWM0_CSGCLRG_CD0R_Pos (0UL) /*!< HRPWM0 CSGCLRG: CD0R (Bit 0) */ +#define HRPWM0_CSGCLRG_CD0R_Msk (0x1UL) /*!< HRPWM0 CSGCLRG: CD0R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CC0R_Pos (1UL) /*!< HRPWM0 CSGCLRG: CC0R (Bit 1) */ +#define HRPWM0_CSGCLRG_CC0R_Msk (0x2UL) /*!< HRPWM0 CSGCLRG: CC0R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CC0P_Pos (2UL) /*!< HRPWM0 CSGCLRG: CC0P (Bit 2) */ +#define HRPWM0_CSGCLRG_CC0P_Msk (0x4UL) /*!< HRPWM0 CSGCLRG: CC0P (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CD1R_Pos (4UL) /*!< HRPWM0 CSGCLRG: CD1R (Bit 4) */ +#define HRPWM0_CSGCLRG_CD1R_Msk (0x10UL) /*!< HRPWM0 CSGCLRG: CD1R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CC1R_Pos (5UL) /*!< HRPWM0 CSGCLRG: CC1R (Bit 5) */ +#define HRPWM0_CSGCLRG_CC1R_Msk (0x20UL) /*!< HRPWM0 CSGCLRG: CC1R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CC1P_Pos (6UL) /*!< HRPWM0 CSGCLRG: CC1P (Bit 6) */ +#define HRPWM0_CSGCLRG_CC1P_Msk (0x40UL) /*!< HRPWM0 CSGCLRG: CC1P (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CD2R_Pos (8UL) /*!< HRPWM0 CSGCLRG: CD2R (Bit 8) */ +#define HRPWM0_CSGCLRG_CD2R_Msk (0x100UL) /*!< HRPWM0 CSGCLRG: CD2R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CC2R_Pos (9UL) /*!< HRPWM0 CSGCLRG: CC2R (Bit 9) */ +#define HRPWM0_CSGCLRG_CC2R_Msk (0x200UL) /*!< HRPWM0 CSGCLRG: CC2R (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGCLRG_CC2P_Pos (10UL) /*!< HRPWM0 CSGCLRG: CC2P (Bit 10) */ +#define HRPWM0_CSGCLRG_CC2P_Msk (0x400UL) /*!< HRPWM0 CSGCLRG: CC2P (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSGSTATG ------------------------------ */ +#define HRPWM0_CSGSTATG_D0RB_Pos (0UL) /*!< HRPWM0 CSGSTATG: D0RB (Bit 0) */ +#define HRPWM0_CSGSTATG_D0RB_Msk (0x1UL) /*!< HRPWM0 CSGSTATG: D0RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_C0RB_Pos (1UL) /*!< HRPWM0 CSGSTATG: C0RB (Bit 1) */ +#define HRPWM0_CSGSTATG_C0RB_Msk (0x2UL) /*!< HRPWM0 CSGSTATG: C0RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_PSLS0_Pos (2UL) /*!< HRPWM0 CSGSTATG: PSLS0 (Bit 2) */ +#define HRPWM0_CSGSTATG_PSLS0_Msk (0x4UL) /*!< HRPWM0 CSGSTATG: PSLS0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_D1RB_Pos (4UL) /*!< HRPWM0 CSGSTATG: D1RB (Bit 4) */ +#define HRPWM0_CSGSTATG_D1RB_Msk (0x10UL) /*!< HRPWM0 CSGSTATG: D1RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_C1RB_Pos (5UL) /*!< HRPWM0 CSGSTATG: C1RB (Bit 5) */ +#define HRPWM0_CSGSTATG_C1RB_Msk (0x20UL) /*!< HRPWM0 CSGSTATG: C1RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_PSLS1_Pos (6UL) /*!< HRPWM0 CSGSTATG: PSLS1 (Bit 6) */ +#define HRPWM0_CSGSTATG_PSLS1_Msk (0x40UL) /*!< HRPWM0 CSGSTATG: PSLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_D2RB_Pos (8UL) /*!< HRPWM0 CSGSTATG: D2RB (Bit 8) */ +#define HRPWM0_CSGSTATG_D2RB_Msk (0x100UL) /*!< HRPWM0 CSGSTATG: D2RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_C2RB_Pos (9UL) /*!< HRPWM0 CSGSTATG: C2RB (Bit 9) */ +#define HRPWM0_CSGSTATG_C2RB_Msk (0x200UL) /*!< HRPWM0 CSGSTATG: C2RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGSTATG_PSLS2_Pos (10UL) /*!< HRPWM0 CSGSTATG: PSLS2 (Bit 10) */ +#define HRPWM0_CSGSTATG_PSLS2_Msk (0x400UL) /*!< HRPWM0 CSGSTATG: PSLS2 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_CSGFCG ------------------------------- */ +#define HRPWM0_CSGFCG_S0STR_Pos (0UL) /*!< HRPWM0 CSGFCG: S0STR (Bit 0) */ +#define HRPWM0_CSGFCG_S0STR_Msk (0x1UL) /*!< HRPWM0 CSGFCG: S0STR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_S0STP_Pos (1UL) /*!< HRPWM0 CSGFCG: S0STP (Bit 1) */ +#define HRPWM0_CSGFCG_S0STP_Msk (0x2UL) /*!< HRPWM0 CSGFCG: S0STP (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS0STR_Pos (2UL) /*!< HRPWM0 CSGFCG: PS0STR (Bit 2) */ +#define HRPWM0_CSGFCG_PS0STR_Msk (0x4UL) /*!< HRPWM0 CSGFCG: PS0STR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS0STP_Pos (3UL) /*!< HRPWM0 CSGFCG: PS0STP (Bit 3) */ +#define HRPWM0_CSGFCG_PS0STP_Msk (0x8UL) /*!< HRPWM0 CSGFCG: PS0STP (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS0CLR_Pos (4UL) /*!< HRPWM0 CSGFCG: PS0CLR (Bit 4) */ +#define HRPWM0_CSGFCG_PS0CLR_Msk (0x10UL) /*!< HRPWM0 CSGFCG: PS0CLR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_S1STR_Pos (8UL) /*!< HRPWM0 CSGFCG: S1STR (Bit 8) */ +#define HRPWM0_CSGFCG_S1STR_Msk (0x100UL) /*!< HRPWM0 CSGFCG: S1STR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_S1STP_Pos (9UL) /*!< HRPWM0 CSGFCG: S1STP (Bit 9) */ +#define HRPWM0_CSGFCG_S1STP_Msk (0x200UL) /*!< HRPWM0 CSGFCG: S1STP (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS1STR_Pos (10UL) /*!< HRPWM0 CSGFCG: PS1STR (Bit 10) */ +#define HRPWM0_CSGFCG_PS1STR_Msk (0x400UL) /*!< HRPWM0 CSGFCG: PS1STR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS1STP_Pos (11UL) /*!< HRPWM0 CSGFCG: PS1STP (Bit 11) */ +#define HRPWM0_CSGFCG_PS1STP_Msk (0x800UL) /*!< HRPWM0 CSGFCG: PS1STP (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS1CLR_Pos (12UL) /*!< HRPWM0 CSGFCG: PS1CLR (Bit 12) */ +#define HRPWM0_CSGFCG_PS1CLR_Msk (0x1000UL) /*!< HRPWM0 CSGFCG: PS1CLR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_S2STR_Pos (16UL) /*!< HRPWM0 CSGFCG: S2STR (Bit 16) */ +#define HRPWM0_CSGFCG_S2STR_Msk (0x10000UL) /*!< HRPWM0 CSGFCG: S2STR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_S2STP_Pos (17UL) /*!< HRPWM0 CSGFCG: S2STP (Bit 17) */ +#define HRPWM0_CSGFCG_S2STP_Msk (0x20000UL) /*!< HRPWM0 CSGFCG: S2STP (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS2STR_Pos (18UL) /*!< HRPWM0 CSGFCG: PS2STR (Bit 18) */ +#define HRPWM0_CSGFCG_PS2STR_Msk (0x40000UL) /*!< HRPWM0 CSGFCG: PS2STR (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS2STP_Pos (19UL) /*!< HRPWM0 CSGFCG: PS2STP (Bit 19) */ +#define HRPWM0_CSGFCG_PS2STP_Msk (0x80000UL) /*!< HRPWM0 CSGFCG: PS2STP (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFCG_PS2CLR_Pos (20UL) /*!< HRPWM0 CSGFCG: PS2CLR (Bit 20) */ +#define HRPWM0_CSGFCG_PS2CLR_Msk (0x100000UL) /*!< HRPWM0 CSGFCG: PS2CLR (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_CSGFSG ------------------------------- */ +#define HRPWM0_CSGFSG_S0RB_Pos (0UL) /*!< HRPWM0 CSGFSG: S0RB (Bit 0) */ +#define HRPWM0_CSGFSG_S0RB_Msk (0x1UL) /*!< HRPWM0 CSGFSG: S0RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFSG_P0RB_Pos (1UL) /*!< HRPWM0 CSGFSG: P0RB (Bit 1) */ +#define HRPWM0_CSGFSG_P0RB_Msk (0x2UL) /*!< HRPWM0 CSGFSG: P0RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFSG_S1RB_Pos (8UL) /*!< HRPWM0 CSGFSG: S1RB (Bit 8) */ +#define HRPWM0_CSGFSG_S1RB_Msk (0x100UL) /*!< HRPWM0 CSGFSG: S1RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFSG_P1RB_Pos (9UL) /*!< HRPWM0 CSGFSG: P1RB (Bit 9) */ +#define HRPWM0_CSGFSG_P1RB_Msk (0x200UL) /*!< HRPWM0 CSGFSG: P1RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFSG_S2RB_Pos (16UL) /*!< HRPWM0 CSGFSG: S2RB (Bit 16) */ +#define HRPWM0_CSGFSG_S2RB_Msk (0x10000UL) /*!< HRPWM0 CSGFSG: S2RB (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGFSG_P2RB_Pos (17UL) /*!< HRPWM0 CSGFSG: P2RB (Bit 17) */ +#define HRPWM0_CSGFSG_P2RB_Msk (0x20000UL) /*!< HRPWM0 CSGFSG: P2RB (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_CSGTRG ------------------------------- */ +#define HRPWM0_CSGTRG_D0SES_Pos (0UL) /*!< HRPWM0 CSGTRG: D0SES (Bit 0) */ +#define HRPWM0_CSGTRG_D0SES_Msk (0x1UL) /*!< HRPWM0 CSGTRG: D0SES (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRG_D0SVS_Pos (1UL) /*!< HRPWM0 CSGTRG: D0SVS (Bit 1) */ +#define HRPWM0_CSGTRG_D0SVS_Msk (0x2UL) /*!< HRPWM0 CSGTRG: D0SVS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRG_D1SES_Pos (4UL) /*!< HRPWM0 CSGTRG: D1SES (Bit 4) */ +#define HRPWM0_CSGTRG_D1SES_Msk (0x10UL) /*!< HRPWM0 CSGTRG: D1SES (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRG_D1SVS_Pos (5UL) /*!< HRPWM0 CSGTRG: D1SVS (Bit 5) */ +#define HRPWM0_CSGTRG_D1SVS_Msk (0x20UL) /*!< HRPWM0 CSGTRG: D1SVS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRG_D2SES_Pos (8UL) /*!< HRPWM0 CSGTRG: D2SES (Bit 8) */ +#define HRPWM0_CSGTRG_D2SES_Msk (0x100UL) /*!< HRPWM0 CSGTRG: D2SES (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRG_D2SVS_Pos (9UL) /*!< HRPWM0 CSGTRG: D2SVS (Bit 9) */ +#define HRPWM0_CSGTRG_D2SVS_Msk (0x200UL) /*!< HRPWM0 CSGTRG: D2SVS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_CSGTRC ------------------------------- */ +#define HRPWM0_CSGTRC_D0SEC_Pos (0UL) /*!< HRPWM0 CSGTRC: D0SEC (Bit 0) */ +#define HRPWM0_CSGTRC_D0SEC_Msk (0x1UL) /*!< HRPWM0 CSGTRC: D0SEC (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRC_D1SEC_Pos (4UL) /*!< HRPWM0 CSGTRC: D1SEC (Bit 4) */ +#define HRPWM0_CSGTRC_D1SEC_Msk (0x10UL) /*!< HRPWM0 CSGTRC: D1SEC (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRC_D2SEC_Pos (8UL) /*!< HRPWM0 CSGTRC: D2SEC (Bit 8) */ +#define HRPWM0_CSGTRC_D2SEC_Msk (0x100UL) /*!< HRPWM0 CSGTRC: D2SEC (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSGTRSG ------------------------------- */ +#define HRPWM0_CSGTRSG_D0STE_Pos (0UL) /*!< HRPWM0 CSGTRSG: D0STE (Bit 0) */ +#define HRPWM0_CSGTRSG_D0STE_Msk (0x1UL) /*!< HRPWM0 CSGTRSG: D0STE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRSG_SW0ST_Pos (1UL) /*!< HRPWM0 CSGTRSG: SW0ST (Bit 1) */ +#define HRPWM0_CSGTRSG_SW0ST_Msk (0x2UL) /*!< HRPWM0 CSGTRSG: SW0ST (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRSG_D1STE_Pos (4UL) /*!< HRPWM0 CSGTRSG: D1STE (Bit 4) */ +#define HRPWM0_CSGTRSG_D1STE_Msk (0x10UL) /*!< HRPWM0 CSGTRSG: D1STE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRSG_SW1ST_Pos (5UL) /*!< HRPWM0 CSGTRSG: SW1ST (Bit 5) */ +#define HRPWM0_CSGTRSG_SW1ST_Msk (0x20UL) /*!< HRPWM0 CSGTRSG: SW1ST (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRSG_D2STE_Pos (8UL) /*!< HRPWM0 CSGTRSG: D2STE (Bit 8) */ +#define HRPWM0_CSGTRSG_D2STE_Msk (0x100UL) /*!< HRPWM0 CSGTRSG: D2STE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSGTRSG_SW2ST_Pos (9UL) /*!< HRPWM0 CSGTRSG: SW2ST (Bit 9) */ +#define HRPWM0_CSGTRSG_SW2ST_Msk (0x200UL) /*!< HRPWM0 CSGTRSG: SW2ST (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_HRCCFG ------------------------------- */ +#define HRPWM0_HRCCFG_HRCPM_Pos (0UL) /*!< HRPWM0 HRCCFG: HRCPM (Bit 0) */ +#define HRPWM0_HRCCFG_HRCPM_Msk (0x1UL) /*!< HRPWM0 HRCCFG: HRCPM (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_HRC0E_Pos (4UL) /*!< HRPWM0 HRCCFG: HRC0E (Bit 4) */ +#define HRPWM0_HRCCFG_HRC0E_Msk (0x10UL) /*!< HRPWM0 HRCCFG: HRC0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_HRC1E_Pos (5UL) /*!< HRPWM0 HRCCFG: HRC1E (Bit 5) */ +#define HRPWM0_HRCCFG_HRC1E_Msk (0x20UL) /*!< HRPWM0 HRCCFG: HRC1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_HRC2E_Pos (6UL) /*!< HRPWM0 HRCCFG: HRC2E (Bit 6) */ +#define HRPWM0_HRCCFG_HRC2E_Msk (0x40UL) /*!< HRPWM0 HRCCFG: HRC2E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_HRC3E_Pos (7UL) /*!< HRPWM0 HRCCFG: HRC3E (Bit 7) */ +#define HRPWM0_HRCCFG_HRC3E_Msk (0x80UL) /*!< HRPWM0 HRCCFG: HRC3E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_CLKC_Pos (16UL) /*!< HRPWM0 HRCCFG: CLKC (Bit 16) */ +#define HRPWM0_HRCCFG_CLKC_Msk (0x70000UL) /*!< HRPWM0 HRCCFG: CLKC (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRCCFG_LRC0E_Pos (20UL) /*!< HRPWM0 HRCCFG: LRC0E (Bit 20) */ +#define HRPWM0_HRCCFG_LRC0E_Msk (0x100000UL) /*!< HRPWM0 HRCCFG: LRC0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_LRC1E_Pos (21UL) /*!< HRPWM0 HRCCFG: LRC1E (Bit 21) */ +#define HRPWM0_HRCCFG_LRC1E_Msk (0x200000UL) /*!< HRPWM0 HRCCFG: LRC1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_LRC2E_Pos (22UL) /*!< HRPWM0 HRCCFG: LRC2E (Bit 22) */ +#define HRPWM0_HRCCFG_LRC2E_Msk (0x400000UL) /*!< HRPWM0 HRCCFG: LRC2E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCFG_LRC3E_Pos (23UL) /*!< HRPWM0 HRCCFG: LRC3E (Bit 23) */ +#define HRPWM0_HRCCFG_LRC3E_Msk (0x800000UL) /*!< HRPWM0 HRCCFG: LRC3E (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRCSTRG ------------------------------- */ +#define HRPWM0_HRCSTRG_H0ES_Pos (0UL) /*!< HRPWM0 HRCSTRG: H0ES (Bit 0) */ +#define HRPWM0_HRCSTRG_H0ES_Msk (0x1UL) /*!< HRPWM0 HRCSTRG: H0ES (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTRG_H0DES_Pos (1UL) /*!< HRPWM0 HRCSTRG: H0DES (Bit 1) */ +#define HRPWM0_HRCSTRG_H0DES_Msk (0x2UL) /*!< HRPWM0 HRCSTRG: H0DES (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTRG_H1ES_Pos (4UL) /*!< HRPWM0 HRCSTRG: H1ES (Bit 4) */ +#define HRPWM0_HRCSTRG_H1ES_Msk (0x10UL) /*!< HRPWM0 HRCSTRG: H1ES (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTRG_H1DES_Pos (5UL) /*!< HRPWM0 HRCSTRG: H1DES (Bit 5) */ +#define HRPWM0_HRCSTRG_H1DES_Msk (0x20UL) /*!< HRPWM0 HRCSTRG: H1DES (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTRG_H2ES_Pos (8UL) /*!< HRPWM0 HRCSTRG: H2ES (Bit 8) */ +#define HRPWM0_HRCSTRG_H2ES_Msk (0x100UL) /*!< HRPWM0 HRCSTRG: H2ES (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTRG_H2DES_Pos (9UL) /*!< HRPWM0 HRCSTRG: H2DES (Bit 9) */ +#define HRPWM0_HRCSTRG_H2DES_Msk (0x200UL) /*!< HRPWM0 HRCSTRG: H2DES (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTRG_H3ES_Pos (12UL) /*!< HRPWM0 HRCSTRG: H3ES (Bit 12) */ +#define HRPWM0_HRCSTRG_H3ES_Msk (0x1000UL) /*!< HRPWM0 HRCSTRG: H3ES (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTRG_H3DES_Pos (13UL) /*!< HRPWM0 HRCSTRG: H3DES (Bit 13) */ +#define HRPWM0_HRCSTRG_H3DES_Msk (0x2000UL) /*!< HRPWM0 HRCSTRG: H3DES (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRCCTRG ------------------------------- */ +#define HRPWM0_HRCCTRG_H0EC_Pos (0UL) /*!< HRPWM0 HRCCTRG: H0EC (Bit 0) */ +#define HRPWM0_HRCCTRG_H0EC_Msk (0x1UL) /*!< HRPWM0 HRCCTRG: H0EC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCTRG_H0DEC_Pos (1UL) /*!< HRPWM0 HRCCTRG: H0DEC (Bit 1) */ +#define HRPWM0_HRCCTRG_H0DEC_Msk (0x2UL) /*!< HRPWM0 HRCCTRG: H0DEC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCTRG_H1EC_Pos (4UL) /*!< HRPWM0 HRCCTRG: H1EC (Bit 4) */ +#define HRPWM0_HRCCTRG_H1EC_Msk (0x10UL) /*!< HRPWM0 HRCCTRG: H1EC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCTRG_H1DEC_Pos (5UL) /*!< HRPWM0 HRCCTRG: H1DEC (Bit 5) */ +#define HRPWM0_HRCCTRG_H1DEC_Msk (0x20UL) /*!< HRPWM0 HRCCTRG: H1DEC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCTRG_H2CEC_Pos (8UL) /*!< HRPWM0 HRCCTRG: H2CEC (Bit 8) */ +#define HRPWM0_HRCCTRG_H2CEC_Msk (0x100UL) /*!< HRPWM0 HRCCTRG: H2CEC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCTRG_H2DEC_Pos (9UL) /*!< HRPWM0 HRCCTRG: H2DEC (Bit 9) */ +#define HRPWM0_HRCCTRG_H2DEC_Msk (0x200UL) /*!< HRPWM0 HRCCTRG: H2DEC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCTRG_H3EC_Pos (12UL) /*!< HRPWM0 HRCCTRG: H3EC (Bit 12) */ +#define HRPWM0_HRCCTRG_H3EC_Msk (0x1000UL) /*!< HRPWM0 HRCCTRG: H3EC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCCTRG_H3DEC_Pos (13UL) /*!< HRPWM0 HRCCTRG: H3DEC (Bit 13) */ +#define HRPWM0_HRCCTRG_H3DEC_Msk (0x2000UL) /*!< HRPWM0 HRCCTRG: H3DEC (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRCSTSG ------------------------------- */ +#define HRPWM0_HRCSTSG_H0STE_Pos (0UL) /*!< HRPWM0 HRCSTSG: H0STE (Bit 0) */ +#define HRPWM0_HRCSTSG_H0STE_Msk (0x1UL) /*!< HRPWM0 HRCSTSG: H0STE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTSG_H0DSTE_Pos (1UL) /*!< HRPWM0 HRCSTSG: H0DSTE (Bit 1) */ +#define HRPWM0_HRCSTSG_H0DSTE_Msk (0x2UL) /*!< HRPWM0 HRCSTSG: H0DSTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTSG_H1STE_Pos (4UL) /*!< HRPWM0 HRCSTSG: H1STE (Bit 4) */ +#define HRPWM0_HRCSTSG_H1STE_Msk (0x10UL) /*!< HRPWM0 HRCSTSG: H1STE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTSG_H1DSTE_Pos (5UL) /*!< HRPWM0 HRCSTSG: H1DSTE (Bit 5) */ +#define HRPWM0_HRCSTSG_H1DSTE_Msk (0x20UL) /*!< HRPWM0 HRCSTSG: H1DSTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTSG_H2STE_Pos (8UL) /*!< HRPWM0 HRCSTSG: H2STE (Bit 8) */ +#define HRPWM0_HRCSTSG_H2STE_Msk (0x100UL) /*!< HRPWM0 HRCSTSG: H2STE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTSG_H2DSTE_Pos (9UL) /*!< HRPWM0 HRCSTSG: H2DSTE (Bit 9) */ +#define HRPWM0_HRCSTSG_H2DSTE_Msk (0x200UL) /*!< HRPWM0 HRCSTSG: H2DSTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTSG_H3STE_Pos (12UL) /*!< HRPWM0 HRCSTSG: H3STE (Bit 12) */ +#define HRPWM0_HRCSTSG_H3STE_Msk (0x1000UL) /*!< HRPWM0 HRCSTSG: H3STE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRCSTSG_H3DSTE_Pos (13UL) /*!< HRPWM0 HRCSTSG: H3DSTE (Bit 13) */ +#define HRPWM0_HRCSTSG_H3DSTE_Msk (0x2000UL) /*!< HRPWM0 HRCSTSG: H3DSTE (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_HRGHRS ------------------------------- */ +#define HRPWM0_HRGHRS_HRGR_Pos (0UL) /*!< HRPWM0 HRGHRS: HRGR (Bit 0) */ +#define HRPWM0_HRGHRS_HRGR_Msk (0x1UL) /*!< HRPWM0 HRGHRS: HRGR (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'HRPWM0_CSG' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_CSG_DCI ------------------------------- */ +#define HRPWM0_CSG_DCI_SVIS_Pos (0UL) /*!< HRPWM0_CSG DCI: SVIS (Bit 0) */ +#define HRPWM0_CSG_DCI_SVIS_Msk (0xfUL) /*!< HRPWM0_CSG DCI: SVIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_DCI_STRIS_Pos (4UL) /*!< HRPWM0_CSG DCI: STRIS (Bit 4) */ +#define HRPWM0_CSG_DCI_STRIS_Msk (0xf0UL) /*!< HRPWM0_CSG DCI: STRIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_DCI_STPIS_Pos (8UL) /*!< HRPWM0_CSG DCI: STPIS (Bit 8) */ +#define HRPWM0_CSG_DCI_STPIS_Msk (0xf00UL) /*!< HRPWM0_CSG DCI: STPIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_DCI_TRGIS_Pos (12UL) /*!< HRPWM0_CSG DCI: TRGIS (Bit 12) */ +#define HRPWM0_CSG_DCI_TRGIS_Msk (0xf000UL) /*!< HRPWM0_CSG DCI: TRGIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_DCI_STIS_Pos (16UL) /*!< HRPWM0_CSG DCI: STIS (Bit 16) */ +#define HRPWM0_CSG_DCI_STIS_Msk (0xf0000UL) /*!< HRPWM0_CSG DCI: STIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_DCI_SCS_Pos (20UL) /*!< HRPWM0_CSG DCI: SCS (Bit 20) */ +#define HRPWM0_CSG_DCI_SCS_Msk (0x300000UL) /*!< HRPWM0_CSG DCI: SCS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG_IES ------------------------------- */ +#define HRPWM0_CSG_IES_SVLS_Pos (0UL) /*!< HRPWM0_CSG IES: SVLS (Bit 0) */ +#define HRPWM0_CSG_IES_SVLS_Msk (0x3UL) /*!< HRPWM0_CSG IES: SVLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_IES_STRES_Pos (2UL) /*!< HRPWM0_CSG IES: STRES (Bit 2) */ +#define HRPWM0_CSG_IES_STRES_Msk (0xcUL) /*!< HRPWM0_CSG IES: STRES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_IES_STPES_Pos (4UL) /*!< HRPWM0_CSG IES: STPES (Bit 4) */ +#define HRPWM0_CSG_IES_STPES_Msk (0x30UL) /*!< HRPWM0_CSG IES: STPES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_IES_TRGES_Pos (6UL) /*!< HRPWM0_CSG IES: TRGES (Bit 6) */ +#define HRPWM0_CSG_IES_TRGES_Msk (0xc0UL) /*!< HRPWM0_CSG IES: TRGES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_IES_STES_Pos (8UL) /*!< HRPWM0_CSG IES: STES (Bit 8) */ +#define HRPWM0_CSG_IES_STES_Msk (0x300UL) /*!< HRPWM0_CSG IES: STES (Bitfield-Mask: 0x03) */ + +/* -------------------------------- HRPWM0_CSG_SC ------------------------------- */ +#define HRPWM0_CSG_SC_PSRM_Pos (0UL) /*!< HRPWM0_CSG SC: PSRM (Bit 0) */ +#define HRPWM0_CSG_SC_PSRM_Msk (0x3UL) /*!< HRPWM0_CSG SC: PSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_PSTM_Pos (2UL) /*!< HRPWM0_CSG SC: PSTM (Bit 2) */ +#define HRPWM0_CSG_SC_PSTM_Msk (0xcUL) /*!< HRPWM0_CSG SC: PSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_FPD_Pos (4UL) /*!< HRPWM0_CSG SC: FPD (Bit 4) */ +#define HRPWM0_CSG_SC_FPD_Msk (0x10UL) /*!< HRPWM0_CSG SC: FPD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SC_PSV_Pos (5UL) /*!< HRPWM0_CSG SC: PSV (Bit 5) */ +#define HRPWM0_CSG_SC_PSV_Msk (0x60UL) /*!< HRPWM0_CSG SC: PSV (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_SCM_Pos (8UL) /*!< HRPWM0_CSG SC: SCM (Bit 8) */ +#define HRPWM0_CSG_SC_SCM_Msk (0x300UL) /*!< HRPWM0_CSG SC: SCM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_SSRM_Pos (10UL) /*!< HRPWM0_CSG SC: SSRM (Bit 10) */ +#define HRPWM0_CSG_SC_SSRM_Msk (0xc00UL) /*!< HRPWM0_CSG SC: SSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_SSTM_Pos (12UL) /*!< HRPWM0_CSG SC: SSTM (Bit 12) */ +#define HRPWM0_CSG_SC_SSTM_Msk (0x3000UL) /*!< HRPWM0_CSG SC: SSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_SVSC_Pos (14UL) /*!< HRPWM0_CSG SC: SVSC (Bit 14) */ +#define HRPWM0_CSG_SC_SVSC_Msk (0xc000UL) /*!< HRPWM0_CSG SC: SVSC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_SWSM_Pos (16UL) /*!< HRPWM0_CSG SC: SWSM (Bit 16) */ +#define HRPWM0_CSG_SC_SWSM_Msk (0x30000UL) /*!< HRPWM0_CSG SC: SWSM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_GCFG_Pos (18UL) /*!< HRPWM0_CSG SC: GCFG (Bit 18) */ +#define HRPWM0_CSG_SC_GCFG_Msk (0xc0000UL) /*!< HRPWM0_CSG SC: GCFG (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SC_IST_Pos (20UL) /*!< HRPWM0_CSG SC: IST (Bit 20) */ +#define HRPWM0_CSG_SC_IST_Msk (0x100000UL) /*!< HRPWM0_CSG SC: IST (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SC_PSE_Pos (21UL) /*!< HRPWM0_CSG SC: PSE (Bit 21) */ +#define HRPWM0_CSG_SC_PSE_Msk (0x200000UL) /*!< HRPWM0_CSG SC: PSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SC_PSWM_Pos (24UL) /*!< HRPWM0_CSG SC: PSWM (Bit 24) */ +#define HRPWM0_CSG_SC_PSWM_Msk (0x3000000UL) /*!< HRPWM0_CSG SC: PSWM (Bitfield-Mask: 0x03) */ + +/* -------------------------------- HRPWM0_CSG_PC ------------------------------- */ +#define HRPWM0_CSG_PC_PSWV_Pos (0UL) /*!< HRPWM0_CSG PC: PSWV (Bit 0) */ +#define HRPWM0_CSG_PC_PSWV_Msk (0x3fUL) /*!< HRPWM0_CSG PC: PSWV (Bitfield-Mask: 0x3f) */ + +/* ------------------------------- HRPWM0_CSG_DSV1 ------------------------------ */ +#define HRPWM0_CSG_DSV1_DSV1_Pos (0UL) /*!< HRPWM0_CSG DSV1: DSV1 (Bit 0) */ +#define HRPWM0_CSG_DSV1_DSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------- HRPWM0_CSG_DSV2 ------------------------------ */ +#define HRPWM0_CSG_DSV2_DSV2_Pos (0UL) /*!< HRPWM0_CSG DSV2: DSV2 (Bit 0) */ +#define HRPWM0_CSG_DSV2_DSV2_Msk (0x3ffUL) /*!< HRPWM0_CSG DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------ HRPWM0_CSG_SDSV1 ------------------------------ */ +#define HRPWM0_CSG_SDSV1_SDSV1_Pos (0UL) /*!< HRPWM0_CSG SDSV1: SDSV1 (Bit 0) */ +#define HRPWM0_CSG_SDSV1_SDSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------- HRPWM0_CSG_SPC ------------------------------- */ +#define HRPWM0_CSG_SPC_SPSWV_Pos (0UL) /*!< HRPWM0_CSG SPC: SPSWV (Bit 0) */ +#define HRPWM0_CSG_SPC_SPSWV_Msk (0x3fUL) /*!< HRPWM0_CSG SPC: SPSWV (Bitfield-Mask: 0x3f) */ + +/* -------------------------------- HRPWM0_CSG_CC ------------------------------- */ +#define HRPWM0_CSG_CC_IBS_Pos (0UL) /*!< HRPWM0_CSG CC: IBS (Bit 0) */ +#define HRPWM0_CSG_CC_IBS_Msk (0xfUL) /*!< HRPWM0_CSG CC: IBS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_CC_IMCS_Pos (8UL) /*!< HRPWM0_CSG CC: IMCS (Bit 8) */ +#define HRPWM0_CSG_CC_IMCS_Msk (0x100UL) /*!< HRPWM0_CSG CC: IMCS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_CC_IMCC_Pos (9UL) /*!< HRPWM0_CSG CC: IMCC (Bit 9) */ +#define HRPWM0_CSG_CC_IMCC_Msk (0x600UL) /*!< HRPWM0_CSG CC: IMCC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_CC_ESE_Pos (11UL) /*!< HRPWM0_CSG CC: ESE (Bit 11) */ +#define HRPWM0_CSG_CC_ESE_Msk (0x800UL) /*!< HRPWM0_CSG CC: ESE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_CC_OIE_Pos (12UL) /*!< HRPWM0_CSG CC: OIE (Bit 12) */ +#define HRPWM0_CSG_CC_OIE_Msk (0x1000UL) /*!< HRPWM0_CSG CC: OIE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_CC_OSE_Pos (13UL) /*!< HRPWM0_CSG CC: OSE (Bit 13) */ +#define HRPWM0_CSG_CC_OSE_Msk (0x2000UL) /*!< HRPWM0_CSG CC: OSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_CC_BLMC_Pos (14UL) /*!< HRPWM0_CSG CC: BLMC (Bit 14) */ +#define HRPWM0_CSG_CC_BLMC_Msk (0xc000UL) /*!< HRPWM0_CSG CC: BLMC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_CC_EBE_Pos (16UL) /*!< HRPWM0_CSG CC: EBE (Bit 16) */ +#define HRPWM0_CSG_CC_EBE_Msk (0x10000UL) /*!< HRPWM0_CSG CC: EBE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_CC_COFE_Pos (17UL) /*!< HRPWM0_CSG CC: COFE (Bit 17) */ +#define HRPWM0_CSG_CC_COFE_Msk (0x20000UL) /*!< HRPWM0_CSG CC: COFE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_CC_COFM_Pos (18UL) /*!< HRPWM0_CSG CC: COFM (Bit 18) */ +#define HRPWM0_CSG_CC_COFM_Msk (0x3c0000UL) /*!< HRPWM0_CSG CC: COFM (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_CC_COFC_Pos (24UL) /*!< HRPWM0_CSG CC: COFC (Bit 24) */ +#define HRPWM0_CSG_CC_COFC_Msk (0x3000000UL) /*!< HRPWM0_CSG CC: COFC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG_PLC ------------------------------- */ +#define HRPWM0_CSG_PLC_IPLS_Pos (0UL) /*!< HRPWM0_CSG PLC: IPLS (Bit 0) */ +#define HRPWM0_CSG_PLC_IPLS_Msk (0xfUL) /*!< HRPWM0_CSG PLC: IPLS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG_PLC_PLCL_Pos (8UL) /*!< HRPWM0_CSG PLC: PLCL (Bit 8) */ +#define HRPWM0_CSG_PLC_PLCL_Msk (0x300UL) /*!< HRPWM0_CSG PLC: PLCL (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_PLC_PSL_Pos (10UL) /*!< HRPWM0_CSG PLC: PSL (Bit 10) */ +#define HRPWM0_CSG_PLC_PSL_Msk (0x400UL) /*!< HRPWM0_CSG PLC: PSL (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_PLC_PLSW_Pos (11UL) /*!< HRPWM0_CSG PLC: PLSW (Bit 11) */ +#define HRPWM0_CSG_PLC_PLSW_Msk (0x800UL) /*!< HRPWM0_CSG PLC: PLSW (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_PLC_PLEC_Pos (12UL) /*!< HRPWM0_CSG PLC: PLEC (Bit 12) */ +#define HRPWM0_CSG_PLC_PLEC_Msk (0x3000UL) /*!< HRPWM0_CSG PLC: PLEC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_PLC_PLXC_Pos (14UL) /*!< HRPWM0_CSG PLC: PLXC (Bit 14) */ +#define HRPWM0_CSG_PLC_PLXC_Msk (0xc000UL) /*!< HRPWM0_CSG PLC: PLXC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG_BLV ------------------------------- */ +#define HRPWM0_CSG_BLV_BLV_Pos (0UL) /*!< HRPWM0_CSG BLV: BLV (Bit 0) */ +#define HRPWM0_CSG_BLV_BLV_Msk (0xffUL) /*!< HRPWM0_CSG BLV: BLV (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_CSG_SRE ------------------------------- */ +#define HRPWM0_CSG_SRE_VLS1E_Pos (0UL) /*!< HRPWM0_CSG SRE: VLS1E (Bit 0) */ +#define HRPWM0_CSG_SRE_VLS1E_Msk (0x1UL) /*!< HRPWM0_CSG SRE: VLS1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_VLS2E_Pos (1UL) /*!< HRPWM0_CSG SRE: VLS2E (Bit 1) */ +#define HRPWM0_CSG_SRE_VLS2E_Msk (0x2UL) /*!< HRPWM0_CSG SRE: VLS2E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_TRGSE_Pos (2UL) /*!< HRPWM0_CSG SRE: TRGSE (Bit 2) */ +#define HRPWM0_CSG_SRE_TRGSE_Msk (0x4UL) /*!< HRPWM0_CSG SRE: TRGSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_STRSE_Pos (3UL) /*!< HRPWM0_CSG SRE: STRSE (Bit 3) */ +#define HRPWM0_CSG_SRE_STRSE_Msk (0x8UL) /*!< HRPWM0_CSG SRE: STRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_STPSE_Pos (4UL) /*!< HRPWM0_CSG SRE: STPSE (Bit 4) */ +#define HRPWM0_CSG_SRE_STPSE_Msk (0x10UL) /*!< HRPWM0_CSG SRE: STPSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_STDE_Pos (5UL) /*!< HRPWM0_CSG SRE: STDE (Bit 5) */ +#define HRPWM0_CSG_SRE_STDE_Msk (0x20UL) /*!< HRPWM0_CSG SRE: STDE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_CRSE_Pos (6UL) /*!< HRPWM0_CSG SRE: CRSE (Bit 6) */ +#define HRPWM0_CSG_SRE_CRSE_Msk (0x40UL) /*!< HRPWM0_CSG SRE: CRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_CFSE_Pos (7UL) /*!< HRPWM0_CSG SRE: CFSE (Bit 7) */ +#define HRPWM0_CSG_SRE_CFSE_Msk (0x80UL) /*!< HRPWM0_CSG SRE: CFSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SRE_CSEE_Pos (8UL) /*!< HRPWM0_CSG SRE: CSEE (Bit 8) */ +#define HRPWM0_CSG_SRE_CSEE_Msk (0x100UL) /*!< HRPWM0_CSG SRE: CSEE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG_SRS ------------------------------- */ +#define HRPWM0_CSG_SRS_VLS1S_Pos (0UL) /*!< HRPWM0_CSG SRS: VLS1S (Bit 0) */ +#define HRPWM0_CSG_SRS_VLS1S_Msk (0x3UL) /*!< HRPWM0_CSG SRS: VLS1S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SRS_VLS2S_Pos (2UL) /*!< HRPWM0_CSG SRS: VLS2S (Bit 2) */ +#define HRPWM0_CSG_SRS_VLS2S_Msk (0xcUL) /*!< HRPWM0_CSG SRS: VLS2S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SRS_TRLS_Pos (4UL) /*!< HRPWM0_CSG SRS: TRLS (Bit 4) */ +#define HRPWM0_CSG_SRS_TRLS_Msk (0x30UL) /*!< HRPWM0_CSG SRS: TRLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SRS_SSLS_Pos (6UL) /*!< HRPWM0_CSG SRS: SSLS (Bit 6) */ +#define HRPWM0_CSG_SRS_SSLS_Msk (0xc0UL) /*!< HRPWM0_CSG SRS: SSLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SRS_STLS_Pos (8UL) /*!< HRPWM0_CSG SRS: STLS (Bit 8) */ +#define HRPWM0_CSG_SRS_STLS_Msk (0x300UL) /*!< HRPWM0_CSG SRS: STLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SRS_CRFLS_Pos (10UL) /*!< HRPWM0_CSG SRS: CRFLS (Bit 10) */ +#define HRPWM0_CSG_SRS_CRFLS_Msk (0xc00UL) /*!< HRPWM0_CSG SRS: CRFLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG_SRS_CSLS_Pos (12UL) /*!< HRPWM0_CSG SRS: CSLS (Bit 12) */ +#define HRPWM0_CSG_SRS_CSLS_Msk (0x3000UL) /*!< HRPWM0_CSG SRS: CSLS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG_SWS ------------------------------- */ +#define HRPWM0_CSG_SWS_SVLS1_Pos (0UL) /*!< HRPWM0_CSG SWS: SVLS1 (Bit 0) */ +#define HRPWM0_CSG_SWS_SVLS1_Msk (0x1UL) /*!< HRPWM0_CSG SWS: SVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_SVLS2_Pos (1UL) /*!< HRPWM0_CSG SWS: SVLS2 (Bit 1) */ +#define HRPWM0_CSG_SWS_SVLS2_Msk (0x2UL) /*!< HRPWM0_CSG SWS: SVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_STRGS_Pos (2UL) /*!< HRPWM0_CSG SWS: STRGS (Bit 2) */ +#define HRPWM0_CSG_SWS_STRGS_Msk (0x4UL) /*!< HRPWM0_CSG SWS: STRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_SSTRS_Pos (3UL) /*!< HRPWM0_CSG SWS: SSTRS (Bit 3) */ +#define HRPWM0_CSG_SWS_SSTRS_Msk (0x8UL) /*!< HRPWM0_CSG SWS: SSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_SSTPS_Pos (4UL) /*!< HRPWM0_CSG SWS: SSTPS (Bit 4) */ +#define HRPWM0_CSG_SWS_SSTPS_Msk (0x10UL) /*!< HRPWM0_CSG SWS: SSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_SSTD_Pos (5UL) /*!< HRPWM0_CSG SWS: SSTD (Bit 5) */ +#define HRPWM0_CSG_SWS_SSTD_Msk (0x20UL) /*!< HRPWM0_CSG SWS: SSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_SCRS_Pos (6UL) /*!< HRPWM0_CSG SWS: SCRS (Bit 6) */ +#define HRPWM0_CSG_SWS_SCRS_Msk (0x40UL) /*!< HRPWM0_CSG SWS: SCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_SCFS_Pos (7UL) /*!< HRPWM0_CSG SWS: SCFS (Bit 7) */ +#define HRPWM0_CSG_SWS_SCFS_Msk (0x80UL) /*!< HRPWM0_CSG SWS: SCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWS_SCSS_Pos (8UL) /*!< HRPWM0_CSG SWS: SCSS (Bit 8) */ +#define HRPWM0_CSG_SWS_SCSS_Msk (0x100UL) /*!< HRPWM0_CSG SWS: SCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG_SWC ------------------------------- */ +#define HRPWM0_CSG_SWC_CVLS1_Pos (0UL) /*!< HRPWM0_CSG SWC: CVLS1 (Bit 0) */ +#define HRPWM0_CSG_SWC_CVLS1_Msk (0x1UL) /*!< HRPWM0_CSG SWC: CVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CVLS2_Pos (1UL) /*!< HRPWM0_CSG SWC: CVLS2 (Bit 1) */ +#define HRPWM0_CSG_SWC_CVLS2_Msk (0x2UL) /*!< HRPWM0_CSG SWC: CVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CTRGS_Pos (2UL) /*!< HRPWM0_CSG SWC: CTRGS (Bit 2) */ +#define HRPWM0_CSG_SWC_CTRGS_Msk (0x4UL) /*!< HRPWM0_CSG SWC: CTRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CSTRS_Pos (3UL) /*!< HRPWM0_CSG SWC: CSTRS (Bit 3) */ +#define HRPWM0_CSG_SWC_CSTRS_Msk (0x8UL) /*!< HRPWM0_CSG SWC: CSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CSTPS_Pos (4UL) /*!< HRPWM0_CSG SWC: CSTPS (Bit 4) */ +#define HRPWM0_CSG_SWC_CSTPS_Msk (0x10UL) /*!< HRPWM0_CSG SWC: CSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CSTD_Pos (5UL) /*!< HRPWM0_CSG SWC: CSTD (Bit 5) */ +#define HRPWM0_CSG_SWC_CSTD_Msk (0x20UL) /*!< HRPWM0_CSG SWC: CSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CCRS_Pos (6UL) /*!< HRPWM0_CSG SWC: CCRS (Bit 6) */ +#define HRPWM0_CSG_SWC_CCRS_Msk (0x40UL) /*!< HRPWM0_CSG SWC: CCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CCFS_Pos (7UL) /*!< HRPWM0_CSG SWC: CCFS (Bit 7) */ +#define HRPWM0_CSG_SWC_CCFS_Msk (0x80UL) /*!< HRPWM0_CSG SWC: CCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_SWC_CCSS_Pos (8UL) /*!< HRPWM0_CSG SWC: CCSS (Bit 8) */ +#define HRPWM0_CSG_SWC_CCSS_Msk (0x100UL) /*!< HRPWM0_CSG SWC: CCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_CSG_ISTAT ------------------------------ */ +#define HRPWM0_CSG_ISTAT_VLS1S_Pos (0UL) /*!< HRPWM0_CSG ISTAT: VLS1S (Bit 0) */ +#define HRPWM0_CSG_ISTAT_VLS1S_Msk (0x1UL) /*!< HRPWM0_CSG ISTAT: VLS1S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_VLS2S_Pos (1UL) /*!< HRPWM0_CSG ISTAT: VLS2S (Bit 1) */ +#define HRPWM0_CSG_ISTAT_VLS2S_Msk (0x2UL) /*!< HRPWM0_CSG ISTAT: VLS2S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_TRGSS_Pos (2UL) /*!< HRPWM0_CSG ISTAT: TRGSS (Bit 2) */ +#define HRPWM0_CSG_ISTAT_TRGSS_Msk (0x4UL) /*!< HRPWM0_CSG ISTAT: TRGSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_STRSS_Pos (3UL) /*!< HRPWM0_CSG ISTAT: STRSS (Bit 3) */ +#define HRPWM0_CSG_ISTAT_STRSS_Msk (0x8UL) /*!< HRPWM0_CSG ISTAT: STRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_STPSS_Pos (4UL) /*!< HRPWM0_CSG ISTAT: STPSS (Bit 4) */ +#define HRPWM0_CSG_ISTAT_STPSS_Msk (0x10UL) /*!< HRPWM0_CSG ISTAT: STPSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_STDS_Pos (5UL) /*!< HRPWM0_CSG ISTAT: STDS (Bit 5) */ +#define HRPWM0_CSG_ISTAT_STDS_Msk (0x20UL) /*!< HRPWM0_CSG ISTAT: STDS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_CRSS_Pos (6UL) /*!< HRPWM0_CSG ISTAT: CRSS (Bit 6) */ +#define HRPWM0_CSG_ISTAT_CRSS_Msk (0x40UL) /*!< HRPWM0_CSG ISTAT: CRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_CFSS_Pos (7UL) /*!< HRPWM0_CSG ISTAT: CFSS (Bit 7) */ +#define HRPWM0_CSG_ISTAT_CFSS_Msk (0x80UL) /*!< HRPWM0_CSG ISTAT: CFSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG_ISTAT_CSES_Pos (8UL) /*!< HRPWM0_CSG ISTAT: CSES (Bit 8) */ +#define HRPWM0_CSG_ISTAT_CSES_Msk (0x100UL) /*!< HRPWM0_CSG ISTAT: CSES (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0_CSG0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_CSG0_DCI ------------------------------ */ +#define HRPWM0_CSG0_DCI_SVIS_Pos (0UL) /*!< HRPWM0_CSG0 DCI: SVIS (Bit 0) */ +#define HRPWM0_CSG0_DCI_SVIS_Msk (0xfUL) /*!< HRPWM0_CSG0 DCI: SVIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_DCI_STRIS_Pos (4UL) /*!< HRPWM0_CSG0 DCI: STRIS (Bit 4) */ +#define HRPWM0_CSG0_DCI_STRIS_Msk (0xf0UL) /*!< HRPWM0_CSG0 DCI: STRIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_DCI_STPIS_Pos (8UL) /*!< HRPWM0_CSG0 DCI: STPIS (Bit 8) */ +#define HRPWM0_CSG0_DCI_STPIS_Msk (0xf00UL) /*!< HRPWM0_CSG0 DCI: STPIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_DCI_TRGIS_Pos (12UL) /*!< HRPWM0_CSG0 DCI: TRGIS (Bit 12) */ +#define HRPWM0_CSG0_DCI_TRGIS_Msk (0xf000UL) /*!< HRPWM0_CSG0 DCI: TRGIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_DCI_STIS_Pos (16UL) /*!< HRPWM0_CSG0 DCI: STIS (Bit 16) */ +#define HRPWM0_CSG0_DCI_STIS_Msk (0xf0000UL) /*!< HRPWM0_CSG0 DCI: STIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_DCI_SCS_Pos (20UL) /*!< HRPWM0_CSG0 DCI: SCS (Bit 20) */ +#define HRPWM0_CSG0_DCI_SCS_Msk (0x300000UL) /*!< HRPWM0_CSG0 DCI: SCS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG0_IES ------------------------------ */ +#define HRPWM0_CSG0_IES_SVLS_Pos (0UL) /*!< HRPWM0_CSG0 IES: SVLS (Bit 0) */ +#define HRPWM0_CSG0_IES_SVLS_Msk (0x3UL) /*!< HRPWM0_CSG0 IES: SVLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_IES_STRES_Pos (2UL) /*!< HRPWM0_CSG0 IES: STRES (Bit 2) */ +#define HRPWM0_CSG0_IES_STRES_Msk (0xcUL) /*!< HRPWM0_CSG0 IES: STRES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_IES_STPES_Pos (4UL) /*!< HRPWM0_CSG0 IES: STPES (Bit 4) */ +#define HRPWM0_CSG0_IES_STPES_Msk (0x30UL) /*!< HRPWM0_CSG0 IES: STPES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_IES_TRGES_Pos (6UL) /*!< HRPWM0_CSG0 IES: TRGES (Bit 6) */ +#define HRPWM0_CSG0_IES_TRGES_Msk (0xc0UL) /*!< HRPWM0_CSG0 IES: TRGES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_IES_STES_Pos (8UL) /*!< HRPWM0_CSG0 IES: STES (Bit 8) */ +#define HRPWM0_CSG0_IES_STES_Msk (0x300UL) /*!< HRPWM0_CSG0 IES: STES (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG0_SC ------------------------------- */ +#define HRPWM0_CSG0_SC_PSRM_Pos (0UL) /*!< HRPWM0_CSG0 SC: PSRM (Bit 0) */ +#define HRPWM0_CSG0_SC_PSRM_Msk (0x3UL) /*!< HRPWM0_CSG0 SC: PSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_PSTM_Pos (2UL) /*!< HRPWM0_CSG0 SC: PSTM (Bit 2) */ +#define HRPWM0_CSG0_SC_PSTM_Msk (0xcUL) /*!< HRPWM0_CSG0 SC: PSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_FPD_Pos (4UL) /*!< HRPWM0_CSG0 SC: FPD (Bit 4) */ +#define HRPWM0_CSG0_SC_FPD_Msk (0x10UL) /*!< HRPWM0_CSG0 SC: FPD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SC_PSV_Pos (5UL) /*!< HRPWM0_CSG0 SC: PSV (Bit 5) */ +#define HRPWM0_CSG0_SC_PSV_Msk (0x60UL) /*!< HRPWM0_CSG0 SC: PSV (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_SCM_Pos (8UL) /*!< HRPWM0_CSG0 SC: SCM (Bit 8) */ +#define HRPWM0_CSG0_SC_SCM_Msk (0x300UL) /*!< HRPWM0_CSG0 SC: SCM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_SSRM_Pos (10UL) /*!< HRPWM0_CSG0 SC: SSRM (Bit 10) */ +#define HRPWM0_CSG0_SC_SSRM_Msk (0xc00UL) /*!< HRPWM0_CSG0 SC: SSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_SSTM_Pos (12UL) /*!< HRPWM0_CSG0 SC: SSTM (Bit 12) */ +#define HRPWM0_CSG0_SC_SSTM_Msk (0x3000UL) /*!< HRPWM0_CSG0 SC: SSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_SVSC_Pos (14UL) /*!< HRPWM0_CSG0 SC: SVSC (Bit 14) */ +#define HRPWM0_CSG0_SC_SVSC_Msk (0xc000UL) /*!< HRPWM0_CSG0 SC: SVSC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_SWSM_Pos (16UL) /*!< HRPWM0_CSG0 SC: SWSM (Bit 16) */ +#define HRPWM0_CSG0_SC_SWSM_Msk (0x30000UL) /*!< HRPWM0_CSG0 SC: SWSM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_GCFG_Pos (18UL) /*!< HRPWM0_CSG0 SC: GCFG (Bit 18) */ +#define HRPWM0_CSG0_SC_GCFG_Msk (0xc0000UL) /*!< HRPWM0_CSG0 SC: GCFG (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SC_IST_Pos (20UL) /*!< HRPWM0_CSG0 SC: IST (Bit 20) */ +#define HRPWM0_CSG0_SC_IST_Msk (0x100000UL) /*!< HRPWM0_CSG0 SC: IST (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SC_PSE_Pos (21UL) /*!< HRPWM0_CSG0 SC: PSE (Bit 21) */ +#define HRPWM0_CSG0_SC_PSE_Msk (0x200000UL) /*!< HRPWM0_CSG0 SC: PSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SC_PSWM_Pos (24UL) /*!< HRPWM0_CSG0 SC: PSWM (Bit 24) */ +#define HRPWM0_CSG0_SC_PSWM_Msk (0x3000000UL) /*!< HRPWM0_CSG0 SC: PSWM (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG0_PC ------------------------------- */ +#define HRPWM0_CSG0_PC_PSWV_Pos (0UL) /*!< HRPWM0_CSG0 PC: PSWV (Bit 0) */ +#define HRPWM0_CSG0_PC_PSWV_Msk (0x3fUL) /*!< HRPWM0_CSG0 PC: PSWV (Bitfield-Mask: 0x3f) */ + +/* ------------------------------ HRPWM0_CSG0_DSV1 ------------------------------ */ +#define HRPWM0_CSG0_DSV1_DSV1_Pos (0UL) /*!< HRPWM0_CSG0 DSV1: DSV1 (Bit 0) */ +#define HRPWM0_CSG0_DSV1_DSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG0 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------ HRPWM0_CSG0_DSV2 ------------------------------ */ +#define HRPWM0_CSG0_DSV2_DSV2_Pos (0UL) /*!< HRPWM0_CSG0 DSV2: DSV2 (Bit 0) */ +#define HRPWM0_CSG0_DSV2_DSV2_Msk (0x3ffUL) /*!< HRPWM0_CSG0 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------ HRPWM0_CSG0_SDSV1 ----------------------------- */ +#define HRPWM0_CSG0_SDSV1_SDSV1_Pos (0UL) /*!< HRPWM0_CSG0 SDSV1: SDSV1 (Bit 0) */ +#define HRPWM0_CSG0_SDSV1_SDSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG0 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------- HRPWM0_CSG0_SPC ------------------------------ */ +#define HRPWM0_CSG0_SPC_SPSWV_Pos (0UL) /*!< HRPWM0_CSG0 SPC: SPSWV (Bit 0) */ +#define HRPWM0_CSG0_SPC_SPSWV_Msk (0x3fUL) /*!< HRPWM0_CSG0 SPC: SPSWV (Bitfield-Mask: 0x3f) */ + +/* ------------------------------- HRPWM0_CSG0_CC ------------------------------- */ +#define HRPWM0_CSG0_CC_IBS_Pos (0UL) /*!< HRPWM0_CSG0 CC: IBS (Bit 0) */ +#define HRPWM0_CSG0_CC_IBS_Msk (0xfUL) /*!< HRPWM0_CSG0 CC: IBS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_CC_IMCS_Pos (8UL) /*!< HRPWM0_CSG0 CC: IMCS (Bit 8) */ +#define HRPWM0_CSG0_CC_IMCS_Msk (0x100UL) /*!< HRPWM0_CSG0 CC: IMCS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_CC_IMCC_Pos (9UL) /*!< HRPWM0_CSG0 CC: IMCC (Bit 9) */ +#define HRPWM0_CSG0_CC_IMCC_Msk (0x600UL) /*!< HRPWM0_CSG0 CC: IMCC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_CC_ESE_Pos (11UL) /*!< HRPWM0_CSG0 CC: ESE (Bit 11) */ +#define HRPWM0_CSG0_CC_ESE_Msk (0x800UL) /*!< HRPWM0_CSG0 CC: ESE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_CC_OIE_Pos (12UL) /*!< HRPWM0_CSG0 CC: OIE (Bit 12) */ +#define HRPWM0_CSG0_CC_OIE_Msk (0x1000UL) /*!< HRPWM0_CSG0 CC: OIE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_CC_OSE_Pos (13UL) /*!< HRPWM0_CSG0 CC: OSE (Bit 13) */ +#define HRPWM0_CSG0_CC_OSE_Msk (0x2000UL) /*!< HRPWM0_CSG0 CC: OSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_CC_BLMC_Pos (14UL) /*!< HRPWM0_CSG0 CC: BLMC (Bit 14) */ +#define HRPWM0_CSG0_CC_BLMC_Msk (0xc000UL) /*!< HRPWM0_CSG0 CC: BLMC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_CC_EBE_Pos (16UL) /*!< HRPWM0_CSG0 CC: EBE (Bit 16) */ +#define HRPWM0_CSG0_CC_EBE_Msk (0x10000UL) /*!< HRPWM0_CSG0 CC: EBE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_CC_COFE_Pos (17UL) /*!< HRPWM0_CSG0 CC: COFE (Bit 17) */ +#define HRPWM0_CSG0_CC_COFE_Msk (0x20000UL) /*!< HRPWM0_CSG0 CC: COFE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_CC_COFM_Pos (18UL) /*!< HRPWM0_CSG0 CC: COFM (Bit 18) */ +#define HRPWM0_CSG0_CC_COFM_Msk (0x3c0000UL) /*!< HRPWM0_CSG0 CC: COFM (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_CC_COFC_Pos (24UL) /*!< HRPWM0_CSG0 CC: COFC (Bit 24) */ +#define HRPWM0_CSG0_CC_COFC_Msk (0x3000000UL) /*!< HRPWM0_CSG0 CC: COFC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG0_PLC ------------------------------ */ +#define HRPWM0_CSG0_PLC_IPLS_Pos (0UL) /*!< HRPWM0_CSG0 PLC: IPLS (Bit 0) */ +#define HRPWM0_CSG0_PLC_IPLS_Msk (0xfUL) /*!< HRPWM0_CSG0 PLC: IPLS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG0_PLC_PLCL_Pos (8UL) /*!< HRPWM0_CSG0 PLC: PLCL (Bit 8) */ +#define HRPWM0_CSG0_PLC_PLCL_Msk (0x300UL) /*!< HRPWM0_CSG0 PLC: PLCL (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_PLC_PSL_Pos (10UL) /*!< HRPWM0_CSG0 PLC: PSL (Bit 10) */ +#define HRPWM0_CSG0_PLC_PSL_Msk (0x400UL) /*!< HRPWM0_CSG0 PLC: PSL (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_PLC_PLSW_Pos (11UL) /*!< HRPWM0_CSG0 PLC: PLSW (Bit 11) */ +#define HRPWM0_CSG0_PLC_PLSW_Msk (0x800UL) /*!< HRPWM0_CSG0 PLC: PLSW (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_PLC_PLEC_Pos (12UL) /*!< HRPWM0_CSG0 PLC: PLEC (Bit 12) */ +#define HRPWM0_CSG0_PLC_PLEC_Msk (0x3000UL) /*!< HRPWM0_CSG0 PLC: PLEC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_PLC_PLXC_Pos (14UL) /*!< HRPWM0_CSG0 PLC: PLXC (Bit 14) */ +#define HRPWM0_CSG0_PLC_PLXC_Msk (0xc000UL) /*!< HRPWM0_CSG0 PLC: PLXC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG0_BLV ------------------------------ */ +#define HRPWM0_CSG0_BLV_BLV_Pos (0UL) /*!< HRPWM0_CSG0 BLV: BLV (Bit 0) */ +#define HRPWM0_CSG0_BLV_BLV_Msk (0xffUL) /*!< HRPWM0_CSG0 BLV: BLV (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_CSG0_SRE ------------------------------ */ +#define HRPWM0_CSG0_SRE_VLS1E_Pos (0UL) /*!< HRPWM0_CSG0 SRE: VLS1E (Bit 0) */ +#define HRPWM0_CSG0_SRE_VLS1E_Msk (0x1UL) /*!< HRPWM0_CSG0 SRE: VLS1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_VLS2E_Pos (1UL) /*!< HRPWM0_CSG0 SRE: VLS2E (Bit 1) */ +#define HRPWM0_CSG0_SRE_VLS2E_Msk (0x2UL) /*!< HRPWM0_CSG0 SRE: VLS2E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_TRGSE_Pos (2UL) /*!< HRPWM0_CSG0 SRE: TRGSE (Bit 2) */ +#define HRPWM0_CSG0_SRE_TRGSE_Msk (0x4UL) /*!< HRPWM0_CSG0 SRE: TRGSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_STRSE_Pos (3UL) /*!< HRPWM0_CSG0 SRE: STRSE (Bit 3) */ +#define HRPWM0_CSG0_SRE_STRSE_Msk (0x8UL) /*!< HRPWM0_CSG0 SRE: STRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_STPSE_Pos (4UL) /*!< HRPWM0_CSG0 SRE: STPSE (Bit 4) */ +#define HRPWM0_CSG0_SRE_STPSE_Msk (0x10UL) /*!< HRPWM0_CSG0 SRE: STPSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_STDE_Pos (5UL) /*!< HRPWM0_CSG0 SRE: STDE (Bit 5) */ +#define HRPWM0_CSG0_SRE_STDE_Msk (0x20UL) /*!< HRPWM0_CSG0 SRE: STDE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_CRSE_Pos (6UL) /*!< HRPWM0_CSG0 SRE: CRSE (Bit 6) */ +#define HRPWM0_CSG0_SRE_CRSE_Msk (0x40UL) /*!< HRPWM0_CSG0 SRE: CRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_CFSE_Pos (7UL) /*!< HRPWM0_CSG0 SRE: CFSE (Bit 7) */ +#define HRPWM0_CSG0_SRE_CFSE_Msk (0x80UL) /*!< HRPWM0_CSG0 SRE: CFSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SRE_CSEE_Pos (8UL) /*!< HRPWM0_CSG0 SRE: CSEE (Bit 8) */ +#define HRPWM0_CSG0_SRE_CSEE_Msk (0x100UL) /*!< HRPWM0_CSG0 SRE: CSEE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG0_SRS ------------------------------ */ +#define HRPWM0_CSG0_SRS_VLS1S_Pos (0UL) /*!< HRPWM0_CSG0 SRS: VLS1S (Bit 0) */ +#define HRPWM0_CSG0_SRS_VLS1S_Msk (0x3UL) /*!< HRPWM0_CSG0 SRS: VLS1S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SRS_VLS2S_Pos (2UL) /*!< HRPWM0_CSG0 SRS: VLS2S (Bit 2) */ +#define HRPWM0_CSG0_SRS_VLS2S_Msk (0xcUL) /*!< HRPWM0_CSG0 SRS: VLS2S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SRS_TRLS_Pos (4UL) /*!< HRPWM0_CSG0 SRS: TRLS (Bit 4) */ +#define HRPWM0_CSG0_SRS_TRLS_Msk (0x30UL) /*!< HRPWM0_CSG0 SRS: TRLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SRS_SSLS_Pos (6UL) /*!< HRPWM0_CSG0 SRS: SSLS (Bit 6) */ +#define HRPWM0_CSG0_SRS_SSLS_Msk (0xc0UL) /*!< HRPWM0_CSG0 SRS: SSLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SRS_STLS_Pos (8UL) /*!< HRPWM0_CSG0 SRS: STLS (Bit 8) */ +#define HRPWM0_CSG0_SRS_STLS_Msk (0x300UL) /*!< HRPWM0_CSG0 SRS: STLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SRS_CRFLS_Pos (10UL) /*!< HRPWM0_CSG0 SRS: CRFLS (Bit 10) */ +#define HRPWM0_CSG0_SRS_CRFLS_Msk (0xc00UL) /*!< HRPWM0_CSG0 SRS: CRFLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG0_SRS_CSLS_Pos (12UL) /*!< HRPWM0_CSG0 SRS: CSLS (Bit 12) */ +#define HRPWM0_CSG0_SRS_CSLS_Msk (0x3000UL) /*!< HRPWM0_CSG0 SRS: CSLS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG0_SWS ------------------------------ */ +#define HRPWM0_CSG0_SWS_SVLS1_Pos (0UL) /*!< HRPWM0_CSG0 SWS: SVLS1 (Bit 0) */ +#define HRPWM0_CSG0_SWS_SVLS1_Msk (0x1UL) /*!< HRPWM0_CSG0 SWS: SVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_SVLS2_Pos (1UL) /*!< HRPWM0_CSG0 SWS: SVLS2 (Bit 1) */ +#define HRPWM0_CSG0_SWS_SVLS2_Msk (0x2UL) /*!< HRPWM0_CSG0 SWS: SVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_STRGS_Pos (2UL) /*!< HRPWM0_CSG0 SWS: STRGS (Bit 2) */ +#define HRPWM0_CSG0_SWS_STRGS_Msk (0x4UL) /*!< HRPWM0_CSG0 SWS: STRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_SSTRS_Pos (3UL) /*!< HRPWM0_CSG0 SWS: SSTRS (Bit 3) */ +#define HRPWM0_CSG0_SWS_SSTRS_Msk (0x8UL) /*!< HRPWM0_CSG0 SWS: SSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_SSTPS_Pos (4UL) /*!< HRPWM0_CSG0 SWS: SSTPS (Bit 4) */ +#define HRPWM0_CSG0_SWS_SSTPS_Msk (0x10UL) /*!< HRPWM0_CSG0 SWS: SSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_SSTD_Pos (5UL) /*!< HRPWM0_CSG0 SWS: SSTD (Bit 5) */ +#define HRPWM0_CSG0_SWS_SSTD_Msk (0x20UL) /*!< HRPWM0_CSG0 SWS: SSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_SCRS_Pos (6UL) /*!< HRPWM0_CSG0 SWS: SCRS (Bit 6) */ +#define HRPWM0_CSG0_SWS_SCRS_Msk (0x40UL) /*!< HRPWM0_CSG0 SWS: SCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_SCFS_Pos (7UL) /*!< HRPWM0_CSG0 SWS: SCFS (Bit 7) */ +#define HRPWM0_CSG0_SWS_SCFS_Msk (0x80UL) /*!< HRPWM0_CSG0 SWS: SCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWS_SCSS_Pos (8UL) /*!< HRPWM0_CSG0 SWS: SCSS (Bit 8) */ +#define HRPWM0_CSG0_SWS_SCSS_Msk (0x100UL) /*!< HRPWM0_CSG0 SWS: SCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG0_SWC ------------------------------ */ +#define HRPWM0_CSG0_SWC_CVLS1_Pos (0UL) /*!< HRPWM0_CSG0 SWC: CVLS1 (Bit 0) */ +#define HRPWM0_CSG0_SWC_CVLS1_Msk (0x1UL) /*!< HRPWM0_CSG0 SWC: CVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CVLS2_Pos (1UL) /*!< HRPWM0_CSG0 SWC: CVLS2 (Bit 1) */ +#define HRPWM0_CSG0_SWC_CVLS2_Msk (0x2UL) /*!< HRPWM0_CSG0 SWC: CVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CTRGS_Pos (2UL) /*!< HRPWM0_CSG0 SWC: CTRGS (Bit 2) */ +#define HRPWM0_CSG0_SWC_CTRGS_Msk (0x4UL) /*!< HRPWM0_CSG0 SWC: CTRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CSTRS_Pos (3UL) /*!< HRPWM0_CSG0 SWC: CSTRS (Bit 3) */ +#define HRPWM0_CSG0_SWC_CSTRS_Msk (0x8UL) /*!< HRPWM0_CSG0 SWC: CSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CSTPS_Pos (4UL) /*!< HRPWM0_CSG0 SWC: CSTPS (Bit 4) */ +#define HRPWM0_CSG0_SWC_CSTPS_Msk (0x10UL) /*!< HRPWM0_CSG0 SWC: CSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CSTD_Pos (5UL) /*!< HRPWM0_CSG0 SWC: CSTD (Bit 5) */ +#define HRPWM0_CSG0_SWC_CSTD_Msk (0x20UL) /*!< HRPWM0_CSG0 SWC: CSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CCRS_Pos (6UL) /*!< HRPWM0_CSG0 SWC: CCRS (Bit 6) */ +#define HRPWM0_CSG0_SWC_CCRS_Msk (0x40UL) /*!< HRPWM0_CSG0 SWC: CCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CCFS_Pos (7UL) /*!< HRPWM0_CSG0 SWC: CCFS (Bit 7) */ +#define HRPWM0_CSG0_SWC_CCFS_Msk (0x80UL) /*!< HRPWM0_CSG0 SWC: CCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_SWC_CCSS_Pos (8UL) /*!< HRPWM0_CSG0 SWC: CCSS (Bit 8) */ +#define HRPWM0_CSG0_SWC_CCSS_Msk (0x100UL) /*!< HRPWM0_CSG0 SWC: CCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_CSG0_ISTAT ----------------------------- */ +#define HRPWM0_CSG0_ISTAT_VLS1S_Pos (0UL) /*!< HRPWM0_CSG0 ISTAT: VLS1S (Bit 0) */ +#define HRPWM0_CSG0_ISTAT_VLS1S_Msk (0x1UL) /*!< HRPWM0_CSG0 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_VLS2S_Pos (1UL) /*!< HRPWM0_CSG0 ISTAT: VLS2S (Bit 1) */ +#define HRPWM0_CSG0_ISTAT_VLS2S_Msk (0x2UL) /*!< HRPWM0_CSG0 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_TRGSS_Pos (2UL) /*!< HRPWM0_CSG0 ISTAT: TRGSS (Bit 2) */ +#define HRPWM0_CSG0_ISTAT_TRGSS_Msk (0x4UL) /*!< HRPWM0_CSG0 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_STRSS_Pos (3UL) /*!< HRPWM0_CSG0 ISTAT: STRSS (Bit 3) */ +#define HRPWM0_CSG0_ISTAT_STRSS_Msk (0x8UL) /*!< HRPWM0_CSG0 ISTAT: STRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_STPSS_Pos (4UL) /*!< HRPWM0_CSG0 ISTAT: STPSS (Bit 4) */ +#define HRPWM0_CSG0_ISTAT_STPSS_Msk (0x10UL) /*!< HRPWM0_CSG0 ISTAT: STPSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_STDS_Pos (5UL) /*!< HRPWM0_CSG0 ISTAT: STDS (Bit 5) */ +#define HRPWM0_CSG0_ISTAT_STDS_Msk (0x20UL) /*!< HRPWM0_CSG0 ISTAT: STDS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_CRSS_Pos (6UL) /*!< HRPWM0_CSG0 ISTAT: CRSS (Bit 6) */ +#define HRPWM0_CSG0_ISTAT_CRSS_Msk (0x40UL) /*!< HRPWM0_CSG0 ISTAT: CRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_CFSS_Pos (7UL) /*!< HRPWM0_CSG0 ISTAT: CFSS (Bit 7) */ +#define HRPWM0_CSG0_ISTAT_CFSS_Msk (0x80UL) /*!< HRPWM0_CSG0 ISTAT: CFSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG0_ISTAT_CSES_Pos (8UL) /*!< HRPWM0_CSG0 ISTAT: CSES (Bit 8) */ +#define HRPWM0_CSG0_ISTAT_CSES_Msk (0x100UL) /*!< HRPWM0_CSG0 ISTAT: CSES (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0_CSG1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_CSG1_DCI ------------------------------ */ +#define HRPWM0_CSG1_DCI_SVIS_Pos (0UL) /*!< HRPWM0_CSG1 DCI: SVIS (Bit 0) */ +#define HRPWM0_CSG1_DCI_SVIS_Msk (0xfUL) /*!< HRPWM0_CSG1 DCI: SVIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_DCI_STRIS_Pos (4UL) /*!< HRPWM0_CSG1 DCI: STRIS (Bit 4) */ +#define HRPWM0_CSG1_DCI_STRIS_Msk (0xf0UL) /*!< HRPWM0_CSG1 DCI: STRIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_DCI_STPIS_Pos (8UL) /*!< HRPWM0_CSG1 DCI: STPIS (Bit 8) */ +#define HRPWM0_CSG1_DCI_STPIS_Msk (0xf00UL) /*!< HRPWM0_CSG1 DCI: STPIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_DCI_TRGIS_Pos (12UL) /*!< HRPWM0_CSG1 DCI: TRGIS (Bit 12) */ +#define HRPWM0_CSG1_DCI_TRGIS_Msk (0xf000UL) /*!< HRPWM0_CSG1 DCI: TRGIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_DCI_STIS_Pos (16UL) /*!< HRPWM0_CSG1 DCI: STIS (Bit 16) */ +#define HRPWM0_CSG1_DCI_STIS_Msk (0xf0000UL) /*!< HRPWM0_CSG1 DCI: STIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_DCI_SCS_Pos (20UL) /*!< HRPWM0_CSG1 DCI: SCS (Bit 20) */ +#define HRPWM0_CSG1_DCI_SCS_Msk (0x300000UL) /*!< HRPWM0_CSG1 DCI: SCS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG1_IES ------------------------------ */ +#define HRPWM0_CSG1_IES_SVLS_Pos (0UL) /*!< HRPWM0_CSG1 IES: SVLS (Bit 0) */ +#define HRPWM0_CSG1_IES_SVLS_Msk (0x3UL) /*!< HRPWM0_CSG1 IES: SVLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_IES_STRES_Pos (2UL) /*!< HRPWM0_CSG1 IES: STRES (Bit 2) */ +#define HRPWM0_CSG1_IES_STRES_Msk (0xcUL) /*!< HRPWM0_CSG1 IES: STRES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_IES_STPES_Pos (4UL) /*!< HRPWM0_CSG1 IES: STPES (Bit 4) */ +#define HRPWM0_CSG1_IES_STPES_Msk (0x30UL) /*!< HRPWM0_CSG1 IES: STPES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_IES_TRGES_Pos (6UL) /*!< HRPWM0_CSG1 IES: TRGES (Bit 6) */ +#define HRPWM0_CSG1_IES_TRGES_Msk (0xc0UL) /*!< HRPWM0_CSG1 IES: TRGES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_IES_STES_Pos (8UL) /*!< HRPWM0_CSG1 IES: STES (Bit 8) */ +#define HRPWM0_CSG1_IES_STES_Msk (0x300UL) /*!< HRPWM0_CSG1 IES: STES (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG1_SC ------------------------------- */ +#define HRPWM0_CSG1_SC_PSRM_Pos (0UL) /*!< HRPWM0_CSG1 SC: PSRM (Bit 0) */ +#define HRPWM0_CSG1_SC_PSRM_Msk (0x3UL) /*!< HRPWM0_CSG1 SC: PSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_PSTM_Pos (2UL) /*!< HRPWM0_CSG1 SC: PSTM (Bit 2) */ +#define HRPWM0_CSG1_SC_PSTM_Msk (0xcUL) /*!< HRPWM0_CSG1 SC: PSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_FPD_Pos (4UL) /*!< HRPWM0_CSG1 SC: FPD (Bit 4) */ +#define HRPWM0_CSG1_SC_FPD_Msk (0x10UL) /*!< HRPWM0_CSG1 SC: FPD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SC_PSV_Pos (5UL) /*!< HRPWM0_CSG1 SC: PSV (Bit 5) */ +#define HRPWM0_CSG1_SC_PSV_Msk (0x60UL) /*!< HRPWM0_CSG1 SC: PSV (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_SCM_Pos (8UL) /*!< HRPWM0_CSG1 SC: SCM (Bit 8) */ +#define HRPWM0_CSG1_SC_SCM_Msk (0x300UL) /*!< HRPWM0_CSG1 SC: SCM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_SSRM_Pos (10UL) /*!< HRPWM0_CSG1 SC: SSRM (Bit 10) */ +#define HRPWM0_CSG1_SC_SSRM_Msk (0xc00UL) /*!< HRPWM0_CSG1 SC: SSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_SSTM_Pos (12UL) /*!< HRPWM0_CSG1 SC: SSTM (Bit 12) */ +#define HRPWM0_CSG1_SC_SSTM_Msk (0x3000UL) /*!< HRPWM0_CSG1 SC: SSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_SVSC_Pos (14UL) /*!< HRPWM0_CSG1 SC: SVSC (Bit 14) */ +#define HRPWM0_CSG1_SC_SVSC_Msk (0xc000UL) /*!< HRPWM0_CSG1 SC: SVSC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_SWSM_Pos (16UL) /*!< HRPWM0_CSG1 SC: SWSM (Bit 16) */ +#define HRPWM0_CSG1_SC_SWSM_Msk (0x30000UL) /*!< HRPWM0_CSG1 SC: SWSM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_GCFG_Pos (18UL) /*!< HRPWM0_CSG1 SC: GCFG (Bit 18) */ +#define HRPWM0_CSG1_SC_GCFG_Msk (0xc0000UL) /*!< HRPWM0_CSG1 SC: GCFG (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SC_IST_Pos (20UL) /*!< HRPWM0_CSG1 SC: IST (Bit 20) */ +#define HRPWM0_CSG1_SC_IST_Msk (0x100000UL) /*!< HRPWM0_CSG1 SC: IST (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SC_PSE_Pos (21UL) /*!< HRPWM0_CSG1 SC: PSE (Bit 21) */ +#define HRPWM0_CSG1_SC_PSE_Msk (0x200000UL) /*!< HRPWM0_CSG1 SC: PSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SC_PSWM_Pos (24UL) /*!< HRPWM0_CSG1 SC: PSWM (Bit 24) */ +#define HRPWM0_CSG1_SC_PSWM_Msk (0x3000000UL) /*!< HRPWM0_CSG1 SC: PSWM (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG1_PC ------------------------------- */ +#define HRPWM0_CSG1_PC_PSWV_Pos (0UL) /*!< HRPWM0_CSG1 PC: PSWV (Bit 0) */ +#define HRPWM0_CSG1_PC_PSWV_Msk (0x3fUL) /*!< HRPWM0_CSG1 PC: PSWV (Bitfield-Mask: 0x3f) */ + +/* ------------------------------ HRPWM0_CSG1_DSV1 ------------------------------ */ +#define HRPWM0_CSG1_DSV1_DSV1_Pos (0UL) /*!< HRPWM0_CSG1 DSV1: DSV1 (Bit 0) */ +#define HRPWM0_CSG1_DSV1_DSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG1 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------ HRPWM0_CSG1_DSV2 ------------------------------ */ +#define HRPWM0_CSG1_DSV2_DSV2_Pos (0UL) /*!< HRPWM0_CSG1 DSV2: DSV2 (Bit 0) */ +#define HRPWM0_CSG1_DSV2_DSV2_Msk (0x3ffUL) /*!< HRPWM0_CSG1 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------ HRPWM0_CSG1_SDSV1 ----------------------------- */ +#define HRPWM0_CSG1_SDSV1_SDSV1_Pos (0UL) /*!< HRPWM0_CSG1 SDSV1: SDSV1 (Bit 0) */ +#define HRPWM0_CSG1_SDSV1_SDSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG1 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------- HRPWM0_CSG1_SPC ------------------------------ */ +#define HRPWM0_CSG1_SPC_SPSWV_Pos (0UL) /*!< HRPWM0_CSG1 SPC: SPSWV (Bit 0) */ +#define HRPWM0_CSG1_SPC_SPSWV_Msk (0x3fUL) /*!< HRPWM0_CSG1 SPC: SPSWV (Bitfield-Mask: 0x3f) */ + +/* ------------------------------- HRPWM0_CSG1_CC ------------------------------- */ +#define HRPWM0_CSG1_CC_IBS_Pos (0UL) /*!< HRPWM0_CSG1 CC: IBS (Bit 0) */ +#define HRPWM0_CSG1_CC_IBS_Msk (0xfUL) /*!< HRPWM0_CSG1 CC: IBS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_CC_IMCS_Pos (8UL) /*!< HRPWM0_CSG1 CC: IMCS (Bit 8) */ +#define HRPWM0_CSG1_CC_IMCS_Msk (0x100UL) /*!< HRPWM0_CSG1 CC: IMCS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_CC_IMCC_Pos (9UL) /*!< HRPWM0_CSG1 CC: IMCC (Bit 9) */ +#define HRPWM0_CSG1_CC_IMCC_Msk (0x600UL) /*!< HRPWM0_CSG1 CC: IMCC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_CC_ESE_Pos (11UL) /*!< HRPWM0_CSG1 CC: ESE (Bit 11) */ +#define HRPWM0_CSG1_CC_ESE_Msk (0x800UL) /*!< HRPWM0_CSG1 CC: ESE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_CC_OIE_Pos (12UL) /*!< HRPWM0_CSG1 CC: OIE (Bit 12) */ +#define HRPWM0_CSG1_CC_OIE_Msk (0x1000UL) /*!< HRPWM0_CSG1 CC: OIE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_CC_OSE_Pos (13UL) /*!< HRPWM0_CSG1 CC: OSE (Bit 13) */ +#define HRPWM0_CSG1_CC_OSE_Msk (0x2000UL) /*!< HRPWM0_CSG1 CC: OSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_CC_BLMC_Pos (14UL) /*!< HRPWM0_CSG1 CC: BLMC (Bit 14) */ +#define HRPWM0_CSG1_CC_BLMC_Msk (0xc000UL) /*!< HRPWM0_CSG1 CC: BLMC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_CC_EBE_Pos (16UL) /*!< HRPWM0_CSG1 CC: EBE (Bit 16) */ +#define HRPWM0_CSG1_CC_EBE_Msk (0x10000UL) /*!< HRPWM0_CSG1 CC: EBE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_CC_COFE_Pos (17UL) /*!< HRPWM0_CSG1 CC: COFE (Bit 17) */ +#define HRPWM0_CSG1_CC_COFE_Msk (0x20000UL) /*!< HRPWM0_CSG1 CC: COFE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_CC_COFM_Pos (18UL) /*!< HRPWM0_CSG1 CC: COFM (Bit 18) */ +#define HRPWM0_CSG1_CC_COFM_Msk (0x3c0000UL) /*!< HRPWM0_CSG1 CC: COFM (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_CC_COFC_Pos (24UL) /*!< HRPWM0_CSG1 CC: COFC (Bit 24) */ +#define HRPWM0_CSG1_CC_COFC_Msk (0x3000000UL) /*!< HRPWM0_CSG1 CC: COFC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG1_PLC ------------------------------ */ +#define HRPWM0_CSG1_PLC_IPLS_Pos (0UL) /*!< HRPWM0_CSG1 PLC: IPLS (Bit 0) */ +#define HRPWM0_CSG1_PLC_IPLS_Msk (0xfUL) /*!< HRPWM0_CSG1 PLC: IPLS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG1_PLC_PLCL_Pos (8UL) /*!< HRPWM0_CSG1 PLC: PLCL (Bit 8) */ +#define HRPWM0_CSG1_PLC_PLCL_Msk (0x300UL) /*!< HRPWM0_CSG1 PLC: PLCL (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_PLC_PSL_Pos (10UL) /*!< HRPWM0_CSG1 PLC: PSL (Bit 10) */ +#define HRPWM0_CSG1_PLC_PSL_Msk (0x400UL) /*!< HRPWM0_CSG1 PLC: PSL (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_PLC_PLSW_Pos (11UL) /*!< HRPWM0_CSG1 PLC: PLSW (Bit 11) */ +#define HRPWM0_CSG1_PLC_PLSW_Msk (0x800UL) /*!< HRPWM0_CSG1 PLC: PLSW (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_PLC_PLEC_Pos (12UL) /*!< HRPWM0_CSG1 PLC: PLEC (Bit 12) */ +#define HRPWM0_CSG1_PLC_PLEC_Msk (0x3000UL) /*!< HRPWM0_CSG1 PLC: PLEC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_PLC_PLXC_Pos (14UL) /*!< HRPWM0_CSG1 PLC: PLXC (Bit 14) */ +#define HRPWM0_CSG1_PLC_PLXC_Msk (0xc000UL) /*!< HRPWM0_CSG1 PLC: PLXC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG1_BLV ------------------------------ */ +#define HRPWM0_CSG1_BLV_BLV_Pos (0UL) /*!< HRPWM0_CSG1 BLV: BLV (Bit 0) */ +#define HRPWM0_CSG1_BLV_BLV_Msk (0xffUL) /*!< HRPWM0_CSG1 BLV: BLV (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_CSG1_SRE ------------------------------ */ +#define HRPWM0_CSG1_SRE_VLS1E_Pos (0UL) /*!< HRPWM0_CSG1 SRE: VLS1E (Bit 0) */ +#define HRPWM0_CSG1_SRE_VLS1E_Msk (0x1UL) /*!< HRPWM0_CSG1 SRE: VLS1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_VLS2E_Pos (1UL) /*!< HRPWM0_CSG1 SRE: VLS2E (Bit 1) */ +#define HRPWM0_CSG1_SRE_VLS2E_Msk (0x2UL) /*!< HRPWM0_CSG1 SRE: VLS2E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_TRGSE_Pos (2UL) /*!< HRPWM0_CSG1 SRE: TRGSE (Bit 2) */ +#define HRPWM0_CSG1_SRE_TRGSE_Msk (0x4UL) /*!< HRPWM0_CSG1 SRE: TRGSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_STRSE_Pos (3UL) /*!< HRPWM0_CSG1 SRE: STRSE (Bit 3) */ +#define HRPWM0_CSG1_SRE_STRSE_Msk (0x8UL) /*!< HRPWM0_CSG1 SRE: STRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_STPSE_Pos (4UL) /*!< HRPWM0_CSG1 SRE: STPSE (Bit 4) */ +#define HRPWM0_CSG1_SRE_STPSE_Msk (0x10UL) /*!< HRPWM0_CSG1 SRE: STPSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_STDE_Pos (5UL) /*!< HRPWM0_CSG1 SRE: STDE (Bit 5) */ +#define HRPWM0_CSG1_SRE_STDE_Msk (0x20UL) /*!< HRPWM0_CSG1 SRE: STDE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_CRSE_Pos (6UL) /*!< HRPWM0_CSG1 SRE: CRSE (Bit 6) */ +#define HRPWM0_CSG1_SRE_CRSE_Msk (0x40UL) /*!< HRPWM0_CSG1 SRE: CRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_CFSE_Pos (7UL) /*!< HRPWM0_CSG1 SRE: CFSE (Bit 7) */ +#define HRPWM0_CSG1_SRE_CFSE_Msk (0x80UL) /*!< HRPWM0_CSG1 SRE: CFSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SRE_CSEE_Pos (8UL) /*!< HRPWM0_CSG1 SRE: CSEE (Bit 8) */ +#define HRPWM0_CSG1_SRE_CSEE_Msk (0x100UL) /*!< HRPWM0_CSG1 SRE: CSEE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG1_SRS ------------------------------ */ +#define HRPWM0_CSG1_SRS_VLS1S_Pos (0UL) /*!< HRPWM0_CSG1 SRS: VLS1S (Bit 0) */ +#define HRPWM0_CSG1_SRS_VLS1S_Msk (0x3UL) /*!< HRPWM0_CSG1 SRS: VLS1S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SRS_VLS2S_Pos (2UL) /*!< HRPWM0_CSG1 SRS: VLS2S (Bit 2) */ +#define HRPWM0_CSG1_SRS_VLS2S_Msk (0xcUL) /*!< HRPWM0_CSG1 SRS: VLS2S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SRS_TRLS_Pos (4UL) /*!< HRPWM0_CSG1 SRS: TRLS (Bit 4) */ +#define HRPWM0_CSG1_SRS_TRLS_Msk (0x30UL) /*!< HRPWM0_CSG1 SRS: TRLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SRS_SSLS_Pos (6UL) /*!< HRPWM0_CSG1 SRS: SSLS (Bit 6) */ +#define HRPWM0_CSG1_SRS_SSLS_Msk (0xc0UL) /*!< HRPWM0_CSG1 SRS: SSLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SRS_STLS_Pos (8UL) /*!< HRPWM0_CSG1 SRS: STLS (Bit 8) */ +#define HRPWM0_CSG1_SRS_STLS_Msk (0x300UL) /*!< HRPWM0_CSG1 SRS: STLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SRS_CRFLS_Pos (10UL) /*!< HRPWM0_CSG1 SRS: CRFLS (Bit 10) */ +#define HRPWM0_CSG1_SRS_CRFLS_Msk (0xc00UL) /*!< HRPWM0_CSG1 SRS: CRFLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG1_SRS_CSLS_Pos (12UL) /*!< HRPWM0_CSG1 SRS: CSLS (Bit 12) */ +#define HRPWM0_CSG1_SRS_CSLS_Msk (0x3000UL) /*!< HRPWM0_CSG1 SRS: CSLS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG1_SWS ------------------------------ */ +#define HRPWM0_CSG1_SWS_SVLS1_Pos (0UL) /*!< HRPWM0_CSG1 SWS: SVLS1 (Bit 0) */ +#define HRPWM0_CSG1_SWS_SVLS1_Msk (0x1UL) /*!< HRPWM0_CSG1 SWS: SVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_SVLS2_Pos (1UL) /*!< HRPWM0_CSG1 SWS: SVLS2 (Bit 1) */ +#define HRPWM0_CSG1_SWS_SVLS2_Msk (0x2UL) /*!< HRPWM0_CSG1 SWS: SVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_STRGS_Pos (2UL) /*!< HRPWM0_CSG1 SWS: STRGS (Bit 2) */ +#define HRPWM0_CSG1_SWS_STRGS_Msk (0x4UL) /*!< HRPWM0_CSG1 SWS: STRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_SSTRS_Pos (3UL) /*!< HRPWM0_CSG1 SWS: SSTRS (Bit 3) */ +#define HRPWM0_CSG1_SWS_SSTRS_Msk (0x8UL) /*!< HRPWM0_CSG1 SWS: SSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_SSTPS_Pos (4UL) /*!< HRPWM0_CSG1 SWS: SSTPS (Bit 4) */ +#define HRPWM0_CSG1_SWS_SSTPS_Msk (0x10UL) /*!< HRPWM0_CSG1 SWS: SSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_SSTD_Pos (5UL) /*!< HRPWM0_CSG1 SWS: SSTD (Bit 5) */ +#define HRPWM0_CSG1_SWS_SSTD_Msk (0x20UL) /*!< HRPWM0_CSG1 SWS: SSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_SCRS_Pos (6UL) /*!< HRPWM0_CSG1 SWS: SCRS (Bit 6) */ +#define HRPWM0_CSG1_SWS_SCRS_Msk (0x40UL) /*!< HRPWM0_CSG1 SWS: SCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_SCFS_Pos (7UL) /*!< HRPWM0_CSG1 SWS: SCFS (Bit 7) */ +#define HRPWM0_CSG1_SWS_SCFS_Msk (0x80UL) /*!< HRPWM0_CSG1 SWS: SCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWS_SCSS_Pos (8UL) /*!< HRPWM0_CSG1 SWS: SCSS (Bit 8) */ +#define HRPWM0_CSG1_SWS_SCSS_Msk (0x100UL) /*!< HRPWM0_CSG1 SWS: SCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG1_SWC ------------------------------ */ +#define HRPWM0_CSG1_SWC_CVLS1_Pos (0UL) /*!< HRPWM0_CSG1 SWC: CVLS1 (Bit 0) */ +#define HRPWM0_CSG1_SWC_CVLS1_Msk (0x1UL) /*!< HRPWM0_CSG1 SWC: CVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CVLS2_Pos (1UL) /*!< HRPWM0_CSG1 SWC: CVLS2 (Bit 1) */ +#define HRPWM0_CSG1_SWC_CVLS2_Msk (0x2UL) /*!< HRPWM0_CSG1 SWC: CVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CTRGS_Pos (2UL) /*!< HRPWM0_CSG1 SWC: CTRGS (Bit 2) */ +#define HRPWM0_CSG1_SWC_CTRGS_Msk (0x4UL) /*!< HRPWM0_CSG1 SWC: CTRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CSTRS_Pos (3UL) /*!< HRPWM0_CSG1 SWC: CSTRS (Bit 3) */ +#define HRPWM0_CSG1_SWC_CSTRS_Msk (0x8UL) /*!< HRPWM0_CSG1 SWC: CSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CSTPS_Pos (4UL) /*!< HRPWM0_CSG1 SWC: CSTPS (Bit 4) */ +#define HRPWM0_CSG1_SWC_CSTPS_Msk (0x10UL) /*!< HRPWM0_CSG1 SWC: CSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CSTD_Pos (5UL) /*!< HRPWM0_CSG1 SWC: CSTD (Bit 5) */ +#define HRPWM0_CSG1_SWC_CSTD_Msk (0x20UL) /*!< HRPWM0_CSG1 SWC: CSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CCRS_Pos (6UL) /*!< HRPWM0_CSG1 SWC: CCRS (Bit 6) */ +#define HRPWM0_CSG1_SWC_CCRS_Msk (0x40UL) /*!< HRPWM0_CSG1 SWC: CCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CCFS_Pos (7UL) /*!< HRPWM0_CSG1 SWC: CCFS (Bit 7) */ +#define HRPWM0_CSG1_SWC_CCFS_Msk (0x80UL) /*!< HRPWM0_CSG1 SWC: CCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_SWC_CCSS_Pos (8UL) /*!< HRPWM0_CSG1 SWC: CCSS (Bit 8) */ +#define HRPWM0_CSG1_SWC_CCSS_Msk (0x100UL) /*!< HRPWM0_CSG1 SWC: CCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_CSG1_ISTAT ----------------------------- */ +#define HRPWM0_CSG1_ISTAT_VLS1S_Pos (0UL) /*!< HRPWM0_CSG1 ISTAT: VLS1S (Bit 0) */ +#define HRPWM0_CSG1_ISTAT_VLS1S_Msk (0x1UL) /*!< HRPWM0_CSG1 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_VLS2S_Pos (1UL) /*!< HRPWM0_CSG1 ISTAT: VLS2S (Bit 1) */ +#define HRPWM0_CSG1_ISTAT_VLS2S_Msk (0x2UL) /*!< HRPWM0_CSG1 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_TRGSS_Pos (2UL) /*!< HRPWM0_CSG1 ISTAT: TRGSS (Bit 2) */ +#define HRPWM0_CSG1_ISTAT_TRGSS_Msk (0x4UL) /*!< HRPWM0_CSG1 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_STRSS_Pos (3UL) /*!< HRPWM0_CSG1 ISTAT: STRSS (Bit 3) */ +#define HRPWM0_CSG1_ISTAT_STRSS_Msk (0x8UL) /*!< HRPWM0_CSG1 ISTAT: STRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_STPSS_Pos (4UL) /*!< HRPWM0_CSG1 ISTAT: STPSS (Bit 4) */ +#define HRPWM0_CSG1_ISTAT_STPSS_Msk (0x10UL) /*!< HRPWM0_CSG1 ISTAT: STPSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_STDS_Pos (5UL) /*!< HRPWM0_CSG1 ISTAT: STDS (Bit 5) */ +#define HRPWM0_CSG1_ISTAT_STDS_Msk (0x20UL) /*!< HRPWM0_CSG1 ISTAT: STDS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_CRSS_Pos (6UL) /*!< HRPWM0_CSG1 ISTAT: CRSS (Bit 6) */ +#define HRPWM0_CSG1_ISTAT_CRSS_Msk (0x40UL) /*!< HRPWM0_CSG1 ISTAT: CRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_CFSS_Pos (7UL) /*!< HRPWM0_CSG1 ISTAT: CFSS (Bit 7) */ +#define HRPWM0_CSG1_ISTAT_CFSS_Msk (0x80UL) /*!< HRPWM0_CSG1 ISTAT: CFSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG1_ISTAT_CSES_Pos (8UL) /*!< HRPWM0_CSG1 ISTAT: CSES (Bit 8) */ +#define HRPWM0_CSG1_ISTAT_CSES_Msk (0x100UL) /*!< HRPWM0_CSG1 ISTAT: CSES (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0_CSG2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_CSG2_DCI ------------------------------ */ +#define HRPWM0_CSG2_DCI_SVIS_Pos (0UL) /*!< HRPWM0_CSG2 DCI: SVIS (Bit 0) */ +#define HRPWM0_CSG2_DCI_SVIS_Msk (0xfUL) /*!< HRPWM0_CSG2 DCI: SVIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_DCI_STRIS_Pos (4UL) /*!< HRPWM0_CSG2 DCI: STRIS (Bit 4) */ +#define HRPWM0_CSG2_DCI_STRIS_Msk (0xf0UL) /*!< HRPWM0_CSG2 DCI: STRIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_DCI_STPIS_Pos (8UL) /*!< HRPWM0_CSG2 DCI: STPIS (Bit 8) */ +#define HRPWM0_CSG2_DCI_STPIS_Msk (0xf00UL) /*!< HRPWM0_CSG2 DCI: STPIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_DCI_TRGIS_Pos (12UL) /*!< HRPWM0_CSG2 DCI: TRGIS (Bit 12) */ +#define HRPWM0_CSG2_DCI_TRGIS_Msk (0xf000UL) /*!< HRPWM0_CSG2 DCI: TRGIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_DCI_STIS_Pos (16UL) /*!< HRPWM0_CSG2 DCI: STIS (Bit 16) */ +#define HRPWM0_CSG2_DCI_STIS_Msk (0xf0000UL) /*!< HRPWM0_CSG2 DCI: STIS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_DCI_SCS_Pos (20UL) /*!< HRPWM0_CSG2 DCI: SCS (Bit 20) */ +#define HRPWM0_CSG2_DCI_SCS_Msk (0x300000UL) /*!< HRPWM0_CSG2 DCI: SCS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG2_IES ------------------------------ */ +#define HRPWM0_CSG2_IES_SVLS_Pos (0UL) /*!< HRPWM0_CSG2 IES: SVLS (Bit 0) */ +#define HRPWM0_CSG2_IES_SVLS_Msk (0x3UL) /*!< HRPWM0_CSG2 IES: SVLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_IES_STRES_Pos (2UL) /*!< HRPWM0_CSG2 IES: STRES (Bit 2) */ +#define HRPWM0_CSG2_IES_STRES_Msk (0xcUL) /*!< HRPWM0_CSG2 IES: STRES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_IES_STPES_Pos (4UL) /*!< HRPWM0_CSG2 IES: STPES (Bit 4) */ +#define HRPWM0_CSG2_IES_STPES_Msk (0x30UL) /*!< HRPWM0_CSG2 IES: STPES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_IES_TRGES_Pos (6UL) /*!< HRPWM0_CSG2 IES: TRGES (Bit 6) */ +#define HRPWM0_CSG2_IES_TRGES_Msk (0xc0UL) /*!< HRPWM0_CSG2 IES: TRGES (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_IES_STES_Pos (8UL) /*!< HRPWM0_CSG2 IES: STES (Bit 8) */ +#define HRPWM0_CSG2_IES_STES_Msk (0x300UL) /*!< HRPWM0_CSG2 IES: STES (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG2_SC ------------------------------- */ +#define HRPWM0_CSG2_SC_PSRM_Pos (0UL) /*!< HRPWM0_CSG2 SC: PSRM (Bit 0) */ +#define HRPWM0_CSG2_SC_PSRM_Msk (0x3UL) /*!< HRPWM0_CSG2 SC: PSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_PSTM_Pos (2UL) /*!< HRPWM0_CSG2 SC: PSTM (Bit 2) */ +#define HRPWM0_CSG2_SC_PSTM_Msk (0xcUL) /*!< HRPWM0_CSG2 SC: PSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_FPD_Pos (4UL) /*!< HRPWM0_CSG2 SC: FPD (Bit 4) */ +#define HRPWM0_CSG2_SC_FPD_Msk (0x10UL) /*!< HRPWM0_CSG2 SC: FPD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SC_PSV_Pos (5UL) /*!< HRPWM0_CSG2 SC: PSV (Bit 5) */ +#define HRPWM0_CSG2_SC_PSV_Msk (0x60UL) /*!< HRPWM0_CSG2 SC: PSV (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_SCM_Pos (8UL) /*!< HRPWM0_CSG2 SC: SCM (Bit 8) */ +#define HRPWM0_CSG2_SC_SCM_Msk (0x300UL) /*!< HRPWM0_CSG2 SC: SCM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_SSRM_Pos (10UL) /*!< HRPWM0_CSG2 SC: SSRM (Bit 10) */ +#define HRPWM0_CSG2_SC_SSRM_Msk (0xc00UL) /*!< HRPWM0_CSG2 SC: SSRM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_SSTM_Pos (12UL) /*!< HRPWM0_CSG2 SC: SSTM (Bit 12) */ +#define HRPWM0_CSG2_SC_SSTM_Msk (0x3000UL) /*!< HRPWM0_CSG2 SC: SSTM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_SVSC_Pos (14UL) /*!< HRPWM0_CSG2 SC: SVSC (Bit 14) */ +#define HRPWM0_CSG2_SC_SVSC_Msk (0xc000UL) /*!< HRPWM0_CSG2 SC: SVSC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_SWSM_Pos (16UL) /*!< HRPWM0_CSG2 SC: SWSM (Bit 16) */ +#define HRPWM0_CSG2_SC_SWSM_Msk (0x30000UL) /*!< HRPWM0_CSG2 SC: SWSM (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_GCFG_Pos (18UL) /*!< HRPWM0_CSG2 SC: GCFG (Bit 18) */ +#define HRPWM0_CSG2_SC_GCFG_Msk (0xc0000UL) /*!< HRPWM0_CSG2 SC: GCFG (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SC_IST_Pos (20UL) /*!< HRPWM0_CSG2 SC: IST (Bit 20) */ +#define HRPWM0_CSG2_SC_IST_Msk (0x100000UL) /*!< HRPWM0_CSG2 SC: IST (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SC_PSE_Pos (21UL) /*!< HRPWM0_CSG2 SC: PSE (Bit 21) */ +#define HRPWM0_CSG2_SC_PSE_Msk (0x200000UL) /*!< HRPWM0_CSG2 SC: PSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SC_PSWM_Pos (24UL) /*!< HRPWM0_CSG2 SC: PSWM (Bit 24) */ +#define HRPWM0_CSG2_SC_PSWM_Msk (0x3000000UL) /*!< HRPWM0_CSG2 SC: PSWM (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG2_PC ------------------------------- */ +#define HRPWM0_CSG2_PC_PSWV_Pos (0UL) /*!< HRPWM0_CSG2 PC: PSWV (Bit 0) */ +#define HRPWM0_CSG2_PC_PSWV_Msk (0x3fUL) /*!< HRPWM0_CSG2 PC: PSWV (Bitfield-Mask: 0x3f) */ + +/* ------------------------------ HRPWM0_CSG2_DSV1 ------------------------------ */ +#define HRPWM0_CSG2_DSV1_DSV1_Pos (0UL) /*!< HRPWM0_CSG2 DSV1: DSV1 (Bit 0) */ +#define HRPWM0_CSG2_DSV1_DSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG2 DSV1: DSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------ HRPWM0_CSG2_DSV2 ------------------------------ */ +#define HRPWM0_CSG2_DSV2_DSV2_Pos (0UL) /*!< HRPWM0_CSG2 DSV2: DSV2 (Bit 0) */ +#define HRPWM0_CSG2_DSV2_DSV2_Msk (0x3ffUL) /*!< HRPWM0_CSG2 DSV2: DSV2 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------ HRPWM0_CSG2_SDSV1 ----------------------------- */ +#define HRPWM0_CSG2_SDSV1_SDSV1_Pos (0UL) /*!< HRPWM0_CSG2 SDSV1: SDSV1 (Bit 0) */ +#define HRPWM0_CSG2_SDSV1_SDSV1_Msk (0x3ffUL) /*!< HRPWM0_CSG2 SDSV1: SDSV1 (Bitfield-Mask: 0x3ff) */ + +/* ------------------------------- HRPWM0_CSG2_SPC ------------------------------ */ +#define HRPWM0_CSG2_SPC_SPSWV_Pos (0UL) /*!< HRPWM0_CSG2 SPC: SPSWV (Bit 0) */ +#define HRPWM0_CSG2_SPC_SPSWV_Msk (0x3fUL) /*!< HRPWM0_CSG2 SPC: SPSWV (Bitfield-Mask: 0x3f) */ + +/* ------------------------------- HRPWM0_CSG2_CC ------------------------------- */ +#define HRPWM0_CSG2_CC_IBS_Pos (0UL) /*!< HRPWM0_CSG2 CC: IBS (Bit 0) */ +#define HRPWM0_CSG2_CC_IBS_Msk (0xfUL) /*!< HRPWM0_CSG2 CC: IBS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_CC_IMCS_Pos (8UL) /*!< HRPWM0_CSG2 CC: IMCS (Bit 8) */ +#define HRPWM0_CSG2_CC_IMCS_Msk (0x100UL) /*!< HRPWM0_CSG2 CC: IMCS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_CC_IMCC_Pos (9UL) /*!< HRPWM0_CSG2 CC: IMCC (Bit 9) */ +#define HRPWM0_CSG2_CC_IMCC_Msk (0x600UL) /*!< HRPWM0_CSG2 CC: IMCC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_CC_ESE_Pos (11UL) /*!< HRPWM0_CSG2 CC: ESE (Bit 11) */ +#define HRPWM0_CSG2_CC_ESE_Msk (0x800UL) /*!< HRPWM0_CSG2 CC: ESE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_CC_OIE_Pos (12UL) /*!< HRPWM0_CSG2 CC: OIE (Bit 12) */ +#define HRPWM0_CSG2_CC_OIE_Msk (0x1000UL) /*!< HRPWM0_CSG2 CC: OIE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_CC_OSE_Pos (13UL) /*!< HRPWM0_CSG2 CC: OSE (Bit 13) */ +#define HRPWM0_CSG2_CC_OSE_Msk (0x2000UL) /*!< HRPWM0_CSG2 CC: OSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_CC_BLMC_Pos (14UL) /*!< HRPWM0_CSG2 CC: BLMC (Bit 14) */ +#define HRPWM0_CSG2_CC_BLMC_Msk (0xc000UL) /*!< HRPWM0_CSG2 CC: BLMC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_CC_EBE_Pos (16UL) /*!< HRPWM0_CSG2 CC: EBE (Bit 16) */ +#define HRPWM0_CSG2_CC_EBE_Msk (0x10000UL) /*!< HRPWM0_CSG2 CC: EBE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_CC_COFE_Pos (17UL) /*!< HRPWM0_CSG2 CC: COFE (Bit 17) */ +#define HRPWM0_CSG2_CC_COFE_Msk (0x20000UL) /*!< HRPWM0_CSG2 CC: COFE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_CC_COFM_Pos (18UL) /*!< HRPWM0_CSG2 CC: COFM (Bit 18) */ +#define HRPWM0_CSG2_CC_COFM_Msk (0x3c0000UL) /*!< HRPWM0_CSG2 CC: COFM (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_CC_COFC_Pos (24UL) /*!< HRPWM0_CSG2 CC: COFC (Bit 24) */ +#define HRPWM0_CSG2_CC_COFC_Msk (0x3000000UL) /*!< HRPWM0_CSG2 CC: COFC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG2_PLC ------------------------------ */ +#define HRPWM0_CSG2_PLC_IPLS_Pos (0UL) /*!< HRPWM0_CSG2 PLC: IPLS (Bit 0) */ +#define HRPWM0_CSG2_PLC_IPLS_Msk (0xfUL) /*!< HRPWM0_CSG2 PLC: IPLS (Bitfield-Mask: 0x0f) */ +#define HRPWM0_CSG2_PLC_PLCL_Pos (8UL) /*!< HRPWM0_CSG2 PLC: PLCL (Bit 8) */ +#define HRPWM0_CSG2_PLC_PLCL_Msk (0x300UL) /*!< HRPWM0_CSG2 PLC: PLCL (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_PLC_PSL_Pos (10UL) /*!< HRPWM0_CSG2 PLC: PSL (Bit 10) */ +#define HRPWM0_CSG2_PLC_PSL_Msk (0x400UL) /*!< HRPWM0_CSG2 PLC: PSL (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_PLC_PLSW_Pos (11UL) /*!< HRPWM0_CSG2 PLC: PLSW (Bit 11) */ +#define HRPWM0_CSG2_PLC_PLSW_Msk (0x800UL) /*!< HRPWM0_CSG2 PLC: PLSW (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_PLC_PLEC_Pos (12UL) /*!< HRPWM0_CSG2 PLC: PLEC (Bit 12) */ +#define HRPWM0_CSG2_PLC_PLEC_Msk (0x3000UL) /*!< HRPWM0_CSG2 PLC: PLEC (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_PLC_PLXC_Pos (14UL) /*!< HRPWM0_CSG2 PLC: PLXC (Bit 14) */ +#define HRPWM0_CSG2_PLC_PLXC_Msk (0xc000UL) /*!< HRPWM0_CSG2 PLC: PLXC (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG2_BLV ------------------------------ */ +#define HRPWM0_CSG2_BLV_BLV_Pos (0UL) /*!< HRPWM0_CSG2 BLV: BLV (Bit 0) */ +#define HRPWM0_CSG2_BLV_BLV_Msk (0xffUL) /*!< HRPWM0_CSG2 BLV: BLV (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_CSG2_SRE ------------------------------ */ +#define HRPWM0_CSG2_SRE_VLS1E_Pos (0UL) /*!< HRPWM0_CSG2 SRE: VLS1E (Bit 0) */ +#define HRPWM0_CSG2_SRE_VLS1E_Msk (0x1UL) /*!< HRPWM0_CSG2 SRE: VLS1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_VLS2E_Pos (1UL) /*!< HRPWM0_CSG2 SRE: VLS2E (Bit 1) */ +#define HRPWM0_CSG2_SRE_VLS2E_Msk (0x2UL) /*!< HRPWM0_CSG2 SRE: VLS2E (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_TRGSE_Pos (2UL) /*!< HRPWM0_CSG2 SRE: TRGSE (Bit 2) */ +#define HRPWM0_CSG2_SRE_TRGSE_Msk (0x4UL) /*!< HRPWM0_CSG2 SRE: TRGSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_STRSE_Pos (3UL) /*!< HRPWM0_CSG2 SRE: STRSE (Bit 3) */ +#define HRPWM0_CSG2_SRE_STRSE_Msk (0x8UL) /*!< HRPWM0_CSG2 SRE: STRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_STPSE_Pos (4UL) /*!< HRPWM0_CSG2 SRE: STPSE (Bit 4) */ +#define HRPWM0_CSG2_SRE_STPSE_Msk (0x10UL) /*!< HRPWM0_CSG2 SRE: STPSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_STDE_Pos (5UL) /*!< HRPWM0_CSG2 SRE: STDE (Bit 5) */ +#define HRPWM0_CSG2_SRE_STDE_Msk (0x20UL) /*!< HRPWM0_CSG2 SRE: STDE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_CRSE_Pos (6UL) /*!< HRPWM0_CSG2 SRE: CRSE (Bit 6) */ +#define HRPWM0_CSG2_SRE_CRSE_Msk (0x40UL) /*!< HRPWM0_CSG2 SRE: CRSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_CFSE_Pos (7UL) /*!< HRPWM0_CSG2 SRE: CFSE (Bit 7) */ +#define HRPWM0_CSG2_SRE_CFSE_Msk (0x80UL) /*!< HRPWM0_CSG2 SRE: CFSE (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SRE_CSEE_Pos (8UL) /*!< HRPWM0_CSG2 SRE: CSEE (Bit 8) */ +#define HRPWM0_CSG2_SRE_CSEE_Msk (0x100UL) /*!< HRPWM0_CSG2 SRE: CSEE (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG2_SRS ------------------------------ */ +#define HRPWM0_CSG2_SRS_VLS1S_Pos (0UL) /*!< HRPWM0_CSG2 SRS: VLS1S (Bit 0) */ +#define HRPWM0_CSG2_SRS_VLS1S_Msk (0x3UL) /*!< HRPWM0_CSG2 SRS: VLS1S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SRS_VLS2S_Pos (2UL) /*!< HRPWM0_CSG2 SRS: VLS2S (Bit 2) */ +#define HRPWM0_CSG2_SRS_VLS2S_Msk (0xcUL) /*!< HRPWM0_CSG2 SRS: VLS2S (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SRS_TRLS_Pos (4UL) /*!< HRPWM0_CSG2 SRS: TRLS (Bit 4) */ +#define HRPWM0_CSG2_SRS_TRLS_Msk (0x30UL) /*!< HRPWM0_CSG2 SRS: TRLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SRS_SSLS_Pos (6UL) /*!< HRPWM0_CSG2 SRS: SSLS (Bit 6) */ +#define HRPWM0_CSG2_SRS_SSLS_Msk (0xc0UL) /*!< HRPWM0_CSG2 SRS: SSLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SRS_STLS_Pos (8UL) /*!< HRPWM0_CSG2 SRS: STLS (Bit 8) */ +#define HRPWM0_CSG2_SRS_STLS_Msk (0x300UL) /*!< HRPWM0_CSG2 SRS: STLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SRS_CRFLS_Pos (10UL) /*!< HRPWM0_CSG2 SRS: CRFLS (Bit 10) */ +#define HRPWM0_CSG2_SRS_CRFLS_Msk (0xc00UL) /*!< HRPWM0_CSG2 SRS: CRFLS (Bitfield-Mask: 0x03) */ +#define HRPWM0_CSG2_SRS_CSLS_Pos (12UL) /*!< HRPWM0_CSG2 SRS: CSLS (Bit 12) */ +#define HRPWM0_CSG2_SRS_CSLS_Msk (0x3000UL) /*!< HRPWM0_CSG2 SRS: CSLS (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_CSG2_SWS ------------------------------ */ +#define HRPWM0_CSG2_SWS_SVLS1_Pos (0UL) /*!< HRPWM0_CSG2 SWS: SVLS1 (Bit 0) */ +#define HRPWM0_CSG2_SWS_SVLS1_Msk (0x1UL) /*!< HRPWM0_CSG2 SWS: SVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_SVLS2_Pos (1UL) /*!< HRPWM0_CSG2 SWS: SVLS2 (Bit 1) */ +#define HRPWM0_CSG2_SWS_SVLS2_Msk (0x2UL) /*!< HRPWM0_CSG2 SWS: SVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_STRGS_Pos (2UL) /*!< HRPWM0_CSG2 SWS: STRGS (Bit 2) */ +#define HRPWM0_CSG2_SWS_STRGS_Msk (0x4UL) /*!< HRPWM0_CSG2 SWS: STRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_SSTRS_Pos (3UL) /*!< HRPWM0_CSG2 SWS: SSTRS (Bit 3) */ +#define HRPWM0_CSG2_SWS_SSTRS_Msk (0x8UL) /*!< HRPWM0_CSG2 SWS: SSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_SSTPS_Pos (4UL) /*!< HRPWM0_CSG2 SWS: SSTPS (Bit 4) */ +#define HRPWM0_CSG2_SWS_SSTPS_Msk (0x10UL) /*!< HRPWM0_CSG2 SWS: SSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_SSTD_Pos (5UL) /*!< HRPWM0_CSG2 SWS: SSTD (Bit 5) */ +#define HRPWM0_CSG2_SWS_SSTD_Msk (0x20UL) /*!< HRPWM0_CSG2 SWS: SSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_SCRS_Pos (6UL) /*!< HRPWM0_CSG2 SWS: SCRS (Bit 6) */ +#define HRPWM0_CSG2_SWS_SCRS_Msk (0x40UL) /*!< HRPWM0_CSG2 SWS: SCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_SCFS_Pos (7UL) /*!< HRPWM0_CSG2 SWS: SCFS (Bit 7) */ +#define HRPWM0_CSG2_SWS_SCFS_Msk (0x80UL) /*!< HRPWM0_CSG2 SWS: SCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWS_SCSS_Pos (8UL) /*!< HRPWM0_CSG2 SWS: SCSS (Bit 8) */ +#define HRPWM0_CSG2_SWS_SCSS_Msk (0x100UL) /*!< HRPWM0_CSG2 SWS: SCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_CSG2_SWC ------------------------------ */ +#define HRPWM0_CSG2_SWC_CVLS1_Pos (0UL) /*!< HRPWM0_CSG2 SWC: CVLS1 (Bit 0) */ +#define HRPWM0_CSG2_SWC_CVLS1_Msk (0x1UL) /*!< HRPWM0_CSG2 SWC: CVLS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CVLS2_Pos (1UL) /*!< HRPWM0_CSG2 SWC: CVLS2 (Bit 1) */ +#define HRPWM0_CSG2_SWC_CVLS2_Msk (0x2UL) /*!< HRPWM0_CSG2 SWC: CVLS2 (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CTRGS_Pos (2UL) /*!< HRPWM0_CSG2 SWC: CTRGS (Bit 2) */ +#define HRPWM0_CSG2_SWC_CTRGS_Msk (0x4UL) /*!< HRPWM0_CSG2 SWC: CTRGS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CSTRS_Pos (3UL) /*!< HRPWM0_CSG2 SWC: CSTRS (Bit 3) */ +#define HRPWM0_CSG2_SWC_CSTRS_Msk (0x8UL) /*!< HRPWM0_CSG2 SWC: CSTRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CSTPS_Pos (4UL) /*!< HRPWM0_CSG2 SWC: CSTPS (Bit 4) */ +#define HRPWM0_CSG2_SWC_CSTPS_Msk (0x10UL) /*!< HRPWM0_CSG2 SWC: CSTPS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CSTD_Pos (5UL) /*!< HRPWM0_CSG2 SWC: CSTD (Bit 5) */ +#define HRPWM0_CSG2_SWC_CSTD_Msk (0x20UL) /*!< HRPWM0_CSG2 SWC: CSTD (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CCRS_Pos (6UL) /*!< HRPWM0_CSG2 SWC: CCRS (Bit 6) */ +#define HRPWM0_CSG2_SWC_CCRS_Msk (0x40UL) /*!< HRPWM0_CSG2 SWC: CCRS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CCFS_Pos (7UL) /*!< HRPWM0_CSG2 SWC: CCFS (Bit 7) */ +#define HRPWM0_CSG2_SWC_CCFS_Msk (0x80UL) /*!< HRPWM0_CSG2 SWC: CCFS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_SWC_CCSS_Pos (8UL) /*!< HRPWM0_CSG2 SWC: CCSS (Bit 8) */ +#define HRPWM0_CSG2_SWC_CCSS_Msk (0x100UL) /*!< HRPWM0_CSG2 SWC: CCSS (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_CSG2_ISTAT ----------------------------- */ +#define HRPWM0_CSG2_ISTAT_VLS1S_Pos (0UL) /*!< HRPWM0_CSG2 ISTAT: VLS1S (Bit 0) */ +#define HRPWM0_CSG2_ISTAT_VLS1S_Msk (0x1UL) /*!< HRPWM0_CSG2 ISTAT: VLS1S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_VLS2S_Pos (1UL) /*!< HRPWM0_CSG2 ISTAT: VLS2S (Bit 1) */ +#define HRPWM0_CSG2_ISTAT_VLS2S_Msk (0x2UL) /*!< HRPWM0_CSG2 ISTAT: VLS2S (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_TRGSS_Pos (2UL) /*!< HRPWM0_CSG2 ISTAT: TRGSS (Bit 2) */ +#define HRPWM0_CSG2_ISTAT_TRGSS_Msk (0x4UL) /*!< HRPWM0_CSG2 ISTAT: TRGSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_STRSS_Pos (3UL) /*!< HRPWM0_CSG2 ISTAT: STRSS (Bit 3) */ +#define HRPWM0_CSG2_ISTAT_STRSS_Msk (0x8UL) /*!< HRPWM0_CSG2 ISTAT: STRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_STPSS_Pos (4UL) /*!< HRPWM0_CSG2 ISTAT: STPSS (Bit 4) */ +#define HRPWM0_CSG2_ISTAT_STPSS_Msk (0x10UL) /*!< HRPWM0_CSG2 ISTAT: STPSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_STDS_Pos (5UL) /*!< HRPWM0_CSG2 ISTAT: STDS (Bit 5) */ +#define HRPWM0_CSG2_ISTAT_STDS_Msk (0x20UL) /*!< HRPWM0_CSG2 ISTAT: STDS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_CRSS_Pos (6UL) /*!< HRPWM0_CSG2 ISTAT: CRSS (Bit 6) */ +#define HRPWM0_CSG2_ISTAT_CRSS_Msk (0x40UL) /*!< HRPWM0_CSG2 ISTAT: CRSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_CFSS_Pos (7UL) /*!< HRPWM0_CSG2 ISTAT: CFSS (Bit 7) */ +#define HRPWM0_CSG2_ISTAT_CFSS_Msk (0x80UL) /*!< HRPWM0_CSG2 ISTAT: CFSS (Bitfield-Mask: 0x01) */ +#define HRPWM0_CSG2_ISTAT_CSES_Pos (8UL) /*!< HRPWM0_CSG2 ISTAT: CSES (Bit 8) */ +#define HRPWM0_CSG2_ISTAT_CSES_Msk (0x100UL) /*!< HRPWM0_CSG2 ISTAT: CSES (Bitfield-Mask: 0x01) */ + + +/* ================================================================================ */ +/* ================ Group 'HRPWM0_HRC' Position & Mask ================ */ +/* ================================================================================ */ + + +/* -------------------------------- HRPWM0_HRC_GC ------------------------------- */ +#define HRPWM0_HRC_GC_HRM0_Pos (0UL) /*!< HRPWM0_HRC GC: HRM0 (Bit 0) */ +#define HRPWM0_HRC_GC_HRM0_Msk (0x3UL) /*!< HRPWM0_HRC GC: HRM0 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GC_HRM1_Pos (2UL) /*!< HRPWM0_HRC GC: HRM1 (Bit 2) */ +#define HRPWM0_HRC_GC_HRM1_Msk (0xcUL) /*!< HRPWM0_HRC GC: HRM1 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GC_DTE_Pos (8UL) /*!< HRPWM0_HRC GC: DTE (Bit 8) */ +#define HRPWM0_HRC_GC_DTE_Msk (0x100UL) /*!< HRPWM0_HRC GC: DTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_GC_TR0E_Pos (9UL) /*!< HRPWM0_HRC GC: TR0E (Bit 9) */ +#define HRPWM0_HRC_GC_TR0E_Msk (0x200UL) /*!< HRPWM0_HRC GC: TR0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_GC_TR1E_Pos (10UL) /*!< HRPWM0_HRC GC: TR1E (Bit 10) */ +#define HRPWM0_HRC_GC_TR1E_Msk (0x400UL) /*!< HRPWM0_HRC GC: TR1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_GC_STC_Pos (11UL) /*!< HRPWM0_HRC GC: STC (Bit 11) */ +#define HRPWM0_HRC_GC_STC_Msk (0x800UL) /*!< HRPWM0_HRC GC: STC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_GC_DSTC_Pos (12UL) /*!< HRPWM0_HRC GC: DSTC (Bit 12) */ +#define HRPWM0_HRC_GC_DSTC_Msk (0x1000UL) /*!< HRPWM0_HRC GC: DSTC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_GC_OCS0_Pos (13UL) /*!< HRPWM0_HRC GC: OCS0 (Bit 13) */ +#define HRPWM0_HRC_GC_OCS0_Msk (0x2000UL) /*!< HRPWM0_HRC GC: OCS0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_GC_OCS1_Pos (14UL) /*!< HRPWM0_HRC GC: OCS1 (Bit 14) */ +#define HRPWM0_HRC_GC_OCS1_Msk (0x4000UL) /*!< HRPWM0_HRC GC: OCS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_GC_DTUS_Pos (16UL) /*!< HRPWM0_HRC GC: DTUS (Bit 16) */ +#define HRPWM0_HRC_GC_DTUS_Msk (0x10000UL) /*!< HRPWM0_HRC GC: DTUS (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_HRC_PL ------------------------------- */ +#define HRPWM0_HRC_PL_PSL0_Pos (0UL) /*!< HRPWM0_HRC PL: PSL0 (Bit 0) */ +#define HRPWM0_HRC_PL_PSL0_Msk (0x1UL) /*!< HRPWM0_HRC PL: PSL0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_PL_PSL1_Pos (1UL) /*!< HRPWM0_HRC PL: PSL1 (Bit 1) */ +#define HRPWM0_HRC_PL_PSL1_Msk (0x2UL) /*!< HRPWM0_HRC PL: PSL1 (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC_GSEL ------------------------------ */ +#define HRPWM0_HRC_GSEL_C0SS_Pos (0UL) /*!< HRPWM0_HRC GSEL: C0SS (Bit 0) */ +#define HRPWM0_HRC_GSEL_C0SS_Msk (0x7UL) /*!< HRPWM0_HRC GSEL: C0SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC_GSEL_C0CS_Pos (3UL) /*!< HRPWM0_HRC GSEL: C0CS (Bit 3) */ +#define HRPWM0_HRC_GSEL_C0CS_Msk (0x38UL) /*!< HRPWM0_HRC GSEL: C0CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC_GSEL_S0M_Pos (6UL) /*!< HRPWM0_HRC GSEL: S0M (Bit 6) */ +#define HRPWM0_HRC_GSEL_S0M_Msk (0xc0UL) /*!< HRPWM0_HRC GSEL: S0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GSEL_C0M_Pos (8UL) /*!< HRPWM0_HRC GSEL: C0M (Bit 8) */ +#define HRPWM0_HRC_GSEL_C0M_Msk (0x300UL) /*!< HRPWM0_HRC GSEL: C0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GSEL_S0ES_Pos (10UL) /*!< HRPWM0_HRC GSEL: S0ES (Bit 10) */ +#define HRPWM0_HRC_GSEL_S0ES_Msk (0xc00UL) /*!< HRPWM0_HRC GSEL: S0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GSEL_C0ES_Pos (12UL) /*!< HRPWM0_HRC GSEL: C0ES (Bit 12) */ +#define HRPWM0_HRC_GSEL_C0ES_Msk (0x3000UL) /*!< HRPWM0_HRC GSEL: C0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GSEL_C1SS_Pos (16UL) /*!< HRPWM0_HRC GSEL: C1SS (Bit 16) */ +#define HRPWM0_HRC_GSEL_C1SS_Msk (0x70000UL) /*!< HRPWM0_HRC GSEL: C1SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC_GSEL_C1CS_Pos (19UL) /*!< HRPWM0_HRC GSEL: C1CS (Bit 19) */ +#define HRPWM0_HRC_GSEL_C1CS_Msk (0x380000UL) /*!< HRPWM0_HRC GSEL: C1CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC_GSEL_S1M_Pos (22UL) /*!< HRPWM0_HRC GSEL: S1M (Bit 22) */ +#define HRPWM0_HRC_GSEL_S1M_Msk (0xc00000UL) /*!< HRPWM0_HRC GSEL: S1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GSEL_C1M_Pos (24UL) /*!< HRPWM0_HRC GSEL: C1M (Bit 24) */ +#define HRPWM0_HRC_GSEL_C1M_Msk (0x3000000UL) /*!< HRPWM0_HRC GSEL: C1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GSEL_S1ES_Pos (26UL) /*!< HRPWM0_HRC GSEL: S1ES (Bit 26) */ +#define HRPWM0_HRC_GSEL_S1ES_Msk (0xc000000UL) /*!< HRPWM0_HRC GSEL: S1ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC_GSEL_C1ES_Pos (28UL) /*!< HRPWM0_HRC GSEL: C1ES (Bit 28) */ +#define HRPWM0_HRC_GSEL_C1ES_Msk (0x30000000UL) /*!< HRPWM0_HRC GSEL: C1ES (Bitfield-Mask: 0x03) */ + +/* ------------------------------- HRPWM0_HRC_TSEL ------------------------------ */ +#define HRPWM0_HRC_TSEL_TSEL0_Pos (0UL) /*!< HRPWM0_HRC TSEL: TSEL0 (Bit 0) */ +#define HRPWM0_HRC_TSEL_TSEL0_Msk (0x7UL) /*!< HRPWM0_HRC TSEL: TSEL0 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC_TSEL_TSEL1_Pos (3UL) /*!< HRPWM0_HRC TSEL: TSEL1 (Bit 3) */ +#define HRPWM0_HRC_TSEL_TSEL1_Msk (0x38UL) /*!< HRPWM0_HRC TSEL: TSEL1 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC_TSEL_TS0E_Pos (16UL) /*!< HRPWM0_HRC TSEL: TS0E (Bit 16) */ +#define HRPWM0_HRC_TSEL_TS0E_Msk (0x10000UL) /*!< HRPWM0_HRC TSEL: TS0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC_TSEL_TS1E_Pos (17UL) /*!< HRPWM0_HRC TSEL: TS1E (Bit 17) */ +#define HRPWM0_HRC_TSEL_TS1E_Msk (0x20000UL) /*!< HRPWM0_HRC TSEL: TS1E (Bitfield-Mask: 0x01) */ + +/* -------------------------------- HRPWM0_HRC_SC ------------------------------- */ +#define HRPWM0_HRC_SC_ST_Pos (0UL) /*!< HRPWM0_HRC SC: ST (Bit 0) */ +#define HRPWM0_HRC_SC_ST_Msk (0x1UL) /*!< HRPWM0_HRC SC: ST (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC_DCR ------------------------------- */ +#define HRPWM0_HRC_DCR_DTRV_Pos (0UL) /*!< HRPWM0_HRC DCR: DTRV (Bit 0) */ +#define HRPWM0_HRC_DCR_DTRV_Msk (0xffffUL) /*!< HRPWM0_HRC DCR: DTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC_DCF ------------------------------- */ +#define HRPWM0_HRC_DCF_DTFV_Pos (0UL) /*!< HRPWM0_HRC DCF: DTFV (Bit 0) */ +#define HRPWM0_HRC_DCF_DTFV_Msk (0xffffUL) /*!< HRPWM0_HRC DCF: DTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC_CR1 ------------------------------- */ +#define HRPWM0_HRC_CR1_CR1_Pos (0UL) /*!< HRPWM0_HRC CR1: CR1 (Bit 0) */ +#define HRPWM0_HRC_CR1_CR1_Msk (0xffUL) /*!< HRPWM0_HRC CR1: CR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC_CR2 ------------------------------- */ +#define HRPWM0_HRC_CR2_CR2_Pos (0UL) /*!< HRPWM0_HRC CR2: CR2 (Bit 0) */ +#define HRPWM0_HRC_CR2_CR2_Msk (0xffUL) /*!< HRPWM0_HRC CR2: CR2 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC_SSC ------------------------------- */ +#define HRPWM0_HRC_SSC_SST_Pos (0UL) /*!< HRPWM0_HRC SSC: SST (Bit 0) */ +#define HRPWM0_HRC_SSC_SST_Msk (0x1UL) /*!< HRPWM0_HRC SSC: SST (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC_SDCR ------------------------------ */ +#define HRPWM0_HRC_SDCR_SDTRV_Pos (0UL) /*!< HRPWM0_HRC SDCR: SDTRV (Bit 0) */ +#define HRPWM0_HRC_SDCR_SDTRV_Msk (0xffffUL) /*!< HRPWM0_HRC SDCR: SDTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC_SDCF ------------------------------ */ +#define HRPWM0_HRC_SDCF_SDTFV_Pos (0UL) /*!< HRPWM0_HRC SDCF: SDTFV (Bit 0) */ +#define HRPWM0_HRC_SDCF_SDTFV_Msk (0xffffUL) /*!< HRPWM0_HRC SDCF: SDTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC_SCR1 ------------------------------ */ +#define HRPWM0_HRC_SCR1_SCR1_Pos (0UL) /*!< HRPWM0_HRC SCR1: SCR1 (Bit 0) */ +#define HRPWM0_HRC_SCR1_SCR1_Msk (0xffUL) /*!< HRPWM0_HRC SCR1: SCR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC_SCR2 ------------------------------ */ +#define HRPWM0_HRC_SCR2_SCR2_Pos (0UL) /*!< HRPWM0_HRC SCR2: SCR2 (Bit 0) */ +#define HRPWM0_HRC_SCR2_SCR2_Msk (0xffUL) /*!< HRPWM0_HRC SCR2: SCR2 (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0_HRC0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_HRC0_GC ------------------------------- */ +#define HRPWM0_HRC0_GC_HRM0_Pos (0UL) /*!< HRPWM0_HRC0 GC: HRM0 (Bit 0) */ +#define HRPWM0_HRC0_GC_HRM0_Msk (0x3UL) /*!< HRPWM0_HRC0 GC: HRM0 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GC_HRM1_Pos (2UL) /*!< HRPWM0_HRC0 GC: HRM1 (Bit 2) */ +#define HRPWM0_HRC0_GC_HRM1_Msk (0xcUL) /*!< HRPWM0_HRC0 GC: HRM1 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GC_DTE_Pos (8UL) /*!< HRPWM0_HRC0 GC: DTE (Bit 8) */ +#define HRPWM0_HRC0_GC_DTE_Msk (0x100UL) /*!< HRPWM0_HRC0 GC: DTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_GC_TR0E_Pos (9UL) /*!< HRPWM0_HRC0 GC: TR0E (Bit 9) */ +#define HRPWM0_HRC0_GC_TR0E_Msk (0x200UL) /*!< HRPWM0_HRC0 GC: TR0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_GC_TR1E_Pos (10UL) /*!< HRPWM0_HRC0 GC: TR1E (Bit 10) */ +#define HRPWM0_HRC0_GC_TR1E_Msk (0x400UL) /*!< HRPWM0_HRC0 GC: TR1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_GC_STC_Pos (11UL) /*!< HRPWM0_HRC0 GC: STC (Bit 11) */ +#define HRPWM0_HRC0_GC_STC_Msk (0x800UL) /*!< HRPWM0_HRC0 GC: STC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_GC_DSTC_Pos (12UL) /*!< HRPWM0_HRC0 GC: DSTC (Bit 12) */ +#define HRPWM0_HRC0_GC_DSTC_Msk (0x1000UL) /*!< HRPWM0_HRC0 GC: DSTC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_GC_OCS0_Pos (13UL) /*!< HRPWM0_HRC0 GC: OCS0 (Bit 13) */ +#define HRPWM0_HRC0_GC_OCS0_Msk (0x2000UL) /*!< HRPWM0_HRC0 GC: OCS0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_GC_OCS1_Pos (14UL) /*!< HRPWM0_HRC0 GC: OCS1 (Bit 14) */ +#define HRPWM0_HRC0_GC_OCS1_Msk (0x4000UL) /*!< HRPWM0_HRC0 GC: OCS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_GC_DTUS_Pos (16UL) /*!< HRPWM0_HRC0 GC: DTUS (Bit 16) */ +#define HRPWM0_HRC0_GC_DTUS_Msk (0x10000UL) /*!< HRPWM0_HRC0 GC: DTUS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC0_PL ------------------------------- */ +#define HRPWM0_HRC0_PL_PSL0_Pos (0UL) /*!< HRPWM0_HRC0 PL: PSL0 (Bit 0) */ +#define HRPWM0_HRC0_PL_PSL0_Msk (0x1UL) /*!< HRPWM0_HRC0 PL: PSL0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_PL_PSL1_Pos (1UL) /*!< HRPWM0_HRC0 PL: PSL1 (Bit 1) */ +#define HRPWM0_HRC0_PL_PSL1_Msk (0x2UL) /*!< HRPWM0_HRC0 PL: PSL1 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC0_GSEL ------------------------------ */ +#define HRPWM0_HRC0_GSEL_C0SS_Pos (0UL) /*!< HRPWM0_HRC0 GSEL: C0SS (Bit 0) */ +#define HRPWM0_HRC0_GSEL_C0SS_Msk (0x7UL) /*!< HRPWM0_HRC0 GSEL: C0SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC0_GSEL_C0CS_Pos (3UL) /*!< HRPWM0_HRC0 GSEL: C0CS (Bit 3) */ +#define HRPWM0_HRC0_GSEL_C0CS_Msk (0x38UL) /*!< HRPWM0_HRC0 GSEL: C0CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC0_GSEL_S0M_Pos (6UL) /*!< HRPWM0_HRC0 GSEL: S0M (Bit 6) */ +#define HRPWM0_HRC0_GSEL_S0M_Msk (0xc0UL) /*!< HRPWM0_HRC0 GSEL: S0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GSEL_C0M_Pos (8UL) /*!< HRPWM0_HRC0 GSEL: C0M (Bit 8) */ +#define HRPWM0_HRC0_GSEL_C0M_Msk (0x300UL) /*!< HRPWM0_HRC0 GSEL: C0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GSEL_S0ES_Pos (10UL) /*!< HRPWM0_HRC0 GSEL: S0ES (Bit 10) */ +#define HRPWM0_HRC0_GSEL_S0ES_Msk (0xc00UL) /*!< HRPWM0_HRC0 GSEL: S0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GSEL_C0ES_Pos (12UL) /*!< HRPWM0_HRC0 GSEL: C0ES (Bit 12) */ +#define HRPWM0_HRC0_GSEL_C0ES_Msk (0x3000UL) /*!< HRPWM0_HRC0 GSEL: C0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GSEL_C1SS_Pos (16UL) /*!< HRPWM0_HRC0 GSEL: C1SS (Bit 16) */ +#define HRPWM0_HRC0_GSEL_C1SS_Msk (0x70000UL) /*!< HRPWM0_HRC0 GSEL: C1SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC0_GSEL_C1CS_Pos (19UL) /*!< HRPWM0_HRC0 GSEL: C1CS (Bit 19) */ +#define HRPWM0_HRC0_GSEL_C1CS_Msk (0x380000UL) /*!< HRPWM0_HRC0 GSEL: C1CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC0_GSEL_S1M_Pos (22UL) /*!< HRPWM0_HRC0 GSEL: S1M (Bit 22) */ +#define HRPWM0_HRC0_GSEL_S1M_Msk (0xc00000UL) /*!< HRPWM0_HRC0 GSEL: S1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GSEL_C1M_Pos (24UL) /*!< HRPWM0_HRC0 GSEL: C1M (Bit 24) */ +#define HRPWM0_HRC0_GSEL_C1M_Msk (0x3000000UL) /*!< HRPWM0_HRC0 GSEL: C1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GSEL_S1ES_Pos (26UL) /*!< HRPWM0_HRC0 GSEL: S1ES (Bit 26) */ +#define HRPWM0_HRC0_GSEL_S1ES_Msk (0xc000000UL) /*!< HRPWM0_HRC0 GSEL: S1ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC0_GSEL_C1ES_Pos (28UL) /*!< HRPWM0_HRC0 GSEL: C1ES (Bit 28) */ +#define HRPWM0_HRC0_GSEL_C1ES_Msk (0x30000000UL) /*!< HRPWM0_HRC0 GSEL: C1ES (Bitfield-Mask: 0x03) */ + +/* ------------------------------ HRPWM0_HRC0_TSEL ------------------------------ */ +#define HRPWM0_HRC0_TSEL_TSEL0_Pos (0UL) /*!< HRPWM0_HRC0 TSEL: TSEL0 (Bit 0) */ +#define HRPWM0_HRC0_TSEL_TSEL0_Msk (0x7UL) /*!< HRPWM0_HRC0 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC0_TSEL_TSEL1_Pos (3UL) /*!< HRPWM0_HRC0 TSEL: TSEL1 (Bit 3) */ +#define HRPWM0_HRC0_TSEL_TSEL1_Msk (0x38UL) /*!< HRPWM0_HRC0 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC0_TSEL_TS0E_Pos (16UL) /*!< HRPWM0_HRC0 TSEL: TS0E (Bit 16) */ +#define HRPWM0_HRC0_TSEL_TS0E_Msk (0x10000UL) /*!< HRPWM0_HRC0 TSEL: TS0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC0_TSEL_TS1E_Pos (17UL) /*!< HRPWM0_HRC0 TSEL: TS1E (Bit 17) */ +#define HRPWM0_HRC0_TSEL_TS1E_Msk (0x20000UL) /*!< HRPWM0_HRC0 TSEL: TS1E (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC0_SC ------------------------------- */ +#define HRPWM0_HRC0_SC_ST_Pos (0UL) /*!< HRPWM0_HRC0 SC: ST (Bit 0) */ +#define HRPWM0_HRC0_SC_ST_Msk (0x1UL) /*!< HRPWM0_HRC0 SC: ST (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC0_DCR ------------------------------ */ +#define HRPWM0_HRC0_DCR_DTRV_Pos (0UL) /*!< HRPWM0_HRC0 DCR: DTRV (Bit 0) */ +#define HRPWM0_HRC0_DCR_DTRV_Msk (0xffffUL) /*!< HRPWM0_HRC0 DCR: DTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC0_DCF ------------------------------ */ +#define HRPWM0_HRC0_DCF_DTFV_Pos (0UL) /*!< HRPWM0_HRC0 DCF: DTFV (Bit 0) */ +#define HRPWM0_HRC0_DCF_DTFV_Msk (0xffffUL) /*!< HRPWM0_HRC0 DCF: DTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC0_CR1 ------------------------------ */ +#define HRPWM0_HRC0_CR1_CR1_Pos (0UL) /*!< HRPWM0_HRC0 CR1: CR1 (Bit 0) */ +#define HRPWM0_HRC0_CR1_CR1_Msk (0xffUL) /*!< HRPWM0_HRC0 CR1: CR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC0_CR2 ------------------------------ */ +#define HRPWM0_HRC0_CR2_CR2_Pos (0UL) /*!< HRPWM0_HRC0 CR2: CR2 (Bit 0) */ +#define HRPWM0_HRC0_CR2_CR2_Msk (0xffUL) /*!< HRPWM0_HRC0 CR2: CR2 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC0_SSC ------------------------------ */ +#define HRPWM0_HRC0_SSC_SST_Pos (0UL) /*!< HRPWM0_HRC0 SSC: SST (Bit 0) */ +#define HRPWM0_HRC0_SSC_SST_Msk (0x1UL) /*!< HRPWM0_HRC0 SSC: SST (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC0_SDCR ------------------------------ */ +#define HRPWM0_HRC0_SDCR_SDTRV_Pos (0UL) /*!< HRPWM0_HRC0 SDCR: SDTRV (Bit 0) */ +#define HRPWM0_HRC0_SDCR_SDTRV_Msk (0xffffUL) /*!< HRPWM0_HRC0 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC0_SDCF ------------------------------ */ +#define HRPWM0_HRC0_SDCF_SDTFV_Pos (0UL) /*!< HRPWM0_HRC0 SDCF: SDTFV (Bit 0) */ +#define HRPWM0_HRC0_SDCF_SDTFV_Msk (0xffffUL) /*!< HRPWM0_HRC0 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC0_SCR1 ------------------------------ */ +#define HRPWM0_HRC0_SCR1_SCR1_Pos (0UL) /*!< HRPWM0_HRC0 SCR1: SCR1 (Bit 0) */ +#define HRPWM0_HRC0_SCR1_SCR1_Msk (0xffUL) /*!< HRPWM0_HRC0 SCR1: SCR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------ HRPWM0_HRC0_SCR2 ------------------------------ */ +#define HRPWM0_HRC0_SCR2_SCR2_Pos (0UL) /*!< HRPWM0_HRC0 SCR2: SCR2 (Bit 0) */ +#define HRPWM0_HRC0_SCR2_SCR2_Msk (0xffUL) /*!< HRPWM0_HRC0 SCR2: SCR2 (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0_HRC1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_HRC1_GC ------------------------------- */ +#define HRPWM0_HRC1_GC_HRM0_Pos (0UL) /*!< HRPWM0_HRC1 GC: HRM0 (Bit 0) */ +#define HRPWM0_HRC1_GC_HRM0_Msk (0x3UL) /*!< HRPWM0_HRC1 GC: HRM0 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GC_HRM1_Pos (2UL) /*!< HRPWM0_HRC1 GC: HRM1 (Bit 2) */ +#define HRPWM0_HRC1_GC_HRM1_Msk (0xcUL) /*!< HRPWM0_HRC1 GC: HRM1 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GC_DTE_Pos (8UL) /*!< HRPWM0_HRC1 GC: DTE (Bit 8) */ +#define HRPWM0_HRC1_GC_DTE_Msk (0x100UL) /*!< HRPWM0_HRC1 GC: DTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_GC_TR0E_Pos (9UL) /*!< HRPWM0_HRC1 GC: TR0E (Bit 9) */ +#define HRPWM0_HRC1_GC_TR0E_Msk (0x200UL) /*!< HRPWM0_HRC1 GC: TR0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_GC_TR1E_Pos (10UL) /*!< HRPWM0_HRC1 GC: TR1E (Bit 10) */ +#define HRPWM0_HRC1_GC_TR1E_Msk (0x400UL) /*!< HRPWM0_HRC1 GC: TR1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_GC_STC_Pos (11UL) /*!< HRPWM0_HRC1 GC: STC (Bit 11) */ +#define HRPWM0_HRC1_GC_STC_Msk (0x800UL) /*!< HRPWM0_HRC1 GC: STC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_GC_DSTC_Pos (12UL) /*!< HRPWM0_HRC1 GC: DSTC (Bit 12) */ +#define HRPWM0_HRC1_GC_DSTC_Msk (0x1000UL) /*!< HRPWM0_HRC1 GC: DSTC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_GC_OCS0_Pos (13UL) /*!< HRPWM0_HRC1 GC: OCS0 (Bit 13) */ +#define HRPWM0_HRC1_GC_OCS0_Msk (0x2000UL) /*!< HRPWM0_HRC1 GC: OCS0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_GC_OCS1_Pos (14UL) /*!< HRPWM0_HRC1 GC: OCS1 (Bit 14) */ +#define HRPWM0_HRC1_GC_OCS1_Msk (0x4000UL) /*!< HRPWM0_HRC1 GC: OCS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_GC_DTUS_Pos (16UL) /*!< HRPWM0_HRC1 GC: DTUS (Bit 16) */ +#define HRPWM0_HRC1_GC_DTUS_Msk (0x10000UL) /*!< HRPWM0_HRC1 GC: DTUS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC1_PL ------------------------------- */ +#define HRPWM0_HRC1_PL_PSL0_Pos (0UL) /*!< HRPWM0_HRC1 PL: PSL0 (Bit 0) */ +#define HRPWM0_HRC1_PL_PSL0_Msk (0x1UL) /*!< HRPWM0_HRC1 PL: PSL0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_PL_PSL1_Pos (1UL) /*!< HRPWM0_HRC1 PL: PSL1 (Bit 1) */ +#define HRPWM0_HRC1_PL_PSL1_Msk (0x2UL) /*!< HRPWM0_HRC1 PL: PSL1 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC1_GSEL ------------------------------ */ +#define HRPWM0_HRC1_GSEL_C0SS_Pos (0UL) /*!< HRPWM0_HRC1 GSEL: C0SS (Bit 0) */ +#define HRPWM0_HRC1_GSEL_C0SS_Msk (0x7UL) /*!< HRPWM0_HRC1 GSEL: C0SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC1_GSEL_C0CS_Pos (3UL) /*!< HRPWM0_HRC1 GSEL: C0CS (Bit 3) */ +#define HRPWM0_HRC1_GSEL_C0CS_Msk (0x38UL) /*!< HRPWM0_HRC1 GSEL: C0CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC1_GSEL_S0M_Pos (6UL) /*!< HRPWM0_HRC1 GSEL: S0M (Bit 6) */ +#define HRPWM0_HRC1_GSEL_S0M_Msk (0xc0UL) /*!< HRPWM0_HRC1 GSEL: S0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GSEL_C0M_Pos (8UL) /*!< HRPWM0_HRC1 GSEL: C0M (Bit 8) */ +#define HRPWM0_HRC1_GSEL_C0M_Msk (0x300UL) /*!< HRPWM0_HRC1 GSEL: C0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GSEL_S0ES_Pos (10UL) /*!< HRPWM0_HRC1 GSEL: S0ES (Bit 10) */ +#define HRPWM0_HRC1_GSEL_S0ES_Msk (0xc00UL) /*!< HRPWM0_HRC1 GSEL: S0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GSEL_C0ES_Pos (12UL) /*!< HRPWM0_HRC1 GSEL: C0ES (Bit 12) */ +#define HRPWM0_HRC1_GSEL_C0ES_Msk (0x3000UL) /*!< HRPWM0_HRC1 GSEL: C0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GSEL_C1SS_Pos (16UL) /*!< HRPWM0_HRC1 GSEL: C1SS (Bit 16) */ +#define HRPWM0_HRC1_GSEL_C1SS_Msk (0x70000UL) /*!< HRPWM0_HRC1 GSEL: C1SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC1_GSEL_C1CS_Pos (19UL) /*!< HRPWM0_HRC1 GSEL: C1CS (Bit 19) */ +#define HRPWM0_HRC1_GSEL_C1CS_Msk (0x380000UL) /*!< HRPWM0_HRC1 GSEL: C1CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC1_GSEL_S1M_Pos (22UL) /*!< HRPWM0_HRC1 GSEL: S1M (Bit 22) */ +#define HRPWM0_HRC1_GSEL_S1M_Msk (0xc00000UL) /*!< HRPWM0_HRC1 GSEL: S1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GSEL_C1M_Pos (24UL) /*!< HRPWM0_HRC1 GSEL: C1M (Bit 24) */ +#define HRPWM0_HRC1_GSEL_C1M_Msk (0x3000000UL) /*!< HRPWM0_HRC1 GSEL: C1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GSEL_S1ES_Pos (26UL) /*!< HRPWM0_HRC1 GSEL: S1ES (Bit 26) */ +#define HRPWM0_HRC1_GSEL_S1ES_Msk (0xc000000UL) /*!< HRPWM0_HRC1 GSEL: S1ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC1_GSEL_C1ES_Pos (28UL) /*!< HRPWM0_HRC1 GSEL: C1ES (Bit 28) */ +#define HRPWM0_HRC1_GSEL_C1ES_Msk (0x30000000UL) /*!< HRPWM0_HRC1 GSEL: C1ES (Bitfield-Mask: 0x03) */ + +/* ------------------------------ HRPWM0_HRC1_TSEL ------------------------------ */ +#define HRPWM0_HRC1_TSEL_TSEL0_Pos (0UL) /*!< HRPWM0_HRC1 TSEL: TSEL0 (Bit 0) */ +#define HRPWM0_HRC1_TSEL_TSEL0_Msk (0x7UL) /*!< HRPWM0_HRC1 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC1_TSEL_TSEL1_Pos (3UL) /*!< HRPWM0_HRC1 TSEL: TSEL1 (Bit 3) */ +#define HRPWM0_HRC1_TSEL_TSEL1_Msk (0x38UL) /*!< HRPWM0_HRC1 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC1_TSEL_TS0E_Pos (16UL) /*!< HRPWM0_HRC1 TSEL: TS0E (Bit 16) */ +#define HRPWM0_HRC1_TSEL_TS0E_Msk (0x10000UL) /*!< HRPWM0_HRC1 TSEL: TS0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC1_TSEL_TS1E_Pos (17UL) /*!< HRPWM0_HRC1 TSEL: TS1E (Bit 17) */ +#define HRPWM0_HRC1_TSEL_TS1E_Msk (0x20000UL) /*!< HRPWM0_HRC1 TSEL: TS1E (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC1_SC ------------------------------- */ +#define HRPWM0_HRC1_SC_ST_Pos (0UL) /*!< HRPWM0_HRC1 SC: ST (Bit 0) */ +#define HRPWM0_HRC1_SC_ST_Msk (0x1UL) /*!< HRPWM0_HRC1 SC: ST (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC1_DCR ------------------------------ */ +#define HRPWM0_HRC1_DCR_DTRV_Pos (0UL) /*!< HRPWM0_HRC1 DCR: DTRV (Bit 0) */ +#define HRPWM0_HRC1_DCR_DTRV_Msk (0xffffUL) /*!< HRPWM0_HRC1 DCR: DTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC1_DCF ------------------------------ */ +#define HRPWM0_HRC1_DCF_DTFV_Pos (0UL) /*!< HRPWM0_HRC1 DCF: DTFV (Bit 0) */ +#define HRPWM0_HRC1_DCF_DTFV_Msk (0xffffUL) /*!< HRPWM0_HRC1 DCF: DTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC1_CR1 ------------------------------ */ +#define HRPWM0_HRC1_CR1_CR1_Pos (0UL) /*!< HRPWM0_HRC1 CR1: CR1 (Bit 0) */ +#define HRPWM0_HRC1_CR1_CR1_Msk (0xffUL) /*!< HRPWM0_HRC1 CR1: CR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC1_CR2 ------------------------------ */ +#define HRPWM0_HRC1_CR2_CR2_Pos (0UL) /*!< HRPWM0_HRC1 CR2: CR2 (Bit 0) */ +#define HRPWM0_HRC1_CR2_CR2_Msk (0xffUL) /*!< HRPWM0_HRC1 CR2: CR2 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC1_SSC ------------------------------ */ +#define HRPWM0_HRC1_SSC_SST_Pos (0UL) /*!< HRPWM0_HRC1 SSC: SST (Bit 0) */ +#define HRPWM0_HRC1_SSC_SST_Msk (0x1UL) /*!< HRPWM0_HRC1 SSC: SST (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC1_SDCR ------------------------------ */ +#define HRPWM0_HRC1_SDCR_SDTRV_Pos (0UL) /*!< HRPWM0_HRC1 SDCR: SDTRV (Bit 0) */ +#define HRPWM0_HRC1_SDCR_SDTRV_Msk (0xffffUL) /*!< HRPWM0_HRC1 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC1_SDCF ------------------------------ */ +#define HRPWM0_HRC1_SDCF_SDTFV_Pos (0UL) /*!< HRPWM0_HRC1 SDCF: SDTFV (Bit 0) */ +#define HRPWM0_HRC1_SDCF_SDTFV_Msk (0xffffUL) /*!< HRPWM0_HRC1 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC1_SCR1 ------------------------------ */ +#define HRPWM0_HRC1_SCR1_SCR1_Pos (0UL) /*!< HRPWM0_HRC1 SCR1: SCR1 (Bit 0) */ +#define HRPWM0_HRC1_SCR1_SCR1_Msk (0xffUL) /*!< HRPWM0_HRC1 SCR1: SCR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------ HRPWM0_HRC1_SCR2 ------------------------------ */ +#define HRPWM0_HRC1_SCR2_SCR2_Pos (0UL) /*!< HRPWM0_HRC1 SCR2: SCR2 (Bit 0) */ +#define HRPWM0_HRC1_SCR2_SCR2_Msk (0xffUL) /*!< HRPWM0_HRC1 SCR2: SCR2 (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0_HRC2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_HRC2_GC ------------------------------- */ +#define HRPWM0_HRC2_GC_HRM0_Pos (0UL) /*!< HRPWM0_HRC2 GC: HRM0 (Bit 0) */ +#define HRPWM0_HRC2_GC_HRM0_Msk (0x3UL) /*!< HRPWM0_HRC2 GC: HRM0 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GC_HRM1_Pos (2UL) /*!< HRPWM0_HRC2 GC: HRM1 (Bit 2) */ +#define HRPWM0_HRC2_GC_HRM1_Msk (0xcUL) /*!< HRPWM0_HRC2 GC: HRM1 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GC_DTE_Pos (8UL) /*!< HRPWM0_HRC2 GC: DTE (Bit 8) */ +#define HRPWM0_HRC2_GC_DTE_Msk (0x100UL) /*!< HRPWM0_HRC2 GC: DTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_GC_TR0E_Pos (9UL) /*!< HRPWM0_HRC2 GC: TR0E (Bit 9) */ +#define HRPWM0_HRC2_GC_TR0E_Msk (0x200UL) /*!< HRPWM0_HRC2 GC: TR0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_GC_TR1E_Pos (10UL) /*!< HRPWM0_HRC2 GC: TR1E (Bit 10) */ +#define HRPWM0_HRC2_GC_TR1E_Msk (0x400UL) /*!< HRPWM0_HRC2 GC: TR1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_GC_STC_Pos (11UL) /*!< HRPWM0_HRC2 GC: STC (Bit 11) */ +#define HRPWM0_HRC2_GC_STC_Msk (0x800UL) /*!< HRPWM0_HRC2 GC: STC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_GC_DSTC_Pos (12UL) /*!< HRPWM0_HRC2 GC: DSTC (Bit 12) */ +#define HRPWM0_HRC2_GC_DSTC_Msk (0x1000UL) /*!< HRPWM0_HRC2 GC: DSTC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_GC_OCS0_Pos (13UL) /*!< HRPWM0_HRC2 GC: OCS0 (Bit 13) */ +#define HRPWM0_HRC2_GC_OCS0_Msk (0x2000UL) /*!< HRPWM0_HRC2 GC: OCS0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_GC_OCS1_Pos (14UL) /*!< HRPWM0_HRC2 GC: OCS1 (Bit 14) */ +#define HRPWM0_HRC2_GC_OCS1_Msk (0x4000UL) /*!< HRPWM0_HRC2 GC: OCS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_GC_DTUS_Pos (16UL) /*!< HRPWM0_HRC2 GC: DTUS (Bit 16) */ +#define HRPWM0_HRC2_GC_DTUS_Msk (0x10000UL) /*!< HRPWM0_HRC2 GC: DTUS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC2_PL ------------------------------- */ +#define HRPWM0_HRC2_PL_PSL0_Pos (0UL) /*!< HRPWM0_HRC2 PL: PSL0 (Bit 0) */ +#define HRPWM0_HRC2_PL_PSL0_Msk (0x1UL) /*!< HRPWM0_HRC2 PL: PSL0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_PL_PSL1_Pos (1UL) /*!< HRPWM0_HRC2 PL: PSL1 (Bit 1) */ +#define HRPWM0_HRC2_PL_PSL1_Msk (0x2UL) /*!< HRPWM0_HRC2 PL: PSL1 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC2_GSEL ------------------------------ */ +#define HRPWM0_HRC2_GSEL_C0SS_Pos (0UL) /*!< HRPWM0_HRC2 GSEL: C0SS (Bit 0) */ +#define HRPWM0_HRC2_GSEL_C0SS_Msk (0x7UL) /*!< HRPWM0_HRC2 GSEL: C0SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC2_GSEL_C0CS_Pos (3UL) /*!< HRPWM0_HRC2 GSEL: C0CS (Bit 3) */ +#define HRPWM0_HRC2_GSEL_C0CS_Msk (0x38UL) /*!< HRPWM0_HRC2 GSEL: C0CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC2_GSEL_S0M_Pos (6UL) /*!< HRPWM0_HRC2 GSEL: S0M (Bit 6) */ +#define HRPWM0_HRC2_GSEL_S0M_Msk (0xc0UL) /*!< HRPWM0_HRC2 GSEL: S0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GSEL_C0M_Pos (8UL) /*!< HRPWM0_HRC2 GSEL: C0M (Bit 8) */ +#define HRPWM0_HRC2_GSEL_C0M_Msk (0x300UL) /*!< HRPWM0_HRC2 GSEL: C0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GSEL_S0ES_Pos (10UL) /*!< HRPWM0_HRC2 GSEL: S0ES (Bit 10) */ +#define HRPWM0_HRC2_GSEL_S0ES_Msk (0xc00UL) /*!< HRPWM0_HRC2 GSEL: S0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GSEL_C0ES_Pos (12UL) /*!< HRPWM0_HRC2 GSEL: C0ES (Bit 12) */ +#define HRPWM0_HRC2_GSEL_C0ES_Msk (0x3000UL) /*!< HRPWM0_HRC2 GSEL: C0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GSEL_C1SS_Pos (16UL) /*!< HRPWM0_HRC2 GSEL: C1SS (Bit 16) */ +#define HRPWM0_HRC2_GSEL_C1SS_Msk (0x70000UL) /*!< HRPWM0_HRC2 GSEL: C1SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC2_GSEL_C1CS_Pos (19UL) /*!< HRPWM0_HRC2 GSEL: C1CS (Bit 19) */ +#define HRPWM0_HRC2_GSEL_C1CS_Msk (0x380000UL) /*!< HRPWM0_HRC2 GSEL: C1CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC2_GSEL_S1M_Pos (22UL) /*!< HRPWM0_HRC2 GSEL: S1M (Bit 22) */ +#define HRPWM0_HRC2_GSEL_S1M_Msk (0xc00000UL) /*!< HRPWM0_HRC2 GSEL: S1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GSEL_C1M_Pos (24UL) /*!< HRPWM0_HRC2 GSEL: C1M (Bit 24) */ +#define HRPWM0_HRC2_GSEL_C1M_Msk (0x3000000UL) /*!< HRPWM0_HRC2 GSEL: C1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GSEL_S1ES_Pos (26UL) /*!< HRPWM0_HRC2 GSEL: S1ES (Bit 26) */ +#define HRPWM0_HRC2_GSEL_S1ES_Msk (0xc000000UL) /*!< HRPWM0_HRC2 GSEL: S1ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC2_GSEL_C1ES_Pos (28UL) /*!< HRPWM0_HRC2 GSEL: C1ES (Bit 28) */ +#define HRPWM0_HRC2_GSEL_C1ES_Msk (0x30000000UL) /*!< HRPWM0_HRC2 GSEL: C1ES (Bitfield-Mask: 0x03) */ + +/* ------------------------------ HRPWM0_HRC2_TSEL ------------------------------ */ +#define HRPWM0_HRC2_TSEL_TSEL0_Pos (0UL) /*!< HRPWM0_HRC2 TSEL: TSEL0 (Bit 0) */ +#define HRPWM0_HRC2_TSEL_TSEL0_Msk (0x7UL) /*!< HRPWM0_HRC2 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC2_TSEL_TSEL1_Pos (3UL) /*!< HRPWM0_HRC2 TSEL: TSEL1 (Bit 3) */ +#define HRPWM0_HRC2_TSEL_TSEL1_Msk (0x38UL) /*!< HRPWM0_HRC2 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC2_TSEL_TS0E_Pos (16UL) /*!< HRPWM0_HRC2 TSEL: TS0E (Bit 16) */ +#define HRPWM0_HRC2_TSEL_TS0E_Msk (0x10000UL) /*!< HRPWM0_HRC2 TSEL: TS0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC2_TSEL_TS1E_Pos (17UL) /*!< HRPWM0_HRC2 TSEL: TS1E (Bit 17) */ +#define HRPWM0_HRC2_TSEL_TS1E_Msk (0x20000UL) /*!< HRPWM0_HRC2 TSEL: TS1E (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC2_SC ------------------------------- */ +#define HRPWM0_HRC2_SC_ST_Pos (0UL) /*!< HRPWM0_HRC2 SC: ST (Bit 0) */ +#define HRPWM0_HRC2_SC_ST_Msk (0x1UL) /*!< HRPWM0_HRC2 SC: ST (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC2_DCR ------------------------------ */ +#define HRPWM0_HRC2_DCR_DTRV_Pos (0UL) /*!< HRPWM0_HRC2 DCR: DTRV (Bit 0) */ +#define HRPWM0_HRC2_DCR_DTRV_Msk (0xffffUL) /*!< HRPWM0_HRC2 DCR: DTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC2_DCF ------------------------------ */ +#define HRPWM0_HRC2_DCF_DTFV_Pos (0UL) /*!< HRPWM0_HRC2 DCF: DTFV (Bit 0) */ +#define HRPWM0_HRC2_DCF_DTFV_Msk (0xffffUL) /*!< HRPWM0_HRC2 DCF: DTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC2_CR1 ------------------------------ */ +#define HRPWM0_HRC2_CR1_CR1_Pos (0UL) /*!< HRPWM0_HRC2 CR1: CR1 (Bit 0) */ +#define HRPWM0_HRC2_CR1_CR1_Msk (0xffUL) /*!< HRPWM0_HRC2 CR1: CR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC2_CR2 ------------------------------ */ +#define HRPWM0_HRC2_CR2_CR2_Pos (0UL) /*!< HRPWM0_HRC2 CR2: CR2 (Bit 0) */ +#define HRPWM0_HRC2_CR2_CR2_Msk (0xffUL) /*!< HRPWM0_HRC2 CR2: CR2 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC2_SSC ------------------------------ */ +#define HRPWM0_HRC2_SSC_SST_Pos (0UL) /*!< HRPWM0_HRC2 SSC: SST (Bit 0) */ +#define HRPWM0_HRC2_SSC_SST_Msk (0x1UL) /*!< HRPWM0_HRC2 SSC: SST (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC2_SDCR ------------------------------ */ +#define HRPWM0_HRC2_SDCR_SDTRV_Pos (0UL) /*!< HRPWM0_HRC2 SDCR: SDTRV (Bit 0) */ +#define HRPWM0_HRC2_SDCR_SDTRV_Msk (0xffffUL) /*!< HRPWM0_HRC2 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC2_SDCF ------------------------------ */ +#define HRPWM0_HRC2_SDCF_SDTFV_Pos (0UL) /*!< HRPWM0_HRC2 SDCF: SDTFV (Bit 0) */ +#define HRPWM0_HRC2_SDCF_SDTFV_Msk (0xffffUL) /*!< HRPWM0_HRC2 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC2_SCR1 ------------------------------ */ +#define HRPWM0_HRC2_SCR1_SCR1_Pos (0UL) /*!< HRPWM0_HRC2 SCR1: SCR1 (Bit 0) */ +#define HRPWM0_HRC2_SCR1_SCR1_Msk (0xffUL) /*!< HRPWM0_HRC2 SCR1: SCR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------ HRPWM0_HRC2_SCR2 ------------------------------ */ +#define HRPWM0_HRC2_SCR2_SCR2_Pos (0UL) /*!< HRPWM0_HRC2 SCR2: SCR2 (Bit 0) */ +#define HRPWM0_HRC2_SCR2_SCR2_Msk (0xffUL) /*!< HRPWM0_HRC2 SCR2: SCR2 (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ struct 'HRPWM0_HRC3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ------------------------------- HRPWM0_HRC3_GC ------------------------------- */ +#define HRPWM0_HRC3_GC_HRM0_Pos (0UL) /*!< HRPWM0_HRC3 GC: HRM0 (Bit 0) */ +#define HRPWM0_HRC3_GC_HRM0_Msk (0x3UL) /*!< HRPWM0_HRC3 GC: HRM0 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GC_HRM1_Pos (2UL) /*!< HRPWM0_HRC3 GC: HRM1 (Bit 2) */ +#define HRPWM0_HRC3_GC_HRM1_Msk (0xcUL) /*!< HRPWM0_HRC3 GC: HRM1 (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GC_DTE_Pos (8UL) /*!< HRPWM0_HRC3 GC: DTE (Bit 8) */ +#define HRPWM0_HRC3_GC_DTE_Msk (0x100UL) /*!< HRPWM0_HRC3 GC: DTE (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_GC_TR0E_Pos (9UL) /*!< HRPWM0_HRC3 GC: TR0E (Bit 9) */ +#define HRPWM0_HRC3_GC_TR0E_Msk (0x200UL) /*!< HRPWM0_HRC3 GC: TR0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_GC_TR1E_Pos (10UL) /*!< HRPWM0_HRC3 GC: TR1E (Bit 10) */ +#define HRPWM0_HRC3_GC_TR1E_Msk (0x400UL) /*!< HRPWM0_HRC3 GC: TR1E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_GC_STC_Pos (11UL) /*!< HRPWM0_HRC3 GC: STC (Bit 11) */ +#define HRPWM0_HRC3_GC_STC_Msk (0x800UL) /*!< HRPWM0_HRC3 GC: STC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_GC_DSTC_Pos (12UL) /*!< HRPWM0_HRC3 GC: DSTC (Bit 12) */ +#define HRPWM0_HRC3_GC_DSTC_Msk (0x1000UL) /*!< HRPWM0_HRC3 GC: DSTC (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_GC_OCS0_Pos (13UL) /*!< HRPWM0_HRC3 GC: OCS0 (Bit 13) */ +#define HRPWM0_HRC3_GC_OCS0_Msk (0x2000UL) /*!< HRPWM0_HRC3 GC: OCS0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_GC_OCS1_Pos (14UL) /*!< HRPWM0_HRC3 GC: OCS1 (Bit 14) */ +#define HRPWM0_HRC3_GC_OCS1_Msk (0x4000UL) /*!< HRPWM0_HRC3 GC: OCS1 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_GC_DTUS_Pos (16UL) /*!< HRPWM0_HRC3 GC: DTUS (Bit 16) */ +#define HRPWM0_HRC3_GC_DTUS_Msk (0x10000UL) /*!< HRPWM0_HRC3 GC: DTUS (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC3_PL ------------------------------- */ +#define HRPWM0_HRC3_PL_PSL0_Pos (0UL) /*!< HRPWM0_HRC3 PL: PSL0 (Bit 0) */ +#define HRPWM0_HRC3_PL_PSL0_Msk (0x1UL) /*!< HRPWM0_HRC3 PL: PSL0 (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_PL_PSL1_Pos (1UL) /*!< HRPWM0_HRC3 PL: PSL1 (Bit 1) */ +#define HRPWM0_HRC3_PL_PSL1_Msk (0x2UL) /*!< HRPWM0_HRC3 PL: PSL1 (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC3_GSEL ------------------------------ */ +#define HRPWM0_HRC3_GSEL_C0SS_Pos (0UL) /*!< HRPWM0_HRC3 GSEL: C0SS (Bit 0) */ +#define HRPWM0_HRC3_GSEL_C0SS_Msk (0x7UL) /*!< HRPWM0_HRC3 GSEL: C0SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC3_GSEL_C0CS_Pos (3UL) /*!< HRPWM0_HRC3 GSEL: C0CS (Bit 3) */ +#define HRPWM0_HRC3_GSEL_C0CS_Msk (0x38UL) /*!< HRPWM0_HRC3 GSEL: C0CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC3_GSEL_S0M_Pos (6UL) /*!< HRPWM0_HRC3 GSEL: S0M (Bit 6) */ +#define HRPWM0_HRC3_GSEL_S0M_Msk (0xc0UL) /*!< HRPWM0_HRC3 GSEL: S0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GSEL_C0M_Pos (8UL) /*!< HRPWM0_HRC3 GSEL: C0M (Bit 8) */ +#define HRPWM0_HRC3_GSEL_C0M_Msk (0x300UL) /*!< HRPWM0_HRC3 GSEL: C0M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GSEL_S0ES_Pos (10UL) /*!< HRPWM0_HRC3 GSEL: S0ES (Bit 10) */ +#define HRPWM0_HRC3_GSEL_S0ES_Msk (0xc00UL) /*!< HRPWM0_HRC3 GSEL: S0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GSEL_C0ES_Pos (12UL) /*!< HRPWM0_HRC3 GSEL: C0ES (Bit 12) */ +#define HRPWM0_HRC3_GSEL_C0ES_Msk (0x3000UL) /*!< HRPWM0_HRC3 GSEL: C0ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GSEL_C1SS_Pos (16UL) /*!< HRPWM0_HRC3 GSEL: C1SS (Bit 16) */ +#define HRPWM0_HRC3_GSEL_C1SS_Msk (0x70000UL) /*!< HRPWM0_HRC3 GSEL: C1SS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC3_GSEL_C1CS_Pos (19UL) /*!< HRPWM0_HRC3 GSEL: C1CS (Bit 19) */ +#define HRPWM0_HRC3_GSEL_C1CS_Msk (0x380000UL) /*!< HRPWM0_HRC3 GSEL: C1CS (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC3_GSEL_S1M_Pos (22UL) /*!< HRPWM0_HRC3 GSEL: S1M (Bit 22) */ +#define HRPWM0_HRC3_GSEL_S1M_Msk (0xc00000UL) /*!< HRPWM0_HRC3 GSEL: S1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GSEL_C1M_Pos (24UL) /*!< HRPWM0_HRC3 GSEL: C1M (Bit 24) */ +#define HRPWM0_HRC3_GSEL_C1M_Msk (0x3000000UL) /*!< HRPWM0_HRC3 GSEL: C1M (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GSEL_S1ES_Pos (26UL) /*!< HRPWM0_HRC3 GSEL: S1ES (Bit 26) */ +#define HRPWM0_HRC3_GSEL_S1ES_Msk (0xc000000UL) /*!< HRPWM0_HRC3 GSEL: S1ES (Bitfield-Mask: 0x03) */ +#define HRPWM0_HRC3_GSEL_C1ES_Pos (28UL) /*!< HRPWM0_HRC3 GSEL: C1ES (Bit 28) */ +#define HRPWM0_HRC3_GSEL_C1ES_Msk (0x30000000UL) /*!< HRPWM0_HRC3 GSEL: C1ES (Bitfield-Mask: 0x03) */ + +/* ------------------------------ HRPWM0_HRC3_TSEL ------------------------------ */ +#define HRPWM0_HRC3_TSEL_TSEL0_Pos (0UL) /*!< HRPWM0_HRC3 TSEL: TSEL0 (Bit 0) */ +#define HRPWM0_HRC3_TSEL_TSEL0_Msk (0x7UL) /*!< HRPWM0_HRC3 TSEL: TSEL0 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC3_TSEL_TSEL1_Pos (3UL) /*!< HRPWM0_HRC3 TSEL: TSEL1 (Bit 3) */ +#define HRPWM0_HRC3_TSEL_TSEL1_Msk (0x38UL) /*!< HRPWM0_HRC3 TSEL: TSEL1 (Bitfield-Mask: 0x07) */ +#define HRPWM0_HRC3_TSEL_TS0E_Pos (16UL) /*!< HRPWM0_HRC3 TSEL: TS0E (Bit 16) */ +#define HRPWM0_HRC3_TSEL_TS0E_Msk (0x10000UL) /*!< HRPWM0_HRC3 TSEL: TS0E (Bitfield-Mask: 0x01) */ +#define HRPWM0_HRC3_TSEL_TS1E_Pos (17UL) /*!< HRPWM0_HRC3 TSEL: TS1E (Bit 17) */ +#define HRPWM0_HRC3_TSEL_TS1E_Msk (0x20000UL) /*!< HRPWM0_HRC3 TSEL: TS1E (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC3_SC ------------------------------- */ +#define HRPWM0_HRC3_SC_ST_Pos (0UL) /*!< HRPWM0_HRC3 SC: ST (Bit 0) */ +#define HRPWM0_HRC3_SC_ST_Msk (0x1UL) /*!< HRPWM0_HRC3 SC: ST (Bitfield-Mask: 0x01) */ + +/* ------------------------------- HRPWM0_HRC3_DCR ------------------------------ */ +#define HRPWM0_HRC3_DCR_DTRV_Pos (0UL) /*!< HRPWM0_HRC3 DCR: DTRV (Bit 0) */ +#define HRPWM0_HRC3_DCR_DTRV_Msk (0xffffUL) /*!< HRPWM0_HRC3 DCR: DTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC3_DCF ------------------------------ */ +#define HRPWM0_HRC3_DCF_DTFV_Pos (0UL) /*!< HRPWM0_HRC3 DCF: DTFV (Bit 0) */ +#define HRPWM0_HRC3_DCF_DTFV_Msk (0xffffUL) /*!< HRPWM0_HRC3 DCF: DTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------- HRPWM0_HRC3_CR1 ------------------------------ */ +#define HRPWM0_HRC3_CR1_CR1_Pos (0UL) /*!< HRPWM0_HRC3 CR1: CR1 (Bit 0) */ +#define HRPWM0_HRC3_CR1_CR1_Msk (0xffUL) /*!< HRPWM0_HRC3 CR1: CR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC3_CR2 ------------------------------ */ +#define HRPWM0_HRC3_CR2_CR2_Pos (0UL) /*!< HRPWM0_HRC3 CR2: CR2 (Bit 0) */ +#define HRPWM0_HRC3_CR2_CR2_Msk (0xffUL) /*!< HRPWM0_HRC3 CR2: CR2 (Bitfield-Mask: 0xff) */ + +/* ------------------------------- HRPWM0_HRC3_SSC ------------------------------ */ +#define HRPWM0_HRC3_SSC_SST_Pos (0UL) /*!< HRPWM0_HRC3 SSC: SST (Bit 0) */ +#define HRPWM0_HRC3_SSC_SST_Msk (0x1UL) /*!< HRPWM0_HRC3 SSC: SST (Bitfield-Mask: 0x01) */ + +/* ------------------------------ HRPWM0_HRC3_SDCR ------------------------------ */ +#define HRPWM0_HRC3_SDCR_SDTRV_Pos (0UL) /*!< HRPWM0_HRC3 SDCR: SDTRV (Bit 0) */ +#define HRPWM0_HRC3_SDCR_SDTRV_Msk (0xffffUL) /*!< HRPWM0_HRC3 SDCR: SDTRV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC3_SDCF ------------------------------ */ +#define HRPWM0_HRC3_SDCF_SDTFV_Pos (0UL) /*!< HRPWM0_HRC3 SDCF: SDTFV (Bit 0) */ +#define HRPWM0_HRC3_SDCF_SDTFV_Msk (0xffffUL) /*!< HRPWM0_HRC3 SDCF: SDTFV (Bitfield-Mask: 0xffff) */ + +/* ------------------------------ HRPWM0_HRC3_SCR1 ------------------------------ */ +#define HRPWM0_HRC3_SCR1_SCR1_Pos (0UL) /*!< HRPWM0_HRC3 SCR1: SCR1 (Bit 0) */ +#define HRPWM0_HRC3_SCR1_SCR1_Msk (0xffUL) /*!< HRPWM0_HRC3 SCR1: SCR1 (Bitfield-Mask: 0xff) */ + +/* ------------------------------ HRPWM0_HRC3_SCR2 ------------------------------ */ +#define HRPWM0_HRC3_SCR2_SCR2_Pos (0UL) /*!< HRPWM0_HRC3 SCR2: SCR2 (Bit 0) */ +#define HRPWM0_HRC3_SCR2_SCR2_Msk (0xffUL) /*!< HRPWM0_HRC3 SCR2: SCR2 (Bitfield-Mask: 0xff) */ + + +/* ================================================================================ */ +/* ================ Group 'POSIF' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- POSIF_PCONF -------------------------------- */ +#define POSIF_PCONF_FSEL_Pos (0UL) /*!< POSIF PCONF: FSEL (Bit 0) */ +#define POSIF_PCONF_FSEL_Msk (0x3UL) /*!< POSIF PCONF: FSEL (Bitfield-Mask: 0x03) */ +#define POSIF_PCONF_QDCM_Pos (2UL) /*!< POSIF PCONF: QDCM (Bit 2) */ +#define POSIF_PCONF_QDCM_Msk (0x4UL) /*!< POSIF PCONF: QDCM (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_HIDG_Pos (4UL) /*!< POSIF PCONF: HIDG (Bit 4) */ +#define POSIF_PCONF_HIDG_Msk (0x10UL) /*!< POSIF PCONF: HIDG (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_MCUE_Pos (5UL) /*!< POSIF PCONF: MCUE (Bit 5) */ +#define POSIF_PCONF_MCUE_Msk (0x20UL) /*!< POSIF PCONF: MCUE (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_INSEL0_Pos (8UL) /*!< POSIF PCONF: INSEL0 (Bit 8) */ +#define POSIF_PCONF_INSEL0_Msk (0x300UL) /*!< POSIF PCONF: INSEL0 (Bitfield-Mask: 0x03) */ +#define POSIF_PCONF_INSEL1_Pos (10UL) /*!< POSIF PCONF: INSEL1 (Bit 10) */ +#define POSIF_PCONF_INSEL1_Msk (0xc00UL) /*!< POSIF PCONF: INSEL1 (Bitfield-Mask: 0x03) */ +#define POSIF_PCONF_INSEL2_Pos (12UL) /*!< POSIF PCONF: INSEL2 (Bit 12) */ +#define POSIF_PCONF_INSEL2_Msk (0x3000UL) /*!< POSIF PCONF: INSEL2 (Bitfield-Mask: 0x03) */ +#define POSIF_PCONF_DSEL_Pos (16UL) /*!< POSIF PCONF: DSEL (Bit 16) */ +#define POSIF_PCONF_DSEL_Msk (0x10000UL) /*!< POSIF PCONF: DSEL (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_SPES_Pos (17UL) /*!< POSIF PCONF: SPES (Bit 17) */ +#define POSIF_PCONF_SPES_Msk (0x20000UL) /*!< POSIF PCONF: SPES (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_MSETS_Pos (18UL) /*!< POSIF PCONF: MSETS (Bit 18) */ +#define POSIF_PCONF_MSETS_Msk (0x1c0000UL) /*!< POSIF PCONF: MSETS (Bitfield-Mask: 0x07) */ +#define POSIF_PCONF_MSES_Pos (21UL) /*!< POSIF PCONF: MSES (Bit 21) */ +#define POSIF_PCONF_MSES_Msk (0x200000UL) /*!< POSIF PCONF: MSES (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_MSYNS_Pos (22UL) /*!< POSIF PCONF: MSYNS (Bit 22) */ +#define POSIF_PCONF_MSYNS_Msk (0xc00000UL) /*!< POSIF PCONF: MSYNS (Bitfield-Mask: 0x03) */ +#define POSIF_PCONF_EWIS_Pos (24UL) /*!< POSIF PCONF: EWIS (Bit 24) */ +#define POSIF_PCONF_EWIS_Msk (0x3000000UL) /*!< POSIF PCONF: EWIS (Bitfield-Mask: 0x03) */ +#define POSIF_PCONF_EWIE_Pos (26UL) /*!< POSIF PCONF: EWIE (Bit 26) */ +#define POSIF_PCONF_EWIE_Msk (0x4000000UL) /*!< POSIF PCONF: EWIE (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_EWIL_Pos (27UL) /*!< POSIF PCONF: EWIL (Bit 27) */ +#define POSIF_PCONF_EWIL_Msk (0x8000000UL) /*!< POSIF PCONF: EWIL (Bitfield-Mask: 0x01) */ +#define POSIF_PCONF_LPC_Pos (28UL) /*!< POSIF PCONF: LPC (Bit 28) */ +#define POSIF_PCONF_LPC_Msk (0x70000000UL) /*!< POSIF PCONF: LPC (Bitfield-Mask: 0x07) */ + +/* --------------------------------- POSIF_PSUS --------------------------------- */ +#define POSIF_PSUS_QSUS_Pos (0UL) /*!< POSIF PSUS: QSUS (Bit 0) */ +#define POSIF_PSUS_QSUS_Msk (0x3UL) /*!< POSIF PSUS: QSUS (Bitfield-Mask: 0x03) */ +#define POSIF_PSUS_MSUS_Pos (2UL) /*!< POSIF PSUS: MSUS (Bit 2) */ +#define POSIF_PSUS_MSUS_Msk (0xcUL) /*!< POSIF PSUS: MSUS (Bitfield-Mask: 0x03) */ + +/* --------------------------------- POSIF_PRUNS -------------------------------- */ +#define POSIF_PRUNS_SRB_Pos (0UL) /*!< POSIF PRUNS: SRB (Bit 0) */ +#define POSIF_PRUNS_SRB_Msk (0x1UL) /*!< POSIF PRUNS: SRB (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_PRUNC -------------------------------- */ +#define POSIF_PRUNC_CRB_Pos (0UL) /*!< POSIF PRUNC: CRB (Bit 0) */ +#define POSIF_PRUNC_CRB_Msk (0x1UL) /*!< POSIF PRUNC: CRB (Bitfield-Mask: 0x01) */ +#define POSIF_PRUNC_CSM_Pos (1UL) /*!< POSIF PRUNC: CSM (Bit 1) */ +#define POSIF_PRUNC_CSM_Msk (0x2UL) /*!< POSIF PRUNC: CSM (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_PRUN --------------------------------- */ +#define POSIF_PRUN_RB_Pos (0UL) /*!< POSIF PRUN: RB (Bit 0) */ +#define POSIF_PRUN_RB_Msk (0x1UL) /*!< POSIF PRUN: RB (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_MIDR --------------------------------- */ +#define POSIF_MIDR_MODR_Pos (0UL) /*!< POSIF MIDR: MODR (Bit 0) */ +#define POSIF_MIDR_MODR_Msk (0xffUL) /*!< POSIF MIDR: MODR (Bitfield-Mask: 0xff) */ +#define POSIF_MIDR_MODT_Pos (8UL) /*!< POSIF MIDR: MODT (Bit 8) */ +#define POSIF_MIDR_MODT_Msk (0xff00UL) /*!< POSIF MIDR: MODT (Bitfield-Mask: 0xff) */ +#define POSIF_MIDR_MODN_Pos (16UL) /*!< POSIF MIDR: MODN (Bit 16) */ +#define POSIF_MIDR_MODN_Msk (0xffff0000UL) /*!< POSIF MIDR: MODN (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- POSIF_HALP --------------------------------- */ +#define POSIF_HALP_HCP_Pos (0UL) /*!< POSIF HALP: HCP (Bit 0) */ +#define POSIF_HALP_HCP_Msk (0x7UL) /*!< POSIF HALP: HCP (Bitfield-Mask: 0x07) */ +#define POSIF_HALP_HEP_Pos (3UL) /*!< POSIF HALP: HEP (Bit 3) */ +#define POSIF_HALP_HEP_Msk (0x38UL) /*!< POSIF HALP: HEP (Bitfield-Mask: 0x07) */ + +/* --------------------------------- POSIF_HALPS -------------------------------- */ +#define POSIF_HALPS_HCPS_Pos (0UL) /*!< POSIF HALPS: HCPS (Bit 0) */ +#define POSIF_HALPS_HCPS_Msk (0x7UL) /*!< POSIF HALPS: HCPS (Bitfield-Mask: 0x07) */ +#define POSIF_HALPS_HEPS_Pos (3UL) /*!< POSIF HALPS: HEPS (Bit 3) */ +#define POSIF_HALPS_HEPS_Msk (0x38UL) /*!< POSIF HALPS: HEPS (Bitfield-Mask: 0x07) */ + +/* ---------------------------------- POSIF_MCM --------------------------------- */ +#define POSIF_MCM_MCMP_Pos (0UL) /*!< POSIF MCM: MCMP (Bit 0) */ +#define POSIF_MCM_MCMP_Msk (0xffffUL) /*!< POSIF MCM: MCMP (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- POSIF_MCSM --------------------------------- */ +#define POSIF_MCSM_MCMPS_Pos (0UL) /*!< POSIF MCSM: MCMPS (Bit 0) */ +#define POSIF_MCSM_MCMPS_Msk (0xffffUL) /*!< POSIF MCSM: MCMPS (Bitfield-Mask: 0xffff) */ + +/* --------------------------------- POSIF_MCMS --------------------------------- */ +#define POSIF_MCMS_MNPS_Pos (0UL) /*!< POSIF MCMS: MNPS (Bit 0) */ +#define POSIF_MCMS_MNPS_Msk (0x1UL) /*!< POSIF MCMS: MNPS (Bitfield-Mask: 0x01) */ +#define POSIF_MCMS_STHR_Pos (1UL) /*!< POSIF MCMS: STHR (Bit 1) */ +#define POSIF_MCMS_STHR_Msk (0x2UL) /*!< POSIF MCMS: STHR (Bitfield-Mask: 0x01) */ +#define POSIF_MCMS_STMR_Pos (2UL) /*!< POSIF MCMS: STMR (Bit 2) */ +#define POSIF_MCMS_STMR_Msk (0x4UL) /*!< POSIF MCMS: STMR (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_MCMC --------------------------------- */ +#define POSIF_MCMC_MNPC_Pos (0UL) /*!< POSIF MCMC: MNPC (Bit 0) */ +#define POSIF_MCMC_MNPC_Msk (0x1UL) /*!< POSIF MCMC: MNPC (Bitfield-Mask: 0x01) */ +#define POSIF_MCMC_MPC_Pos (1UL) /*!< POSIF MCMC: MPC (Bit 1) */ +#define POSIF_MCMC_MPC_Msk (0x2UL) /*!< POSIF MCMC: MPC (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_MCMF --------------------------------- */ +#define POSIF_MCMF_MSS_Pos (0UL) /*!< POSIF MCMF: MSS (Bit 0) */ +#define POSIF_MCMF_MSS_Msk (0x1UL) /*!< POSIF MCMF: MSS (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- POSIF_QDC --------------------------------- */ +#define POSIF_QDC_PALS_Pos (0UL) /*!< POSIF QDC: PALS (Bit 0) */ +#define POSIF_QDC_PALS_Msk (0x1UL) /*!< POSIF QDC: PALS (Bitfield-Mask: 0x01) */ +#define POSIF_QDC_PBLS_Pos (1UL) /*!< POSIF QDC: PBLS (Bit 1) */ +#define POSIF_QDC_PBLS_Msk (0x2UL) /*!< POSIF QDC: PBLS (Bitfield-Mask: 0x01) */ +#define POSIF_QDC_PHS_Pos (2UL) /*!< POSIF QDC: PHS (Bit 2) */ +#define POSIF_QDC_PHS_Msk (0x4UL) /*!< POSIF QDC: PHS (Bitfield-Mask: 0x01) */ +#define POSIF_QDC_ICM_Pos (4UL) /*!< POSIF QDC: ICM (Bit 4) */ +#define POSIF_QDC_ICM_Msk (0x30UL) /*!< POSIF QDC: ICM (Bitfield-Mask: 0x03) */ +#define POSIF_QDC_DVAL_Pos (8UL) /*!< POSIF QDC: DVAL (Bit 8) */ +#define POSIF_QDC_DVAL_Msk (0x100UL) /*!< POSIF QDC: DVAL (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_PFLG --------------------------------- */ +#define POSIF_PFLG_CHES_Pos (0UL) /*!< POSIF PFLG: CHES (Bit 0) */ +#define POSIF_PFLG_CHES_Msk (0x1UL) /*!< POSIF PFLG: CHES (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_WHES_Pos (1UL) /*!< POSIF PFLG: WHES (Bit 1) */ +#define POSIF_PFLG_WHES_Msk (0x2UL) /*!< POSIF PFLG: WHES (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_HIES_Pos (2UL) /*!< POSIF PFLG: HIES (Bit 2) */ +#define POSIF_PFLG_HIES_Msk (0x4UL) /*!< POSIF PFLG: HIES (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_MSTS_Pos (4UL) /*!< POSIF PFLG: MSTS (Bit 4) */ +#define POSIF_PFLG_MSTS_Msk (0x10UL) /*!< POSIF PFLG: MSTS (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_INDXS_Pos (8UL) /*!< POSIF PFLG: INDXS (Bit 8) */ +#define POSIF_PFLG_INDXS_Msk (0x100UL) /*!< POSIF PFLG: INDXS (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_ERRS_Pos (9UL) /*!< POSIF PFLG: ERRS (Bit 9) */ +#define POSIF_PFLG_ERRS_Msk (0x200UL) /*!< POSIF PFLG: ERRS (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_CNTS_Pos (10UL) /*!< POSIF PFLG: CNTS (Bit 10) */ +#define POSIF_PFLG_CNTS_Msk (0x400UL) /*!< POSIF PFLG: CNTS (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_DIRS_Pos (11UL) /*!< POSIF PFLG: DIRS (Bit 11) */ +#define POSIF_PFLG_DIRS_Msk (0x800UL) /*!< POSIF PFLG: DIRS (Bitfield-Mask: 0x01) */ +#define POSIF_PFLG_PCLKS_Pos (12UL) /*!< POSIF PFLG: PCLKS (Bit 12) */ +#define POSIF_PFLG_PCLKS_Msk (0x1000UL) /*!< POSIF PFLG: PCLKS (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_PFLGE -------------------------------- */ +#define POSIF_PFLGE_ECHE_Pos (0UL) /*!< POSIF PFLGE: ECHE (Bit 0) */ +#define POSIF_PFLGE_ECHE_Msk (0x1UL) /*!< POSIF PFLGE: ECHE (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_EWHE_Pos (1UL) /*!< POSIF PFLGE: EWHE (Bit 1) */ +#define POSIF_PFLGE_EWHE_Msk (0x2UL) /*!< POSIF PFLGE: EWHE (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_EHIE_Pos (2UL) /*!< POSIF PFLGE: EHIE (Bit 2) */ +#define POSIF_PFLGE_EHIE_Msk (0x4UL) /*!< POSIF PFLGE: EHIE (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_EMST_Pos (4UL) /*!< POSIF PFLGE: EMST (Bit 4) */ +#define POSIF_PFLGE_EMST_Msk (0x10UL) /*!< POSIF PFLGE: EMST (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_EINDX_Pos (8UL) /*!< POSIF PFLGE: EINDX (Bit 8) */ +#define POSIF_PFLGE_EINDX_Msk (0x100UL) /*!< POSIF PFLGE: EINDX (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_EERR_Pos (9UL) /*!< POSIF PFLGE: EERR (Bit 9) */ +#define POSIF_PFLGE_EERR_Msk (0x200UL) /*!< POSIF PFLGE: EERR (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_ECNT_Pos (10UL) /*!< POSIF PFLGE: ECNT (Bit 10) */ +#define POSIF_PFLGE_ECNT_Msk (0x400UL) /*!< POSIF PFLGE: ECNT (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_EDIR_Pos (11UL) /*!< POSIF PFLGE: EDIR (Bit 11) */ +#define POSIF_PFLGE_EDIR_Msk (0x800UL) /*!< POSIF PFLGE: EDIR (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_EPCLK_Pos (12UL) /*!< POSIF PFLGE: EPCLK (Bit 12) */ +#define POSIF_PFLGE_EPCLK_Msk (0x1000UL) /*!< POSIF PFLGE: EPCLK (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_CHESEL_Pos (16UL) /*!< POSIF PFLGE: CHESEL (Bit 16) */ +#define POSIF_PFLGE_CHESEL_Msk (0x10000UL) /*!< POSIF PFLGE: CHESEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_WHESEL_Pos (17UL) /*!< POSIF PFLGE: WHESEL (Bit 17) */ +#define POSIF_PFLGE_WHESEL_Msk (0x20000UL) /*!< POSIF PFLGE: WHESEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_HIESEL_Pos (18UL) /*!< POSIF PFLGE: HIESEL (Bit 18) */ +#define POSIF_PFLGE_HIESEL_Msk (0x40000UL) /*!< POSIF PFLGE: HIESEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_MSTSEL_Pos (20UL) /*!< POSIF PFLGE: MSTSEL (Bit 20) */ +#define POSIF_PFLGE_MSTSEL_Msk (0x100000UL) /*!< POSIF PFLGE: MSTSEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_INDSEL_Pos (24UL) /*!< POSIF PFLGE: INDSEL (Bit 24) */ +#define POSIF_PFLGE_INDSEL_Msk (0x1000000UL) /*!< POSIF PFLGE: INDSEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_ERRSEL_Pos (25UL) /*!< POSIF PFLGE: ERRSEL (Bit 25) */ +#define POSIF_PFLGE_ERRSEL_Msk (0x2000000UL) /*!< POSIF PFLGE: ERRSEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_CNTSEL_Pos (26UL) /*!< POSIF PFLGE: CNTSEL (Bit 26) */ +#define POSIF_PFLGE_CNTSEL_Msk (0x4000000UL) /*!< POSIF PFLGE: CNTSEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_DIRSEL_Pos (27UL) /*!< POSIF PFLGE: DIRSEL (Bit 27) */ +#define POSIF_PFLGE_DIRSEL_Msk (0x8000000UL) /*!< POSIF PFLGE: DIRSEL (Bitfield-Mask: 0x01) */ +#define POSIF_PFLGE_PCLSEL_Pos (28UL) /*!< POSIF PFLGE: PCLSEL (Bit 28) */ +#define POSIF_PFLGE_PCLSEL_Msk (0x10000000UL) /*!< POSIF PFLGE: PCLSEL (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_SPFLG -------------------------------- */ +#define POSIF_SPFLG_SCHE_Pos (0UL) /*!< POSIF SPFLG: SCHE (Bit 0) */ +#define POSIF_SPFLG_SCHE_Msk (0x1UL) /*!< POSIF SPFLG: SCHE (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SWHE_Pos (1UL) /*!< POSIF SPFLG: SWHE (Bit 1) */ +#define POSIF_SPFLG_SWHE_Msk (0x2UL) /*!< POSIF SPFLG: SWHE (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SHIE_Pos (2UL) /*!< POSIF SPFLG: SHIE (Bit 2) */ +#define POSIF_SPFLG_SHIE_Msk (0x4UL) /*!< POSIF SPFLG: SHIE (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SMST_Pos (4UL) /*!< POSIF SPFLG: SMST (Bit 4) */ +#define POSIF_SPFLG_SMST_Msk (0x10UL) /*!< POSIF SPFLG: SMST (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SINDX_Pos (8UL) /*!< POSIF SPFLG: SINDX (Bit 8) */ +#define POSIF_SPFLG_SINDX_Msk (0x100UL) /*!< POSIF SPFLG: SINDX (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SERR_Pos (9UL) /*!< POSIF SPFLG: SERR (Bit 9) */ +#define POSIF_SPFLG_SERR_Msk (0x200UL) /*!< POSIF SPFLG: SERR (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SCNT_Pos (10UL) /*!< POSIF SPFLG: SCNT (Bit 10) */ +#define POSIF_SPFLG_SCNT_Msk (0x400UL) /*!< POSIF SPFLG: SCNT (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SDIR_Pos (11UL) /*!< POSIF SPFLG: SDIR (Bit 11) */ +#define POSIF_SPFLG_SDIR_Msk (0x800UL) /*!< POSIF SPFLG: SDIR (Bitfield-Mask: 0x01) */ +#define POSIF_SPFLG_SPCLK_Pos (12UL) /*!< POSIF SPFLG: SPCLK (Bit 12) */ +#define POSIF_SPFLG_SPCLK_Msk (0x1000UL) /*!< POSIF SPFLG: SPCLK (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_RPFLG -------------------------------- */ +#define POSIF_RPFLG_RCHE_Pos (0UL) /*!< POSIF RPFLG: RCHE (Bit 0) */ +#define POSIF_RPFLG_RCHE_Msk (0x1UL) /*!< POSIF RPFLG: RCHE (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RWHE_Pos (1UL) /*!< POSIF RPFLG: RWHE (Bit 1) */ +#define POSIF_RPFLG_RWHE_Msk (0x2UL) /*!< POSIF RPFLG: RWHE (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RHIE_Pos (2UL) /*!< POSIF RPFLG: RHIE (Bit 2) */ +#define POSIF_RPFLG_RHIE_Msk (0x4UL) /*!< POSIF RPFLG: RHIE (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RMST_Pos (4UL) /*!< POSIF RPFLG: RMST (Bit 4) */ +#define POSIF_RPFLG_RMST_Msk (0x10UL) /*!< POSIF RPFLG: RMST (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RINDX_Pos (8UL) /*!< POSIF RPFLG: RINDX (Bit 8) */ +#define POSIF_RPFLG_RINDX_Msk (0x100UL) /*!< POSIF RPFLG: RINDX (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RERR_Pos (9UL) /*!< POSIF RPFLG: RERR (Bit 9) */ +#define POSIF_RPFLG_RERR_Msk (0x200UL) /*!< POSIF RPFLG: RERR (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RCNT_Pos (10UL) /*!< POSIF RPFLG: RCNT (Bit 10) */ +#define POSIF_RPFLG_RCNT_Msk (0x400UL) /*!< POSIF RPFLG: RCNT (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RDIR_Pos (11UL) /*!< POSIF RPFLG: RDIR (Bit 11) */ +#define POSIF_RPFLG_RDIR_Msk (0x800UL) /*!< POSIF RPFLG: RDIR (Bitfield-Mask: 0x01) */ +#define POSIF_RPFLG_RPCLK_Pos (12UL) /*!< POSIF RPFLG: RPCLK (Bit 12) */ +#define POSIF_RPFLG_RPCLK_Msk (0x1000UL) /*!< POSIF RPFLG: RPCLK (Bitfield-Mask: 0x01) */ + +/* --------------------------------- POSIF_PDBG --------------------------------- */ +#define POSIF_PDBG_QCSV_Pos (0UL) /*!< POSIF PDBG: QCSV (Bit 0) */ +#define POSIF_PDBG_QCSV_Msk (0x3UL) /*!< POSIF PDBG: QCSV (Bitfield-Mask: 0x03) */ +#define POSIF_PDBG_QPSV_Pos (2UL) /*!< POSIF PDBG: QPSV (Bit 2) */ +#define POSIF_PDBG_QPSV_Msk (0xcUL) /*!< POSIF PDBG: QPSV (Bitfield-Mask: 0x03) */ +#define POSIF_PDBG_IVAL_Pos (4UL) /*!< POSIF PDBG: IVAL (Bit 4) */ +#define POSIF_PDBG_IVAL_Msk (0x10UL) /*!< POSIF PDBG: IVAL (Bitfield-Mask: 0x01) */ +#define POSIF_PDBG_HSP_Pos (5UL) /*!< POSIF PDBG: HSP (Bit 5) */ +#define POSIF_PDBG_HSP_Msk (0xe0UL) /*!< POSIF PDBG: HSP (Bitfield-Mask: 0x07) */ +#define POSIF_PDBG_LPP0_Pos (8UL) /*!< POSIF PDBG: LPP0 (Bit 8) */ +#define POSIF_PDBG_LPP0_Msk (0x3f00UL) /*!< POSIF PDBG: LPP0 (Bitfield-Mask: 0x3f) */ +#define POSIF_PDBG_LPP1_Pos (16UL) /*!< POSIF PDBG: LPP1 (Bit 16) */ +#define POSIF_PDBG_LPP1_Msk (0x3f0000UL) /*!< POSIF PDBG: LPP1 (Bitfield-Mask: 0x3f) */ +#define POSIF_PDBG_LPP2_Pos (22UL) /*!< POSIF PDBG: LPP2 (Bit 22) */ +#define POSIF_PDBG_LPP2_Msk (0xfc00000UL) /*!< POSIF PDBG: LPP2 (Bitfield-Mask: 0x3f) */ + + +/* ================================================================================ */ +/* ================ struct 'PORT0' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- PORT0_OUT --------------------------------- */ +#define PORT0_OUT_P0_Pos (0UL) /*!< PORT0 OUT: P0 (Bit 0) */ +#define PORT0_OUT_P0_Msk (0x1UL) /*!< PORT0 OUT: P0 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P1_Pos (1UL) /*!< PORT0 OUT: P1 (Bit 1) */ +#define PORT0_OUT_P1_Msk (0x2UL) /*!< PORT0 OUT: P1 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P2_Pos (2UL) /*!< PORT0 OUT: P2 (Bit 2) */ +#define PORT0_OUT_P2_Msk (0x4UL) /*!< PORT0 OUT: P2 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P3_Pos (3UL) /*!< PORT0 OUT: P3 (Bit 3) */ +#define PORT0_OUT_P3_Msk (0x8UL) /*!< PORT0 OUT: P3 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P4_Pos (4UL) /*!< PORT0 OUT: P4 (Bit 4) */ +#define PORT0_OUT_P4_Msk (0x10UL) /*!< PORT0 OUT: P4 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P5_Pos (5UL) /*!< PORT0 OUT: P5 (Bit 5) */ +#define PORT0_OUT_P5_Msk (0x20UL) /*!< PORT0 OUT: P5 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P6_Pos (6UL) /*!< PORT0 OUT: P6 (Bit 6) */ +#define PORT0_OUT_P6_Msk (0x40UL) /*!< PORT0 OUT: P6 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P7_Pos (7UL) /*!< PORT0 OUT: P7 (Bit 7) */ +#define PORT0_OUT_P7_Msk (0x80UL) /*!< PORT0 OUT: P7 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P8_Pos (8UL) /*!< PORT0 OUT: P8 (Bit 8) */ +#define PORT0_OUT_P8_Msk (0x100UL) /*!< PORT0 OUT: P8 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P9_Pos (9UL) /*!< PORT0 OUT: P9 (Bit 9) */ +#define PORT0_OUT_P9_Msk (0x200UL) /*!< PORT0 OUT: P9 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P10_Pos (10UL) /*!< PORT0 OUT: P10 (Bit 10) */ +#define PORT0_OUT_P10_Msk (0x400UL) /*!< PORT0 OUT: P10 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P11_Pos (11UL) /*!< PORT0 OUT: P11 (Bit 11) */ +#define PORT0_OUT_P11_Msk (0x800UL) /*!< PORT0 OUT: P11 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P12_Pos (12UL) /*!< PORT0 OUT: P12 (Bit 12) */ +#define PORT0_OUT_P12_Msk (0x1000UL) /*!< PORT0 OUT: P12 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P13_Pos (13UL) /*!< PORT0 OUT: P13 (Bit 13) */ +#define PORT0_OUT_P13_Msk (0x2000UL) /*!< PORT0 OUT: P13 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P14_Pos (14UL) /*!< PORT0 OUT: P14 (Bit 14) */ +#define PORT0_OUT_P14_Msk (0x4000UL) /*!< PORT0 OUT: P14 (Bitfield-Mask: 0x01) */ +#define PORT0_OUT_P15_Pos (15UL) /*!< PORT0 OUT: P15 (Bit 15) */ +#define PORT0_OUT_P15_Msk (0x8000UL) /*!< PORT0 OUT: P15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT0_OMR --------------------------------- */ +#define PORT0_OMR_PS0_Pos (0UL) /*!< PORT0 OMR: PS0 (Bit 0) */ +#define PORT0_OMR_PS0_Msk (0x1UL) /*!< PORT0 OMR: PS0 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS1_Pos (1UL) /*!< PORT0 OMR: PS1 (Bit 1) */ +#define PORT0_OMR_PS1_Msk (0x2UL) /*!< PORT0 OMR: PS1 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS2_Pos (2UL) /*!< PORT0 OMR: PS2 (Bit 2) */ +#define PORT0_OMR_PS2_Msk (0x4UL) /*!< PORT0 OMR: PS2 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS3_Pos (3UL) /*!< PORT0 OMR: PS3 (Bit 3) */ +#define PORT0_OMR_PS3_Msk (0x8UL) /*!< PORT0 OMR: PS3 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS4_Pos (4UL) /*!< PORT0 OMR: PS4 (Bit 4) */ +#define PORT0_OMR_PS4_Msk (0x10UL) /*!< PORT0 OMR: PS4 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS5_Pos (5UL) /*!< PORT0 OMR: PS5 (Bit 5) */ +#define PORT0_OMR_PS5_Msk (0x20UL) /*!< PORT0 OMR: PS5 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS6_Pos (6UL) /*!< PORT0 OMR: PS6 (Bit 6) */ +#define PORT0_OMR_PS6_Msk (0x40UL) /*!< PORT0 OMR: PS6 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS7_Pos (7UL) /*!< PORT0 OMR: PS7 (Bit 7) */ +#define PORT0_OMR_PS7_Msk (0x80UL) /*!< PORT0 OMR: PS7 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS8_Pos (8UL) /*!< PORT0 OMR: PS8 (Bit 8) */ +#define PORT0_OMR_PS8_Msk (0x100UL) /*!< PORT0 OMR: PS8 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS9_Pos (9UL) /*!< PORT0 OMR: PS9 (Bit 9) */ +#define PORT0_OMR_PS9_Msk (0x200UL) /*!< PORT0 OMR: PS9 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS10_Pos (10UL) /*!< PORT0 OMR: PS10 (Bit 10) */ +#define PORT0_OMR_PS10_Msk (0x400UL) /*!< PORT0 OMR: PS10 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS11_Pos (11UL) /*!< PORT0 OMR: PS11 (Bit 11) */ +#define PORT0_OMR_PS11_Msk (0x800UL) /*!< PORT0 OMR: PS11 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS12_Pos (12UL) /*!< PORT0 OMR: PS12 (Bit 12) */ +#define PORT0_OMR_PS12_Msk (0x1000UL) /*!< PORT0 OMR: PS12 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS13_Pos (13UL) /*!< PORT0 OMR: PS13 (Bit 13) */ +#define PORT0_OMR_PS13_Msk (0x2000UL) /*!< PORT0 OMR: PS13 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS14_Pos (14UL) /*!< PORT0 OMR: PS14 (Bit 14) */ +#define PORT0_OMR_PS14_Msk (0x4000UL) /*!< PORT0 OMR: PS14 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PS15_Pos (15UL) /*!< PORT0 OMR: PS15 (Bit 15) */ +#define PORT0_OMR_PS15_Msk (0x8000UL) /*!< PORT0 OMR: PS15 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR0_Pos (16UL) /*!< PORT0 OMR: PR0 (Bit 16) */ +#define PORT0_OMR_PR0_Msk (0x10000UL) /*!< PORT0 OMR: PR0 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR1_Pos (17UL) /*!< PORT0 OMR: PR1 (Bit 17) */ +#define PORT0_OMR_PR1_Msk (0x20000UL) /*!< PORT0 OMR: PR1 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR2_Pos (18UL) /*!< PORT0 OMR: PR2 (Bit 18) */ +#define PORT0_OMR_PR2_Msk (0x40000UL) /*!< PORT0 OMR: PR2 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR3_Pos (19UL) /*!< PORT0 OMR: PR3 (Bit 19) */ +#define PORT0_OMR_PR3_Msk (0x80000UL) /*!< PORT0 OMR: PR3 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR4_Pos (20UL) /*!< PORT0 OMR: PR4 (Bit 20) */ +#define PORT0_OMR_PR4_Msk (0x100000UL) /*!< PORT0 OMR: PR4 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR5_Pos (21UL) /*!< PORT0 OMR: PR5 (Bit 21) */ +#define PORT0_OMR_PR5_Msk (0x200000UL) /*!< PORT0 OMR: PR5 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR6_Pos (22UL) /*!< PORT0 OMR: PR6 (Bit 22) */ +#define PORT0_OMR_PR6_Msk (0x400000UL) /*!< PORT0 OMR: PR6 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR7_Pos (23UL) /*!< PORT0 OMR: PR7 (Bit 23) */ +#define PORT0_OMR_PR7_Msk (0x800000UL) /*!< PORT0 OMR: PR7 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR8_Pos (24UL) /*!< PORT0 OMR: PR8 (Bit 24) */ +#define PORT0_OMR_PR8_Msk (0x1000000UL) /*!< PORT0 OMR: PR8 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR9_Pos (25UL) /*!< PORT0 OMR: PR9 (Bit 25) */ +#define PORT0_OMR_PR9_Msk (0x2000000UL) /*!< PORT0 OMR: PR9 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR10_Pos (26UL) /*!< PORT0 OMR: PR10 (Bit 26) */ +#define PORT0_OMR_PR10_Msk (0x4000000UL) /*!< PORT0 OMR: PR10 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR11_Pos (27UL) /*!< PORT0 OMR: PR11 (Bit 27) */ +#define PORT0_OMR_PR11_Msk (0x8000000UL) /*!< PORT0 OMR: PR11 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR12_Pos (28UL) /*!< PORT0 OMR: PR12 (Bit 28) */ +#define PORT0_OMR_PR12_Msk (0x10000000UL) /*!< PORT0 OMR: PR12 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR13_Pos (29UL) /*!< PORT0 OMR: PR13 (Bit 29) */ +#define PORT0_OMR_PR13_Msk (0x20000000UL) /*!< PORT0 OMR: PR13 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR14_Pos (30UL) /*!< PORT0 OMR: PR14 (Bit 30) */ +#define PORT0_OMR_PR14_Msk (0x40000000UL) /*!< PORT0 OMR: PR14 (Bitfield-Mask: 0x01) */ +#define PORT0_OMR_PR15_Pos (31UL) /*!< PORT0 OMR: PR15 (Bit 31) */ +#define PORT0_OMR_PR15_Msk (0x80000000UL) /*!< PORT0 OMR: PR15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT0_IOCR0 -------------------------------- */ +#define PORT0_IOCR0_PC0_Pos (3UL) /*!< PORT0 IOCR0: PC0 (Bit 3) */ +#define PORT0_IOCR0_PC0_Msk (0xf8UL) /*!< PORT0 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR0_PC1_Pos (11UL) /*!< PORT0 IOCR0: PC1 (Bit 11) */ +#define PORT0_IOCR0_PC1_Msk (0xf800UL) /*!< PORT0 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR0_PC2_Pos (19UL) /*!< PORT0 IOCR0: PC2 (Bit 19) */ +#define PORT0_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT0 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR0_PC3_Pos (27UL) /*!< PORT0 IOCR0: PC3 (Bit 27) */ +#define PORT0_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT0 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ + +/* --------------------------------- PORT0_IOCR4 -------------------------------- */ +#define PORT0_IOCR4_PC4_Pos (3UL) /*!< PORT0 IOCR4: PC4 (Bit 3) */ +#define PORT0_IOCR4_PC4_Msk (0xf8UL) /*!< PORT0 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR4_PC5_Pos (11UL) /*!< PORT0 IOCR4: PC5 (Bit 11) */ +#define PORT0_IOCR4_PC5_Msk (0xf800UL) /*!< PORT0 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR4_PC6_Pos (19UL) /*!< PORT0 IOCR4: PC6 (Bit 19) */ +#define PORT0_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT0 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR4_PC7_Pos (27UL) /*!< PORT0 IOCR4: PC7 (Bit 27) */ +#define PORT0_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT0 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ + +/* --------------------------------- PORT0_IOCR8 -------------------------------- */ +#define PORT0_IOCR8_PC8_Pos (3UL) /*!< PORT0 IOCR8: PC8 (Bit 3) */ +#define PORT0_IOCR8_PC8_Msk (0xf8UL) /*!< PORT0 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR8_PC9_Pos (11UL) /*!< PORT0 IOCR8: PC9 (Bit 11) */ +#define PORT0_IOCR8_PC9_Msk (0xf800UL) /*!< PORT0 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR8_PC10_Pos (19UL) /*!< PORT0 IOCR8: PC10 (Bit 19) */ +#define PORT0_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT0 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ +#define PORT0_IOCR8_PC11_Pos (27UL) /*!< PORT0 IOCR8: PC11 (Bit 27) */ +#define PORT0_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT0 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ + +/* ---------------------------------- PORT0_IN ---------------------------------- */ +#define PORT0_IN_P0_Pos (0UL) /*!< PORT0 IN: P0 (Bit 0) */ +#define PORT0_IN_P0_Msk (0x1UL) /*!< PORT0 IN: P0 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P1_Pos (1UL) /*!< PORT0 IN: P1 (Bit 1) */ +#define PORT0_IN_P1_Msk (0x2UL) /*!< PORT0 IN: P1 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P2_Pos (2UL) /*!< PORT0 IN: P2 (Bit 2) */ +#define PORT0_IN_P2_Msk (0x4UL) /*!< PORT0 IN: P2 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P3_Pos (3UL) /*!< PORT0 IN: P3 (Bit 3) */ +#define PORT0_IN_P3_Msk (0x8UL) /*!< PORT0 IN: P3 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P4_Pos (4UL) /*!< PORT0 IN: P4 (Bit 4) */ +#define PORT0_IN_P4_Msk (0x10UL) /*!< PORT0 IN: P4 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P5_Pos (5UL) /*!< PORT0 IN: P5 (Bit 5) */ +#define PORT0_IN_P5_Msk (0x20UL) /*!< PORT0 IN: P5 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P6_Pos (6UL) /*!< PORT0 IN: P6 (Bit 6) */ +#define PORT0_IN_P6_Msk (0x40UL) /*!< PORT0 IN: P6 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P7_Pos (7UL) /*!< PORT0 IN: P7 (Bit 7) */ +#define PORT0_IN_P7_Msk (0x80UL) /*!< PORT0 IN: P7 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P8_Pos (8UL) /*!< PORT0 IN: P8 (Bit 8) */ +#define PORT0_IN_P8_Msk (0x100UL) /*!< PORT0 IN: P8 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P9_Pos (9UL) /*!< PORT0 IN: P9 (Bit 9) */ +#define PORT0_IN_P9_Msk (0x200UL) /*!< PORT0 IN: P9 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P10_Pos (10UL) /*!< PORT0 IN: P10 (Bit 10) */ +#define PORT0_IN_P10_Msk (0x400UL) /*!< PORT0 IN: P10 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P11_Pos (11UL) /*!< PORT0 IN: P11 (Bit 11) */ +#define PORT0_IN_P11_Msk (0x800UL) /*!< PORT0 IN: P11 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P12_Pos (12UL) /*!< PORT0 IN: P12 (Bit 12) */ +#define PORT0_IN_P12_Msk (0x1000UL) /*!< PORT0 IN: P12 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P13_Pos (13UL) /*!< PORT0 IN: P13 (Bit 13) */ +#define PORT0_IN_P13_Msk (0x2000UL) /*!< PORT0 IN: P13 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P14_Pos (14UL) /*!< PORT0 IN: P14 (Bit 14) */ +#define PORT0_IN_P14_Msk (0x4000UL) /*!< PORT0 IN: P14 (Bitfield-Mask: 0x01) */ +#define PORT0_IN_P15_Pos (15UL) /*!< PORT0 IN: P15 (Bit 15) */ +#define PORT0_IN_P15_Msk (0x8000UL) /*!< PORT0 IN: P15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT0_PDR0 --------------------------------- */ +#define PORT0_PDR0_PD0_Pos (0UL) /*!< PORT0 PDR0: PD0 (Bit 0) */ +#define PORT0_PDR0_PD0_Msk (0x7UL) /*!< PORT0 PDR0: PD0 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR0_PD1_Pos (4UL) /*!< PORT0 PDR0: PD1 (Bit 4) */ +#define PORT0_PDR0_PD1_Msk (0x70UL) /*!< PORT0 PDR0: PD1 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR0_PD2_Pos (8UL) /*!< PORT0 PDR0: PD2 (Bit 8) */ +#define PORT0_PDR0_PD2_Msk (0x700UL) /*!< PORT0 PDR0: PD2 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR0_PD3_Pos (12UL) /*!< PORT0 PDR0: PD3 (Bit 12) */ +#define PORT0_PDR0_PD3_Msk (0x7000UL) /*!< PORT0 PDR0: PD3 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR0_PD4_Pos (16UL) /*!< PORT0 PDR0: PD4 (Bit 16) */ +#define PORT0_PDR0_PD4_Msk (0x70000UL) /*!< PORT0 PDR0: PD4 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR0_PD5_Pos (20UL) /*!< PORT0 PDR0: PD5 (Bit 20) */ +#define PORT0_PDR0_PD5_Msk (0x700000UL) /*!< PORT0 PDR0: PD5 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR0_PD6_Pos (24UL) /*!< PORT0 PDR0: PD6 (Bit 24) */ +#define PORT0_PDR0_PD6_Msk (0x7000000UL) /*!< PORT0 PDR0: PD6 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR0_PD7_Pos (28UL) /*!< PORT0 PDR0: PD7 (Bit 28) */ +#define PORT0_PDR0_PD7_Msk (0x70000000UL) /*!< PORT0 PDR0: PD7 (Bitfield-Mask: 0x07) */ + +/* --------------------------------- PORT0_PDR1 --------------------------------- */ +#define PORT0_PDR1_PD8_Pos (0UL) /*!< PORT0 PDR1: PD8 (Bit 0) */ +#define PORT0_PDR1_PD8_Msk (0x7UL) /*!< PORT0 PDR1: PD8 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR1_PD9_Pos (4UL) /*!< PORT0 PDR1: PD9 (Bit 4) */ +#define PORT0_PDR1_PD9_Msk (0x70UL) /*!< PORT0 PDR1: PD9 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR1_PD10_Pos (8UL) /*!< PORT0 PDR1: PD10 (Bit 8) */ +#define PORT0_PDR1_PD10_Msk (0x700UL) /*!< PORT0 PDR1: PD10 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR1_PD11_Pos (12UL) /*!< PORT0 PDR1: PD11 (Bit 12) */ +#define PORT0_PDR1_PD11_Msk (0x7000UL) /*!< PORT0 PDR1: PD11 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR1_PD12_Pos (16UL) /*!< PORT0 PDR1: PD12 (Bit 16) */ +#define PORT0_PDR1_PD12_Msk (0x70000UL) /*!< PORT0 PDR1: PD12 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR1_PD13_Pos (20UL) /*!< PORT0 PDR1: PD13 (Bit 20) */ +#define PORT0_PDR1_PD13_Msk (0x700000UL) /*!< PORT0 PDR1: PD13 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR1_PD14_Pos (24UL) /*!< PORT0 PDR1: PD14 (Bit 24) */ +#define PORT0_PDR1_PD14_Msk (0x7000000UL) /*!< PORT0 PDR1: PD14 (Bitfield-Mask: 0x07) */ +#define PORT0_PDR1_PD15_Pos (28UL) /*!< PORT0 PDR1: PD15 (Bit 28) */ +#define PORT0_PDR1_PD15_Msk (0x70000000UL) /*!< PORT0 PDR1: PD15 (Bitfield-Mask: 0x07) */ + +/* --------------------------------- PORT0_PDISC -------------------------------- */ +#define PORT0_PDISC_PDIS0_Pos (0UL) /*!< PORT0 PDISC: PDIS0 (Bit 0) */ +#define PORT0_PDISC_PDIS0_Msk (0x1UL) /*!< PORT0 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS1_Pos (1UL) /*!< PORT0 PDISC: PDIS1 (Bit 1) */ +#define PORT0_PDISC_PDIS1_Msk (0x2UL) /*!< PORT0 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS2_Pos (2UL) /*!< PORT0 PDISC: PDIS2 (Bit 2) */ +#define PORT0_PDISC_PDIS2_Msk (0x4UL) /*!< PORT0 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS3_Pos (3UL) /*!< PORT0 PDISC: PDIS3 (Bit 3) */ +#define PORT0_PDISC_PDIS3_Msk (0x8UL) /*!< PORT0 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS4_Pos (4UL) /*!< PORT0 PDISC: PDIS4 (Bit 4) */ +#define PORT0_PDISC_PDIS4_Msk (0x10UL) /*!< PORT0 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS5_Pos (5UL) /*!< PORT0 PDISC: PDIS5 (Bit 5) */ +#define PORT0_PDISC_PDIS5_Msk (0x20UL) /*!< PORT0 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS6_Pos (6UL) /*!< PORT0 PDISC: PDIS6 (Bit 6) */ +#define PORT0_PDISC_PDIS6_Msk (0x40UL) /*!< PORT0 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS7_Pos (7UL) /*!< PORT0 PDISC: PDIS7 (Bit 7) */ +#define PORT0_PDISC_PDIS7_Msk (0x80UL) /*!< PORT0 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS8_Pos (8UL) /*!< PORT0 PDISC: PDIS8 (Bit 8) */ +#define PORT0_PDISC_PDIS8_Msk (0x100UL) /*!< PORT0 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS9_Pos (9UL) /*!< PORT0 PDISC: PDIS9 (Bit 9) */ +#define PORT0_PDISC_PDIS9_Msk (0x200UL) /*!< PORT0 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS10_Pos (10UL) /*!< PORT0 PDISC: PDIS10 (Bit 10) */ +#define PORT0_PDISC_PDIS10_Msk (0x400UL) /*!< PORT0 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS11_Pos (11UL) /*!< PORT0 PDISC: PDIS11 (Bit 11) */ +#define PORT0_PDISC_PDIS11_Msk (0x800UL) /*!< PORT0 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS12_Pos (12UL) /*!< PORT0 PDISC: PDIS12 (Bit 12) */ +#define PORT0_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT0 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS13_Pos (13UL) /*!< PORT0 PDISC: PDIS13 (Bit 13) */ +#define PORT0_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT0 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS14_Pos (14UL) /*!< PORT0 PDISC: PDIS14 (Bit 14) */ +#define PORT0_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT0 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ +#define PORT0_PDISC_PDIS15_Pos (15UL) /*!< PORT0 PDISC: PDIS15 (Bit 15) */ +#define PORT0_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT0 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT0_PPS --------------------------------- */ +#define PORT0_PPS_PPS0_Pos (0UL) /*!< PORT0 PPS: PPS0 (Bit 0) */ +#define PORT0_PPS_PPS0_Msk (0x1UL) /*!< PORT0 PPS: PPS0 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS1_Pos (1UL) /*!< PORT0 PPS: PPS1 (Bit 1) */ +#define PORT0_PPS_PPS1_Msk (0x2UL) /*!< PORT0 PPS: PPS1 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS2_Pos (2UL) /*!< PORT0 PPS: PPS2 (Bit 2) */ +#define PORT0_PPS_PPS2_Msk (0x4UL) /*!< PORT0 PPS: PPS2 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS3_Pos (3UL) /*!< PORT0 PPS: PPS3 (Bit 3) */ +#define PORT0_PPS_PPS3_Msk (0x8UL) /*!< PORT0 PPS: PPS3 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS4_Pos (4UL) /*!< PORT0 PPS: PPS4 (Bit 4) */ +#define PORT0_PPS_PPS4_Msk (0x10UL) /*!< PORT0 PPS: PPS4 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS5_Pos (5UL) /*!< PORT0 PPS: PPS5 (Bit 5) */ +#define PORT0_PPS_PPS5_Msk (0x20UL) /*!< PORT0 PPS: PPS5 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS6_Pos (6UL) /*!< PORT0 PPS: PPS6 (Bit 6) */ +#define PORT0_PPS_PPS6_Msk (0x40UL) /*!< PORT0 PPS: PPS6 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS7_Pos (7UL) /*!< PORT0 PPS: PPS7 (Bit 7) */ +#define PORT0_PPS_PPS7_Msk (0x80UL) /*!< PORT0 PPS: PPS7 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS8_Pos (8UL) /*!< PORT0 PPS: PPS8 (Bit 8) */ +#define PORT0_PPS_PPS8_Msk (0x100UL) /*!< PORT0 PPS: PPS8 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS9_Pos (9UL) /*!< PORT0 PPS: PPS9 (Bit 9) */ +#define PORT0_PPS_PPS9_Msk (0x200UL) /*!< PORT0 PPS: PPS9 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS10_Pos (10UL) /*!< PORT0 PPS: PPS10 (Bit 10) */ +#define PORT0_PPS_PPS10_Msk (0x400UL) /*!< PORT0 PPS: PPS10 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS11_Pos (11UL) /*!< PORT0 PPS: PPS11 (Bit 11) */ +#define PORT0_PPS_PPS11_Msk (0x800UL) /*!< PORT0 PPS: PPS11 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS12_Pos (12UL) /*!< PORT0 PPS: PPS12 (Bit 12) */ +#define PORT0_PPS_PPS12_Msk (0x1000UL) /*!< PORT0 PPS: PPS12 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS13_Pos (13UL) /*!< PORT0 PPS: PPS13 (Bit 13) */ +#define PORT0_PPS_PPS13_Msk (0x2000UL) /*!< PORT0 PPS: PPS13 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS14_Pos (14UL) /*!< PORT0 PPS: PPS14 (Bit 14) */ +#define PORT0_PPS_PPS14_Msk (0x4000UL) /*!< PORT0 PPS: PPS14 (Bitfield-Mask: 0x01) */ +#define PORT0_PPS_PPS15_Pos (15UL) /*!< PORT0 PPS: PPS15 (Bit 15) */ +#define PORT0_PPS_PPS15_Msk (0x8000UL) /*!< PORT0 PPS: PPS15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT0_HWSEL -------------------------------- */ +#define PORT0_HWSEL_HW0_Pos (0UL) /*!< PORT0 HWSEL: HW0 (Bit 0) */ +#define PORT0_HWSEL_HW0_Msk (0x3UL) /*!< PORT0 HWSEL: HW0 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW1_Pos (2UL) /*!< PORT0 HWSEL: HW1 (Bit 2) */ +#define PORT0_HWSEL_HW1_Msk (0xcUL) /*!< PORT0 HWSEL: HW1 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW2_Pos (4UL) /*!< PORT0 HWSEL: HW2 (Bit 4) */ +#define PORT0_HWSEL_HW2_Msk (0x30UL) /*!< PORT0 HWSEL: HW2 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW3_Pos (6UL) /*!< PORT0 HWSEL: HW3 (Bit 6) */ +#define PORT0_HWSEL_HW3_Msk (0xc0UL) /*!< PORT0 HWSEL: HW3 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW4_Pos (8UL) /*!< PORT0 HWSEL: HW4 (Bit 8) */ +#define PORT0_HWSEL_HW4_Msk (0x300UL) /*!< PORT0 HWSEL: HW4 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW5_Pos (10UL) /*!< PORT0 HWSEL: HW5 (Bit 10) */ +#define PORT0_HWSEL_HW5_Msk (0xc00UL) /*!< PORT0 HWSEL: HW5 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW6_Pos (12UL) /*!< PORT0 HWSEL: HW6 (Bit 12) */ +#define PORT0_HWSEL_HW6_Msk (0x3000UL) /*!< PORT0 HWSEL: HW6 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW7_Pos (14UL) /*!< PORT0 HWSEL: HW7 (Bit 14) */ +#define PORT0_HWSEL_HW7_Msk (0xc000UL) /*!< PORT0 HWSEL: HW7 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW8_Pos (16UL) /*!< PORT0 HWSEL: HW8 (Bit 16) */ +#define PORT0_HWSEL_HW8_Msk (0x30000UL) /*!< PORT0 HWSEL: HW8 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW9_Pos (18UL) /*!< PORT0 HWSEL: HW9 (Bit 18) */ +#define PORT0_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT0 HWSEL: HW9 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW10_Pos (20UL) /*!< PORT0 HWSEL: HW10 (Bit 20) */ +#define PORT0_HWSEL_HW10_Msk (0x300000UL) /*!< PORT0 HWSEL: HW10 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW11_Pos (22UL) /*!< PORT0 HWSEL: HW11 (Bit 22) */ +#define PORT0_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT0 HWSEL: HW11 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW12_Pos (24UL) /*!< PORT0 HWSEL: HW12 (Bit 24) */ +#define PORT0_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT0 HWSEL: HW12 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW13_Pos (26UL) /*!< PORT0 HWSEL: HW13 (Bit 26) */ +#define PORT0_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT0 HWSEL: HW13 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW14_Pos (28UL) /*!< PORT0 HWSEL: HW14 (Bit 28) */ +#define PORT0_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT0 HWSEL: HW14 (Bitfield-Mask: 0x03) */ +#define PORT0_HWSEL_HW15_Pos (30UL) /*!< PORT0 HWSEL: HW15 (Bit 30) */ +#define PORT0_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT0 HWSEL: HW15 (Bitfield-Mask: 0x03) */ + + +/* ================================================================================ */ +/* ================ struct 'PORT1' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- PORT1_OUT --------------------------------- */ +#define PORT1_OUT_P0_Pos (0UL) /*!< PORT1 OUT: P0 (Bit 0) */ +#define PORT1_OUT_P0_Msk (0x1UL) /*!< PORT1 OUT: P0 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P1_Pos (1UL) /*!< PORT1 OUT: P1 (Bit 1) */ +#define PORT1_OUT_P1_Msk (0x2UL) /*!< PORT1 OUT: P1 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P2_Pos (2UL) /*!< PORT1 OUT: P2 (Bit 2) */ +#define PORT1_OUT_P2_Msk (0x4UL) /*!< PORT1 OUT: P2 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P3_Pos (3UL) /*!< PORT1 OUT: P3 (Bit 3) */ +#define PORT1_OUT_P3_Msk (0x8UL) /*!< PORT1 OUT: P3 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P4_Pos (4UL) /*!< PORT1 OUT: P4 (Bit 4) */ +#define PORT1_OUT_P4_Msk (0x10UL) /*!< PORT1 OUT: P4 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P5_Pos (5UL) /*!< PORT1 OUT: P5 (Bit 5) */ +#define PORT1_OUT_P5_Msk (0x20UL) /*!< PORT1 OUT: P5 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P6_Pos (6UL) /*!< PORT1 OUT: P6 (Bit 6) */ +#define PORT1_OUT_P6_Msk (0x40UL) /*!< PORT1 OUT: P6 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P7_Pos (7UL) /*!< PORT1 OUT: P7 (Bit 7) */ +#define PORT1_OUT_P7_Msk (0x80UL) /*!< PORT1 OUT: P7 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P8_Pos (8UL) /*!< PORT1 OUT: P8 (Bit 8) */ +#define PORT1_OUT_P8_Msk (0x100UL) /*!< PORT1 OUT: P8 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P9_Pos (9UL) /*!< PORT1 OUT: P9 (Bit 9) */ +#define PORT1_OUT_P9_Msk (0x200UL) /*!< PORT1 OUT: P9 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P10_Pos (10UL) /*!< PORT1 OUT: P10 (Bit 10) */ +#define PORT1_OUT_P10_Msk (0x400UL) /*!< PORT1 OUT: P10 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P11_Pos (11UL) /*!< PORT1 OUT: P11 (Bit 11) */ +#define PORT1_OUT_P11_Msk (0x800UL) /*!< PORT1 OUT: P11 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P12_Pos (12UL) /*!< PORT1 OUT: P12 (Bit 12) */ +#define PORT1_OUT_P12_Msk (0x1000UL) /*!< PORT1 OUT: P12 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P13_Pos (13UL) /*!< PORT1 OUT: P13 (Bit 13) */ +#define PORT1_OUT_P13_Msk (0x2000UL) /*!< PORT1 OUT: P13 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P14_Pos (14UL) /*!< PORT1 OUT: P14 (Bit 14) */ +#define PORT1_OUT_P14_Msk (0x4000UL) /*!< PORT1 OUT: P14 (Bitfield-Mask: 0x01) */ +#define PORT1_OUT_P15_Pos (15UL) /*!< PORT1 OUT: P15 (Bit 15) */ +#define PORT1_OUT_P15_Msk (0x8000UL) /*!< PORT1 OUT: P15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT1_OMR --------------------------------- */ +#define PORT1_OMR_PS0_Pos (0UL) /*!< PORT1 OMR: PS0 (Bit 0) */ +#define PORT1_OMR_PS0_Msk (0x1UL) /*!< PORT1 OMR: PS0 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS1_Pos (1UL) /*!< PORT1 OMR: PS1 (Bit 1) */ +#define PORT1_OMR_PS1_Msk (0x2UL) /*!< PORT1 OMR: PS1 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS2_Pos (2UL) /*!< PORT1 OMR: PS2 (Bit 2) */ +#define PORT1_OMR_PS2_Msk (0x4UL) /*!< PORT1 OMR: PS2 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS3_Pos (3UL) /*!< PORT1 OMR: PS3 (Bit 3) */ +#define PORT1_OMR_PS3_Msk (0x8UL) /*!< PORT1 OMR: PS3 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS4_Pos (4UL) /*!< PORT1 OMR: PS4 (Bit 4) */ +#define PORT1_OMR_PS4_Msk (0x10UL) /*!< PORT1 OMR: PS4 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS5_Pos (5UL) /*!< PORT1 OMR: PS5 (Bit 5) */ +#define PORT1_OMR_PS5_Msk (0x20UL) /*!< PORT1 OMR: PS5 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS6_Pos (6UL) /*!< PORT1 OMR: PS6 (Bit 6) */ +#define PORT1_OMR_PS6_Msk (0x40UL) /*!< PORT1 OMR: PS6 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS7_Pos (7UL) /*!< PORT1 OMR: PS7 (Bit 7) */ +#define PORT1_OMR_PS7_Msk (0x80UL) /*!< PORT1 OMR: PS7 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS8_Pos (8UL) /*!< PORT1 OMR: PS8 (Bit 8) */ +#define PORT1_OMR_PS8_Msk (0x100UL) /*!< PORT1 OMR: PS8 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS9_Pos (9UL) /*!< PORT1 OMR: PS9 (Bit 9) */ +#define PORT1_OMR_PS9_Msk (0x200UL) /*!< PORT1 OMR: PS9 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS10_Pos (10UL) /*!< PORT1 OMR: PS10 (Bit 10) */ +#define PORT1_OMR_PS10_Msk (0x400UL) /*!< PORT1 OMR: PS10 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS11_Pos (11UL) /*!< PORT1 OMR: PS11 (Bit 11) */ +#define PORT1_OMR_PS11_Msk (0x800UL) /*!< PORT1 OMR: PS11 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS12_Pos (12UL) /*!< PORT1 OMR: PS12 (Bit 12) */ +#define PORT1_OMR_PS12_Msk (0x1000UL) /*!< PORT1 OMR: PS12 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS13_Pos (13UL) /*!< PORT1 OMR: PS13 (Bit 13) */ +#define PORT1_OMR_PS13_Msk (0x2000UL) /*!< PORT1 OMR: PS13 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS14_Pos (14UL) /*!< PORT1 OMR: PS14 (Bit 14) */ +#define PORT1_OMR_PS14_Msk (0x4000UL) /*!< PORT1 OMR: PS14 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PS15_Pos (15UL) /*!< PORT1 OMR: PS15 (Bit 15) */ +#define PORT1_OMR_PS15_Msk (0x8000UL) /*!< PORT1 OMR: PS15 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR0_Pos (16UL) /*!< PORT1 OMR: PR0 (Bit 16) */ +#define PORT1_OMR_PR0_Msk (0x10000UL) /*!< PORT1 OMR: PR0 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR1_Pos (17UL) /*!< PORT1 OMR: PR1 (Bit 17) */ +#define PORT1_OMR_PR1_Msk (0x20000UL) /*!< PORT1 OMR: PR1 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR2_Pos (18UL) /*!< PORT1 OMR: PR2 (Bit 18) */ +#define PORT1_OMR_PR2_Msk (0x40000UL) /*!< PORT1 OMR: PR2 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR3_Pos (19UL) /*!< PORT1 OMR: PR3 (Bit 19) */ +#define PORT1_OMR_PR3_Msk (0x80000UL) /*!< PORT1 OMR: PR3 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR4_Pos (20UL) /*!< PORT1 OMR: PR4 (Bit 20) */ +#define PORT1_OMR_PR4_Msk (0x100000UL) /*!< PORT1 OMR: PR4 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR5_Pos (21UL) /*!< PORT1 OMR: PR5 (Bit 21) */ +#define PORT1_OMR_PR5_Msk (0x200000UL) /*!< PORT1 OMR: PR5 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR6_Pos (22UL) /*!< PORT1 OMR: PR6 (Bit 22) */ +#define PORT1_OMR_PR6_Msk (0x400000UL) /*!< PORT1 OMR: PR6 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR7_Pos (23UL) /*!< PORT1 OMR: PR7 (Bit 23) */ +#define PORT1_OMR_PR7_Msk (0x800000UL) /*!< PORT1 OMR: PR7 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR8_Pos (24UL) /*!< PORT1 OMR: PR8 (Bit 24) */ +#define PORT1_OMR_PR8_Msk (0x1000000UL) /*!< PORT1 OMR: PR8 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR9_Pos (25UL) /*!< PORT1 OMR: PR9 (Bit 25) */ +#define PORT1_OMR_PR9_Msk (0x2000000UL) /*!< PORT1 OMR: PR9 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR10_Pos (26UL) /*!< PORT1 OMR: PR10 (Bit 26) */ +#define PORT1_OMR_PR10_Msk (0x4000000UL) /*!< PORT1 OMR: PR10 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR11_Pos (27UL) /*!< PORT1 OMR: PR11 (Bit 27) */ +#define PORT1_OMR_PR11_Msk (0x8000000UL) /*!< PORT1 OMR: PR11 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR12_Pos (28UL) /*!< PORT1 OMR: PR12 (Bit 28) */ +#define PORT1_OMR_PR12_Msk (0x10000000UL) /*!< PORT1 OMR: PR12 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR13_Pos (29UL) /*!< PORT1 OMR: PR13 (Bit 29) */ +#define PORT1_OMR_PR13_Msk (0x20000000UL) /*!< PORT1 OMR: PR13 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR14_Pos (30UL) /*!< PORT1 OMR: PR14 (Bit 30) */ +#define PORT1_OMR_PR14_Msk (0x40000000UL) /*!< PORT1 OMR: PR14 (Bitfield-Mask: 0x01) */ +#define PORT1_OMR_PR15_Pos (31UL) /*!< PORT1 OMR: PR15 (Bit 31) */ +#define PORT1_OMR_PR15_Msk (0x80000000UL) /*!< PORT1 OMR: PR15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT1_IOCR0 -------------------------------- */ +#define PORT1_IOCR0_PC0_Pos (3UL) /*!< PORT1 IOCR0: PC0 (Bit 3) */ +#define PORT1_IOCR0_PC0_Msk (0xf8UL) /*!< PORT1 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR0_PC1_Pos (11UL) /*!< PORT1 IOCR0: PC1 (Bit 11) */ +#define PORT1_IOCR0_PC1_Msk (0xf800UL) /*!< PORT1 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR0_PC2_Pos (19UL) /*!< PORT1 IOCR0: PC2 (Bit 19) */ +#define PORT1_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT1 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR0_PC3_Pos (27UL) /*!< PORT1 IOCR0: PC3 (Bit 27) */ +#define PORT1_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT1 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ + +/* --------------------------------- PORT1_IOCR4 -------------------------------- */ +#define PORT1_IOCR4_PC4_Pos (3UL) /*!< PORT1 IOCR4: PC4 (Bit 3) */ +#define PORT1_IOCR4_PC4_Msk (0xf8UL) /*!< PORT1 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR4_PC5_Pos (11UL) /*!< PORT1 IOCR4: PC5 (Bit 11) */ +#define PORT1_IOCR4_PC5_Msk (0xf800UL) /*!< PORT1 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR4_PC6_Pos (19UL) /*!< PORT1 IOCR4: PC6 (Bit 19) */ +#define PORT1_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT1 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR4_PC7_Pos (27UL) /*!< PORT1 IOCR4: PC7 (Bit 27) */ +#define PORT1_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT1 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ + +/* --------------------------------- PORT1_IOCR8 -------------------------------- */ +#define PORT1_IOCR8_PC8_Pos (3UL) /*!< PORT1 IOCR8: PC8 (Bit 3) */ +#define PORT1_IOCR8_PC8_Msk (0xf8UL) /*!< PORT1 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR8_PC9_Pos (11UL) /*!< PORT1 IOCR8: PC9 (Bit 11) */ +#define PORT1_IOCR8_PC9_Msk (0xf800UL) /*!< PORT1 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR8_PC10_Pos (19UL) /*!< PORT1 IOCR8: PC10 (Bit 19) */ +#define PORT1_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT1 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR8_PC11_Pos (27UL) /*!< PORT1 IOCR8: PC11 (Bit 27) */ +#define PORT1_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT1 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- PORT1_IOCR12 -------------------------------- */ +#define PORT1_IOCR12_PC12_Pos (3UL) /*!< PORT1 IOCR12: PC12 (Bit 3) */ +#define PORT1_IOCR12_PC12_Msk (0xf8UL) /*!< PORT1 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR12_PC13_Pos (11UL) /*!< PORT1 IOCR12: PC13 (Bit 11) */ +#define PORT1_IOCR12_PC13_Msk (0xf800UL) /*!< PORT1 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR12_PC14_Pos (19UL) /*!< PORT1 IOCR12: PC14 (Bit 19) */ +#define PORT1_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT1 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ +#define PORT1_IOCR12_PC15_Pos (27UL) /*!< PORT1 IOCR12: PC15 (Bit 27) */ +#define PORT1_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT1 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ + +/* ---------------------------------- PORT1_IN ---------------------------------- */ +#define PORT1_IN_P0_Pos (0UL) /*!< PORT1 IN: P0 (Bit 0) */ +#define PORT1_IN_P0_Msk (0x1UL) /*!< PORT1 IN: P0 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P1_Pos (1UL) /*!< PORT1 IN: P1 (Bit 1) */ +#define PORT1_IN_P1_Msk (0x2UL) /*!< PORT1 IN: P1 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P2_Pos (2UL) /*!< PORT1 IN: P2 (Bit 2) */ +#define PORT1_IN_P2_Msk (0x4UL) /*!< PORT1 IN: P2 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P3_Pos (3UL) /*!< PORT1 IN: P3 (Bit 3) */ +#define PORT1_IN_P3_Msk (0x8UL) /*!< PORT1 IN: P3 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P4_Pos (4UL) /*!< PORT1 IN: P4 (Bit 4) */ +#define PORT1_IN_P4_Msk (0x10UL) /*!< PORT1 IN: P4 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P5_Pos (5UL) /*!< PORT1 IN: P5 (Bit 5) */ +#define PORT1_IN_P5_Msk (0x20UL) /*!< PORT1 IN: P5 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P6_Pos (6UL) /*!< PORT1 IN: P6 (Bit 6) */ +#define PORT1_IN_P6_Msk (0x40UL) /*!< PORT1 IN: P6 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P7_Pos (7UL) /*!< PORT1 IN: P7 (Bit 7) */ +#define PORT1_IN_P7_Msk (0x80UL) /*!< PORT1 IN: P7 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P8_Pos (8UL) /*!< PORT1 IN: P8 (Bit 8) */ +#define PORT1_IN_P8_Msk (0x100UL) /*!< PORT1 IN: P8 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P9_Pos (9UL) /*!< PORT1 IN: P9 (Bit 9) */ +#define PORT1_IN_P9_Msk (0x200UL) /*!< PORT1 IN: P9 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P10_Pos (10UL) /*!< PORT1 IN: P10 (Bit 10) */ +#define PORT1_IN_P10_Msk (0x400UL) /*!< PORT1 IN: P10 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P11_Pos (11UL) /*!< PORT1 IN: P11 (Bit 11) */ +#define PORT1_IN_P11_Msk (0x800UL) /*!< PORT1 IN: P11 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P12_Pos (12UL) /*!< PORT1 IN: P12 (Bit 12) */ +#define PORT1_IN_P12_Msk (0x1000UL) /*!< PORT1 IN: P12 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P13_Pos (13UL) /*!< PORT1 IN: P13 (Bit 13) */ +#define PORT1_IN_P13_Msk (0x2000UL) /*!< PORT1 IN: P13 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P14_Pos (14UL) /*!< PORT1 IN: P14 (Bit 14) */ +#define PORT1_IN_P14_Msk (0x4000UL) /*!< PORT1 IN: P14 (Bitfield-Mask: 0x01) */ +#define PORT1_IN_P15_Pos (15UL) /*!< PORT1 IN: P15 (Bit 15) */ +#define PORT1_IN_P15_Msk (0x8000UL) /*!< PORT1 IN: P15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT1_PDR0 --------------------------------- */ +#define PORT1_PDR0_PD0_Pos (0UL) /*!< PORT1 PDR0: PD0 (Bit 0) */ +#define PORT1_PDR0_PD0_Msk (0x7UL) /*!< PORT1 PDR0: PD0 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR0_PD1_Pos (4UL) /*!< PORT1 PDR0: PD1 (Bit 4) */ +#define PORT1_PDR0_PD1_Msk (0x70UL) /*!< PORT1 PDR0: PD1 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR0_PD2_Pos (8UL) /*!< PORT1 PDR0: PD2 (Bit 8) */ +#define PORT1_PDR0_PD2_Msk (0x700UL) /*!< PORT1 PDR0: PD2 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR0_PD3_Pos (12UL) /*!< PORT1 PDR0: PD3 (Bit 12) */ +#define PORT1_PDR0_PD3_Msk (0x7000UL) /*!< PORT1 PDR0: PD3 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR0_PD4_Pos (16UL) /*!< PORT1 PDR0: PD4 (Bit 16) */ +#define PORT1_PDR0_PD4_Msk (0x70000UL) /*!< PORT1 PDR0: PD4 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR0_PD5_Pos (20UL) /*!< PORT1 PDR0: PD5 (Bit 20) */ +#define PORT1_PDR0_PD5_Msk (0x700000UL) /*!< PORT1 PDR0: PD5 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR0_PD6_Pos (24UL) /*!< PORT1 PDR0: PD6 (Bit 24) */ +#define PORT1_PDR0_PD6_Msk (0x7000000UL) /*!< PORT1 PDR0: PD6 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR0_PD7_Pos (28UL) /*!< PORT1 PDR0: PD7 (Bit 28) */ +#define PORT1_PDR0_PD7_Msk (0x70000000UL) /*!< PORT1 PDR0: PD7 (Bitfield-Mask: 0x07) */ + +/* --------------------------------- PORT1_PDR1 --------------------------------- */ +#define PORT1_PDR1_PD8_Pos (0UL) /*!< PORT1 PDR1: PD8 (Bit 0) */ +#define PORT1_PDR1_PD8_Msk (0x7UL) /*!< PORT1 PDR1: PD8 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR1_PD9_Pos (4UL) /*!< PORT1 PDR1: PD9 (Bit 4) */ +#define PORT1_PDR1_PD9_Msk (0x70UL) /*!< PORT1 PDR1: PD9 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR1_PD10_Pos (8UL) /*!< PORT1 PDR1: PD10 (Bit 8) */ +#define PORT1_PDR1_PD10_Msk (0x700UL) /*!< PORT1 PDR1: PD10 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR1_PD11_Pos (12UL) /*!< PORT1 PDR1: PD11 (Bit 12) */ +#define PORT1_PDR1_PD11_Msk (0x7000UL) /*!< PORT1 PDR1: PD11 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR1_PD12_Pos (16UL) /*!< PORT1 PDR1: PD12 (Bit 16) */ +#define PORT1_PDR1_PD12_Msk (0x70000UL) /*!< PORT1 PDR1: PD12 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR1_PD13_Pos (20UL) /*!< PORT1 PDR1: PD13 (Bit 20) */ +#define PORT1_PDR1_PD13_Msk (0x700000UL) /*!< PORT1 PDR1: PD13 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR1_PD14_Pos (24UL) /*!< PORT1 PDR1: PD14 (Bit 24) */ +#define PORT1_PDR1_PD14_Msk (0x7000000UL) /*!< PORT1 PDR1: PD14 (Bitfield-Mask: 0x07) */ +#define PORT1_PDR1_PD15_Pos (28UL) /*!< PORT1 PDR1: PD15 (Bit 28) */ +#define PORT1_PDR1_PD15_Msk (0x70000000UL) /*!< PORT1 PDR1: PD15 (Bitfield-Mask: 0x07) */ + +/* --------------------------------- PORT1_PDISC -------------------------------- */ +#define PORT1_PDISC_PDIS0_Pos (0UL) /*!< PORT1 PDISC: PDIS0 (Bit 0) */ +#define PORT1_PDISC_PDIS0_Msk (0x1UL) /*!< PORT1 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS1_Pos (1UL) /*!< PORT1 PDISC: PDIS1 (Bit 1) */ +#define PORT1_PDISC_PDIS1_Msk (0x2UL) /*!< PORT1 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS2_Pos (2UL) /*!< PORT1 PDISC: PDIS2 (Bit 2) */ +#define PORT1_PDISC_PDIS2_Msk (0x4UL) /*!< PORT1 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS3_Pos (3UL) /*!< PORT1 PDISC: PDIS3 (Bit 3) */ +#define PORT1_PDISC_PDIS3_Msk (0x8UL) /*!< PORT1 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS4_Pos (4UL) /*!< PORT1 PDISC: PDIS4 (Bit 4) */ +#define PORT1_PDISC_PDIS4_Msk (0x10UL) /*!< PORT1 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS5_Pos (5UL) /*!< PORT1 PDISC: PDIS5 (Bit 5) */ +#define PORT1_PDISC_PDIS5_Msk (0x20UL) /*!< PORT1 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS6_Pos (6UL) /*!< PORT1 PDISC: PDIS6 (Bit 6) */ +#define PORT1_PDISC_PDIS6_Msk (0x40UL) /*!< PORT1 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS7_Pos (7UL) /*!< PORT1 PDISC: PDIS7 (Bit 7) */ +#define PORT1_PDISC_PDIS7_Msk (0x80UL) /*!< PORT1 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS8_Pos (8UL) /*!< PORT1 PDISC: PDIS8 (Bit 8) */ +#define PORT1_PDISC_PDIS8_Msk (0x100UL) /*!< PORT1 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS9_Pos (9UL) /*!< PORT1 PDISC: PDIS9 (Bit 9) */ +#define PORT1_PDISC_PDIS9_Msk (0x200UL) /*!< PORT1 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS10_Pos (10UL) /*!< PORT1 PDISC: PDIS10 (Bit 10) */ +#define PORT1_PDISC_PDIS10_Msk (0x400UL) /*!< PORT1 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS11_Pos (11UL) /*!< PORT1 PDISC: PDIS11 (Bit 11) */ +#define PORT1_PDISC_PDIS11_Msk (0x800UL) /*!< PORT1 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS12_Pos (12UL) /*!< PORT1 PDISC: PDIS12 (Bit 12) */ +#define PORT1_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT1 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS13_Pos (13UL) /*!< PORT1 PDISC: PDIS13 (Bit 13) */ +#define PORT1_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT1 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS14_Pos (14UL) /*!< PORT1 PDISC: PDIS14 (Bit 14) */ +#define PORT1_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT1 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ +#define PORT1_PDISC_PDIS15_Pos (15UL) /*!< PORT1 PDISC: PDIS15 (Bit 15) */ +#define PORT1_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT1 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT1_PPS --------------------------------- */ +#define PORT1_PPS_PPS0_Pos (0UL) /*!< PORT1 PPS: PPS0 (Bit 0) */ +#define PORT1_PPS_PPS0_Msk (0x1UL) /*!< PORT1 PPS: PPS0 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS1_Pos (1UL) /*!< PORT1 PPS: PPS1 (Bit 1) */ +#define PORT1_PPS_PPS1_Msk (0x2UL) /*!< PORT1 PPS: PPS1 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS2_Pos (2UL) /*!< PORT1 PPS: PPS2 (Bit 2) */ +#define PORT1_PPS_PPS2_Msk (0x4UL) /*!< PORT1 PPS: PPS2 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS3_Pos (3UL) /*!< PORT1 PPS: PPS3 (Bit 3) */ +#define PORT1_PPS_PPS3_Msk (0x8UL) /*!< PORT1 PPS: PPS3 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS4_Pos (4UL) /*!< PORT1 PPS: PPS4 (Bit 4) */ +#define PORT1_PPS_PPS4_Msk (0x10UL) /*!< PORT1 PPS: PPS4 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS5_Pos (5UL) /*!< PORT1 PPS: PPS5 (Bit 5) */ +#define PORT1_PPS_PPS5_Msk (0x20UL) /*!< PORT1 PPS: PPS5 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS6_Pos (6UL) /*!< PORT1 PPS: PPS6 (Bit 6) */ +#define PORT1_PPS_PPS6_Msk (0x40UL) /*!< PORT1 PPS: PPS6 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS7_Pos (7UL) /*!< PORT1 PPS: PPS7 (Bit 7) */ +#define PORT1_PPS_PPS7_Msk (0x80UL) /*!< PORT1 PPS: PPS7 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS8_Pos (8UL) /*!< PORT1 PPS: PPS8 (Bit 8) */ +#define PORT1_PPS_PPS8_Msk (0x100UL) /*!< PORT1 PPS: PPS8 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS9_Pos (9UL) /*!< PORT1 PPS: PPS9 (Bit 9) */ +#define PORT1_PPS_PPS9_Msk (0x200UL) /*!< PORT1 PPS: PPS9 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS10_Pos (10UL) /*!< PORT1 PPS: PPS10 (Bit 10) */ +#define PORT1_PPS_PPS10_Msk (0x400UL) /*!< PORT1 PPS: PPS10 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS11_Pos (11UL) /*!< PORT1 PPS: PPS11 (Bit 11) */ +#define PORT1_PPS_PPS11_Msk (0x800UL) /*!< PORT1 PPS: PPS11 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS12_Pos (12UL) /*!< PORT1 PPS: PPS12 (Bit 12) */ +#define PORT1_PPS_PPS12_Msk (0x1000UL) /*!< PORT1 PPS: PPS12 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS13_Pos (13UL) /*!< PORT1 PPS: PPS13 (Bit 13) */ +#define PORT1_PPS_PPS13_Msk (0x2000UL) /*!< PORT1 PPS: PPS13 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS14_Pos (14UL) /*!< PORT1 PPS: PPS14 (Bit 14) */ +#define PORT1_PPS_PPS14_Msk (0x4000UL) /*!< PORT1 PPS: PPS14 (Bitfield-Mask: 0x01) */ +#define PORT1_PPS_PPS15_Pos (15UL) /*!< PORT1 PPS: PPS15 (Bit 15) */ +#define PORT1_PPS_PPS15_Msk (0x8000UL) /*!< PORT1 PPS: PPS15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT1_HWSEL -------------------------------- */ +#define PORT1_HWSEL_HW0_Pos (0UL) /*!< PORT1 HWSEL: HW0 (Bit 0) */ +#define PORT1_HWSEL_HW0_Msk (0x3UL) /*!< PORT1 HWSEL: HW0 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW1_Pos (2UL) /*!< PORT1 HWSEL: HW1 (Bit 2) */ +#define PORT1_HWSEL_HW1_Msk (0xcUL) /*!< PORT1 HWSEL: HW1 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW2_Pos (4UL) /*!< PORT1 HWSEL: HW2 (Bit 4) */ +#define PORT1_HWSEL_HW2_Msk (0x30UL) /*!< PORT1 HWSEL: HW2 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW3_Pos (6UL) /*!< PORT1 HWSEL: HW3 (Bit 6) */ +#define PORT1_HWSEL_HW3_Msk (0xc0UL) /*!< PORT1 HWSEL: HW3 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW4_Pos (8UL) /*!< PORT1 HWSEL: HW4 (Bit 8) */ +#define PORT1_HWSEL_HW4_Msk (0x300UL) /*!< PORT1 HWSEL: HW4 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW5_Pos (10UL) /*!< PORT1 HWSEL: HW5 (Bit 10) */ +#define PORT1_HWSEL_HW5_Msk (0xc00UL) /*!< PORT1 HWSEL: HW5 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW6_Pos (12UL) /*!< PORT1 HWSEL: HW6 (Bit 12) */ +#define PORT1_HWSEL_HW6_Msk (0x3000UL) /*!< PORT1 HWSEL: HW6 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW7_Pos (14UL) /*!< PORT1 HWSEL: HW7 (Bit 14) */ +#define PORT1_HWSEL_HW7_Msk (0xc000UL) /*!< PORT1 HWSEL: HW7 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW8_Pos (16UL) /*!< PORT1 HWSEL: HW8 (Bit 16) */ +#define PORT1_HWSEL_HW8_Msk (0x30000UL) /*!< PORT1 HWSEL: HW8 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW9_Pos (18UL) /*!< PORT1 HWSEL: HW9 (Bit 18) */ +#define PORT1_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT1 HWSEL: HW9 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW10_Pos (20UL) /*!< PORT1 HWSEL: HW10 (Bit 20) */ +#define PORT1_HWSEL_HW10_Msk (0x300000UL) /*!< PORT1 HWSEL: HW10 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW11_Pos (22UL) /*!< PORT1 HWSEL: HW11 (Bit 22) */ +#define PORT1_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT1 HWSEL: HW11 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW12_Pos (24UL) /*!< PORT1 HWSEL: HW12 (Bit 24) */ +#define PORT1_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT1 HWSEL: HW12 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW13_Pos (26UL) /*!< PORT1 HWSEL: HW13 (Bit 26) */ +#define PORT1_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT1 HWSEL: HW13 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW14_Pos (28UL) /*!< PORT1 HWSEL: HW14 (Bit 28) */ +#define PORT1_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT1 HWSEL: HW14 (Bitfield-Mask: 0x03) */ +#define PORT1_HWSEL_HW15_Pos (30UL) /*!< PORT1 HWSEL: HW15 (Bit 30) */ +#define PORT1_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT1 HWSEL: HW15 (Bitfield-Mask: 0x03) */ + + +/* ================================================================================ */ +/* ================ struct 'PORT2' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- PORT2_OUT --------------------------------- */ +#define PORT2_OUT_P0_Pos (0UL) /*!< PORT2 OUT: P0 (Bit 0) */ +#define PORT2_OUT_P0_Msk (0x1UL) /*!< PORT2 OUT: P0 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P1_Pos (1UL) /*!< PORT2 OUT: P1 (Bit 1) */ +#define PORT2_OUT_P1_Msk (0x2UL) /*!< PORT2 OUT: P1 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P2_Pos (2UL) /*!< PORT2 OUT: P2 (Bit 2) */ +#define PORT2_OUT_P2_Msk (0x4UL) /*!< PORT2 OUT: P2 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P3_Pos (3UL) /*!< PORT2 OUT: P3 (Bit 3) */ +#define PORT2_OUT_P3_Msk (0x8UL) /*!< PORT2 OUT: P3 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P4_Pos (4UL) /*!< PORT2 OUT: P4 (Bit 4) */ +#define PORT2_OUT_P4_Msk (0x10UL) /*!< PORT2 OUT: P4 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P5_Pos (5UL) /*!< PORT2 OUT: P5 (Bit 5) */ +#define PORT2_OUT_P5_Msk (0x20UL) /*!< PORT2 OUT: P5 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P6_Pos (6UL) /*!< PORT2 OUT: P6 (Bit 6) */ +#define PORT2_OUT_P6_Msk (0x40UL) /*!< PORT2 OUT: P6 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P7_Pos (7UL) /*!< PORT2 OUT: P7 (Bit 7) */ +#define PORT2_OUT_P7_Msk (0x80UL) /*!< PORT2 OUT: P7 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P8_Pos (8UL) /*!< PORT2 OUT: P8 (Bit 8) */ +#define PORT2_OUT_P8_Msk (0x100UL) /*!< PORT2 OUT: P8 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P9_Pos (9UL) /*!< PORT2 OUT: P9 (Bit 9) */ +#define PORT2_OUT_P9_Msk (0x200UL) /*!< PORT2 OUT: P9 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P10_Pos (10UL) /*!< PORT2 OUT: P10 (Bit 10) */ +#define PORT2_OUT_P10_Msk (0x400UL) /*!< PORT2 OUT: P10 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P11_Pos (11UL) /*!< PORT2 OUT: P11 (Bit 11) */ +#define PORT2_OUT_P11_Msk (0x800UL) /*!< PORT2 OUT: P11 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P12_Pos (12UL) /*!< PORT2 OUT: P12 (Bit 12) */ +#define PORT2_OUT_P12_Msk (0x1000UL) /*!< PORT2 OUT: P12 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P13_Pos (13UL) /*!< PORT2 OUT: P13 (Bit 13) */ +#define PORT2_OUT_P13_Msk (0x2000UL) /*!< PORT2 OUT: P13 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P14_Pos (14UL) /*!< PORT2 OUT: P14 (Bit 14) */ +#define PORT2_OUT_P14_Msk (0x4000UL) /*!< PORT2 OUT: P14 (Bitfield-Mask: 0x01) */ +#define PORT2_OUT_P15_Pos (15UL) /*!< PORT2 OUT: P15 (Bit 15) */ +#define PORT2_OUT_P15_Msk (0x8000UL) /*!< PORT2 OUT: P15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT2_OMR --------------------------------- */ +#define PORT2_OMR_PS0_Pos (0UL) /*!< PORT2 OMR: PS0 (Bit 0) */ +#define PORT2_OMR_PS0_Msk (0x1UL) /*!< PORT2 OMR: PS0 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS1_Pos (1UL) /*!< PORT2 OMR: PS1 (Bit 1) */ +#define PORT2_OMR_PS1_Msk (0x2UL) /*!< PORT2 OMR: PS1 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS2_Pos (2UL) /*!< PORT2 OMR: PS2 (Bit 2) */ +#define PORT2_OMR_PS2_Msk (0x4UL) /*!< PORT2 OMR: PS2 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS3_Pos (3UL) /*!< PORT2 OMR: PS3 (Bit 3) */ +#define PORT2_OMR_PS3_Msk (0x8UL) /*!< PORT2 OMR: PS3 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS4_Pos (4UL) /*!< PORT2 OMR: PS4 (Bit 4) */ +#define PORT2_OMR_PS4_Msk (0x10UL) /*!< PORT2 OMR: PS4 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS5_Pos (5UL) /*!< PORT2 OMR: PS5 (Bit 5) */ +#define PORT2_OMR_PS5_Msk (0x20UL) /*!< PORT2 OMR: PS5 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS6_Pos (6UL) /*!< PORT2 OMR: PS6 (Bit 6) */ +#define PORT2_OMR_PS6_Msk (0x40UL) /*!< PORT2 OMR: PS6 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS7_Pos (7UL) /*!< PORT2 OMR: PS7 (Bit 7) */ +#define PORT2_OMR_PS7_Msk (0x80UL) /*!< PORT2 OMR: PS7 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS8_Pos (8UL) /*!< PORT2 OMR: PS8 (Bit 8) */ +#define PORT2_OMR_PS8_Msk (0x100UL) /*!< PORT2 OMR: PS8 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS9_Pos (9UL) /*!< PORT2 OMR: PS9 (Bit 9) */ +#define PORT2_OMR_PS9_Msk (0x200UL) /*!< PORT2 OMR: PS9 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS10_Pos (10UL) /*!< PORT2 OMR: PS10 (Bit 10) */ +#define PORT2_OMR_PS10_Msk (0x400UL) /*!< PORT2 OMR: PS10 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS11_Pos (11UL) /*!< PORT2 OMR: PS11 (Bit 11) */ +#define PORT2_OMR_PS11_Msk (0x800UL) /*!< PORT2 OMR: PS11 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS12_Pos (12UL) /*!< PORT2 OMR: PS12 (Bit 12) */ +#define PORT2_OMR_PS12_Msk (0x1000UL) /*!< PORT2 OMR: PS12 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS13_Pos (13UL) /*!< PORT2 OMR: PS13 (Bit 13) */ +#define PORT2_OMR_PS13_Msk (0x2000UL) /*!< PORT2 OMR: PS13 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS14_Pos (14UL) /*!< PORT2 OMR: PS14 (Bit 14) */ +#define PORT2_OMR_PS14_Msk (0x4000UL) /*!< PORT2 OMR: PS14 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PS15_Pos (15UL) /*!< PORT2 OMR: PS15 (Bit 15) */ +#define PORT2_OMR_PS15_Msk (0x8000UL) /*!< PORT2 OMR: PS15 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR0_Pos (16UL) /*!< PORT2 OMR: PR0 (Bit 16) */ +#define PORT2_OMR_PR0_Msk (0x10000UL) /*!< PORT2 OMR: PR0 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR1_Pos (17UL) /*!< PORT2 OMR: PR1 (Bit 17) */ +#define PORT2_OMR_PR1_Msk (0x20000UL) /*!< PORT2 OMR: PR1 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR2_Pos (18UL) /*!< PORT2 OMR: PR2 (Bit 18) */ +#define PORT2_OMR_PR2_Msk (0x40000UL) /*!< PORT2 OMR: PR2 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR3_Pos (19UL) /*!< PORT2 OMR: PR3 (Bit 19) */ +#define PORT2_OMR_PR3_Msk (0x80000UL) /*!< PORT2 OMR: PR3 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR4_Pos (20UL) /*!< PORT2 OMR: PR4 (Bit 20) */ +#define PORT2_OMR_PR4_Msk (0x100000UL) /*!< PORT2 OMR: PR4 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR5_Pos (21UL) /*!< PORT2 OMR: PR5 (Bit 21) */ +#define PORT2_OMR_PR5_Msk (0x200000UL) /*!< PORT2 OMR: PR5 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR6_Pos (22UL) /*!< PORT2 OMR: PR6 (Bit 22) */ +#define PORT2_OMR_PR6_Msk (0x400000UL) /*!< PORT2 OMR: PR6 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR7_Pos (23UL) /*!< PORT2 OMR: PR7 (Bit 23) */ +#define PORT2_OMR_PR7_Msk (0x800000UL) /*!< PORT2 OMR: PR7 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR8_Pos (24UL) /*!< PORT2 OMR: PR8 (Bit 24) */ +#define PORT2_OMR_PR8_Msk (0x1000000UL) /*!< PORT2 OMR: PR8 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR9_Pos (25UL) /*!< PORT2 OMR: PR9 (Bit 25) */ +#define PORT2_OMR_PR9_Msk (0x2000000UL) /*!< PORT2 OMR: PR9 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR10_Pos (26UL) /*!< PORT2 OMR: PR10 (Bit 26) */ +#define PORT2_OMR_PR10_Msk (0x4000000UL) /*!< PORT2 OMR: PR10 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR11_Pos (27UL) /*!< PORT2 OMR: PR11 (Bit 27) */ +#define PORT2_OMR_PR11_Msk (0x8000000UL) /*!< PORT2 OMR: PR11 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR12_Pos (28UL) /*!< PORT2 OMR: PR12 (Bit 28) */ +#define PORT2_OMR_PR12_Msk (0x10000000UL) /*!< PORT2 OMR: PR12 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR13_Pos (29UL) /*!< PORT2 OMR: PR13 (Bit 29) */ +#define PORT2_OMR_PR13_Msk (0x20000000UL) /*!< PORT2 OMR: PR13 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR14_Pos (30UL) /*!< PORT2 OMR: PR14 (Bit 30) */ +#define PORT2_OMR_PR14_Msk (0x40000000UL) /*!< PORT2 OMR: PR14 (Bitfield-Mask: 0x01) */ +#define PORT2_OMR_PR15_Pos (31UL) /*!< PORT2 OMR: PR15 (Bit 31) */ +#define PORT2_OMR_PR15_Msk (0x80000000UL) /*!< PORT2 OMR: PR15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT2_IOCR0 -------------------------------- */ +#define PORT2_IOCR0_PC0_Pos (3UL) /*!< PORT2 IOCR0: PC0 (Bit 3) */ +#define PORT2_IOCR0_PC0_Msk (0xf8UL) /*!< PORT2 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR0_PC1_Pos (11UL) /*!< PORT2 IOCR0: PC1 (Bit 11) */ +#define PORT2_IOCR0_PC1_Msk (0xf800UL) /*!< PORT2 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR0_PC2_Pos (19UL) /*!< PORT2 IOCR0: PC2 (Bit 19) */ +#define PORT2_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT2 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR0_PC3_Pos (27UL) /*!< PORT2 IOCR0: PC3 (Bit 27) */ +#define PORT2_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT2 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ + +/* --------------------------------- PORT2_IOCR4 -------------------------------- */ +#define PORT2_IOCR4_PC4_Pos (3UL) /*!< PORT2 IOCR4: PC4 (Bit 3) */ +#define PORT2_IOCR4_PC4_Msk (0xf8UL) /*!< PORT2 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR4_PC5_Pos (11UL) /*!< PORT2 IOCR4: PC5 (Bit 11) */ +#define PORT2_IOCR4_PC5_Msk (0xf800UL) /*!< PORT2 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR4_PC6_Pos (19UL) /*!< PORT2 IOCR4: PC6 (Bit 19) */ +#define PORT2_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT2 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR4_PC7_Pos (27UL) /*!< PORT2 IOCR4: PC7 (Bit 27) */ +#define PORT2_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT2 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ + +/* --------------------------------- PORT2_IOCR8 -------------------------------- */ +#define PORT2_IOCR8_PC8_Pos (3UL) /*!< PORT2 IOCR8: PC8 (Bit 3) */ +#define PORT2_IOCR8_PC8_Msk (0xf8UL) /*!< PORT2 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR8_PC9_Pos (11UL) /*!< PORT2 IOCR8: PC9 (Bit 11) */ +#define PORT2_IOCR8_PC9_Msk (0xf800UL) /*!< PORT2 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR8_PC10_Pos (19UL) /*!< PORT2 IOCR8: PC10 (Bit 19) */ +#define PORT2_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT2 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR8_PC11_Pos (27UL) /*!< PORT2 IOCR8: PC11 (Bit 27) */ +#define PORT2_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT2 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- PORT2_IOCR12 -------------------------------- */ +#define PORT2_IOCR12_PC12_Pos (3UL) /*!< PORT2 IOCR12: PC12 (Bit 3) */ +#define PORT2_IOCR12_PC12_Msk (0xf8UL) /*!< PORT2 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR12_PC13_Pos (11UL) /*!< PORT2 IOCR12: PC13 (Bit 11) */ +#define PORT2_IOCR12_PC13_Msk (0xf800UL) /*!< PORT2 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR12_PC14_Pos (19UL) /*!< PORT2 IOCR12: PC14 (Bit 19) */ +#define PORT2_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT2 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ +#define PORT2_IOCR12_PC15_Pos (27UL) /*!< PORT2 IOCR12: PC15 (Bit 27) */ +#define PORT2_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT2 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ + +/* ---------------------------------- PORT2_IN ---------------------------------- */ +#define PORT2_IN_P0_Pos (0UL) /*!< PORT2 IN: P0 (Bit 0) */ +#define PORT2_IN_P0_Msk (0x1UL) /*!< PORT2 IN: P0 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P1_Pos (1UL) /*!< PORT2 IN: P1 (Bit 1) */ +#define PORT2_IN_P1_Msk (0x2UL) /*!< PORT2 IN: P1 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P2_Pos (2UL) /*!< PORT2 IN: P2 (Bit 2) */ +#define PORT2_IN_P2_Msk (0x4UL) /*!< PORT2 IN: P2 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P3_Pos (3UL) /*!< PORT2 IN: P3 (Bit 3) */ +#define PORT2_IN_P3_Msk (0x8UL) /*!< PORT2 IN: P3 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P4_Pos (4UL) /*!< PORT2 IN: P4 (Bit 4) */ +#define PORT2_IN_P4_Msk (0x10UL) /*!< PORT2 IN: P4 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P5_Pos (5UL) /*!< PORT2 IN: P5 (Bit 5) */ +#define PORT2_IN_P5_Msk (0x20UL) /*!< PORT2 IN: P5 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P6_Pos (6UL) /*!< PORT2 IN: P6 (Bit 6) */ +#define PORT2_IN_P6_Msk (0x40UL) /*!< PORT2 IN: P6 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P7_Pos (7UL) /*!< PORT2 IN: P7 (Bit 7) */ +#define PORT2_IN_P7_Msk (0x80UL) /*!< PORT2 IN: P7 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P8_Pos (8UL) /*!< PORT2 IN: P8 (Bit 8) */ +#define PORT2_IN_P8_Msk (0x100UL) /*!< PORT2 IN: P8 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P9_Pos (9UL) /*!< PORT2 IN: P9 (Bit 9) */ +#define PORT2_IN_P9_Msk (0x200UL) /*!< PORT2 IN: P9 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P10_Pos (10UL) /*!< PORT2 IN: P10 (Bit 10) */ +#define PORT2_IN_P10_Msk (0x400UL) /*!< PORT2 IN: P10 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P11_Pos (11UL) /*!< PORT2 IN: P11 (Bit 11) */ +#define PORT2_IN_P11_Msk (0x800UL) /*!< PORT2 IN: P11 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P12_Pos (12UL) /*!< PORT2 IN: P12 (Bit 12) */ +#define PORT2_IN_P12_Msk (0x1000UL) /*!< PORT2 IN: P12 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P13_Pos (13UL) /*!< PORT2 IN: P13 (Bit 13) */ +#define PORT2_IN_P13_Msk (0x2000UL) /*!< PORT2 IN: P13 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P14_Pos (14UL) /*!< PORT2 IN: P14 (Bit 14) */ +#define PORT2_IN_P14_Msk (0x4000UL) /*!< PORT2 IN: P14 (Bitfield-Mask: 0x01) */ +#define PORT2_IN_P15_Pos (15UL) /*!< PORT2 IN: P15 (Bit 15) */ +#define PORT2_IN_P15_Msk (0x8000UL) /*!< PORT2 IN: P15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT2_PDR0 --------------------------------- */ +#define PORT2_PDR0_PD0_Pos (0UL) /*!< PORT2 PDR0: PD0 (Bit 0) */ +#define PORT2_PDR0_PD0_Msk (0x7UL) /*!< PORT2 PDR0: PD0 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR0_PD1_Pos (4UL) /*!< PORT2 PDR0: PD1 (Bit 4) */ +#define PORT2_PDR0_PD1_Msk (0x70UL) /*!< PORT2 PDR0: PD1 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR0_PD2_Pos (8UL) /*!< PORT2 PDR0: PD2 (Bit 8) */ +#define PORT2_PDR0_PD2_Msk (0x700UL) /*!< PORT2 PDR0: PD2 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR0_PD3_Pos (12UL) /*!< PORT2 PDR0: PD3 (Bit 12) */ +#define PORT2_PDR0_PD3_Msk (0x7000UL) /*!< PORT2 PDR0: PD3 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR0_PD4_Pos (16UL) /*!< PORT2 PDR0: PD4 (Bit 16) */ +#define PORT2_PDR0_PD4_Msk (0x70000UL) /*!< PORT2 PDR0: PD4 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR0_PD5_Pos (20UL) /*!< PORT2 PDR0: PD5 (Bit 20) */ +#define PORT2_PDR0_PD5_Msk (0x700000UL) /*!< PORT2 PDR0: PD5 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR0_PD6_Pos (24UL) /*!< PORT2 PDR0: PD6 (Bit 24) */ +#define PORT2_PDR0_PD6_Msk (0x7000000UL) /*!< PORT2 PDR0: PD6 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR0_PD7_Pos (28UL) /*!< PORT2 PDR0: PD7 (Bit 28) */ +#define PORT2_PDR0_PD7_Msk (0x70000000UL) /*!< PORT2 PDR0: PD7 (Bitfield-Mask: 0x07) */ + +/* --------------------------------- PORT2_PDR1 --------------------------------- */ +#define PORT2_PDR1_PD8_Pos (0UL) /*!< PORT2 PDR1: PD8 (Bit 0) */ +#define PORT2_PDR1_PD8_Msk (0x7UL) /*!< PORT2 PDR1: PD8 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR1_PD9_Pos (4UL) /*!< PORT2 PDR1: PD9 (Bit 4) */ +#define PORT2_PDR1_PD9_Msk (0x70UL) /*!< PORT2 PDR1: PD9 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR1_PD10_Pos (8UL) /*!< PORT2 PDR1: PD10 (Bit 8) */ +#define PORT2_PDR1_PD10_Msk (0x700UL) /*!< PORT2 PDR1: PD10 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR1_PD11_Pos (12UL) /*!< PORT2 PDR1: PD11 (Bit 12) */ +#define PORT2_PDR1_PD11_Msk (0x7000UL) /*!< PORT2 PDR1: PD11 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR1_PD12_Pos (16UL) /*!< PORT2 PDR1: PD12 (Bit 16) */ +#define PORT2_PDR1_PD12_Msk (0x70000UL) /*!< PORT2 PDR1: PD12 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR1_PD13_Pos (20UL) /*!< PORT2 PDR1: PD13 (Bit 20) */ +#define PORT2_PDR1_PD13_Msk (0x700000UL) /*!< PORT2 PDR1: PD13 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR1_PD14_Pos (24UL) /*!< PORT2 PDR1: PD14 (Bit 24) */ +#define PORT2_PDR1_PD14_Msk (0x7000000UL) /*!< PORT2 PDR1: PD14 (Bitfield-Mask: 0x07) */ +#define PORT2_PDR1_PD15_Pos (28UL) /*!< PORT2 PDR1: PD15 (Bit 28) */ +#define PORT2_PDR1_PD15_Msk (0x70000000UL) /*!< PORT2 PDR1: PD15 (Bitfield-Mask: 0x07) */ + +/* --------------------------------- PORT2_PDISC -------------------------------- */ +#define PORT2_PDISC_PDIS0_Pos (0UL) /*!< PORT2 PDISC: PDIS0 (Bit 0) */ +#define PORT2_PDISC_PDIS0_Msk (0x1UL) /*!< PORT2 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS1_Pos (1UL) /*!< PORT2 PDISC: PDIS1 (Bit 1) */ +#define PORT2_PDISC_PDIS1_Msk (0x2UL) /*!< PORT2 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS2_Pos (2UL) /*!< PORT2 PDISC: PDIS2 (Bit 2) */ +#define PORT2_PDISC_PDIS2_Msk (0x4UL) /*!< PORT2 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS3_Pos (3UL) /*!< PORT2 PDISC: PDIS3 (Bit 3) */ +#define PORT2_PDISC_PDIS3_Msk (0x8UL) /*!< PORT2 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS4_Pos (4UL) /*!< PORT2 PDISC: PDIS4 (Bit 4) */ +#define PORT2_PDISC_PDIS4_Msk (0x10UL) /*!< PORT2 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS5_Pos (5UL) /*!< PORT2 PDISC: PDIS5 (Bit 5) */ +#define PORT2_PDISC_PDIS5_Msk (0x20UL) /*!< PORT2 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS6_Pos (6UL) /*!< PORT2 PDISC: PDIS6 (Bit 6) */ +#define PORT2_PDISC_PDIS6_Msk (0x40UL) /*!< PORT2 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS7_Pos (7UL) /*!< PORT2 PDISC: PDIS7 (Bit 7) */ +#define PORT2_PDISC_PDIS7_Msk (0x80UL) /*!< PORT2 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS8_Pos (8UL) /*!< PORT2 PDISC: PDIS8 (Bit 8) */ +#define PORT2_PDISC_PDIS8_Msk (0x100UL) /*!< PORT2 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS9_Pos (9UL) /*!< PORT2 PDISC: PDIS9 (Bit 9) */ +#define PORT2_PDISC_PDIS9_Msk (0x200UL) /*!< PORT2 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS10_Pos (10UL) /*!< PORT2 PDISC: PDIS10 (Bit 10) */ +#define PORT2_PDISC_PDIS10_Msk (0x400UL) /*!< PORT2 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS11_Pos (11UL) /*!< PORT2 PDISC: PDIS11 (Bit 11) */ +#define PORT2_PDISC_PDIS11_Msk (0x800UL) /*!< PORT2 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS12_Pos (12UL) /*!< PORT2 PDISC: PDIS12 (Bit 12) */ +#define PORT2_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT2 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS13_Pos (13UL) /*!< PORT2 PDISC: PDIS13 (Bit 13) */ +#define PORT2_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT2 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS14_Pos (14UL) /*!< PORT2 PDISC: PDIS14 (Bit 14) */ +#define PORT2_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT2 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ +#define PORT2_PDISC_PDIS15_Pos (15UL) /*!< PORT2 PDISC: PDIS15 (Bit 15) */ +#define PORT2_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT2 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT2_PPS --------------------------------- */ +#define PORT2_PPS_PPS0_Pos (0UL) /*!< PORT2 PPS: PPS0 (Bit 0) */ +#define PORT2_PPS_PPS0_Msk (0x1UL) /*!< PORT2 PPS: PPS0 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS1_Pos (1UL) /*!< PORT2 PPS: PPS1 (Bit 1) */ +#define PORT2_PPS_PPS1_Msk (0x2UL) /*!< PORT2 PPS: PPS1 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS2_Pos (2UL) /*!< PORT2 PPS: PPS2 (Bit 2) */ +#define PORT2_PPS_PPS2_Msk (0x4UL) /*!< PORT2 PPS: PPS2 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS3_Pos (3UL) /*!< PORT2 PPS: PPS3 (Bit 3) */ +#define PORT2_PPS_PPS3_Msk (0x8UL) /*!< PORT2 PPS: PPS3 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS4_Pos (4UL) /*!< PORT2 PPS: PPS4 (Bit 4) */ +#define PORT2_PPS_PPS4_Msk (0x10UL) /*!< PORT2 PPS: PPS4 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS5_Pos (5UL) /*!< PORT2 PPS: PPS5 (Bit 5) */ +#define PORT2_PPS_PPS5_Msk (0x20UL) /*!< PORT2 PPS: PPS5 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS6_Pos (6UL) /*!< PORT2 PPS: PPS6 (Bit 6) */ +#define PORT2_PPS_PPS6_Msk (0x40UL) /*!< PORT2 PPS: PPS6 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS7_Pos (7UL) /*!< PORT2 PPS: PPS7 (Bit 7) */ +#define PORT2_PPS_PPS7_Msk (0x80UL) /*!< PORT2 PPS: PPS7 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS8_Pos (8UL) /*!< PORT2 PPS: PPS8 (Bit 8) */ +#define PORT2_PPS_PPS8_Msk (0x100UL) /*!< PORT2 PPS: PPS8 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS9_Pos (9UL) /*!< PORT2 PPS: PPS9 (Bit 9) */ +#define PORT2_PPS_PPS9_Msk (0x200UL) /*!< PORT2 PPS: PPS9 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS10_Pos (10UL) /*!< PORT2 PPS: PPS10 (Bit 10) */ +#define PORT2_PPS_PPS10_Msk (0x400UL) /*!< PORT2 PPS: PPS10 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS11_Pos (11UL) /*!< PORT2 PPS: PPS11 (Bit 11) */ +#define PORT2_PPS_PPS11_Msk (0x800UL) /*!< PORT2 PPS: PPS11 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS12_Pos (12UL) /*!< PORT2 PPS: PPS12 (Bit 12) */ +#define PORT2_PPS_PPS12_Msk (0x1000UL) /*!< PORT2 PPS: PPS12 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS13_Pos (13UL) /*!< PORT2 PPS: PPS13 (Bit 13) */ +#define PORT2_PPS_PPS13_Msk (0x2000UL) /*!< PORT2 PPS: PPS13 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS14_Pos (14UL) /*!< PORT2 PPS: PPS14 (Bit 14) */ +#define PORT2_PPS_PPS14_Msk (0x4000UL) /*!< PORT2 PPS: PPS14 (Bitfield-Mask: 0x01) */ +#define PORT2_PPS_PPS15_Pos (15UL) /*!< PORT2 PPS: PPS15 (Bit 15) */ +#define PORT2_PPS_PPS15_Msk (0x8000UL) /*!< PORT2 PPS: PPS15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT2_HWSEL -------------------------------- */ +#define PORT2_HWSEL_HW0_Pos (0UL) /*!< PORT2 HWSEL: HW0 (Bit 0) */ +#define PORT2_HWSEL_HW0_Msk (0x3UL) /*!< PORT2 HWSEL: HW0 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW1_Pos (2UL) /*!< PORT2 HWSEL: HW1 (Bit 2) */ +#define PORT2_HWSEL_HW1_Msk (0xcUL) /*!< PORT2 HWSEL: HW1 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW2_Pos (4UL) /*!< PORT2 HWSEL: HW2 (Bit 4) */ +#define PORT2_HWSEL_HW2_Msk (0x30UL) /*!< PORT2 HWSEL: HW2 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW3_Pos (6UL) /*!< PORT2 HWSEL: HW3 (Bit 6) */ +#define PORT2_HWSEL_HW3_Msk (0xc0UL) /*!< PORT2 HWSEL: HW3 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW4_Pos (8UL) /*!< PORT2 HWSEL: HW4 (Bit 8) */ +#define PORT2_HWSEL_HW4_Msk (0x300UL) /*!< PORT2 HWSEL: HW4 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW5_Pos (10UL) /*!< PORT2 HWSEL: HW5 (Bit 10) */ +#define PORT2_HWSEL_HW5_Msk (0xc00UL) /*!< PORT2 HWSEL: HW5 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW6_Pos (12UL) /*!< PORT2 HWSEL: HW6 (Bit 12) */ +#define PORT2_HWSEL_HW6_Msk (0x3000UL) /*!< PORT2 HWSEL: HW6 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW7_Pos (14UL) /*!< PORT2 HWSEL: HW7 (Bit 14) */ +#define PORT2_HWSEL_HW7_Msk (0xc000UL) /*!< PORT2 HWSEL: HW7 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW8_Pos (16UL) /*!< PORT2 HWSEL: HW8 (Bit 16) */ +#define PORT2_HWSEL_HW8_Msk (0x30000UL) /*!< PORT2 HWSEL: HW8 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW9_Pos (18UL) /*!< PORT2 HWSEL: HW9 (Bit 18) */ +#define PORT2_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT2 HWSEL: HW9 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW10_Pos (20UL) /*!< PORT2 HWSEL: HW10 (Bit 20) */ +#define PORT2_HWSEL_HW10_Msk (0x300000UL) /*!< PORT2 HWSEL: HW10 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW11_Pos (22UL) /*!< PORT2 HWSEL: HW11 (Bit 22) */ +#define PORT2_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT2 HWSEL: HW11 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW12_Pos (24UL) /*!< PORT2 HWSEL: HW12 (Bit 24) */ +#define PORT2_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT2 HWSEL: HW12 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW13_Pos (26UL) /*!< PORT2 HWSEL: HW13 (Bit 26) */ +#define PORT2_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT2 HWSEL: HW13 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW14_Pos (28UL) /*!< PORT2 HWSEL: HW14 (Bit 28) */ +#define PORT2_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT2 HWSEL: HW14 (Bitfield-Mask: 0x03) */ +#define PORT2_HWSEL_HW15_Pos (30UL) /*!< PORT2 HWSEL: HW15 (Bit 30) */ +#define PORT2_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT2 HWSEL: HW15 (Bitfield-Mask: 0x03) */ + + +/* ================================================================================ */ +/* ================ struct 'PORT3' Position & Mask ================ */ +/* ================================================================================ */ + + +/* ---------------------------------- PORT3_OUT --------------------------------- */ +#define PORT3_OUT_P0_Pos (0UL) /*!< PORT3 OUT: P0 (Bit 0) */ +#define PORT3_OUT_P0_Msk (0x1UL) /*!< PORT3 OUT: P0 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P1_Pos (1UL) /*!< PORT3 OUT: P1 (Bit 1) */ +#define PORT3_OUT_P1_Msk (0x2UL) /*!< PORT3 OUT: P1 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P2_Pos (2UL) /*!< PORT3 OUT: P2 (Bit 2) */ +#define PORT3_OUT_P2_Msk (0x4UL) /*!< PORT3 OUT: P2 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P3_Pos (3UL) /*!< PORT3 OUT: P3 (Bit 3) */ +#define PORT3_OUT_P3_Msk (0x8UL) /*!< PORT3 OUT: P3 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P4_Pos (4UL) /*!< PORT3 OUT: P4 (Bit 4) */ +#define PORT3_OUT_P4_Msk (0x10UL) /*!< PORT3 OUT: P4 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P5_Pos (5UL) /*!< PORT3 OUT: P5 (Bit 5) */ +#define PORT3_OUT_P5_Msk (0x20UL) /*!< PORT3 OUT: P5 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P6_Pos (6UL) /*!< PORT3 OUT: P6 (Bit 6) */ +#define PORT3_OUT_P6_Msk (0x40UL) /*!< PORT3 OUT: P6 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P7_Pos (7UL) /*!< PORT3 OUT: P7 (Bit 7) */ +#define PORT3_OUT_P7_Msk (0x80UL) /*!< PORT3 OUT: P7 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P8_Pos (8UL) /*!< PORT3 OUT: P8 (Bit 8) */ +#define PORT3_OUT_P8_Msk (0x100UL) /*!< PORT3 OUT: P8 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P9_Pos (9UL) /*!< PORT3 OUT: P9 (Bit 9) */ +#define PORT3_OUT_P9_Msk (0x200UL) /*!< PORT3 OUT: P9 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P10_Pos (10UL) /*!< PORT3 OUT: P10 (Bit 10) */ +#define PORT3_OUT_P10_Msk (0x400UL) /*!< PORT3 OUT: P10 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P11_Pos (11UL) /*!< PORT3 OUT: P11 (Bit 11) */ +#define PORT3_OUT_P11_Msk (0x800UL) /*!< PORT3 OUT: P11 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P12_Pos (12UL) /*!< PORT3 OUT: P12 (Bit 12) */ +#define PORT3_OUT_P12_Msk (0x1000UL) /*!< PORT3 OUT: P12 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P13_Pos (13UL) /*!< PORT3 OUT: P13 (Bit 13) */ +#define PORT3_OUT_P13_Msk (0x2000UL) /*!< PORT3 OUT: P13 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P14_Pos (14UL) /*!< PORT3 OUT: P14 (Bit 14) */ +#define PORT3_OUT_P14_Msk (0x4000UL) /*!< PORT3 OUT: P14 (Bitfield-Mask: 0x01) */ +#define PORT3_OUT_P15_Pos (15UL) /*!< PORT3 OUT: P15 (Bit 15) */ +#define PORT3_OUT_P15_Msk (0x8000UL) /*!< PORT3 OUT: P15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT3_OMR --------------------------------- */ +#define PORT3_OMR_PS0_Pos (0UL) /*!< PORT3 OMR: PS0 (Bit 0) */ +#define PORT3_OMR_PS0_Msk (0x1UL) /*!< PORT3 OMR: PS0 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS1_Pos (1UL) /*!< PORT3 OMR: PS1 (Bit 1) */ +#define PORT3_OMR_PS1_Msk (0x2UL) /*!< PORT3 OMR: PS1 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS2_Pos (2UL) /*!< PORT3 OMR: PS2 (Bit 2) */ +#define PORT3_OMR_PS2_Msk (0x4UL) /*!< PORT3 OMR: PS2 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS3_Pos (3UL) /*!< PORT3 OMR: PS3 (Bit 3) */ +#define PORT3_OMR_PS3_Msk (0x8UL) /*!< PORT3 OMR: PS3 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS4_Pos (4UL) /*!< PORT3 OMR: PS4 (Bit 4) */ +#define PORT3_OMR_PS4_Msk (0x10UL) /*!< PORT3 OMR: PS4 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS5_Pos (5UL) /*!< PORT3 OMR: PS5 (Bit 5) */ +#define PORT3_OMR_PS5_Msk (0x20UL) /*!< PORT3 OMR: PS5 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS6_Pos (6UL) /*!< PORT3 OMR: PS6 (Bit 6) */ +#define PORT3_OMR_PS6_Msk (0x40UL) /*!< PORT3 OMR: PS6 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS7_Pos (7UL) /*!< PORT3 OMR: PS7 (Bit 7) */ +#define PORT3_OMR_PS7_Msk (0x80UL) /*!< PORT3 OMR: PS7 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS8_Pos (8UL) /*!< PORT3 OMR: PS8 (Bit 8) */ +#define PORT3_OMR_PS8_Msk (0x100UL) /*!< PORT3 OMR: PS8 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS9_Pos (9UL) /*!< PORT3 OMR: PS9 (Bit 9) */ +#define PORT3_OMR_PS9_Msk (0x200UL) /*!< PORT3 OMR: PS9 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS10_Pos (10UL) /*!< PORT3 OMR: PS10 (Bit 10) */ +#define PORT3_OMR_PS10_Msk (0x400UL) /*!< PORT3 OMR: PS10 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS11_Pos (11UL) /*!< PORT3 OMR: PS11 (Bit 11) */ +#define PORT3_OMR_PS11_Msk (0x800UL) /*!< PORT3 OMR: PS11 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS12_Pos (12UL) /*!< PORT3 OMR: PS12 (Bit 12) */ +#define PORT3_OMR_PS12_Msk (0x1000UL) /*!< PORT3 OMR: PS12 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS13_Pos (13UL) /*!< PORT3 OMR: PS13 (Bit 13) */ +#define PORT3_OMR_PS13_Msk (0x2000UL) /*!< PORT3 OMR: PS13 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS14_Pos (14UL) /*!< PORT3 OMR: PS14 (Bit 14) */ +#define PORT3_OMR_PS14_Msk (0x4000UL) /*!< PORT3 OMR: PS14 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PS15_Pos (15UL) /*!< PORT3 OMR: PS15 (Bit 15) */ +#define PORT3_OMR_PS15_Msk (0x8000UL) /*!< PORT3 OMR: PS15 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR0_Pos (16UL) /*!< PORT3 OMR: PR0 (Bit 16) */ +#define PORT3_OMR_PR0_Msk (0x10000UL) /*!< PORT3 OMR: PR0 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR1_Pos (17UL) /*!< PORT3 OMR: PR1 (Bit 17) */ +#define PORT3_OMR_PR1_Msk (0x20000UL) /*!< PORT3 OMR: PR1 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR2_Pos (18UL) /*!< PORT3 OMR: PR2 (Bit 18) */ +#define PORT3_OMR_PR2_Msk (0x40000UL) /*!< PORT3 OMR: PR2 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR3_Pos (19UL) /*!< PORT3 OMR: PR3 (Bit 19) */ +#define PORT3_OMR_PR3_Msk (0x80000UL) /*!< PORT3 OMR: PR3 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR4_Pos (20UL) /*!< PORT3 OMR: PR4 (Bit 20) */ +#define PORT3_OMR_PR4_Msk (0x100000UL) /*!< PORT3 OMR: PR4 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR5_Pos (21UL) /*!< PORT3 OMR: PR5 (Bit 21) */ +#define PORT3_OMR_PR5_Msk (0x200000UL) /*!< PORT3 OMR: PR5 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR6_Pos (22UL) /*!< PORT3 OMR: PR6 (Bit 22) */ +#define PORT3_OMR_PR6_Msk (0x400000UL) /*!< PORT3 OMR: PR6 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR7_Pos (23UL) /*!< PORT3 OMR: PR7 (Bit 23) */ +#define PORT3_OMR_PR7_Msk (0x800000UL) /*!< PORT3 OMR: PR7 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR8_Pos (24UL) /*!< PORT3 OMR: PR8 (Bit 24) */ +#define PORT3_OMR_PR8_Msk (0x1000000UL) /*!< PORT3 OMR: PR8 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR9_Pos (25UL) /*!< PORT3 OMR: PR9 (Bit 25) */ +#define PORT3_OMR_PR9_Msk (0x2000000UL) /*!< PORT3 OMR: PR9 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR10_Pos (26UL) /*!< PORT3 OMR: PR10 (Bit 26) */ +#define PORT3_OMR_PR10_Msk (0x4000000UL) /*!< PORT3 OMR: PR10 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR11_Pos (27UL) /*!< PORT3 OMR: PR11 (Bit 27) */ +#define PORT3_OMR_PR11_Msk (0x8000000UL) /*!< PORT3 OMR: PR11 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR12_Pos (28UL) /*!< PORT3 OMR: PR12 (Bit 28) */ +#define PORT3_OMR_PR12_Msk (0x10000000UL) /*!< PORT3 OMR: PR12 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR13_Pos (29UL) /*!< PORT3 OMR: PR13 (Bit 29) */ +#define PORT3_OMR_PR13_Msk (0x20000000UL) /*!< PORT3 OMR: PR13 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR14_Pos (30UL) /*!< PORT3 OMR: PR14 (Bit 30) */ +#define PORT3_OMR_PR14_Msk (0x40000000UL) /*!< PORT3 OMR: PR14 (Bitfield-Mask: 0x01) */ +#define PORT3_OMR_PR15_Pos (31UL) /*!< PORT3 OMR: PR15 (Bit 31) */ +#define PORT3_OMR_PR15_Msk (0x80000000UL) /*!< PORT3 OMR: PR15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT3_IOCR0 -------------------------------- */ +#define PORT3_IOCR0_PC0_Pos (3UL) /*!< PORT3 IOCR0: PC0 (Bit 3) */ +#define PORT3_IOCR0_PC0_Msk (0xf8UL) /*!< PORT3 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ +#define PORT3_IOCR0_PC1_Pos (11UL) /*!< PORT3 IOCR0: PC1 (Bit 11) */ +#define PORT3_IOCR0_PC1_Msk (0xf800UL) /*!< PORT3 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ +#define PORT3_IOCR0_PC2_Pos (19UL) /*!< PORT3 IOCR0: PC2 (Bit 19) */ +#define PORT3_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT3 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ +#define PORT3_IOCR0_PC3_Pos (27UL) /*!< PORT3 IOCR0: PC3 (Bit 27) */ +#define PORT3_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT3 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ + +/* ---------------------------------- PORT3_IN ---------------------------------- */ +#define PORT3_IN_P0_Pos (0UL) /*!< PORT3 IN: P0 (Bit 0) */ +#define PORT3_IN_P0_Msk (0x1UL) /*!< PORT3 IN: P0 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P1_Pos (1UL) /*!< PORT3 IN: P1 (Bit 1) */ +#define PORT3_IN_P1_Msk (0x2UL) /*!< PORT3 IN: P1 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P2_Pos (2UL) /*!< PORT3 IN: P2 (Bit 2) */ +#define PORT3_IN_P2_Msk (0x4UL) /*!< PORT3 IN: P2 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P3_Pos (3UL) /*!< PORT3 IN: P3 (Bit 3) */ +#define PORT3_IN_P3_Msk (0x8UL) /*!< PORT3 IN: P3 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P4_Pos (4UL) /*!< PORT3 IN: P4 (Bit 4) */ +#define PORT3_IN_P4_Msk (0x10UL) /*!< PORT3 IN: P4 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P5_Pos (5UL) /*!< PORT3 IN: P5 (Bit 5) */ +#define PORT3_IN_P5_Msk (0x20UL) /*!< PORT3 IN: P5 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P6_Pos (6UL) /*!< PORT3 IN: P6 (Bit 6) */ +#define PORT3_IN_P6_Msk (0x40UL) /*!< PORT3 IN: P6 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P7_Pos (7UL) /*!< PORT3 IN: P7 (Bit 7) */ +#define PORT3_IN_P7_Msk (0x80UL) /*!< PORT3 IN: P7 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P8_Pos (8UL) /*!< PORT3 IN: P8 (Bit 8) */ +#define PORT3_IN_P8_Msk (0x100UL) /*!< PORT3 IN: P8 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P9_Pos (9UL) /*!< PORT3 IN: P9 (Bit 9) */ +#define PORT3_IN_P9_Msk (0x200UL) /*!< PORT3 IN: P9 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P10_Pos (10UL) /*!< PORT3 IN: P10 (Bit 10) */ +#define PORT3_IN_P10_Msk (0x400UL) /*!< PORT3 IN: P10 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P11_Pos (11UL) /*!< PORT3 IN: P11 (Bit 11) */ +#define PORT3_IN_P11_Msk (0x800UL) /*!< PORT3 IN: P11 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P12_Pos (12UL) /*!< PORT3 IN: P12 (Bit 12) */ +#define PORT3_IN_P12_Msk (0x1000UL) /*!< PORT3 IN: P12 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P13_Pos (13UL) /*!< PORT3 IN: P13 (Bit 13) */ +#define PORT3_IN_P13_Msk (0x2000UL) /*!< PORT3 IN: P13 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P14_Pos (14UL) /*!< PORT3 IN: P14 (Bit 14) */ +#define PORT3_IN_P14_Msk (0x4000UL) /*!< PORT3 IN: P14 (Bitfield-Mask: 0x01) */ +#define PORT3_IN_P15_Pos (15UL) /*!< PORT3 IN: P15 (Bit 15) */ +#define PORT3_IN_P15_Msk (0x8000UL) /*!< PORT3 IN: P15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT3_PDR0 --------------------------------- */ +#define PORT3_PDR0_PD0_Pos (0UL) /*!< PORT3 PDR0: PD0 (Bit 0) */ +#define PORT3_PDR0_PD0_Msk (0x7UL) /*!< PORT3 PDR0: PD0 (Bitfield-Mask: 0x07) */ +#define PORT3_PDR0_PD1_Pos (4UL) /*!< PORT3 PDR0: PD1 (Bit 4) */ +#define PORT3_PDR0_PD1_Msk (0x70UL) /*!< PORT3 PDR0: PD1 (Bitfield-Mask: 0x07) */ +#define PORT3_PDR0_PD2_Pos (8UL) /*!< PORT3 PDR0: PD2 (Bit 8) */ +#define PORT3_PDR0_PD2_Msk (0x700UL) /*!< PORT3 PDR0: PD2 (Bitfield-Mask: 0x07) */ +#define PORT3_PDR0_PD3_Pos (12UL) /*!< PORT3 PDR0: PD3 (Bit 12) */ +#define PORT3_PDR0_PD3_Msk (0x7000UL) /*!< PORT3 PDR0: PD3 (Bitfield-Mask: 0x07) */ +#define PORT3_PDR0_PD4_Pos (16UL) /*!< PORT3 PDR0: PD4 (Bit 16) */ +#define PORT3_PDR0_PD4_Msk (0x70000UL) /*!< PORT3 PDR0: PD4 (Bitfield-Mask: 0x07) */ +#define PORT3_PDR0_PD5_Pos (20UL) /*!< PORT3 PDR0: PD5 (Bit 20) */ +#define PORT3_PDR0_PD5_Msk (0x700000UL) /*!< PORT3 PDR0: PD5 (Bitfield-Mask: 0x07) */ +#define PORT3_PDR0_PD6_Pos (24UL) /*!< PORT3 PDR0: PD6 (Bit 24) */ +#define PORT3_PDR0_PD6_Msk (0x7000000UL) /*!< PORT3 PDR0: PD6 (Bitfield-Mask: 0x07) */ +#define PORT3_PDR0_PD7_Pos (28UL) /*!< PORT3 PDR0: PD7 (Bit 28) */ +#define PORT3_PDR0_PD7_Msk (0x70000000UL) /*!< PORT3 PDR0: PD7 (Bitfield-Mask: 0x07) */ + +/* --------------------------------- PORT3_PDISC -------------------------------- */ +#define PORT3_PDISC_PDIS0_Pos (0UL) /*!< PORT3 PDISC: PDIS0 (Bit 0) */ +#define PORT3_PDISC_PDIS0_Msk (0x1UL) /*!< PORT3 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS1_Pos (1UL) /*!< PORT3 PDISC: PDIS1 (Bit 1) */ +#define PORT3_PDISC_PDIS1_Msk (0x2UL) /*!< PORT3 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS2_Pos (2UL) /*!< PORT3 PDISC: PDIS2 (Bit 2) */ +#define PORT3_PDISC_PDIS2_Msk (0x4UL) /*!< PORT3 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS3_Pos (3UL) /*!< PORT3 PDISC: PDIS3 (Bit 3) */ +#define PORT3_PDISC_PDIS3_Msk (0x8UL) /*!< PORT3 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS4_Pos (4UL) /*!< PORT3 PDISC: PDIS4 (Bit 4) */ +#define PORT3_PDISC_PDIS4_Msk (0x10UL) /*!< PORT3 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS5_Pos (5UL) /*!< PORT3 PDISC: PDIS5 (Bit 5) */ +#define PORT3_PDISC_PDIS5_Msk (0x20UL) /*!< PORT3 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS6_Pos (6UL) /*!< PORT3 PDISC: PDIS6 (Bit 6) */ +#define PORT3_PDISC_PDIS6_Msk (0x40UL) /*!< PORT3 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS7_Pos (7UL) /*!< PORT3 PDISC: PDIS7 (Bit 7) */ +#define PORT3_PDISC_PDIS7_Msk (0x80UL) /*!< PORT3 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS8_Pos (8UL) /*!< PORT3 PDISC: PDIS8 (Bit 8) */ +#define PORT3_PDISC_PDIS8_Msk (0x100UL) /*!< PORT3 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS9_Pos (9UL) /*!< PORT3 PDISC: PDIS9 (Bit 9) */ +#define PORT3_PDISC_PDIS9_Msk (0x200UL) /*!< PORT3 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS10_Pos (10UL) /*!< PORT3 PDISC: PDIS10 (Bit 10) */ +#define PORT3_PDISC_PDIS10_Msk (0x400UL) /*!< PORT3 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS11_Pos (11UL) /*!< PORT3 PDISC: PDIS11 (Bit 11) */ +#define PORT3_PDISC_PDIS11_Msk (0x800UL) /*!< PORT3 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS12_Pos (12UL) /*!< PORT3 PDISC: PDIS12 (Bit 12) */ +#define PORT3_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT3 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS13_Pos (13UL) /*!< PORT3 PDISC: PDIS13 (Bit 13) */ +#define PORT3_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT3 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS14_Pos (14UL) /*!< PORT3 PDISC: PDIS14 (Bit 14) */ +#define PORT3_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT3 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ +#define PORT3_PDISC_PDIS15_Pos (15UL) /*!< PORT3 PDISC: PDIS15 (Bit 15) */ +#define PORT3_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT3 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ + +/* ---------------------------------- PORT3_PPS --------------------------------- */ +#define PORT3_PPS_PPS0_Pos (0UL) /*!< PORT3 PPS: PPS0 (Bit 0) */ +#define PORT3_PPS_PPS0_Msk (0x1UL) /*!< PORT3 PPS: PPS0 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS1_Pos (1UL) /*!< PORT3 PPS: PPS1 (Bit 1) */ +#define PORT3_PPS_PPS1_Msk (0x2UL) /*!< PORT3 PPS: PPS1 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS2_Pos (2UL) /*!< PORT3 PPS: PPS2 (Bit 2) */ +#define PORT3_PPS_PPS2_Msk (0x4UL) /*!< PORT3 PPS: PPS2 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS3_Pos (3UL) /*!< PORT3 PPS: PPS3 (Bit 3) */ +#define PORT3_PPS_PPS3_Msk (0x8UL) /*!< PORT3 PPS: PPS3 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS4_Pos (4UL) /*!< PORT3 PPS: PPS4 (Bit 4) */ +#define PORT3_PPS_PPS4_Msk (0x10UL) /*!< PORT3 PPS: PPS4 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS5_Pos (5UL) /*!< PORT3 PPS: PPS5 (Bit 5) */ +#define PORT3_PPS_PPS5_Msk (0x20UL) /*!< PORT3 PPS: PPS5 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS6_Pos (6UL) /*!< PORT3 PPS: PPS6 (Bit 6) */ +#define PORT3_PPS_PPS6_Msk (0x40UL) /*!< PORT3 PPS: PPS6 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS7_Pos (7UL) /*!< PORT3 PPS: PPS7 (Bit 7) */ +#define PORT3_PPS_PPS7_Msk (0x80UL) /*!< PORT3 PPS: PPS7 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS8_Pos (8UL) /*!< PORT3 PPS: PPS8 (Bit 8) */ +#define PORT3_PPS_PPS8_Msk (0x100UL) /*!< PORT3 PPS: PPS8 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS9_Pos (9UL) /*!< PORT3 PPS: PPS9 (Bit 9) */ +#define PORT3_PPS_PPS9_Msk (0x200UL) /*!< PORT3 PPS: PPS9 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS10_Pos (10UL) /*!< PORT3 PPS: PPS10 (Bit 10) */ +#define PORT3_PPS_PPS10_Msk (0x400UL) /*!< PORT3 PPS: PPS10 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS11_Pos (11UL) /*!< PORT3 PPS: PPS11 (Bit 11) */ +#define PORT3_PPS_PPS11_Msk (0x800UL) /*!< PORT3 PPS: PPS11 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS12_Pos (12UL) /*!< PORT3 PPS: PPS12 (Bit 12) */ +#define PORT3_PPS_PPS12_Msk (0x1000UL) /*!< PORT3 PPS: PPS12 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS13_Pos (13UL) /*!< PORT3 PPS: PPS13 (Bit 13) */ +#define PORT3_PPS_PPS13_Msk (0x2000UL) /*!< PORT3 PPS: PPS13 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS14_Pos (14UL) /*!< PORT3 PPS: PPS14 (Bit 14) */ +#define PORT3_PPS_PPS14_Msk (0x4000UL) /*!< PORT3 PPS: PPS14 (Bitfield-Mask: 0x01) */ +#define PORT3_PPS_PPS15_Pos (15UL) /*!< PORT3 PPS: PPS15 (Bit 15) */ +#define PORT3_PPS_PPS15_Msk (0x8000UL) /*!< PORT3 PPS: PPS15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT3_HWSEL -------------------------------- */ +#define PORT3_HWSEL_HW0_Pos (0UL) /*!< PORT3 HWSEL: HW0 (Bit 0) */ +#define PORT3_HWSEL_HW0_Msk (0x3UL) /*!< PORT3 HWSEL: HW0 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW1_Pos (2UL) /*!< PORT3 HWSEL: HW1 (Bit 2) */ +#define PORT3_HWSEL_HW1_Msk (0xcUL) /*!< PORT3 HWSEL: HW1 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW2_Pos (4UL) /*!< PORT3 HWSEL: HW2 (Bit 4) */ +#define PORT3_HWSEL_HW2_Msk (0x30UL) /*!< PORT3 HWSEL: HW2 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW3_Pos (6UL) /*!< PORT3 HWSEL: HW3 (Bit 6) */ +#define PORT3_HWSEL_HW3_Msk (0xc0UL) /*!< PORT3 HWSEL: HW3 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW4_Pos (8UL) /*!< PORT3 HWSEL: HW4 (Bit 8) */ +#define PORT3_HWSEL_HW4_Msk (0x300UL) /*!< PORT3 HWSEL: HW4 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW5_Pos (10UL) /*!< PORT3 HWSEL: HW5 (Bit 10) */ +#define PORT3_HWSEL_HW5_Msk (0xc00UL) /*!< PORT3 HWSEL: HW5 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW6_Pos (12UL) /*!< PORT3 HWSEL: HW6 (Bit 12) */ +#define PORT3_HWSEL_HW6_Msk (0x3000UL) /*!< PORT3 HWSEL: HW6 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW7_Pos (14UL) /*!< PORT3 HWSEL: HW7 (Bit 14) */ +#define PORT3_HWSEL_HW7_Msk (0xc000UL) /*!< PORT3 HWSEL: HW7 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW8_Pos (16UL) /*!< PORT3 HWSEL: HW8 (Bit 16) */ +#define PORT3_HWSEL_HW8_Msk (0x30000UL) /*!< PORT3 HWSEL: HW8 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW9_Pos (18UL) /*!< PORT3 HWSEL: HW9 (Bit 18) */ +#define PORT3_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT3 HWSEL: HW9 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW10_Pos (20UL) /*!< PORT3 HWSEL: HW10 (Bit 20) */ +#define PORT3_HWSEL_HW10_Msk (0x300000UL) /*!< PORT3 HWSEL: HW10 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW11_Pos (22UL) /*!< PORT3 HWSEL: HW11 (Bit 22) */ +#define PORT3_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT3 HWSEL: HW11 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW12_Pos (24UL) /*!< PORT3 HWSEL: HW12 (Bit 24) */ +#define PORT3_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT3 HWSEL: HW12 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW13_Pos (26UL) /*!< PORT3 HWSEL: HW13 (Bit 26) */ +#define PORT3_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT3 HWSEL: HW13 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW14_Pos (28UL) /*!< PORT3 HWSEL: HW14 (Bit 28) */ +#define PORT3_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT3 HWSEL: HW14 (Bitfield-Mask: 0x03) */ +#define PORT3_HWSEL_HW15_Pos (30UL) /*!< PORT3 HWSEL: HW15 (Bit 30) */ +#define PORT3_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT3 HWSEL: HW15 (Bitfield-Mask: 0x03) */ + + +/* ================================================================================ */ +/* ================ struct 'PORT14' Position & Mask ================ */ +/* ================================================================================ */ + + +/* --------------------------------- PORT14_OUT --------------------------------- */ +#define PORT14_OUT_P0_Pos (0UL) /*!< PORT14 OUT: P0 (Bit 0) */ +#define PORT14_OUT_P0_Msk (0x1UL) /*!< PORT14 OUT: P0 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P1_Pos (1UL) /*!< PORT14 OUT: P1 (Bit 1) */ +#define PORT14_OUT_P1_Msk (0x2UL) /*!< PORT14 OUT: P1 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P2_Pos (2UL) /*!< PORT14 OUT: P2 (Bit 2) */ +#define PORT14_OUT_P2_Msk (0x4UL) /*!< PORT14 OUT: P2 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P3_Pos (3UL) /*!< PORT14 OUT: P3 (Bit 3) */ +#define PORT14_OUT_P3_Msk (0x8UL) /*!< PORT14 OUT: P3 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P4_Pos (4UL) /*!< PORT14 OUT: P4 (Bit 4) */ +#define PORT14_OUT_P4_Msk (0x10UL) /*!< PORT14 OUT: P4 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P5_Pos (5UL) /*!< PORT14 OUT: P5 (Bit 5) */ +#define PORT14_OUT_P5_Msk (0x20UL) /*!< PORT14 OUT: P5 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P6_Pos (6UL) /*!< PORT14 OUT: P6 (Bit 6) */ +#define PORT14_OUT_P6_Msk (0x40UL) /*!< PORT14 OUT: P6 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P7_Pos (7UL) /*!< PORT14 OUT: P7 (Bit 7) */ +#define PORT14_OUT_P7_Msk (0x80UL) /*!< PORT14 OUT: P7 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P8_Pos (8UL) /*!< PORT14 OUT: P8 (Bit 8) */ +#define PORT14_OUT_P8_Msk (0x100UL) /*!< PORT14 OUT: P8 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P9_Pos (9UL) /*!< PORT14 OUT: P9 (Bit 9) */ +#define PORT14_OUT_P9_Msk (0x200UL) /*!< PORT14 OUT: P9 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P10_Pos (10UL) /*!< PORT14 OUT: P10 (Bit 10) */ +#define PORT14_OUT_P10_Msk (0x400UL) /*!< PORT14 OUT: P10 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P11_Pos (11UL) /*!< PORT14 OUT: P11 (Bit 11) */ +#define PORT14_OUT_P11_Msk (0x800UL) /*!< PORT14 OUT: P11 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P12_Pos (12UL) /*!< PORT14 OUT: P12 (Bit 12) */ +#define PORT14_OUT_P12_Msk (0x1000UL) /*!< PORT14 OUT: P12 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P13_Pos (13UL) /*!< PORT14 OUT: P13 (Bit 13) */ +#define PORT14_OUT_P13_Msk (0x2000UL) /*!< PORT14 OUT: P13 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P14_Pos (14UL) /*!< PORT14 OUT: P14 (Bit 14) */ +#define PORT14_OUT_P14_Msk (0x4000UL) /*!< PORT14 OUT: P14 (Bitfield-Mask: 0x01) */ +#define PORT14_OUT_P15_Pos (15UL) /*!< PORT14 OUT: P15 (Bit 15) */ +#define PORT14_OUT_P15_Msk (0x8000UL) /*!< PORT14 OUT: P15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT14_OMR --------------------------------- */ +#define PORT14_OMR_PS0_Pos (0UL) /*!< PORT14 OMR: PS0 (Bit 0) */ +#define PORT14_OMR_PS0_Msk (0x1UL) /*!< PORT14 OMR: PS0 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS1_Pos (1UL) /*!< PORT14 OMR: PS1 (Bit 1) */ +#define PORT14_OMR_PS1_Msk (0x2UL) /*!< PORT14 OMR: PS1 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS2_Pos (2UL) /*!< PORT14 OMR: PS2 (Bit 2) */ +#define PORT14_OMR_PS2_Msk (0x4UL) /*!< PORT14 OMR: PS2 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS3_Pos (3UL) /*!< PORT14 OMR: PS3 (Bit 3) */ +#define PORT14_OMR_PS3_Msk (0x8UL) /*!< PORT14 OMR: PS3 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS4_Pos (4UL) /*!< PORT14 OMR: PS4 (Bit 4) */ +#define PORT14_OMR_PS4_Msk (0x10UL) /*!< PORT14 OMR: PS4 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS5_Pos (5UL) /*!< PORT14 OMR: PS5 (Bit 5) */ +#define PORT14_OMR_PS5_Msk (0x20UL) /*!< PORT14 OMR: PS5 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS6_Pos (6UL) /*!< PORT14 OMR: PS6 (Bit 6) */ +#define PORT14_OMR_PS6_Msk (0x40UL) /*!< PORT14 OMR: PS6 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS7_Pos (7UL) /*!< PORT14 OMR: PS7 (Bit 7) */ +#define PORT14_OMR_PS7_Msk (0x80UL) /*!< PORT14 OMR: PS7 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS8_Pos (8UL) /*!< PORT14 OMR: PS8 (Bit 8) */ +#define PORT14_OMR_PS8_Msk (0x100UL) /*!< PORT14 OMR: PS8 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS9_Pos (9UL) /*!< PORT14 OMR: PS9 (Bit 9) */ +#define PORT14_OMR_PS9_Msk (0x200UL) /*!< PORT14 OMR: PS9 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS10_Pos (10UL) /*!< PORT14 OMR: PS10 (Bit 10) */ +#define PORT14_OMR_PS10_Msk (0x400UL) /*!< PORT14 OMR: PS10 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS11_Pos (11UL) /*!< PORT14 OMR: PS11 (Bit 11) */ +#define PORT14_OMR_PS11_Msk (0x800UL) /*!< PORT14 OMR: PS11 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS12_Pos (12UL) /*!< PORT14 OMR: PS12 (Bit 12) */ +#define PORT14_OMR_PS12_Msk (0x1000UL) /*!< PORT14 OMR: PS12 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS13_Pos (13UL) /*!< PORT14 OMR: PS13 (Bit 13) */ +#define PORT14_OMR_PS13_Msk (0x2000UL) /*!< PORT14 OMR: PS13 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS14_Pos (14UL) /*!< PORT14 OMR: PS14 (Bit 14) */ +#define PORT14_OMR_PS14_Msk (0x4000UL) /*!< PORT14 OMR: PS14 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PS15_Pos (15UL) /*!< PORT14 OMR: PS15 (Bit 15) */ +#define PORT14_OMR_PS15_Msk (0x8000UL) /*!< PORT14 OMR: PS15 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR0_Pos (16UL) /*!< PORT14 OMR: PR0 (Bit 16) */ +#define PORT14_OMR_PR0_Msk (0x10000UL) /*!< PORT14 OMR: PR0 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR1_Pos (17UL) /*!< PORT14 OMR: PR1 (Bit 17) */ +#define PORT14_OMR_PR1_Msk (0x20000UL) /*!< PORT14 OMR: PR1 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR2_Pos (18UL) /*!< PORT14 OMR: PR2 (Bit 18) */ +#define PORT14_OMR_PR2_Msk (0x40000UL) /*!< PORT14 OMR: PR2 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR3_Pos (19UL) /*!< PORT14 OMR: PR3 (Bit 19) */ +#define PORT14_OMR_PR3_Msk (0x80000UL) /*!< PORT14 OMR: PR3 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR4_Pos (20UL) /*!< PORT14 OMR: PR4 (Bit 20) */ +#define PORT14_OMR_PR4_Msk (0x100000UL) /*!< PORT14 OMR: PR4 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR5_Pos (21UL) /*!< PORT14 OMR: PR5 (Bit 21) */ +#define PORT14_OMR_PR5_Msk (0x200000UL) /*!< PORT14 OMR: PR5 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR6_Pos (22UL) /*!< PORT14 OMR: PR6 (Bit 22) */ +#define PORT14_OMR_PR6_Msk (0x400000UL) /*!< PORT14 OMR: PR6 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR7_Pos (23UL) /*!< PORT14 OMR: PR7 (Bit 23) */ +#define PORT14_OMR_PR7_Msk (0x800000UL) /*!< PORT14 OMR: PR7 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR8_Pos (24UL) /*!< PORT14 OMR: PR8 (Bit 24) */ +#define PORT14_OMR_PR8_Msk (0x1000000UL) /*!< PORT14 OMR: PR8 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR9_Pos (25UL) /*!< PORT14 OMR: PR9 (Bit 25) */ +#define PORT14_OMR_PR9_Msk (0x2000000UL) /*!< PORT14 OMR: PR9 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR10_Pos (26UL) /*!< PORT14 OMR: PR10 (Bit 26) */ +#define PORT14_OMR_PR10_Msk (0x4000000UL) /*!< PORT14 OMR: PR10 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR11_Pos (27UL) /*!< PORT14 OMR: PR11 (Bit 27) */ +#define PORT14_OMR_PR11_Msk (0x8000000UL) /*!< PORT14 OMR: PR11 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR12_Pos (28UL) /*!< PORT14 OMR: PR12 (Bit 28) */ +#define PORT14_OMR_PR12_Msk (0x10000000UL) /*!< PORT14 OMR: PR12 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR13_Pos (29UL) /*!< PORT14 OMR: PR13 (Bit 29) */ +#define PORT14_OMR_PR13_Msk (0x20000000UL) /*!< PORT14 OMR: PR13 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR14_Pos (30UL) /*!< PORT14 OMR: PR14 (Bit 30) */ +#define PORT14_OMR_PR14_Msk (0x40000000UL) /*!< PORT14 OMR: PR14 (Bitfield-Mask: 0x01) */ +#define PORT14_OMR_PR15_Pos (31UL) /*!< PORT14 OMR: PR15 (Bit 31) */ +#define PORT14_OMR_PR15_Msk (0x80000000UL) /*!< PORT14 OMR: PR15 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PORT14_IOCR0 -------------------------------- */ +#define PORT14_IOCR0_PC0_Pos (3UL) /*!< PORT14 IOCR0: PC0 (Bit 3) */ +#define PORT14_IOCR0_PC0_Msk (0xf8UL) /*!< PORT14 IOCR0: PC0 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR0_PC1_Pos (11UL) /*!< PORT14 IOCR0: PC1 (Bit 11) */ +#define PORT14_IOCR0_PC1_Msk (0xf800UL) /*!< PORT14 IOCR0: PC1 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR0_PC2_Pos (19UL) /*!< PORT14 IOCR0: PC2 (Bit 19) */ +#define PORT14_IOCR0_PC2_Msk (0xf80000UL) /*!< PORT14 IOCR0: PC2 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR0_PC3_Pos (27UL) /*!< PORT14 IOCR0: PC3 (Bit 27) */ +#define PORT14_IOCR0_PC3_Msk (0xf8000000UL) /*!< PORT14 IOCR0: PC3 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- PORT14_IOCR4 -------------------------------- */ +#define PORT14_IOCR4_PC4_Pos (3UL) /*!< PORT14 IOCR4: PC4 (Bit 3) */ +#define PORT14_IOCR4_PC4_Msk (0xf8UL) /*!< PORT14 IOCR4: PC4 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR4_PC5_Pos (11UL) /*!< PORT14 IOCR4: PC5 (Bit 11) */ +#define PORT14_IOCR4_PC5_Msk (0xf800UL) /*!< PORT14 IOCR4: PC5 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR4_PC6_Pos (19UL) /*!< PORT14 IOCR4: PC6 (Bit 19) */ +#define PORT14_IOCR4_PC6_Msk (0xf80000UL) /*!< PORT14 IOCR4: PC6 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR4_PC7_Pos (27UL) /*!< PORT14 IOCR4: PC7 (Bit 27) */ +#define PORT14_IOCR4_PC7_Msk (0xf8000000UL) /*!< PORT14 IOCR4: PC7 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- PORT14_IOCR8 -------------------------------- */ +#define PORT14_IOCR8_PC8_Pos (3UL) /*!< PORT14 IOCR8: PC8 (Bit 3) */ +#define PORT14_IOCR8_PC8_Msk (0xf8UL) /*!< PORT14 IOCR8: PC8 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR8_PC9_Pos (11UL) /*!< PORT14 IOCR8: PC9 (Bit 11) */ +#define PORT14_IOCR8_PC9_Msk (0xf800UL) /*!< PORT14 IOCR8: PC9 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR8_PC10_Pos (19UL) /*!< PORT14 IOCR8: PC10 (Bit 19) */ +#define PORT14_IOCR8_PC10_Msk (0xf80000UL) /*!< PORT14 IOCR8: PC10 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR8_PC11_Pos (27UL) /*!< PORT14 IOCR8: PC11 (Bit 27) */ +#define PORT14_IOCR8_PC11_Msk (0xf8000000UL) /*!< PORT14 IOCR8: PC11 (Bitfield-Mask: 0x1f) */ + +/* -------------------------------- PORT14_IOCR12 ------------------------------- */ +#define PORT14_IOCR12_PC12_Pos (3UL) /*!< PORT14 IOCR12: PC12 (Bit 3) */ +#define PORT14_IOCR12_PC12_Msk (0xf8UL) /*!< PORT14 IOCR12: PC12 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR12_PC13_Pos (11UL) /*!< PORT14 IOCR12: PC13 (Bit 11) */ +#define PORT14_IOCR12_PC13_Msk (0xf800UL) /*!< PORT14 IOCR12: PC13 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR12_PC14_Pos (19UL) /*!< PORT14 IOCR12: PC14 (Bit 19) */ +#define PORT14_IOCR12_PC14_Msk (0xf80000UL) /*!< PORT14 IOCR12: PC14 (Bitfield-Mask: 0x1f) */ +#define PORT14_IOCR12_PC15_Pos (27UL) /*!< PORT14 IOCR12: PC15 (Bit 27) */ +#define PORT14_IOCR12_PC15_Msk (0xf8000000UL) /*!< PORT14 IOCR12: PC15 (Bitfield-Mask: 0x1f) */ + +/* ---------------------------------- PORT14_IN --------------------------------- */ +#define PORT14_IN_P0_Pos (0UL) /*!< PORT14 IN: P0 (Bit 0) */ +#define PORT14_IN_P0_Msk (0x1UL) /*!< PORT14 IN: P0 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P1_Pos (1UL) /*!< PORT14 IN: P1 (Bit 1) */ +#define PORT14_IN_P1_Msk (0x2UL) /*!< PORT14 IN: P1 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P2_Pos (2UL) /*!< PORT14 IN: P2 (Bit 2) */ +#define PORT14_IN_P2_Msk (0x4UL) /*!< PORT14 IN: P2 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P3_Pos (3UL) /*!< PORT14 IN: P3 (Bit 3) */ +#define PORT14_IN_P3_Msk (0x8UL) /*!< PORT14 IN: P3 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P4_Pos (4UL) /*!< PORT14 IN: P4 (Bit 4) */ +#define PORT14_IN_P4_Msk (0x10UL) /*!< PORT14 IN: P4 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P5_Pos (5UL) /*!< PORT14 IN: P5 (Bit 5) */ +#define PORT14_IN_P5_Msk (0x20UL) /*!< PORT14 IN: P5 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P6_Pos (6UL) /*!< PORT14 IN: P6 (Bit 6) */ +#define PORT14_IN_P6_Msk (0x40UL) /*!< PORT14 IN: P6 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P7_Pos (7UL) /*!< PORT14 IN: P7 (Bit 7) */ +#define PORT14_IN_P7_Msk (0x80UL) /*!< PORT14 IN: P7 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P8_Pos (8UL) /*!< PORT14 IN: P8 (Bit 8) */ +#define PORT14_IN_P8_Msk (0x100UL) /*!< PORT14 IN: P8 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P9_Pos (9UL) /*!< PORT14 IN: P9 (Bit 9) */ +#define PORT14_IN_P9_Msk (0x200UL) /*!< PORT14 IN: P9 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P10_Pos (10UL) /*!< PORT14 IN: P10 (Bit 10) */ +#define PORT14_IN_P10_Msk (0x400UL) /*!< PORT14 IN: P10 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P11_Pos (11UL) /*!< PORT14 IN: P11 (Bit 11) */ +#define PORT14_IN_P11_Msk (0x800UL) /*!< PORT14 IN: P11 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P12_Pos (12UL) /*!< PORT14 IN: P12 (Bit 12) */ +#define PORT14_IN_P12_Msk (0x1000UL) /*!< PORT14 IN: P12 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P13_Pos (13UL) /*!< PORT14 IN: P13 (Bit 13) */ +#define PORT14_IN_P13_Msk (0x2000UL) /*!< PORT14 IN: P13 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P14_Pos (14UL) /*!< PORT14 IN: P14 (Bit 14) */ +#define PORT14_IN_P14_Msk (0x4000UL) /*!< PORT14 IN: P14 (Bitfield-Mask: 0x01) */ +#define PORT14_IN_P15_Pos (15UL) /*!< PORT14 IN: P15 (Bit 15) */ +#define PORT14_IN_P15_Msk (0x8000UL) /*!< PORT14 IN: P15 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PORT14_PDISC -------------------------------- */ +#define PORT14_PDISC_PDIS0_Pos (0UL) /*!< PORT14 PDISC: PDIS0 (Bit 0) */ +#define PORT14_PDISC_PDIS0_Msk (0x1UL) /*!< PORT14 PDISC: PDIS0 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS1_Pos (1UL) /*!< PORT14 PDISC: PDIS1 (Bit 1) */ +#define PORT14_PDISC_PDIS1_Msk (0x2UL) /*!< PORT14 PDISC: PDIS1 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS2_Pos (2UL) /*!< PORT14 PDISC: PDIS2 (Bit 2) */ +#define PORT14_PDISC_PDIS2_Msk (0x4UL) /*!< PORT14 PDISC: PDIS2 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS3_Pos (3UL) /*!< PORT14 PDISC: PDIS3 (Bit 3) */ +#define PORT14_PDISC_PDIS3_Msk (0x8UL) /*!< PORT14 PDISC: PDIS3 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS4_Pos (4UL) /*!< PORT14 PDISC: PDIS4 (Bit 4) */ +#define PORT14_PDISC_PDIS4_Msk (0x10UL) /*!< PORT14 PDISC: PDIS4 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS5_Pos (5UL) /*!< PORT14 PDISC: PDIS5 (Bit 5) */ +#define PORT14_PDISC_PDIS5_Msk (0x20UL) /*!< PORT14 PDISC: PDIS5 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS6_Pos (6UL) /*!< PORT14 PDISC: PDIS6 (Bit 6) */ +#define PORT14_PDISC_PDIS6_Msk (0x40UL) /*!< PORT14 PDISC: PDIS6 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS7_Pos (7UL) /*!< PORT14 PDISC: PDIS7 (Bit 7) */ +#define PORT14_PDISC_PDIS7_Msk (0x80UL) /*!< PORT14 PDISC: PDIS7 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS8_Pos (8UL) /*!< PORT14 PDISC: PDIS8 (Bit 8) */ +#define PORT14_PDISC_PDIS8_Msk (0x100UL) /*!< PORT14 PDISC: PDIS8 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS9_Pos (9UL) /*!< PORT14 PDISC: PDIS9 (Bit 9) */ +#define PORT14_PDISC_PDIS9_Msk (0x200UL) /*!< PORT14 PDISC: PDIS9 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS10_Pos (10UL) /*!< PORT14 PDISC: PDIS10 (Bit 10) */ +#define PORT14_PDISC_PDIS10_Msk (0x400UL) /*!< PORT14 PDISC: PDIS10 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS11_Pos (11UL) /*!< PORT14 PDISC: PDIS11 (Bit 11) */ +#define PORT14_PDISC_PDIS11_Msk (0x800UL) /*!< PORT14 PDISC: PDIS11 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS12_Pos (12UL) /*!< PORT14 PDISC: PDIS12 (Bit 12) */ +#define PORT14_PDISC_PDIS12_Msk (0x1000UL) /*!< PORT14 PDISC: PDIS12 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS13_Pos (13UL) /*!< PORT14 PDISC: PDIS13 (Bit 13) */ +#define PORT14_PDISC_PDIS13_Msk (0x2000UL) /*!< PORT14 PDISC: PDIS13 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS14_Pos (14UL) /*!< PORT14 PDISC: PDIS14 (Bit 14) */ +#define PORT14_PDISC_PDIS14_Msk (0x4000UL) /*!< PORT14 PDISC: PDIS14 (Bitfield-Mask: 0x01) */ +#define PORT14_PDISC_PDIS15_Pos (15UL) /*!< PORT14 PDISC: PDIS15 (Bit 15) */ +#define PORT14_PDISC_PDIS15_Msk (0x8000UL) /*!< PORT14 PDISC: PDIS15 (Bitfield-Mask: 0x01) */ + +/* --------------------------------- PORT14_PPS --------------------------------- */ +#define PORT14_PPS_PPS0_Pos (0UL) /*!< PORT14 PPS: PPS0 (Bit 0) */ +#define PORT14_PPS_PPS0_Msk (0x1UL) /*!< PORT14 PPS: PPS0 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS1_Pos (1UL) /*!< PORT14 PPS: PPS1 (Bit 1) */ +#define PORT14_PPS_PPS1_Msk (0x2UL) /*!< PORT14 PPS: PPS1 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS2_Pos (2UL) /*!< PORT14 PPS: PPS2 (Bit 2) */ +#define PORT14_PPS_PPS2_Msk (0x4UL) /*!< PORT14 PPS: PPS2 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS3_Pos (3UL) /*!< PORT14 PPS: PPS3 (Bit 3) */ +#define PORT14_PPS_PPS3_Msk (0x8UL) /*!< PORT14 PPS: PPS3 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS4_Pos (4UL) /*!< PORT14 PPS: PPS4 (Bit 4) */ +#define PORT14_PPS_PPS4_Msk (0x10UL) /*!< PORT14 PPS: PPS4 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS5_Pos (5UL) /*!< PORT14 PPS: PPS5 (Bit 5) */ +#define PORT14_PPS_PPS5_Msk (0x20UL) /*!< PORT14 PPS: PPS5 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS6_Pos (6UL) /*!< PORT14 PPS: PPS6 (Bit 6) */ +#define PORT14_PPS_PPS6_Msk (0x40UL) /*!< PORT14 PPS: PPS6 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS7_Pos (7UL) /*!< PORT14 PPS: PPS7 (Bit 7) */ +#define PORT14_PPS_PPS7_Msk (0x80UL) /*!< PORT14 PPS: PPS7 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS8_Pos (8UL) /*!< PORT14 PPS: PPS8 (Bit 8) */ +#define PORT14_PPS_PPS8_Msk (0x100UL) /*!< PORT14 PPS: PPS8 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS9_Pos (9UL) /*!< PORT14 PPS: PPS9 (Bit 9) */ +#define PORT14_PPS_PPS9_Msk (0x200UL) /*!< PORT14 PPS: PPS9 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS10_Pos (10UL) /*!< PORT14 PPS: PPS10 (Bit 10) */ +#define PORT14_PPS_PPS10_Msk (0x400UL) /*!< PORT14 PPS: PPS10 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS11_Pos (11UL) /*!< PORT14 PPS: PPS11 (Bit 11) */ +#define PORT14_PPS_PPS11_Msk (0x800UL) /*!< PORT14 PPS: PPS11 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS12_Pos (12UL) /*!< PORT14 PPS: PPS12 (Bit 12) */ +#define PORT14_PPS_PPS12_Msk (0x1000UL) /*!< PORT14 PPS: PPS12 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS13_Pos (13UL) /*!< PORT14 PPS: PPS13 (Bit 13) */ +#define PORT14_PPS_PPS13_Msk (0x2000UL) /*!< PORT14 PPS: PPS13 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS14_Pos (14UL) /*!< PORT14 PPS: PPS14 (Bit 14) */ +#define PORT14_PPS_PPS14_Msk (0x4000UL) /*!< PORT14 PPS: PPS14 (Bitfield-Mask: 0x01) */ +#define PORT14_PPS_PPS15_Pos (15UL) /*!< PORT14 PPS: PPS15 (Bit 15) */ +#define PORT14_PPS_PPS15_Msk (0x8000UL) /*!< PORT14 PPS: PPS15 (Bitfield-Mask: 0x01) */ + +/* -------------------------------- PORT14_HWSEL -------------------------------- */ +#define PORT14_HWSEL_HW0_Pos (0UL) /*!< PORT14 HWSEL: HW0 (Bit 0) */ +#define PORT14_HWSEL_HW0_Msk (0x3UL) /*!< PORT14 HWSEL: HW0 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW1_Pos (2UL) /*!< PORT14 HWSEL: HW1 (Bit 2) */ +#define PORT14_HWSEL_HW1_Msk (0xcUL) /*!< PORT14 HWSEL: HW1 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW2_Pos (4UL) /*!< PORT14 HWSEL: HW2 (Bit 4) */ +#define PORT14_HWSEL_HW2_Msk (0x30UL) /*!< PORT14 HWSEL: HW2 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW3_Pos (6UL) /*!< PORT14 HWSEL: HW3 (Bit 6) */ +#define PORT14_HWSEL_HW3_Msk (0xc0UL) /*!< PORT14 HWSEL: HW3 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW4_Pos (8UL) /*!< PORT14 HWSEL: HW4 (Bit 8) */ +#define PORT14_HWSEL_HW4_Msk (0x300UL) /*!< PORT14 HWSEL: HW4 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW5_Pos (10UL) /*!< PORT14 HWSEL: HW5 (Bit 10) */ +#define PORT14_HWSEL_HW5_Msk (0xc00UL) /*!< PORT14 HWSEL: HW5 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW6_Pos (12UL) /*!< PORT14 HWSEL: HW6 (Bit 12) */ +#define PORT14_HWSEL_HW6_Msk (0x3000UL) /*!< PORT14 HWSEL: HW6 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW7_Pos (14UL) /*!< PORT14 HWSEL: HW7 (Bit 14) */ +#define PORT14_HWSEL_HW7_Msk (0xc000UL) /*!< PORT14 HWSEL: HW7 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW8_Pos (16UL) /*!< PORT14 HWSEL: HW8 (Bit 16) */ +#define PORT14_HWSEL_HW8_Msk (0x30000UL) /*!< PORT14 HWSEL: HW8 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW9_Pos (18UL) /*!< PORT14 HWSEL: HW9 (Bit 18) */ +#define PORT14_HWSEL_HW9_Msk (0xc0000UL) /*!< PORT14 HWSEL: HW9 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW10_Pos (20UL) /*!< PORT14 HWSEL: HW10 (Bit 20) */ +#define PORT14_HWSEL_HW10_Msk (0x300000UL) /*!< PORT14 HWSEL: HW10 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW11_Pos (22UL) /*!< PORT14 HWSEL: HW11 (Bit 22) */ +#define PORT14_HWSEL_HW11_Msk (0xc00000UL) /*!< PORT14 HWSEL: HW11 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW12_Pos (24UL) /*!< PORT14 HWSEL: HW12 (Bit 24) */ +#define PORT14_HWSEL_HW12_Msk (0x3000000UL) /*!< PORT14 HWSEL: HW12 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW13_Pos (26UL) /*!< PORT14 HWSEL: HW13 (Bit 26) */ +#define PORT14_HWSEL_HW13_Msk (0xc000000UL) /*!< PORT14 HWSEL: HW13 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW14_Pos (28UL) /*!< PORT14 HWSEL: HW14 (Bit 28) */ +#define PORT14_HWSEL_HW14_Msk (0x30000000UL) /*!< PORT14 HWSEL: HW14 (Bitfield-Mask: 0x03) */ +#define PORT14_HWSEL_HW15_Pos (30UL) /*!< PORT14 HWSEL: HW15 (Bit 30) */ +#define PORT14_HWSEL_HW15_Msk (0xc0000000UL) /*!< PORT14 HWSEL: HW15 (Bitfield-Mask: 0x03) */ + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define PPB_BASE 0xE000E000UL +#define DLR_BASE 0x50004900UL +#define ERU0_BASE 0x50004800UL +#define ERU1_BASE 0x40044000UL +#define GPDMA0_BASE 0x500142C0UL +#define GPDMA0_CH0_BASE 0x50014000UL +#define GPDMA0_CH1_BASE 0x50014058UL +#define GPDMA0_CH2_BASE 0x500140B0UL +#define GPDMA0_CH3_BASE 0x50014108UL +#define GPDMA0_CH4_BASE 0x50014160UL +#define GPDMA0_CH5_BASE 0x500141B8UL +#define GPDMA0_CH6_BASE 0x50014210UL +#define GPDMA0_CH7_BASE 0x50014268UL +#define FCE_BASE 0x50020000UL +#define FCE_KE0_BASE 0x50020020UL +#define FCE_KE1_BASE 0x50020040UL +#define FCE_KE2_BASE 0x50020060UL +#define FCE_KE3_BASE 0x50020080UL +#define PBA0_BASE 0x40000000UL +#define PBA1_BASE 0x48000000UL +#define FLASH0_BASE 0x58001000UL +#define PREF_BASE 0x58004000UL +#define PMU0_BASE 0x58000508UL +#define WDT_BASE 0x50008000UL +#define RTC_BASE 0x50004A00UL +#define SCU_CLK_BASE 0x50004600UL +#define SCU_OSC_BASE 0x50004700UL +#define SCU_PLL_BASE 0x50004710UL +#define SCU_GENERAL_BASE 0x50004000UL +#define SCU_INTERRUPT_BASE 0x50004074UL +#define SCU_PARITY_BASE 0x5000413CUL +#define SCU_TRAP_BASE 0x50004160UL +#define SCU_HIBERNATE_BASE 0x50004300UL +#define SCU_POWER_BASE 0x50004200UL +#define SCU_RESET_BASE 0x50004400UL +#define LEDTS0_BASE 0x48010000UL +#define USB0_BASE 0x50040000UL +#define USB_EP_BASE 0x50040900UL +#define USB0_EP1_BASE 0x50040920UL +#define USB0_EP2_BASE 0x50040940UL +#define USB0_EP3_BASE 0x50040960UL +#define USB0_EP4_BASE 0x50040980UL +#define USB0_EP5_BASE 0x500409A0UL +#define USB0_EP6_BASE 0x500409C0UL +#define USIC0_BASE 0x40030008UL +#define USIC1_BASE 0x48020008UL +#define USIC0_CH0_BASE 0x40030000UL +#define USIC0_CH1_BASE 0x40030200UL +#define USIC1_CH0_BASE 0x48020000UL +#define USIC1_CH1_BASE 0x48020200UL +#define CAN_BASE 0x48014000UL +#define CAN_NODE0_BASE 0x48014200UL +#define CAN_NODE1_BASE 0x48014300UL +#define CAN_MO0_BASE 0x48015000UL +#define CAN_MO1_BASE 0x48015020UL +#define CAN_MO2_BASE 0x48015040UL +#define CAN_MO3_BASE 0x48015060UL +#define CAN_MO4_BASE 0x48015080UL +#define CAN_MO5_BASE 0x480150A0UL +#define CAN_MO6_BASE 0x480150C0UL +#define CAN_MO7_BASE 0x480150E0UL +#define CAN_MO8_BASE 0x48015100UL +#define CAN_MO9_BASE 0x48015120UL +#define CAN_MO10_BASE 0x48015140UL +#define CAN_MO11_BASE 0x48015160UL +#define CAN_MO12_BASE 0x48015180UL +#define CAN_MO13_BASE 0x480151A0UL +#define CAN_MO14_BASE 0x480151C0UL +#define CAN_MO15_BASE 0x480151E0UL +#define CAN_MO16_BASE 0x48015200UL +#define CAN_MO17_BASE 0x48015220UL +#define CAN_MO18_BASE 0x48015240UL +#define CAN_MO19_BASE 0x48015260UL +#define CAN_MO20_BASE 0x48015280UL +#define CAN_MO21_BASE 0x480152A0UL +#define CAN_MO22_BASE 0x480152C0UL +#define CAN_MO23_BASE 0x480152E0UL +#define CAN_MO24_BASE 0x48015300UL +#define CAN_MO25_BASE 0x48015320UL +#define CAN_MO26_BASE 0x48015340UL +#define CAN_MO27_BASE 0x48015360UL +#define CAN_MO28_BASE 0x48015380UL +#define CAN_MO29_BASE 0x480153A0UL +#define CAN_MO30_BASE 0x480153C0UL +#define CAN_MO31_BASE 0x480153E0UL +#define CAN_MO32_BASE 0x48015400UL +#define CAN_MO33_BASE 0x48015420UL +#define CAN_MO34_BASE 0x48015440UL +#define CAN_MO35_BASE 0x48015460UL +#define CAN_MO36_BASE 0x48015480UL +#define CAN_MO37_BASE 0x480154A0UL +#define CAN_MO38_BASE 0x480154C0UL +#define CAN_MO39_BASE 0x480154E0UL +#define CAN_MO40_BASE 0x48015500UL +#define CAN_MO41_BASE 0x48015520UL +#define CAN_MO42_BASE 0x48015540UL +#define CAN_MO43_BASE 0x48015560UL +#define CAN_MO44_BASE 0x48015580UL +#define CAN_MO45_BASE 0x480155A0UL +#define CAN_MO46_BASE 0x480155C0UL +#define CAN_MO47_BASE 0x480155E0UL +#define CAN_MO48_BASE 0x48015600UL +#define CAN_MO49_BASE 0x48015620UL +#define CAN_MO50_BASE 0x48015640UL +#define CAN_MO51_BASE 0x48015660UL +#define CAN_MO52_BASE 0x48015680UL +#define CAN_MO53_BASE 0x480156A0UL +#define CAN_MO54_BASE 0x480156C0UL +#define CAN_MO55_BASE 0x480156E0UL +#define CAN_MO56_BASE 0x48015700UL +#define CAN_MO57_BASE 0x48015720UL +#define CAN_MO58_BASE 0x48015740UL +#define CAN_MO59_BASE 0x48015760UL +#define CAN_MO60_BASE 0x48015780UL +#define CAN_MO61_BASE 0x480157A0UL +#define CAN_MO62_BASE 0x480157C0UL +#define CAN_MO63_BASE 0x480157E0UL +#define VADC_BASE 0x40004000UL +#define VADC_G0_BASE 0x40004400UL +#define VADC_G1_BASE 0x40004800UL +#define DAC_BASE 0x48018000UL +#define CCU40_BASE 0x4000C000UL +#define CCU41_BASE 0x40010000UL +#define CCU40_CC40_BASE 0x4000C100UL +#define CCU40_CC41_BASE 0x4000C200UL +#define CCU40_CC42_BASE 0x4000C300UL +#define CCU40_CC43_BASE 0x4000C400UL +#define CCU41_CC40_BASE 0x40010100UL +#define CCU41_CC41_BASE 0x40010200UL +#define CCU41_CC42_BASE 0x40010300UL +#define CCU41_CC43_BASE 0x40010400UL +#define CCU80_BASE 0x40020000UL +#define CCU80_CC80_BASE 0x40020100UL +#define CCU80_CC81_BASE 0x40020200UL +#define CCU80_CC82_BASE 0x40020300UL +#define CCU80_CC83_BASE 0x40020400UL +#define HRPWM0_BASE 0x40020900UL +#define HRPWM0_CSG0_BASE 0x40020A00UL +#define HRPWM0_CSG1_BASE 0x40020B00UL +#define HRPWM0_CSG2_BASE 0x40020C00UL +#define HRPWM0_HRC0_BASE 0x40021300UL +#define HRPWM0_HRC1_BASE 0x40021400UL +#define HRPWM0_HRC2_BASE 0x40021500UL +#define HRPWM0_HRC3_BASE 0x40021600UL +#define POSIF0_BASE 0x40028000UL +#define PORT0_BASE 0x48028000UL +#define PORT1_BASE 0x48028100UL +#define PORT2_BASE 0x48028200UL +#define PORT3_BASE 0x48028300UL +#define PORT14_BASE 0x48028E00UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define PPB ((PPB_Type *) PPB_BASE) +#define DLR ((DLR_GLOBAL_TypeDef *) DLR_BASE) +#define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE) +#define ERU1 ((ERU_GLOBAL_TypeDef *) ERU1_BASE) +#define GPDMA0 ((GPDMA0_GLOBAL_TypeDef *) GPDMA0_BASE) +#define GPDMA0_CH0 ((GPDMA0_CH_TypeDef *) GPDMA0_CH0_BASE) +#define GPDMA0_CH1 ((GPDMA0_CH_TypeDef *) GPDMA0_CH1_BASE) +#define GPDMA0_CH2 ((GPDMA0_CH_TypeDef *) GPDMA0_CH2_BASE) +#define GPDMA0_CH3 ((GPDMA0_CH_TypeDef *) GPDMA0_CH3_BASE) +#define GPDMA0_CH4 ((GPDMA0_CH_TypeDef *) GPDMA0_CH4_BASE) +#define GPDMA0_CH5 ((GPDMA0_CH_TypeDef *) GPDMA0_CH5_BASE) +#define GPDMA0_CH6 ((GPDMA0_CH_TypeDef *) GPDMA0_CH6_BASE) +#define GPDMA0_CH7 ((GPDMA0_CH_TypeDef *) GPDMA0_CH7_BASE) +#define FCE ((FCE_GLOBAL_TypeDef *) FCE_BASE) +#define FCE_KE0 ((FCE_KE_TypeDef *) FCE_KE0_BASE) +#define FCE_KE1 ((FCE_KE_TypeDef *) FCE_KE1_BASE) +#define FCE_KE2 ((FCE_KE_TypeDef *) FCE_KE2_BASE) +#define FCE_KE3 ((FCE_KE_TypeDef *) FCE_KE3_BASE) +#define PBA0 ((PBA_GLOBAL_TypeDef *) PBA0_BASE) +#define PBA1 ((PBA_GLOBAL_TypeDef *) PBA1_BASE) +#define FLASH0 ((FLASH0_GLOBAL_TypeDef *) FLASH0_BASE) +#define PREF ((PREF_GLOBAL_TypeDef *) PREF_BASE) +#define PMU0 ((PMU0_GLOBAL_TypeDef *) PMU0_BASE) +#define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE) +#define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE) +#define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE) +#define SCU_OSC ((SCU_OSC_TypeDef *) SCU_OSC_BASE) +#define SCU_PLL ((SCU_PLL_TypeDef *) SCU_PLL_BASE) +#define SCU_GENERAL ((SCU_GENERAL_TypeDef *) SCU_GENERAL_BASE) +#define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE) +#define SCU_PARITY ((SCU_PARITY_TypeDef *) SCU_PARITY_BASE) +#define SCU_TRAP ((SCU_TRAP_TypeDef *) SCU_TRAP_BASE) +#define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE) +#define SCU_POWER ((SCU_POWER_TypeDef *) SCU_POWER_BASE) +#define SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE) +#define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE) +#define USB0 ((USB0_GLOBAL_TypeDef *) USB0_BASE) +#define USB0_EP0 ((USB0_EP0_TypeDef *) USB_EP_BASE) +#define USB0_EP1 ((USB0_EP_TypeDef *) USB0_EP1_BASE) +#define USB0_EP2 ((USB0_EP_TypeDef *) USB0_EP2_BASE) +#define USB0_EP3 ((USB0_EP_TypeDef *) USB0_EP3_BASE) +#define USB0_EP4 ((USB0_EP_TypeDef *) USB0_EP4_BASE) +#define USB0_EP5 ((USB0_EP_TypeDef *) USB0_EP5_BASE) +#define USB0_EP6 ((USB0_EP_TypeDef *) USB0_EP6_BASE) +#define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE) +#define USIC1 ((USIC_GLOBAL_TypeDef *) USIC1_BASE) +#define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE) +#define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE) +#define USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE) +#define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE) +#define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE) +#define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE) +#define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE) +#define CAN_MO0 ((CAN_MO_TypeDef *) CAN_MO0_BASE) +#define CAN_MO1 ((CAN_MO_TypeDef *) CAN_MO1_BASE) +#define CAN_MO2 ((CAN_MO_TypeDef *) CAN_MO2_BASE) +#define CAN_MO3 ((CAN_MO_TypeDef *) CAN_MO3_BASE) +#define CAN_MO4 ((CAN_MO_TypeDef *) CAN_MO4_BASE) +#define CAN_MO5 ((CAN_MO_TypeDef *) CAN_MO5_BASE) +#define CAN_MO6 ((CAN_MO_TypeDef *) CAN_MO6_BASE) +#define CAN_MO7 ((CAN_MO_TypeDef *) CAN_MO7_BASE) +#define CAN_MO8 ((CAN_MO_TypeDef *) CAN_MO8_BASE) +#define CAN_MO9 ((CAN_MO_TypeDef *) CAN_MO9_BASE) +#define CAN_MO10 ((CAN_MO_TypeDef *) CAN_MO10_BASE) +#define CAN_MO11 ((CAN_MO_TypeDef *) CAN_MO11_BASE) +#define CAN_MO12 ((CAN_MO_TypeDef *) CAN_MO12_BASE) +#define CAN_MO13 ((CAN_MO_TypeDef *) CAN_MO13_BASE) +#define CAN_MO14 ((CAN_MO_TypeDef *) CAN_MO14_BASE) +#define CAN_MO15 ((CAN_MO_TypeDef *) CAN_MO15_BASE) +#define CAN_MO16 ((CAN_MO_TypeDef *) CAN_MO16_BASE) +#define CAN_MO17 ((CAN_MO_TypeDef *) CAN_MO17_BASE) +#define CAN_MO18 ((CAN_MO_TypeDef *) CAN_MO18_BASE) +#define CAN_MO19 ((CAN_MO_TypeDef *) CAN_MO19_BASE) +#define CAN_MO20 ((CAN_MO_TypeDef *) CAN_MO20_BASE) +#define CAN_MO21 ((CAN_MO_TypeDef *) CAN_MO21_BASE) +#define CAN_MO22 ((CAN_MO_TypeDef *) CAN_MO22_BASE) +#define CAN_MO23 ((CAN_MO_TypeDef *) CAN_MO23_BASE) +#define CAN_MO24 ((CAN_MO_TypeDef *) CAN_MO24_BASE) +#define CAN_MO25 ((CAN_MO_TypeDef *) CAN_MO25_BASE) +#define CAN_MO26 ((CAN_MO_TypeDef *) CAN_MO26_BASE) +#define CAN_MO27 ((CAN_MO_TypeDef *) CAN_MO27_BASE) +#define CAN_MO28 ((CAN_MO_TypeDef *) CAN_MO28_BASE) +#define CAN_MO29 ((CAN_MO_TypeDef *) CAN_MO29_BASE) +#define CAN_MO30 ((CAN_MO_TypeDef *) CAN_MO30_BASE) +#define CAN_MO31 ((CAN_MO_TypeDef *) CAN_MO31_BASE) +#define CAN_MO32 ((CAN_MO_TypeDef *) CAN_MO32_BASE) +#define CAN_MO33 ((CAN_MO_TypeDef *) CAN_MO33_BASE) +#define CAN_MO34 ((CAN_MO_TypeDef *) CAN_MO34_BASE) +#define CAN_MO35 ((CAN_MO_TypeDef *) CAN_MO35_BASE) +#define CAN_MO36 ((CAN_MO_TypeDef *) CAN_MO36_BASE) +#define CAN_MO37 ((CAN_MO_TypeDef *) CAN_MO37_BASE) +#define CAN_MO38 ((CAN_MO_TypeDef *) CAN_MO38_BASE) +#define CAN_MO39 ((CAN_MO_TypeDef *) CAN_MO39_BASE) +#define CAN_MO40 ((CAN_MO_TypeDef *) CAN_MO40_BASE) +#define CAN_MO41 ((CAN_MO_TypeDef *) CAN_MO41_BASE) +#define CAN_MO42 ((CAN_MO_TypeDef *) CAN_MO42_BASE) +#define CAN_MO43 ((CAN_MO_TypeDef *) CAN_MO43_BASE) +#define CAN_MO44 ((CAN_MO_TypeDef *) CAN_MO44_BASE) +#define CAN_MO45 ((CAN_MO_TypeDef *) CAN_MO45_BASE) +#define CAN_MO46 ((CAN_MO_TypeDef *) CAN_MO46_BASE) +#define CAN_MO47 ((CAN_MO_TypeDef *) CAN_MO47_BASE) +#define CAN_MO48 ((CAN_MO_TypeDef *) CAN_MO48_BASE) +#define CAN_MO49 ((CAN_MO_TypeDef *) CAN_MO49_BASE) +#define CAN_MO50 ((CAN_MO_TypeDef *) CAN_MO50_BASE) +#define CAN_MO51 ((CAN_MO_TypeDef *) CAN_MO51_BASE) +#define CAN_MO52 ((CAN_MO_TypeDef *) CAN_MO52_BASE) +#define CAN_MO53 ((CAN_MO_TypeDef *) CAN_MO53_BASE) +#define CAN_MO54 ((CAN_MO_TypeDef *) CAN_MO54_BASE) +#define CAN_MO55 ((CAN_MO_TypeDef *) CAN_MO55_BASE) +#define CAN_MO56 ((CAN_MO_TypeDef *) CAN_MO56_BASE) +#define CAN_MO57 ((CAN_MO_TypeDef *) CAN_MO57_BASE) +#define CAN_MO58 ((CAN_MO_TypeDef *) CAN_MO58_BASE) +#define CAN_MO59 ((CAN_MO_TypeDef *) CAN_MO59_BASE) +#define CAN_MO60 ((CAN_MO_TypeDef *) CAN_MO60_BASE) +#define CAN_MO61 ((CAN_MO_TypeDef *) CAN_MO61_BASE) +#define CAN_MO62 ((CAN_MO_TypeDef *) CAN_MO62_BASE) +#define CAN_MO63 ((CAN_MO_TypeDef *) CAN_MO63_BASE) +#define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE) +#define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE) +#define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE) +#define DAC ((DAC_GLOBAL_TypeDef *) DAC_BASE) +#define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE) +#define CCU41 ((CCU4_GLOBAL_TypeDef *) CCU41_BASE) +#define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE) +#define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE) +#define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE) +#define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE) +#define CCU41_CC40 ((CCU4_CC4_TypeDef *) CCU41_CC40_BASE) +#define CCU41_CC41 ((CCU4_CC4_TypeDef *) CCU41_CC41_BASE) +#define CCU41_CC42 ((CCU4_CC4_TypeDef *) CCU41_CC42_BASE) +#define CCU41_CC43 ((CCU4_CC4_TypeDef *) CCU41_CC43_BASE) +#define CCU80 ((CCU8_GLOBAL_TypeDef *) CCU80_BASE) +#define CCU80_CC80 ((CCU8_CC8_TypeDef *) CCU80_CC80_BASE) +#define CCU80_CC81 ((CCU8_CC8_TypeDef *) CCU80_CC81_BASE) +#define CCU80_CC82 ((CCU8_CC8_TypeDef *) CCU80_CC82_BASE) +#define CCU80_CC83 ((CCU8_CC8_TypeDef *) CCU80_CC83_BASE) +#define HRPWM0 ((HRPWM0_Type *) HRPWM0_BASE) +#define HRPWM0_CSG0 ((HRPWM0_CSG_Type *) HRPWM0_CSG0_BASE) +#define HRPWM0_CSG1 ((HRPWM0_CSG_Type *) HRPWM0_CSG1_BASE) +#define HRPWM0_CSG2 ((HRPWM0_CSG_Type *) HRPWM0_CSG2_BASE) +#define HRPWM0_HRC0 ((HRPWM0_HRC_Type *) HRPWM0_HRC0_BASE) +#define HRPWM0_HRC1 ((HRPWM0_HRC_Type *) HRPWM0_HRC1_BASE) +#define HRPWM0_HRC2 ((HRPWM0_HRC_Type *) HRPWM0_HRC2_BASE) +#define HRPWM0_HRC3 ((HRPWM0_HRC_Type *) HRPWM0_HRC3_BASE) +#define POSIF0 ((POSIF_GLOBAL_TypeDef *) POSIF0_BASE) +#define PORT0 ((PORT0_Type *) PORT0_BASE) +#define PORT1 ((PORT1_Type *) PORT1_BASE) +#define PORT2 ((PORT2_Type *) PORT2_BASE) +#define PORT3 ((PORT3_Type *) PORT3_BASE) +#define PORT14 ((PORT14_Type *) PORT14_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group XMC4200 */ +/** @} */ /* End of group Infineon */ + +#ifdef __cplusplus +} +#endif + + +#endif /* XMC4200_H */ + diff --git a/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h b/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h new file mode 100644 index 00000000..edc90ce4 --- /dev/null +++ b/variants/XMC4200/config/XMC4200_Platform2GO/pins_arduino.h @@ -0,0 +1,349 @@ +/* + pins_arduino.h - Pin definition functions for Arduino + Part of Arduino - http://www.arduino.cc/ + + Copyright (c) 2007 David A. Mellis + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General + Public License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place, Suite 330, + Boston, MA 02111-1307 USA + + Copyright (c) 2019 Infineon Technologies AG + This file has been modified for the XMC microcontroller series. +*/ +#ifndef PINS_ARDUINO_H_ +#define PINS_ARDUINO_H_ + +//**************************************************************************** +// @Project Includes +//**************************************************************************** +#include + +//**************************************************************************** +// @Defines +//**************************************************************************** +#define XMC_BOARD XMC 4200 Platform 2GO + +/* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ +#define XMC_LED_ON 1 + +// Following were defines now evaluated by compilation as const variables +// After definitions of associated mapping arrays +extern const uint8_t NUM_DIGITAL; +extern const uint8_t GND; +extern const uint8_t NUM_PWM4; +extern const uint8_t NUM_PWM8; +extern const uint8_t NUM_PWM; +extern const uint8_t NUM_INTERRUPT; +extern const uint8_t NUM_ANALOG_INPUTS; +#ifdef DAC +extern const uint8_t NUM_ANALOG_OUTPUTS; +#endif +#define NUM_LEDS 1 +#define NUM_BUTTONS 1 +#define NUM_SERIAL 1 +#define NUM_TONE_PINS 7 +#define NUM_TASKS_VARIANT 12 + +// Indicate unit has RTC/Alarm +#define HAS_RTC 1 + +//Generate 490Hz @fCCU=80MHz +#define PWM4_TIMER_PERIOD (0x09F7) +// Generate 490Hz @fCCU=80MHz +#define PWM8_TIMER_PERIOD (0x09F7) + +#define PCLK 80000000u + +#define PIN_SPI_SS 10 +#define PIN_SPI_MOSI 11 +#define PIN_SPI_MISO 12 +#define PIN_SPI_SCK 13 + +extern uint8_t SS; +extern uint8_t MOSI; +extern uint8_t MISO; +extern uint8_t SCK; + +#define A0 0 // ADC G0CH0 P14.0 +#define A1 1 // ADC G0CH6 P14.6 +#define A2 2 // ADC G0CH7 P14.7 +#define A3 3 // ADC G1CH0 P14.8 +#define A4 4 // ADC G0CH4 P14.4 +#define A5 5 // ADC G0CH5 P14.5 +//Additional ADC ports starting here +#define A6 6 // ADC G1CH6 on P14.14 +#define A7 7 // ADC G1CH1 on P14.9 + +#define LED1 36 // Additional LED1 +#define LED_BUILTIN LED1 // Standard Arduino LED: Uses LED1 +#define LED2 LED1 // Dummy LED define macro; added to comply with LED Library examples in CI/CD workflow +#define BUTTON1 27 // Additional BUTTON1 + +#define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) + +#ifdef ARDUINO_MAIN +// Mapping of digital pins and comments +const XMC_PORT_PIN_t mapping_port_pin[]= + { + /* 0 */ {XMC_GPIO_PORT2, 15}, // RX P2.15 X1-4 + /* 1 */ {XMC_GPIO_PORT2, 14}, // TX P2.14 X1-3 + /* 2 */ {XMC_GPIO_PORT1, 0}, // GPIO / External INT 0 P1.0 X1-11 + /* 3 */ {XMC_GPIO_PORT2, 2}, // PWM41-3 / PWM0 / External INT 1 P2.2 X1-31 + /* 4 */ {XMC_GPIO_PORT2, 9}, // IO_0 P2.9 X1-36 + /* 5 */ {XMC_GPIO_PORT2, 3}, // PWM41-2 output / PWM1 P2.3 X1-32 + /* 6 */ {XMC_GPIO_PORT2, 4}, // PWM41-1 output / PWM2 P2.4 X1-33 + /* 7 */ {XMC_GPIO_PORT2, 8}, // IO_1 P2.8 X1-35 + + /* 8 */ {XMC_GPIO_PORT2, 6}, // IO_2 P2.6 X1-27 + /* 9 */ {XMC_GPIO_PORT0, 11}, // PWM80-31 output / PWM3 P0.11 X2-7 + /* 10 */ {XMC_GPIO_PORT1, 7}, // SPI-CS P1.7 X1-8 + /* 11 */ {XMC_GPIO_PORT1, 9}, // SPI-MOSI P1.9 X1-10 + /* 12 */ {XMC_GPIO_PORT0, 0}, // SPI-MISO P0.0 X2-18 + /* 13 */ {XMC_GPIO_PORT1, 8}, // SPI-SCK P1.8 X1-9 + /* 14 */ {XMC_GPIO_PORT2, 5}, // I2C Data / Address SDA / A4 P2.5 (Hardwired to A4) X1-34 + /* 15 */ {XMC_GPIO_PORT3, 0}, // I2C Clock SCL / A5 P3.0 (Hardwired to A5) X2-19 + /* 16 */ {XMC_GPIO_PORT14, 0}, // A0 / ADC Input P14.0 (INPUT ONLY) X2-34 + /* 17 */ {XMC_GPIO_PORT14, 6}, // A1 / ADC Input P14.6 (INPUT ONLY) X2-25 + /* 18 */ {XMC_GPIO_PORT14, 7}, // A2 / ADC Input P14.7 (INPUT ONLY) X2-28 + /* 19 */ {XMC_GPIO_PORT14, 8}, // A3 / ADC Input / AN_MikroBus / DAC0 P14.8 X2-33 + /* 20 */ {XMC_GPIO_PORT14, 4}, // A4 / ADC Input / SDA / AN1_2GO_1 P14.4 (Hardwired to SDA) X2-24 + /* 21 */ {XMC_GPIO_PORT14, 5}, // A5 / ADC Input / SCL / AN2_2GO_2 P14.5 (Hardwired to SCL) X2-30 + + //Additional pins for port X1 starting here + /* 22 */ {XMC_GPIO_PORT1, 1}, // PWM_MikroBus / PWM40-2 P1.1 X1-12 + /* 23 */ {XMC_GPIO_PORT1, 2}, // PWM / PWM40-1 / GPIO4_S2GO_1 P1.2 X1-13 + /* 24 */ {XMC_GPIO_PORT1, 3}, // PWM / PWM40-0 / GPIO4_2GO_2 P1.3 X1-14 + /* 25 */ {XMC_GPIO_PORT1, 4}, // PC_TXD P1.4 X1-15 + /* 26 */ {XMC_GPIO_PORT1, 5}, // PC_RXD P1.5 X1-16 + /* 27 */ {XMC_GPIO_PORT1, 15}, // BUTTON1 P1.15 X1-22 + /* 28 */ {XMC_GPIO_PORT2, 7}, // RST_MikroBus P2.7 X1-28 + /* 29 */ {XMC_GPIO_PORT2, 0}, // CAN_TX P2.0 X1-29 + /* 30 */ {XMC_GPIO_PORT2, 1}, // GPIO1_2GO_2 P2.1 X1-30 + + //Additional pins for port X2 starting here + /* 31 */ {XMC_GPIO_PORT0, 7}, // SPI-CS_MikroBus P0.7 X2-1 + /* 32 */ {XMC_GPIO_PORT0, 8}, // RST / GPIO2_2GO_1 P0.8 X2-4 + /* 33 */ {XMC_GPIO_PORT0, 5}, // INT / GPIO3_2GO_1 P0.5 X2-9 + /* 34 */ {XMC_GPIO_PORT0, 3}, // INT / GPIO3_2GO_2 P0.3 X2-11 + /* 35 */ {XMC_GPIO_PORT0, 6}, // RST / GPIO2_2GO_2 P0.6 X2-12 + /* 36 */ {XMC_GPIO_PORT0, 1}, // LED1 P0.1 X2-13 + /* 37 */ {XMC_GPIO_PORT0, 4}, // GPIO1_S2GO_1 P0.4 X2-14 + /* 38 */ {XMC_GPIO_PORT0, 10}, // INT_MikroBus P0.10 X2-15 + /* 39 */ {XMC_GPIO_PORT0, 2}, // SPI-CS_2GO_1 P0.2 X2-16 + /* 40 */ {XMC_GPIO_PORT0, 9}, // SPI-CS_2GO_2 P0.9 X2-20 + /* 41 */ {XMC_GPIO_PORT14, 14}, // AN2_2GO_1 / A6 / ADC Input P14.14 (INPUT ONLY) X2-21 + /* 42 */ {XMC_GPIO_PORT14, 3}, // CAN_RX P14.3 X2-32 + /* 43 */ {XMC_GPIO_PORT14, 9}, // AN1_2GO_2 / A7 / ADC Input / DAC1 P14.9 X2-36 + }; + +const uint8_t GND = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); +const uint8_t NUM_DIGITAL = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) );; + +const XMC_PIN_INTERRUPT_t mapping_interrupt[] = + { + /* 0 */ {XMC_ERU0, XMC_ERU_ETL_INPUT_A0, XMC_ERU_ETL_INPUT_B0, 3, 3, 0}, + /* 1 */ {XMC_ERU0, XMC_ERU_ETL_INPUT_A0, XMC_ERU_ETL_INPUT_B2, 1, 0, 1} + }; +const uint8_t NUM_INTERRUPT = ( sizeof( mapping_interrupt ) / sizeof( XMC_PIN_INTERRUPT_t ) ); + +/* Mapping of Arduino Pins to PWM4 channels as pin and index in PWM4 channel + mapping array XMC_PWM4_t mapping_pwm4[] + last entry 255 for both parts. + Putting both parts in array means if a PWM4 channel gets reassigned for + another function later a gap in channel numbers will not mess things up */ +const uint8_t mapping_pin_PWM4[][ 2 ] = { + { 3, 0 }, // PWM0 + { 5, 1 }, // PWM1 + { 6, 2 }, // PWM2 + { 22, 3 }, // PWM + { 23, 4 }, // PWM + { 24, 5 }, // PWM + { 255, 255 } }; + +/* Configurations of PWM channels for CCU4 type */ +XMC_PWM4_t mapping_pwm4[] = + { + {CCU41, CCU41_CC43, 3, mapping_port_pin[3], P2_2_AF_CCU41_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P2.2 + {CCU41, CCU41_CC42, 2, mapping_port_pin[5], P2_3_AF_CCU41_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 5 P2.3 + {CCU41, CCU41_CC41, 1, mapping_port_pin[6], P2_4_AF_CCU41_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P2.4 + //additional pwm outputs starting here + {CCU40, CCU40_CC42, 2, mapping_port_pin[22], P1_1_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 22 P1.1 + {CCU40, CCU40_CC41, 1, mapping_port_pin[23], P1_2_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 23 P1.2 + {CCU40, CCU40_CC40, 0, mapping_port_pin[24], P1_3_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 24 P1.3 + }; +const uint8_t NUM_PWM4 = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); + +/* Mapping in same manner as PWM4 for PWM8 channels */ +const uint8_t mapping_pin_PWM8[][ 2 ] = { + { 9, 0 }, // PWM3 + { 255, 255 } }; + +/* Configurations of PWM channels for CCU8 type */ +XMC_PWM8_t mapping_pwm8[] = + { + {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[9], P0_11_AF_CCU80_OUT31, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED} // PWM disabled 9 P0.11 + }; +const uint8_t NUM_PWM8 = ( sizeof( mapping_pwm8 ) / sizeof( XMC_PWM8_t ) ); +const uint8_t NUM_PWM = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ) + + ( sizeof( mapping_pwm8 ) / sizeof( XMC_PWM8_t ) ); + +/* Analog Pin mappings and configurations */ +#ifdef DAC +const uint8_t mapping_pin_DAC[][ 2 ] = { + { 19, 0 }, + { 43, 1 }, + { 255, 255 } }; + +/* Analog Pin mappings and configurations */ +XMC_ARD_DAC_t mapping_dac[] = + { + {XMC_DAC0, 0, 12}, + {XMC_DAC0, 1, 12} + }; +const uint8_t NUM_ANALOG_OUTPUTS = ( sizeof( mapping_dac ) / sizeof( XMC_ARD_DAC_t ) ); +#endif + +XMC_ADC_t mapping_adc[] = + { + //Result reg numbers are now equal to channel numbers + {VADC, 0, VADC_G0, 0, 0, DISABLED}, //A0 + {VADC, 6, VADC_G0, 0, 1, DISABLED}, //A1 + {VADC, 7, VADC_G0, 0, 2, DISABLED}, //A2 + {VADC, 0, VADC_G1, 1, 0, DISABLED}, //A3 + {VADC, 4, VADC_G0, 0, 3, DISABLED}, //A4 + {VADC, 5, VADC_G0, 0, 4, DISABLED}, //A5 + //Additional ADC channels starting here + {VADC, 6, VADC_G1, 1, 1, DISABLED}, //A6 + {VADC, 1, VADC_G1, 1, 2, DISABLED}, //A7 + }; +const uint8_t NUM_ANALOG_INPUTS = ( sizeof( mapping_adc ) / sizeof( XMC_ADC_t ) ); + +/* + * UART objects + * + */ + +// Since both the UART interfaces are present on different USIC instances, +// both can be enabled independently. + +// Serial is PC-DEBUG interface +// Serial1 is ONBOARD interface + +RingBuffer rx_buffer_0; +RingBuffer tx_buffer_0; + +RingBuffer rx_buffer_1; +RingBuffer tx_buffer_1; + +XMC_UART_t XMC_UART_0 = + { + .channel = XMC_UART0_CH0, + .rx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)4 + }, + .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE + }, + .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .pin = (uint8_t)5 + }, + .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE + }, + .input_source_dx0 = (XMC_USIC_INPUT_t)USIC0_C0_DX0_P1_4, + .input_source_dx1 = XMC_INPUT_INVALID, + .input_source_dx2 = XMC_INPUT_INVALID, + .input_source_dx3 = XMC_INPUT_INVALID, + .irq_num = USIC0_0_IRQn, + .irq_service_request = 0 + }; + +XMC_UART_t XMC_UART_1 = + { + .channel = XMC_UART1_CH0, + .rx = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)15 + }, + .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE + }, + .tx = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)14 + }, + .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, + .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, + .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE + }, + .input_source_dx0 = (XMC_USIC_INPUT_t)USIC1_C0_DX0_P2_15, + .input_source_dx1 = XMC_INPUT_INVALID, + .input_source_dx2 = XMC_INPUT_INVALID, + .input_source_dx3 = XMC_INPUT_INVALID, + .irq_num = USIC1_0_IRQn, + .irq_service_request = 0 + }; + + +// Object instantiated of the HardwareSerial class for UART PC (debug) interface +HardwareSerial Serial( &XMC_UART_0, &rx_buffer_0, &tx_buffer_0 ); +// Object instantiated of the HardwareSerial class for UART ONBOARD interface +HardwareSerial Serial1( &XMC_UART_1, &rx_buffer_1, &tx_buffer_1 ); + +// Serial Interrupt and event handling +#ifdef __cplusplus +extern "C" { +#endif +void serialEventRun( ); +void serialEvent( ) __attribute__((weak)); +void serialEvent1( ) __attribute__((weak)); + +void serialEventRun( ) +{ +if( serialEvent ) + { + if( Serial.available( ) ) + serialEvent( ); + } +if( serialEvent1 ) + { + if( Serial1.available( ) ) + serialEvent1( ); + } +} + +// IRQ Handler of Serial Onboard (USIC1) +void USIC1_0_IRQHandler( ) +{ + Serial1.IrqHandler( ); +} + +// IRQ Handler of Serial to PC USB (USIC0) +void USIC0_0_IRQHandler( ) +{ + Serial.IrqHandler( ); +} + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_MAIN*/ + +#ifdef __cplusplus +extern HardwareSerial Serial; +extern HardwareSerial Serial1; +#endif /* cplusplus */ +#endif diff --git a/variants/XMC4200/linker_script.ld b/variants/XMC4200/linker_script.ld new file mode 100644 index 00000000..6c17ab3d --- /dev/null +++ b/variants/XMC4200/linker_script.ld @@ -0,0 +1,286 @@ +/** + * @file XMC4200x256.ld + * @date 2017-04-20 + * + * @cond + ********************************************************************************************************************* + * Linker file for the GNU C Compiler v1.8 + * Supported devices: XMC4200-F64x256 + * XMC4200-Q48x256 + * + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ********************************************************************************************************************* + * + * Change History + * -------------- + * + * 2015-07-07: + * - Product splitting + * - Copyright notice update + * + * 2015-11-24: + * - Compatibility with GCC 4.9 2015q2 + * + * 2016-03-08: + * - Fix size of BSS and DATA sections to be multiple of 4 + * - Add assertion to check that region SRAM_combined does not overflowed no_init section + * + * 2017-04-07: + * - Added new symbols __text_size and eText + * + * 2017-04-20: + * - Change vtable location to flash area to save ram + * + * @endcond + * + */ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Reset_Handler) + +MEMORY +{ + FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0x40000 + FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0x40000 + PSRAM_1(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0x4000 + DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x6000 + SRAM_combined(!RX) : ORIGIN = 0x1FFFC000, LENGTH = 0xA000 +} + +stack_size = DEFINED(stack_size) ? stack_size : 2048; +no_init_size = 64; + +SECTIONS +{ + /* TEXT section */ + + .text : + { + sText = .; + KEEP(*(.reset)); + *(.text .text.* .gnu.linkonce.t.*); + + /* C++ Support */ + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata .rodata.*) + *(.gnu.linkonce.r*) + + *(vtable) + + . = ALIGN(4); + } > FLASH_1_cached AT > FLASH_1_uncached + + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } > FLASH_1_cached AT > FLASH_1_uncached + + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } > FLASH_1_cached AT > FLASH_1_uncached + + /* Exception handling, exidx needs a dedicated section */ + .ARM.extab : ALIGN(4) + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH_1_cached AT > FLASH_1_uncached + + . = ALIGN(4); + __exidx_start = .; + .ARM.exidx : ALIGN(4) + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH_1_cached AT > FLASH_1_uncached + __exidx_end = .; + . = ALIGN(4); + + /* DSRAM layout (Lowest to highest)*/ + Stack (NOLOAD) : + { + __stack_start = .; + . = . + stack_size; + __stack_end = .; + __initial_sp = .; + } > SRAM_combined + + /* functions with __attribute__((section(".ram_code"))) */ + .ram_code : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __ram_code_start = .; + *(.ram_code) + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __ram_code_end = .; + } > SRAM_combined AT > FLASH_1_uncached + __ram_code_load = LOADADDR (.ram_code); + __ram_code_size = __ram_code_end - __ram_code_start; + + /* Standard DATA and user defined DATA/BSS/CONST sections */ + .data : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __data_start = .; + * (.data); + * (.data*); + *(*.data); + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __data_end = .; + } > SRAM_combined AT > FLASH_1_uncached + __data_load = LOADADDR (.data); + __data_size = __data_end - __data_start; + + __text_size = (__exidx_end - sText) + __data_size + __ram_code_size; + eText = sText + __text_size; + + /* BSS section */ + .bss (NOLOAD) : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __bss_start = .; + * (.bss); + * (.bss*); + * (COMMON); + *(.gnu.linkonce.b*) + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + __bss_end = .; + } > SRAM_combined + __bss_size = __bss_end - __bss_start; + + /* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */ + __shift_loc = (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end); + + USB_RAM (__bss_end + __shift_loc) (NOLOAD) : + { + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + USB_RAM_start = .; + *(USB_RAM) + . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */ + USB_RAM_end = .; + . = ALIGN(8); + Heap_Bank1_Start = .; + } > SRAM_combined + USB_RAM_size = USB_RAM_end - USB_RAM_start; + + /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file */ + .no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) : + { + Heap_Bank1_End = .; + * (.no_init); + } > SRAM_combined + + /* Heap - Bank1*/ + Heap_Bank1_Size = Heap_Bank1_End - Heap_Bank1_Start; + + ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section") + + /DISCARD/ : + { + *(.comment) + } + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_pubtypes 0 : { *(.debug_pubtypes) } + + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Build attributes */ + .build_attributes 0 : { *(.ARM.attributes) } +} diff --git a/variants/XMC4200/startup_XMC4200.S b/variants/XMC4200/startup_XMC4200.S new file mode 100644 index 00000000..362c9ea6 --- /dev/null +++ b/variants/XMC4200/startup_XMC4200.S @@ -0,0 +1,434 @@ +/********************************************************************************************************************* + * @file startup_XMC4200.S + * @brief CMSIS Core Device Startup File for Infineon XMC4200 Device Series + * @version V1.1 + * @date 15 Mai 2020 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2012-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ********************************************************************************************************************* + * + **************************** Change history ******************************** + * V0.1,Sep, 13, 2012 ES : initial version + * V0.2,Oct, 12, 2012 PKB: C++ support + * V0.3,Jan, 26, 2013 PKB: Workaround for prefetch bug + * V0.4,Jul, 29, 2013 PKB: AAPCS violation in V0.3 fixed + * V0.5,Feb, 05, 2014 PKB: Removed redundant alignment code from copy+clear funcs + * V0.6,May, 05, 2014 JFT: Added ram_code section + * V0.7,Nov, 25, 2014 JFT: CPU workaround disabled. Single default handler. + * Removed DAVE3 dependency + * V0.8,Jan, 05, 2016 JFT: Fix .reset section attributes + * V0.9,March,04,2016 JFT: Fix weak definition of Veneers. + * Only relevant for AA, which needs ENABLE_PMU_CM_001_WORKAROUND + * V1.0,June ,01,2016 JFT: Rename ENABLE_CPU_CM_001_WORKAROUND to ENABLE_PMU_CM_001_WORKAROUND + * Action required: If using AA step, use ENABLE_PMU_CM_001_WORKAROUND instead of ENABLE_CPU_CM_001_WORKAROUND + * V1.1,Mai, 15, 2020 JFT:Added option (ENABLE_OWN_HANDLER) to generate a individual interrupt handlers for unhandled vectors + * @endcond + */ + +/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ + +.macro Entry Handler +#if defined(ENABLE_PMU_CM_001_WORKAROUND) + .long \Handler\()_Veneer +#else + .long \Handler +#endif +.endm + +.macro Insert_ExceptionHandler Handler_Func + .weak \Handler_Func +#if defined(ENABLE_OWN_HANDLER) + .thumb_func + .type \Handler_Func, %function +\Handler_Func: + b . + .size \Handler_Func, . - \Handler_Func +#else + .thumb_set \Handler_Func, Default_Handler +#endif + +#if defined(ENABLE_PMU_CM_001_WORKAROUND) + .weak \Handler_Func\()_Veneer + .type \Handler_Func\()_Veneer, %function +\Handler_Func\()_Veneer: + push {r0, lr} + ldr r0, =\Handler_Func + blx r0 + pop {r0, pc} + .size \Handler_Func\()_Veneer, . - \Handler_Func\()_Veneer +#endif +.endm + +/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */ + +/* ================== START OF VECTOR TABLE DEFINITION ====================== */ +/* Vector Table - This gets programed into VTOR register by onchip BootROM */ + .syntax unified + + .section .reset, "a", %progbits + + .align 2 + .globl __Vectors + .type __Vectors, %object +__Vectors: + .long __initial_sp /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + + Entry NMI_Handler /* NMI Handler */ + Entry HardFault_Handler /* Hard Fault Handler */ + Entry MemManage_Handler /* MPU Fault Handler */ + Entry BusFault_Handler /* Bus Fault Handler */ + Entry UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + Entry SVC_Handler /* SVCall Handler */ + Entry DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + Entry PendSV_Handler /* PendSV Handler */ + Entry SysTick_Handler /* SysTick Handler */ + + /* Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */ + Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */ + Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */ + Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */ + Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */ + Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */ + Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */ + Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */ + Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */ + Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */ + .long 0 /* Not Available */ + Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */ + Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */ + Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */ + Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */ + Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */ + Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */ + Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */ + Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */ + Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */ + Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */ + Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */ + Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_1 */ + Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */ + Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */ + Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */ + Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */ + Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */ + Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */ + Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */ + Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */ + Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */ + Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */ + Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */ + Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry HRPWM_0_IRQHandler /* Handler name for SR HRPWM_0 */ + Entry HRPWM_1_IRQHandler /* Handler name for SR HRPWM_1 */ + Entry HRPWM_2_IRQHandler /* Handler name for SR HRPWM_2 */ + Entry HRPWM_3_IRQHandler /* Handler name for SR HRPWM_3 */ + Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */ + Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */ + Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */ + Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */ + Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */ + Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */ + Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */ + Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */ + Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */ + Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */ + Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */ + Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */ + Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */ + Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */ + Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */ + Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */ + Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */ + Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */ + Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */ + Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */ + .long 0 /* Not Available */ + Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */ + Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */ + .long 0 /* Not Available */ + Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + .long 0 /* Not Available */ + + .size __Vectors, . - __Vectors +/* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +/* ================== START OF VECTOR ROUTINES ============================= */ + + .align 1 + .thumb + +/* Reset Handler */ + .thumb_func + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp,=__initial_sp + +#ifndef __SKIP_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + +/* Initialize data + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: + +/* Zero initialized data + * Between symbol address __zero_table_start__ and __zero_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + * + * Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup. + */ +#ifndef __SKIP_BSS_CLEAR + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#endif /* __SKIP_BSS_CLEAR */ + +#ifndef __SKIP_LIBC_INIT_ARRAY + ldr r0, =__libc_init_array + blx r0 +#endif + + ldr r0, =main + blx r0 + +.align 2 +__copy_table_start__: + .long __data_load, __data_start, __data_size + .long __ram_code_load, __ram_code_start, __ram_code_size +__copy_table_end__: + +__zero_table_start__: + .long __bss_start, __bss_size + .long USB_RAM_start, USB_RAM_size +__zero_table_end__: + + .pool + .size Reset_Handler,.-Reset_Handler + +/* ======================================================================== */ +/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + +/* Default exception Handlers - Users may override this default functionality by + defining handlers of the same name in their C code */ + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + Insert_ExceptionHandler NMI_Handler + Insert_ExceptionHandler HardFault_Handler + Insert_ExceptionHandler MemManage_Handler + Insert_ExceptionHandler BusFault_Handler + Insert_ExceptionHandler UsageFault_Handler + Insert_ExceptionHandler SVC_Handler + Insert_ExceptionHandler DebugMon_Handler + Insert_ExceptionHandler PendSV_Handler + Insert_ExceptionHandler SysTick_Handler + + Insert_ExceptionHandler SCU_0_IRQHandler + Insert_ExceptionHandler ERU0_0_IRQHandler + Insert_ExceptionHandler ERU0_1_IRQHandler + Insert_ExceptionHandler ERU0_2_IRQHandler + Insert_ExceptionHandler ERU0_3_IRQHandler + Insert_ExceptionHandler ERU1_0_IRQHandler + Insert_ExceptionHandler ERU1_1_IRQHandler + Insert_ExceptionHandler ERU1_2_IRQHandler + Insert_ExceptionHandler ERU1_3_IRQHandler + Insert_ExceptionHandler PMU0_0_IRQHandler + Insert_ExceptionHandler VADC0_C0_0_IRQHandler + Insert_ExceptionHandler VADC0_C0_1_IRQHandler + Insert_ExceptionHandler VADC0_C0_2_IRQHandler + Insert_ExceptionHandler VADC0_C0_3_IRQHandler + Insert_ExceptionHandler VADC0_G0_0_IRQHandler + Insert_ExceptionHandler VADC0_G0_1_IRQHandler + Insert_ExceptionHandler VADC0_G0_2_IRQHandler + Insert_ExceptionHandler VADC0_G0_3_IRQHandler + Insert_ExceptionHandler VADC0_G1_0_IRQHandler + Insert_ExceptionHandler VADC0_G1_1_IRQHandler + Insert_ExceptionHandler VADC0_G1_2_IRQHandler + Insert_ExceptionHandler VADC0_G1_3_IRQHandler + Insert_ExceptionHandler DAC0_0_IRQHandler + Insert_ExceptionHandler DAC0_1_IRQHandler + Insert_ExceptionHandler CCU40_0_IRQHandler + Insert_ExceptionHandler CCU40_1_IRQHandler + Insert_ExceptionHandler CCU40_2_IRQHandler + Insert_ExceptionHandler CCU40_3_IRQHandler + Insert_ExceptionHandler CCU41_0_IRQHandler + Insert_ExceptionHandler CCU41_1_IRQHandler + Insert_ExceptionHandler CCU41_2_IRQHandler + Insert_ExceptionHandler CCU41_3_IRQHandler + Insert_ExceptionHandler CCU80_0_IRQHandler + Insert_ExceptionHandler CCU80_1_IRQHandler + Insert_ExceptionHandler CCU80_2_IRQHandler + Insert_ExceptionHandler CCU80_3_IRQHandler + Insert_ExceptionHandler POSIF0_0_IRQHandler + Insert_ExceptionHandler POSIF0_1_IRQHandler + Insert_ExceptionHandler HRPWM_0_IRQHandler + Insert_ExceptionHandler HRPWM_1_IRQHandler + Insert_ExceptionHandler HRPWM_2_IRQHandler + Insert_ExceptionHandler HRPWM_3_IRQHandler + Insert_ExceptionHandler CAN0_0_IRQHandler + Insert_ExceptionHandler CAN0_1_IRQHandler + Insert_ExceptionHandler CAN0_2_IRQHandler + Insert_ExceptionHandler CAN0_3_IRQHandler + Insert_ExceptionHandler CAN0_4_IRQHandler + Insert_ExceptionHandler CAN0_5_IRQHandler + Insert_ExceptionHandler CAN0_6_IRQHandler + Insert_ExceptionHandler CAN0_7_IRQHandler + Insert_ExceptionHandler USIC0_0_IRQHandler + Insert_ExceptionHandler USIC0_1_IRQHandler + Insert_ExceptionHandler USIC0_2_IRQHandler + Insert_ExceptionHandler USIC0_3_IRQHandler + Insert_ExceptionHandler USIC0_4_IRQHandler + Insert_ExceptionHandler USIC0_5_IRQHandler + Insert_ExceptionHandler USIC1_0_IRQHandler + Insert_ExceptionHandler USIC1_1_IRQHandler + Insert_ExceptionHandler USIC1_2_IRQHandler + Insert_ExceptionHandler USIC1_3_IRQHandler + Insert_ExceptionHandler USIC1_4_IRQHandler + Insert_ExceptionHandler USIC1_5_IRQHandler + Insert_ExceptionHandler LEDTS0_0_IRQHandler + Insert_ExceptionHandler FCE0_0_IRQHandler + Insert_ExceptionHandler GPDMA0_0_IRQHandler + Insert_ExceptionHandler USB0_0_IRQHandler + +/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */ + + .end diff --git a/variants/XMC4200/system_XMC4200.c b/variants/XMC4200/system_XMC4200.c new file mode 100644 index 00000000..b79c6895 --- /dev/null +++ b/variants/XMC4200/system_XMC4200.c @@ -0,0 +1,728 @@ +/********************************************************************************************************************* + * @file system_XMC4200.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4200 Device Series + * @version V3.1.6 + * @date 27. Aug 2020 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2015-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ********************************************************************************************************************* + * + ********************** Version History *************************************** + * V3.1.0, Dec 2014, Added options to configure clock settings + * V3.1.1, 01. Jun 2016, Fix masking of OSCHPCTRL value + * V3.1.2, 19. Jun 2017, Rely on cmsis_compiler.h instead of defining __WEAK + * Added support for ARM Compiler 6 (armclang) + * V3.1.3, 26. Sep 2017, Disable FPU if FPU_USED is zero + * V3.1.4, 29. Oct 2018, Fix variable location of SystemCoreClock, g_hrpwm_char_data and g_chipid for ARMCC compiler + * V3.1.5, 02. Dec 2019, Fix including device header file following the convention: angle brackets are used for standard includes and double quotes for everything else. + * Fix EXTCLKDIV macro definition + * Fix code for condition EXTCLK_PIN == EXTCLK_PIN_P1_15 + * V3.1.6, 27. Aug 2020. Fix K1 divider input clock for PLL in prescaler mode + * Added compiler checks for input VCO and VCO frequencies + * Added wait for K2 divider ready after updating the K2 divider in the PLL ramp up + * Removed wait for lock after changing the K2 divider in the PLL ramp up since a modification of the K2-divider has no impact on the VCO Lock status + * Use P,N,K2 even values dividers for system PLL to minimize jitter (for the case of external clock 12MHz) + * Use P,N,K2 value dividers for system PLL when running out of internal oscillator that centers the input frequency of the VCO to 6MHz instead of 4MHz (minimum value in DS) + ****************************************************************************** + * @endcond + */ + + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ +#include + +#include "XMC4200.h" +#include "system_XMC4200.h" + +/******************************************************************************* + * MACROS + *******************************************************************************/ +#define CHIPID_LOC ((uint8_t *)0x20000000UL) +#define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL) + +#define PMU_FLASH_WS (0x2U) +#define FPLL_FREQUENCY (80000000U) +#define FOSCREF (2500000U) +#define DELAY_CNT_50US_50MHZ (2500UL) +#define DELAY_CNT_150US_50MHZ (7500UL) +#define DELAY_CNT_50US_60MHZ (3000UL) +#define DELAY_CNT_50US_80MHZ (4000UL) + +#define VCO_INPUT_MIN (4000000UL) +#define VCO_INPUT_MAX (16000000UL) +#define VCO_MIN (260000000UL) +#define VCO_MAX (520000000UL) + +#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \ + SCU_PLL_PLLSTAT_PLLLV_Msk | \ + SCU_PLL_PLLSTAT_PLLSP_Msk) + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/* +// Clock configuration +*/ + +/* +// External crystal frequency [Hz] +// <8000000=> 8MHz +// <12000000=> 12MHz +// <16000000=> 16MHz +// Defines external crystal frequency +// Default: 8MHz +*/ +#define OSCHP_FREQUENCY (12000000U) + +#if OSCHP_FREQUENCY == 8000000U +#define USB_PDIV (1U) +#define USB_NDIV (95U) +#define USB_DIV (3U) + +#elif OSCHP_FREQUENCY == 12000000U +#define USB_PDIV (1U) +#define USB_NDIV (63U) +#define USB_DIV (3U) + +#elif OSCHP_FREQUENCY == 16000000U +#define USB_PDIV (1U) +#define USB_NDIV (47U) +#define USB_DIV (3U) + +#else +#error "External crystal frequency not supported" + +#endif + +#define USB_VCO ((OSCHP_FREQUENCY / (USB_PDIV + 1UL)) * (USB_NDIV + 1UL)) +#define USB_VCO_INPUT (OSCHP_FREQUENCY / (USB_PDIV + 1UL)) + +/* +// System clock (fSYS) source selection +// <0=> Backup clock (24MHz) +// <1=> Maximum clock frequency using PLL (80MHz) +// Default: Maximum clock frequency using PLL (80MHz) +*/ +#define SYS_CLOCK_SRC 1 +#define SYS_CLOCK_SRC_OFI 0 +#define SYS_CLOCK_SRC_PLL 1 + +/* +// Backup clock calibration mode +// <0=> Factory calibration +// <1=> Automatic calibration +// Default: Automatic calibration +*/ +#define FOFI_CALIBRATION_MODE 1 +#define FOFI_CALIBRATION_MODE_FACTORY 0 +#define FOFI_CALIBRATION_MODE_AUTOMATIC 1 + +/* +// Standby clock (fSTDBY) source selection +// <0=> Internal slow oscillator (32768Hz) +// <1=> External crystal (32768Hz) +// Default: Internal slow oscillator (32768Hz) +*/ +#define STDBY_CLOCK_SRC 0 +#define STDBY_CLOCK_SRC_OSI 0 +#define STDBY_CLOCK_SRC_OSCULP 1 + +/* +// PLL clock source selection +// <0=> External crystal +// <1=> External direct input +// <2=> Internal fast oscillator +// Default: External crystal +*/ +#define PLL_CLOCK_SRC 0 +#define PLL_CLOCK_SRC_EXT_XTAL 0 +#define PLL_CLOCK_SRC_EXT_DIRECT 1 +#define PLL_CLOCK_SRC_OFI 2 + +#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL +#if OSCHP_FREQUENCY == 8000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (79U) +#define PLL_K2DIV (3U) + +#elif OSCHP_FREQUENCY == 12000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (79U) +#define PLL_K2DIV (5U) + +#elif OSCHP_FREQUENCY == 16000000U +#define PLL_PDIV (1U) +#define PLL_NDIV (39U) +#define PLL_K2DIV (3U) + +#else +#error "External crystal frequency not supported" + +#endif + +#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) +#define VCO_INPUT (OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) + +#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */ +#define PLL_PDIV (3U) +#define PLL_NDIV (79U) +#define PLL_K2DIV (5U) + +#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL)) +#define VCO_INPUT (OFI_FREQUENCY / (PLL_PDIV + 1UL)) + +#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */ + +#if (VCO_INPUT < VCO_INPUT_MIN) || (VCO_INPUT > VCO_INPUT_MAX) +#error VCO_INPUT frequency out of range. +#endif + +#if (VCO < VCO_MIN) || (VCO > VCO_MAX) +#error VCO frequency out of range. +#endif + +#if (USB_VCO_INPUT < VCO_INPUT_MIN) || (USB_VCO_INPUT > VCO_INPUT_MAX) +#error USB_VCO_INPUT frequency out of range. +#endif + +#if (USB_VCO < VCO_MIN) || (USB_VCO > VCO_MAX) +#error USB_VCO frequency out of range. +#endif + +#define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL) +#define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL) + +#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk +#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk + +#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos) +#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos) + +#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) +#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) +#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos) + +#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) +#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) +#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) +#define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos) + +#define EXTCLK_PIN_P0_8 (0) +#define EXTCLK_PIN_P1_15 (1) + +/* +// Clock tree +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// Enable CCU clock +// CCU clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// Enable WDT clock +// WDT clock divider <1-256><#-1> +// WDT clock source <0=> fOFI +// <1=> fSTDBY +// <2=> fPLL +// +// Enable USB clock +// USB clock source <0=> USBPLL +// <1=> PLL +// +// External Clock configuration +// External clock source selection +// <0=> System clock +// <2=> USB PLL clock +// <3=> PLL clock +// <4=> Standby clock +// External clock divider <1-512><#-1> +// Only valid for USB PLL and PLL clocks +// External Pin Selection +// <0=> P0.8 +// <1=> P1.15 +// +// +*/ +#define ENABLE_SCUCLK (0U) +#define CPUCLKDIV (0U) +#define PBCLKDIV (0U) +#define CCUCLKDIV (0U) +#define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI) +#define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV) + +#define ENABLE_EXTCLK (0U) +#define EXTCLKDIV ((0U << SCU_CLK_EXTCLKCR_ECKDIV_Pos) | SCU_CLK_EXTCLKCR_ECKSEL_SYS) +#define EXTCLK_PIN (0U) + +#define ENABLE_PLL \ + (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \ + (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \ + (((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL)) + +/* +// +*/ + +/* +//-------- <<< end of configuration section >>> ------------------ +*/ + +/******************************************************************************* + * GLOBAL VARIABLES + *******************************************************************************/ +#if defined ( __CC_ARM ) +uint32_t SystemCoreClock __attribute__((at(0x20005FC0))); +uint8_t g_chipid[16] __attribute__((at(0x20005FC4))); +uint32_t g_hrpwm_char_data[3] __attribute__((at(0x20005FD4))); +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +uint32_t SystemCoreClock __attribute__((section(".bss.ARM.__at_0x20005FC0"))); +uint8_t g_chipid[16] __attribute__((section(".bss.ARM.__at_0x20005FC4"))); +uint32_t g_hrpwm_char_data[3] __attribute__((section(".bss.ARM.__at_0x20005FD4"))); +#elif defined ( __ICCARM__ ) +__no_init uint32_t SystemCoreClock; +__no_init uint8_t g_chipid[16]; +__no_init uint32_t g_hrpwm_char_data[3]; +#elif defined ( __GNUC__ ) +uint32_t SystemCoreClock __attribute__((section(".no_init"))); +uint8_t g_chipid[16] __attribute__((section(".no_init"))); +uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init"))); +#elif defined ( __TASKING__ ) +uint32_t SystemCoreClock __at( 0x20005FC0 ); +uint8_t g_chipid[16] __at( 0x20005FC4 ); +uint32_t g_hrpwm_char_data[3] __at( 0x20005FD4 ); +#endif + +extern uint32_t __Vectors; + +/******************************************************************************* + * LOCAL FUNCTIONS + *******************************************************************************/ +static void delay(uint32_t cycles) +{ + volatile uint32_t i; + + for(i = 0UL; i < cycles ;++i) + { + __NOP(); + } +} + +/******************************************************************************* + * API IMPLEMENTATION + *******************************************************************************/ + +__WEAK void SystemInit(void) +{ + memcpy(g_chipid, CHIPID_LOC, 16); + memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12); + + SystemCoreSetup(); + SystemCoreClockSetup(); +} + +__WEAK void SystemCoreSetup(void) +{ + uint32_t temp; + + /* relocate vector table */ + __disable_irq(); + SCB->VTOR = (uint32_t)(&__Vectors); + __DSB(); + __enable_irq(); + + /* __FPU_PRESENT = 1 defined in device header file */ + /* __FPU_USED value depends on compiler/linker options. */ + /* __FPU_USED = 0 if -mfloat-abi=soft is selected */ + /* __FPU_USED = 1 if -mfloat-abi=softfp or –mfloat-abi=hard */ + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#else + SCB->CPACR = 0; +#endif + + /* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ + SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + + temp = FLASH0->FCON; + temp &= ~FLASH_FCON_WSPFLASH_Msk; + temp |= PMU_FLASH_WS; + FLASH0->FCON = temp; +} + +__WEAK void SystemCoreClockSetup(void) +{ +#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY + /* Enable factory calibration */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk; +#else + /* Automatic calibration uses the fSTDBY */ + + /* Enable HIB domain */ + /* Power up HIB domain if and only if it is currently powered down */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + { + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; + + while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + { + /* wait until HIB domain is enabled */ + } + } + + /* Remove the reset only if HIB domain were in a state of reset */ + if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk) + { + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; + delay(DELAY_CNT_150US_50MHZ); + } + +#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP + /* Enable OSC_ULP */ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) + { + /*enable OSC_ULP*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; + + /* Check if the clock is OK using OSCULP Oscillator Watchdog*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + + /* wait till clock is stable */ + do + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + + delay(DELAY_CNT_50US_50MHZ); + + } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); + + } + + /* now OSC_ULP is running and can be used*/ + /* Select OSC_ULP as the clock source for RTC and STDBY*/ + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk) + { + /* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */ + } + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + +#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */ + + /* Enable automatic calibration of internal fast oscillator */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; +#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */ + + delay(DELAY_CNT_50US_50MHZ); + +#if ENABLE_PLL + + /* enable PLL */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI + /* enable OSC_HP */ + if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) + { + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); + SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; + + /* select OSC_HP clock as PLL input */ + SCU_PLL->PLLCON2 = 0; + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) + { + /* wait till OSC_HP output frequency is usable */ + } + } +#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */ + + /* select backup clock as PLL input */ + SCU_PLL->PLLCON2 = SCU_PLL_PLLCON2_PINSEL_Msk | SCU_PLL_PLLCON2_K1INSEL_Msk; +#endif + + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) == 0U) + { + /* wait for prescaler mode */ + } + + /* disconnect Oscillator from PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + + /* Setup divider settings for main PLL */ + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + /* connect Oscillator to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } + + /* Disable bypass- put PLL clock back */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U) + { + /* wait for normal mode */ + } +#endif /* ENABLE_PLL */ + +#if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk; +#else + /* Switch system clock to backup clock */ + SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; +#endif + + /* Before scaling to final frequency we need to setup the clock dividers */ + SCU_CLK->PBCLKCR = PBCLKDIV; + SCU_CLK->CPUCLKCR = CPUCLKDIV; + SCU_CLK->CCUCLKCR = CCUCLKDIV; + SCU_CLK->WDTCLKCR = WDTCLKDIV; + SCU_CLK->USBCLKCR = USBCLKDIV; + +#if ENABLE_PLL + /* PLL frequency stepping...*/ + /* Reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) + { + /* wait until K2-divider operates on the configured value */ + } + + delay(DELAY_CNT_50US_60MHZ); + + SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) | + (PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) | + (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_K2RDY_Msk) == 0U) + { + /* wait until K2-divider operates on the configured value */ + } + + delay(DELAY_CNT_50US_80MHZ); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; +#endif /* ENABLE_PLL */ + +#if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)) + /* enable USB PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); + + /* USB PLL uses as clock input the OSC_HP */ + /* check and if not already running enable OSC_HP */ + if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U) + { + /* check if Main PLL is switched on for OSC WDG*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL) + { + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk); + SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos; + + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE) + { + /* wait till OSC_HP output frequency is usable */ + } + } + + /* Setup USB PLL */ + /* Go to bypass the USB PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) == 0U) + { + /* wait for prescaler mode */ + } + + /* disconnect Oscillator from USB PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* Setup Divider settings for USB PLL */ + SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) | + (USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos)); + + /* Set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + + /* connect Oscillator to USB PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U) + { + /* wait for PLL Lock */ + } + + /* Disable bypass- put PLL clock back */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_VCOBYP_Msk; + while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOBYST_Msk) != 0U) + { + /* wait for normal mode */ + } + + /* Reset OSCDISCDIS */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_UVCOLCKT_Msk; +#endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */ + + /* Enable selected clocks */ + SCU_CLK->CLKSET = ENABLE_SCUCLK; + +#if ENABLE_EXTCLK == 1 + /* Configure external clock */ + SCU_CLK->EXTCLKCR = EXTCLKDIV; + +#if EXTCLK_PIN == EXTCLK_PIN_P1_15 + /* P1.15 */ + PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; + PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT1_IOCR12_PC15_Msk) | (0x11U << PORT1_IOCR12_PC15_Pos); +#else + /* P0.8 */ + PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk; + PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; + PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos); +#endif + +#endif /* ENABLE_EXTCLK == 1 */ + + SystemCoreClockUpdate(); +} + +__WEAK void SystemCoreClockUpdate(void) +{ + uint32_t pdiv; + uint32_t ndiv; + uint32_t kdiv; + uint32_t temp; + + if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) + { + /* fPLL is clock source for fSYS */ + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk) + { + /* PLL input clock is the backup clock (fOFI) */ + temp = OFI_FREQUENCY; + } + else + { + /* PLL input clock is the high performance osicllator (fOSCHP) */ + temp = OSCHP_GetFrequency(); + } + + /* check if PLL is locked */ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* PLL normal mode */ + /* read back divider settings */ + pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1; + ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1; + kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1; + + temp = (temp / (pdiv * kdiv)) * ndiv; + } + else + { + /* PLL prescalar mode */ + /* read back divider settings */ + kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1; + + temp = (temp / kdiv); + } + } + else + { + /* fOFI is clock source for fSYS */ + temp = OFI_FREQUENCY; + } + + temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1); + temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1); + + SystemCoreClock = temp; +} + +__WEAK uint32_t OSCHP_GetFrequency(void) +{ + return OSCHP_FREQUENCY; +} diff --git a/variants/XMC4200/system_XMC4200.h b/variants/XMC4200/system_XMC4200.h new file mode 100644 index 00000000..730d8d9e --- /dev/null +++ b/variants/XMC4200/system_XMC4200.h @@ -0,0 +1,111 @@ +/********************************************************************************************************************* + * @file system_XMC4200.h + * @brief Device specific initialization for the XMC4200-Series according to CMSIS + * @version V1.6 + * @date 23 October 2012 + * + * @cond + ********************************************************************************************************************* + * Copyright (c) 2012-2020, Infineon Technologies AG + * All rights reserved. + * + * Boost Software License - Version 1.0 - August 17th, 2003 + * + * Permission is hereby granted, free of charge, to any person or organization + * obtaining a copy of the software and accompanying documentation covered by + * this license (the "Software") to use, reproduce, display, distribute, + * execute, and transmit the Software, and to prepare derivative works of the + * Software, and to permit third-parties to whom the Software is furnished to + * do so, all subject to the following: + * + * The copyright notices in the Software and this entire statement, including + * the above license grant, this restriction and the following disclaimer, + * must be included in all copies of the Software, in whole or in part, and + * all derivative works of the Software, unless such copies or derivative + * works are solely in the form of machine-executable object code generated by + * a source language processor. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT + * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE + * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * To improve the quality of the software, users are encouraged to share + * modifications, enhancements or bug fixes with Infineon Technologies AG + * at XMCSupport@infineon.com. + ********************************************************************************************************************* + * + **************************** Change history ********************************* + ***************************************************************************** + * @endcond + */ + +#ifndef SYSTEM_XMC4200_H +#define SYSTEM_XMC4200_H + +/******************************************************************************* + * HEADER FILES + *******************************************************************************/ + +#include + +/******************************************************************************* + * MACROS + *******************************************************************************/ +#define OFI_FREQUENCY (24000000UL) /**< 24MHz Backup Clock (fOFI) frequency. */ +#define OSI_FREQUENCY (32768UL) /**< 32KHz Internal Slow Clock source (fOSI) frequency. */ + +/******************************************************************************* + * GLOBAL VARIABLES + *******************************************************************************/ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint8_t g_chipid[16]; /*!< Unique chip ID */ +extern uint32_t g_hrpwm_char_data[3]; /*!< HRPWM characterization data */ + +/******************************************************************************* + * API PROTOTYPES + *******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the system + * + */ +void SystemInit(void); + +/** + * @brief Initialize CPU settings + * + */ +void SystemCoreSetup(void); + +/** + * @brief Initialize clock + * + */ +void SystemCoreClockSetup(void); + +/** + * @brief Update SystemCoreClock variable + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Returns frequency of the high performace oscillator + * User needs to overload this function to return the correct oscillator frequency + */ +uint32_t OSCHP_GetFrequency(void); + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/variants/XMC4400/XMC4400.h b/variants/XMC4400/XMC4400.h old mode 100755 new mode 100644 diff --git a/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h b/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h index 74dadc1c..2b4f83bd 100644 --- a/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h +++ b/variants/XMC4400/config/XMC4400_Platform2GO/pins_arduino.h @@ -35,8 +35,8 @@ //**************************************************************************** #define XMC_BOARD XMC 4400 Platform 2GO -/* On board LED is ON when digital output is 0, LOW, False, OFF */ -#define XMC_LED_ON 0 +/* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ +#define XMC_LED_ON 1 // Following were defines now evaluated by compilation as const variables // After definitions of associated mapping arrays @@ -59,8 +59,10 @@ extern const uint8_t NUM_ANALOG_OUTPUTS; // Indicate unit has RTC/Alarm #define HAS_RTC 1 -#define PWM4_TIMER_PERIOD (0x11EF) //Generate 490Hz @fCCU=144MHz -#define PWM8_TIMER_PERIOD (0x11EF) // Generate 490Hz @fCCU=144MHz +//Generate 490Hz @fCCU=144MHz +#define PWM4_TIMER_PERIOD (0x11EF) +// Generate 490Hz @fCCU=144MHz +#define PWM8_TIMER_PERIOD (0x11EF) #define PCLK 64000000u @@ -74,145 +76,131 @@ extern uint8_t MOSI; extern uint8_t MISO; extern uint8_t SCK; -#define A0 0 // ADC G0CH0 P14.0 -#define A1 1 // ADC G0CH1 P14.1 -#define A2 2 // ADC G0CH2 P14.2 -#define A3 3 // ADC G0CH3 P14.3 -#define A4 4 // ADC G0CH4 P14.4 -#define A5 5 // ADC G0CH5 P14.5 +#define A0 0 +#define A1 1 +#define A2 2 +#define A3 3 +#define A4 4 +#define A5 5 //Additional ADC ports starting here -#define A6 6 // ADC G0CH6 on P14.6 -#define A7 7 // ADC G0CH7 on P14.7 -#define A8 8 // ADC G1CH4 on P14.12 -#define A9 9 // ADC G1CH5 on P14.13 -#define A10 10 // ADC G1CH6 on P14.14 -#define A11 11 // ADC G1CH7 on P14.15 -#define A12 12 // ADC G2CH2 on P15.2 -#define A13 13 // ADC G2CH3 on P15.3 -#define A14 14 // ADC G1CH0 on P14.8 -#define A15 15 // ADC G1CH1 on P14.9 -#define A16 16 // ADC G3CH0 on P15.8 -#define A17 17 // ADC G3CH1 on P15.9 - -#define LED1 82 // Additional LED1 -#define LED2 77 // Additional LED2 -#define LED_BUILTIN LED1 // Standard Arduino LED: Uses LED1 -#define BUTTON1 87 // Additional BUTTON1 -#define BUTTON2 69 // Additional BUTTON2 +#define A6 6 +#define A7 7 +#define A8 8 +#define A9 9 +#define A10 10 +#define A11 11 +#define A12 12 +#define A13 13 +#define A14 14 +#define A15 15 +#define A16 16 +#define A17 17 + +#define LED1 66 +#define LED2 63 +#define LED_BUILTIN LED1 + +#define BUTTON1 69 +#define BUTTON2 58 #define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) #ifdef ARDUINO_MAIN // Mapping of digital pins and comments +/*** +IMPORTANT NOTE + Entry at Arduino pin 14 is a PLACEHOLDER + Invalid pin assignment, but removing would lead to breaking legacy code, due to change + of other pin assignments. +***/ const XMC_PORT_PIN_t mapping_port_pin[]= { - /* 0 */ {XMC_GPIO_PORT2, 15}, // RX P2.15 - /* 1 */ {XMC_GPIO_PORT2, 14}, // TX P2.14 - /* 2 */ {XMC_GPIO_PORT1, 0}, // GPIO / External INT 0 P1.0 - /* 3 */ {XMC_GPIO_PORT3, 6}, // PWM42-0(PWM0)/ External INT 1 P3.6 - /* 4 */ {XMC_GPIO_PORT1, 6}, // GPIO P1.6 - /* 5 */ {XMC_GPIO_PORT3, 3}, // PWM42-3 output / PWM1 P3.3 - /* 6 */ {XMC_GPIO_PORT3, 4}, // PWM42-2 output / PWM2 P3.4 - /* 7 */ {XMC_GPIO_PORT1, 14}, // GPIO P1.14 - /* 8 */ {XMC_GPIO_PORT4, 1}, // GPIO P4.1 - /* 9 */ {XMC_GPIO_PORT0, 11}, // PWM80-31 output / PWM3 P0.11 - /* 10 */ {XMC_GPIO_PORT0, 2}, // SPI-SS / PWM80-01 / PWM4 P0.2 - /* 11 */ {XMC_GPIO_PORT1, 9}, // SPI-MOSI / PWM41-2 / PWM5 P1.9 - /* 12 */ {XMC_GPIO_PORT0, 0}, // SPI-MISO P0.0 - /* 13 */ {XMC_GPIO_PORT1, 8}, // SPI-SCK P1.8 - /* 14 */ {XMC_GPIO_PORT2, 3}, // AREF TODO: P2.3 - /* 15 */ {XMC_GPIO_PORT2, 5}, // I2C Data / Address SDA / A4 P2.5 (Hardwired to A4) - /* 16 */ {XMC_GPIO_PORT3, 0}, // I2C Clock SCL / A5 P3.0 (Hardwired to A5) - /* 17 */ {XMC_GPIO_PORT14, 0}, // A0 / ADC Input P14.0 (INPUT ONLY) - /* 18 */ {XMC_GPIO_PORT14, 1}, // A1 / ADC Input P14.1 (INPUT ONLY) - /* 19 */ {XMC_GPIO_PORT14, 2}, // A2 / ADC Input P14.2 (INPUT ONLY) - /* 20 */ {XMC_GPIO_PORT14, 3}, // A3 / ADC Input P14.3 (INPUT ONLY) - /* 21 */ {XMC_GPIO_PORT14, 4}, // A4 / ADC Input / SDA P14.4 (Hardwired to SDA) - /* 22 */ {XMC_GPIO_PORT14, 5}, // A5 / ADC Input / SCL P14.5 (Hardwired to SCL) - /* 23 */ {XMC_GPIO_PORT1, 15}, // USB Debug RX P1.15 - /* 24 */ {XMC_GPIO_PORT0, 5}, // USB Debug TX P0.5 + /* 0 */ {XMC_GPIO_PORT2, 15}, // RX P2.15 X1-4 + /* 1 */ {XMC_GPIO_PORT2, 14}, // TX P2.14 X1-3 + /* 2 */ {XMC_GPIO_PORT1, 0}, // GPIO / External INT 0 P1.0 X1-11 + /* 3 */ {XMC_GPIO_PORT3, 6}, // PWM42-0 / PWM0 / External INT 1 P3.6 X2-6 + /* 4 */ {XMC_GPIO_PORT1, 6}, // GPIO / IO_0 P1.6 X1-7 + /* 5 */ {XMC_GPIO_PORT3, 3}, // PWM42-3 output / PWM1 P3.3 X2-5 + /* 6 */ {XMC_GPIO_PORT3, 4}, // PWM42-2 output / PWM2 P3.4 X2-8 + /* 7 */ {XMC_GPIO_PORT1, 14}, // GPIO / IO_1 P1.14 X1-21 + /* 8 */ {XMC_GPIO_PORT4, 1}, // GPIO / IO_2 P4.1 X1-6 + /* 9 */ {XMC_GPIO_PORT0, 11}, // PWM80-31 output / PWM3 P0.11 X2-7 + /* 10 */ {XMC_GPIO_PORT0, 2}, // SPI-SS / PWM80-01 / PWM4 P0.2 X2-16 + /* 11 */ {XMC_GPIO_PORT1, 9}, // SPI-MOSI P1.9 X1-10 + /* 12 */ {XMC_GPIO_PORT0, 0}, // SPI-MISO P0.0 X2-18 + /* 13 */ {XMC_GPIO_PORT1, 8}, // SPI-SCK / GPIO P1.8 X1-9 + /* 14 */ {XMC_GPIO_PORT15, 2}, // --- Note: DUMMY pin assignment, to prevent incompatibility of legacy code! --- + /* 15 */ {XMC_GPIO_PORT2, 5}, // I2C Data / Address SDA / A4 / PWM41-0 P2.5 (Hardwired to A4) X1-34 + /* 16 */ {XMC_GPIO_PORT3, 0}, // I2C Clock SCL / A5 - ADC Input P3.0 (Hardwired to A5) X2-19 + /* 17 */ {XMC_GPIO_PORT14, 0}, // A0 / ADC Input P14.0 (INPUT ONLY) + /* 18 */ {XMC_GPIO_PORT14, 1}, // A1 / ADC Input P14.1 (INPUT ONLY) + /* 19 */ {XMC_GPIO_PORT14, 2}, // A2 / ADC Input P14.2 (INPUT ONLY) + /* 20 */ {XMC_GPIO_PORT14, 3}, // A3 / ADC Input P14.3 (INPUT ONLY) X2-31 + /* 21 */ {XMC_GPIO_PORT14, 4}, // A4 / ADC Input / SDA / GPIO P14.4 (Hardwired to SDA) X2-24 + /* 22 */ {XMC_GPIO_PORT14, 5}, // A5 / ADC Input / SCL P14.5 (Hardwired to SCL) X2-30 + /* 23 */ {XMC_GPIO_PORT1, 15}, // USB Debug RX P1.15 X1-22 + /* 24 */ {XMC_GPIO_PORT0, 5}, // USB Debug TX P0.5 X2-9 //Additional pins for port X1 starting here - /* 25 */ {XMC_GPIO_PORT2, 10}, // GPIO / ETH_LED P2.10 - /* 26 */ {XMC_GPIO_PORT2, 8}, // GPIO / ETH_TXDO P2.8 - /* 27 */ {XMC_GPIO_PORT2, 4}, // GPIO / ETH_RXER P2.4 - /* 28 */ {XMC_GPIO_PORT2, 2}, // GPIO / ETH_RXDO P2.2 - /* 29 */ {XMC_GPIO_PORT2, 0}, // GPIO / ETH_MDIO P2.0 - /* 30 */ {XMC_GPIO_PORT2, 6}, // PWM8 - / PWM / GPIO4_2GO_2 P2.6 - /* 31 */ {XMC_GPIO_PORT5, 2}, // GPIO / RST P5.2 - /* 32 */ {XMC_GPIO_PORT5, 0}, // GPIO1_2GO_1 P5.0 - /* 33 */ {XMC_GPIO_PORT1, 14}, // GPIO / IO_1 P1.14 - /* 34 */ {XMC_GPIO_PORT1, 12}, // GPIO / CAN_TX P1.12 - /* 35 */ {XMC_GPIO_PORT1, 10}, // GPIO / GPIO2_2GO_1 P1.10 - /* 36 */ {XMC_GPIO_PORT1, 4}, // GPIO / QSPI_IO1 P1.4 - /* 37 */ {XMC_GPIO_PORT1, 2}, // GPIO / QSPI_IO3 P1.2 - /* 38 */ {XMC_GPIO_PORT1, 0}, // GPIO / External INT 0 P1.0 - /* 39 */ {XMC_GPIO_PORT1, 8}, // GPIO / SPI-SCK P1.8 - /* 40 */ {XMC_GPIO_PORT1, 6}, // GPIO / IO_0 P1.6 - /* 41 */ {XMC_GPIO_PORT4, 0}, // GPIO / GPIO2_2GO_2 P1.0 - /* 42 */ {XMC_GPIO_PORT2, 14}, // UART TX P2.14 - /* 43 */ {XMC_GPIO_PORT2, 15}, // UART RX P2.15 - /* 44 */ {XMC_GPIO_PORT4, 1}, // GPIO / IO_2 P4.1. - /* 45 */ {XMC_GPIO_PORT1, 7}, // GPIO / SPI_CS_2GO_2 P1.7 (Chip Select - Slot 2) - /* 46 */ {XMC_GPIO_PORT1, 9}, // SPI-MOSI / PWM41-2 / PWM5 P1.9 - /* 47 */ {XMC_GPIO_PORT1, 1}, // GPIO1_2GO_2 P1.1 - /* 48 */ {XMC_GPIO_PORT1, 3}, // GPIO / QSPI_IO3 P1.3 - /* 49 */ {XMC_GPIO_PORT1, 5}, // GPIO / QSPI_IO0 P1.5 - /* 50 */ {XMC_GPIO_PORT1, 11}, // GPIO / QSPI_CS P1.11 - /* 51 */ {XMC_GPIO_PORT1, 13}, // GPIO / CAN_RX P1.13 - /* 52 */ {XMC_GPIO_PORT1, 15}, // USB Debug RX P1.15 - /* 53 */ {XMC_GPIO_PORT5, 1}, // GPIO / ETH_INT P5.1 - /* 54 */ {XMC_GPIO_PORT5, 7}, // PWM8 - / PWM P5.7 - /* 55 */ {XMC_GPIO_PORT2, 7}, // PWM8 - / PWM / ETH_MDC P2.7 - /* 56 */ {XMC_GPIO_PORT2, 1}, // SWV ""DEBUG Do NOT Use ** P2.1 - /* 57 */ {XMC_GPIO_PORT2, 3}, // AREF TODO: / ETH_RXD1 P2.3 - /* 58 */ {XMC_GPIO_PORT2, 5}, // I2C Data - SDA / A4 P2.5 (Hardwired to A4) - /* 59 */ {XMC_GPIO_PORT2, 9}, // PWM8 - / PWM / ETH_TXD1 P2.9 - /* 60 */ {XMC_GPIO_PORT15, 8}, // A16 / ETH_CLK P15.8 + /* 25 */ {XMC_GPIO_PORT2, 10}, // GPIO / ETH_LED P2.10 X1-37 + /* 26 */ {XMC_GPIO_PORT2, 8}, // GPIO / ETH_TXDO / PWM80-32 P2.8 X1-35 + /* 27 */ {XMC_GPIO_PORT2, 4}, // GPIO / ETH_RXER / PWM41-1 P2.4 X1-33 + /* 28 */ {XMC_GPIO_PORT2, 3}, // ETH_RXD1 / PWM41-2 P2.3 X1-32 + /* 29 */ {XMC_GPIO_PORT2, 2}, // GPIO / ETH_RXDO / PWM41-3 P2.2 X1-31 + /* 30 */ {XMC_GPIO_PORT2, 0}, // GPIO / ETH_MDIO / PWM81-21 P2.0 X1-29 + /* 31 */ {XMC_GPIO_PORT2, 6}, // PWM80-13 / GPIO4_2GO_2 P2.6 X1-27 + /* 32 */ {XMC_GPIO_PORT5, 2}, // GPIO / RST P5.2 X1-25 + /* 33 */ {XMC_GPIO_PORT5, 0}, // GPIO1_2GO_1 P5.0 X1-23 + /* 34 */ {XMC_GPIO_PORT1, 12}, // GPIO / CAN_TX P1.12 X1-19 + /* 35 */ {XMC_GPIO_PORT1, 10}, // GPIO / GPIO2_2GO_1 P1.10 X1-17 + /* 36 */ {XMC_GPIO_PORT1, 4}, // GPIO / QSPI_IO1 P1.4 X1-15 + /* 37 */ {XMC_GPIO_PORT1, 2}, // GPIO / QSPI_IO3 P1.2 X1-13 + /* 38 */ {XMC_GPIO_PORT4, 0}, // GPIO / GPIO2_2GO_2 P4.0 X1-5 + /* 39 */ {XMC_GPIO_PORT1, 7}, // GPIO / SPI_CS_2GO_2 P1.7 (Chip Select - Slot 2) X1-8 + /* 40 */ {XMC_GPIO_PORT1, 1}, // GPIO1_2GO_2 P1.1 X1-12 + /* 41 */ {XMC_GPIO_PORT1, 3}, // GPIO / QSPI_IO3 P1.3 X1-14 + /* 42 */ {XMC_GPIO_PORT1, 5}, // GPIO / QSPI_IO0 P1.5 X1-16 + /* 43 */ {XMC_GPIO_PORT1, 11}, // GPIO / QSPI_CS P1.11 X1-18 + /* 44 */ {XMC_GPIO_PORT1, 13}, // GPIO / CAN_RX P1.13 X1-20 + /* 45 */ {XMC_GPIO_PORT5, 1}, // GPIO / ETH_INT P5.1 X1-24 + /* 46 */ {XMC_GPIO_PORT5, 7}, // PWM81-02 P5.7 X1-26 + /* 47 */ {XMC_GPIO_PORT2, 7}, // PWM80-03 / ETH_MDC P2.7 X1-28 + /* 48 */ {XMC_GPIO_PORT2, 1}, // SWV ""DEBUG Do NOT Use ** P2.1 X1-30 + /* 49 */ {XMC_GPIO_PORT2, 9}, // PWM80-22 / ETH_TXD1 P2.9 X1-36 + /* 50 */ {XMC_GPIO_PORT15, 8}, // A16 / ETH_CLK P15.8 X1-38 //Additional pins for port X2 starting here - /* 61 */ {XMC_GPIO_PORT14, 8}, // A14 / DAC 0 Output P14.8 - /* 62 */ {XMC_GPIO_PORT15, 2}, // A12 - ADC Input P15.2 (INPUT ONLY) - /* 63 */ {XMC_GPIO_PORT14, 15}, // A11 - ADC Input P14.15 (INPUT ONLY) - /* 64 */ {XMC_GPIO_PORT15, 9}, // A17 - ADC Input / ETH_CRS P15.9 - /* 65 */ {XMC_GPIO_PORT14, 6}, // A6 / AN1_2GO_1 - ADC Input P14.6 (INPUT ONLY) - /* 66 */ {XMC_GPIO_PORT14, 12}, // A8 / AN1_2GO_2 - ADC Input P14.12 (INPUT ONLY) - /* 67 */ {XMC_GPIO_PORT14, 14}, // A10 / ADC Input P14.14 (INPUT ONLY) - /* 68 */ {XMC_GPIO_PORT3, 0}, // I2C Clk SCL / A5 - ADC Input P3.0 (Hardwired to A5) - /* 69 */ {XMC_GPIO_PORT3, 2}, // BUTTON2 P3.2 - /* 70 */ {XMC_GPIO_PORT0, 10}, // INT / GPIO3_2GO_1 P0.10 - /* 71 */ {XMC_GPIO_PORT0, 1}, // INT P0.1 - /* 72 */ {XMC_GPIO_PORT0, 3}, // INT / GPIO3_2GO_2 P0.3 - /* 73 */ {XMC_GPIO_PORT0, 5}, // USB Debug TX P0.5 - /* 74 */ {XMC_GPIO_PORT0, 11}, // PWM80-31 output / PWM3 P0.11 - /* 75 */ {XMC_GPIO_PORT3, 3}, // PWM42-3 output / PWM1 P3.3 - /* 76 */ {XMC_GPIO_PORT3, 5}, // CS_2GO_1 P3.5 (Chip Select - Slot 1) - /* 77 */ {XMC_GPIO_PORT0, 7}, // LED2 P0.7 - /* 78 */ {XMC_GPIO_PORT0, 8}, // QSPI_CLK P0.8 - /* 79 */ {XMC_GPIO_PORT3, 6}, // PWM42-0(PWM0)/ External INT 1 P3.6 - /* 80 */ {XMC_GPIO_PORT3, 4}, // PWM42-2 output / PWM2 P3.4 - /* 81 */ {XMC_GPIO_PORT0, 12}, // CS_MB P0.12 - /* 82 */ {XMC_GPIO_PORT0, 6}, // LED1 P0.6 - /* 83 */ {XMC_GPIO_PORT0, 4}, // ETH_TXEN P0.4 - /* 84 */ {XMC_GPIO_PORT0, 2}, // SPI-CS / PWM80-01 / PWM4 P0.2 - /* 85 */ {XMC_GPIO_PORT0, 0}, // SPI-MISO P0.0 - /* 86 */ {XMC_GPIO_PORT0, 9}, // GPIO4_2GO_1 / PWM80-01 / PWM P0.9 - /* 87 */ {XMC_GPIO_PORT3, 1}, // BUTTON1 P3.1 - /* 88 */ {XMC_GPIO_PORT14, 4}, // A4 - ADC Input / SDA P14.4 (Hardwired to SDA) - /* 89 */ {XMC_GPIO_PORT14, 13}, // A9 / AN2_2GO_2 - ADC Input P14.13 (INPUT ONLY) - /* 90 */ {XMC_GPIO_PORT14, 7}, // A7 / AN2_2GO_1 - ADC Input P14.7 (INPUT ONLY) - /* 91 */ {XMC_GPIO_PORT14, 5}, // A5 - ADC Input / SCL P14.5 (Hardwired to SCL) - /* 92 */ {XMC_GPIO_PORT14, 3}, // A3 - ADC Input P14.3 (INPUT ONLY) - /* 93 */ {XMC_GPIO_PORT15, 3}, // A13 - ADC Input P15.3 (INPUT ONLY) - /* 94 */ {XMC_GPIO_PORT14, 9} // A15 / DAC 1 Output P14.9 + /* 51 */ {XMC_GPIO_PORT14, 8}, // A14 / DAC 0 Output P14.8 X2-33 + /* 52 */ {XMC_GPIO_PORT15, 2}, // A12 - ADC Input P15.2 (INPUT ONLY) X2-32 + /* 53 */ {XMC_GPIO_PORT14, 15}, // A11 - ADC Input P14.15 (INPUT ONLY) X2-29 + /* 54 */ {XMC_GPIO_PORT15, 9}, // A17 - ADC Input / ETH_CRS P15.9 X2-27 + /* 55 */ {XMC_GPIO_PORT14, 6}, // A6 / AN1_2GO_1 - ADC Input P14.6 (INPUT ONLY) X2-25 + /* 56 */ {XMC_GPIO_PORT14, 12}, // A8 / AN1_2GO_2 - ADC Input P14.12 (INPUT ONLY) X2-23 + /* 57 */ {XMC_GPIO_PORT14, 14}, // A10 / ADC Input P14.14 (INPUT ONLY) X2-21 + /* 58 */ {XMC_GPIO_PORT3, 2}, // BUTTON2 P3.2 X2-17 + /* 59 */ {XMC_GPIO_PORT0, 10}, // INT / GPIO3_2GO_1 P0.10 X2-15 + /* 60 */ {XMC_GPIO_PORT0, 1}, // INT P0.1 X2-13 + /* 61 */ {XMC_GPIO_PORT0, 3}, // INT / GPIO3_2GO_2 P0.3 X2-11 + /* 62 */ {XMC_GPIO_PORT3, 5}, // CS_2GO_1 P3.5 (Chip Select - Slot 1) X2-3 + /* 63 */ {XMC_GPIO_PORT0, 7}, // LED2 P0.7 X2-1 + /* 64 */ {XMC_GPIO_PORT0, 8}, // QSPI_CLK P0.8 X2-4 + /* 65 */ {XMC_GPIO_PORT0, 12}, // CS_MB P0.12 (Chip Select - MikroBUS) X2-10 + /* 66 */ {XMC_GPIO_PORT0, 6}, // LED1 P0.6 X2-12 + /* 67 */ {XMC_GPIO_PORT0, 4}, // ETH_TXEN P0.4 X2-14 + /* 68 */ {XMC_GPIO_PORT0, 9}, // GPIO4_2GO_1 / PWM80-12 / PWM P0.9 X2-20 + /* 69 */ {XMC_GPIO_PORT3, 1}, // BUTTON1 P3.1 X2-22 + /* 70 */ {XMC_GPIO_PORT14, 13}, // A9 / AN2_2GO_2 - ADC Input P14.13 (INPUT ONLY) X2-26 + /* 71 */ {XMC_GPIO_PORT14, 7}, // A7 / AN2_2GO_1 - ADC Input P14.7 (INPUT ONLY) X2-28 + /* 72 */ {XMC_GPIO_PORT15, 3}, // A13 - ADC Input P15.3 (INPUT ONLY) X2-34 + /* 73 */ {XMC_GPIO_PORT14, 9} // A15 / DAC 1 Output P14.9 X2-36 }; const uint8_t GND = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); const uint8_t NUM_DIGITAL = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) );; const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { - /* 0 */ {CCU40, CCU40_CC43, 3, 0, CCU40_IN3_P1_0}, - /* 1 */ {CCU42, CCU42_CC40, 0, 1, CCU42_IN0_P3_6} + /* 0 */ {CCU40, CCU40_CC43, 3, 0, CCU40_IN3_P1_0}, + /* 1 */ {CCU42, CCU42_CC40, 0, 1, CCU42_IN0_P3_6} }; const uint8_t NUM_INTERRUPT = ( sizeof( mapping_interrupt ) / sizeof( XMC_PIN_INTERRUPT_t ) ); @@ -225,11 +213,10 @@ const uint8_t mapping_pin_PWM4[][ 2 ] = { { 3, 0 }, // PWM0 { 5, 1 }, // PWM1 { 6, 2 }, // PWM2 - { 11, 3 }, // PWM5 - { 27, 4 }, // PWM + { 27, 3 }, // PWM + { 29, 4 }, // PWM { 28, 5 }, // PWM - { 57, 6 }, // PWM - { 58, 7 }, // PWM + { 15, 6 }, // PWM { 255, 255 } }; /* Configurations of PWM channels for CCU4 type */ @@ -239,11 +226,10 @@ XMC_PWM4_t mapping_pwm4[] = {CCU42, CCU42_CC43, 3, mapping_port_pin[5], P3_3_AF_CCU42_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 5 P3.3 {CCU42, CCU42_CC42, 2, mapping_port_pin[6], P3_4_AF_CCU42_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P3.4 - //additional pwm outputs starting here {CCU41, CCU41_CC41, 1, mapping_port_pin[27], P2_4_AF_CCU41_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 27 P2.4 - {CCU41, CCU41_CC43, 3, mapping_port_pin[28], P2_2_AF_CCU41_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 28 P2.2 - {CCU41, CCU41_CC42, 2, mapping_port_pin[57], P2_3_AF_CCU41_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 57 P2.3 - {CCU41, CCU41_CC41, 0, mapping_port_pin[58], P2_5_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 58 P2.5 + {CCU41, CCU41_CC43, 3, mapping_port_pin[29], P2_2_AF_CCU41_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 29 P2.2 + {CCU41, CCU41_CC42, 2, mapping_port_pin[28], P2_3_AF_CCU41_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 28 P2.3 + {CCU41, CCU41_CC40, 0, mapping_port_pin[15], P2_5_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 15 P2.5 }; const uint8_t NUM_PWM4 = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); @@ -252,31 +238,29 @@ const uint8_t mapping_pin_PWM8[][ 2 ] = { { 9, 0 }, // PWM3 { 10, 1 }, // PWM4 { 26, 2 }, // PWM - { 29, 3 }, // PWM - { 30, 4 }, // PWM - { 54, 5 }, // PWM - { 55, 6 }, // PWM - { 59, 7 }, // PWM - { 86, 8 }, // PWM + { 30, 3 }, // PWM + { 31, 4 }, // PWM + { 46, 5 }, // PWM + { 47, 6 }, // PWM + { 49, 7 }, // PWM + { 68, 8 }, // PWM { 255, 255 } }; /* Configurations of PWM channels for CCU8 type */ XMC_PWM8_t mapping_pwm8[] = { - {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[9], P0_11_AF_CCU80_OUT31, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 9 P0.11 - {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[10], P0_2_AF_CCU80_OUT01, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 10 P0.2 - + {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[9], P0_11_AF_CCU80_OUT31, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 9 P0.11 + {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[10], P0_2_AF_CCU80_OUT01, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 10 P0.2 //additional pwm outputs starting here - {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[55], P2_7_AF_CCU80_OUT03, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 55 P2.7 - {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[86], P0_9_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 86 P0.9 - {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[30], P2_6_AF_CCU80_OUT13, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 30 P2.6 - {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[59], P2_9_AF_CCU80_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 59 P2.9 - {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[26], P2_8_AF_CCU80_OUT32, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 26 P2.8 - {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[54], P5_7_AF_CCU81_OUT02, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 54 P5.7 - {CCU81, CCU81_CC82, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[29], P2_0_AF_CCU81_OUT21, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED} // PWM disabled 29 P2.0 -/* {CCU81, CCU81_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[82], P5_5_AF_CCU81_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 82 P5.5 - {CCU81, CCU81_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[81], P5_3_AF_CCU81_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED} // PWM disabled 81 P5.3*/ + {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[26], P2_8_AF_CCU80_OUT32, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 26 P2.8 + {CCU81, CCU81_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[30], P2_0_AF_CCU81_OUT21, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 30 P2.0 + {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[31], P2_6_AF_CCU80_OUT13, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 31 P2.6 + {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[46], P5_7_AF_CCU81_OUT02, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 46 P5.7 + {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[47], P2_7_AF_CCU80_OUT03, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 47 P2.7 + {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[49], P2_9_AF_CCU80_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 49 P2.9 + {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[68], P0_9_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED} // PWM disabled 68 P0.9 }; + const uint8_t NUM_PWM8 = ( sizeof( mapping_pwm8 ) / sizeof( XMC_PWM8_t ) ); const uint8_t NUM_PWM = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ) + ( sizeof( mapping_pwm8 ) / sizeof( XMC_PWM8_t ) ); @@ -284,8 +268,8 @@ const uint8_t NUM_PWM = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ) /* Analog Pin mappings and configurations */ #ifdef DAC const uint8_t mapping_pin_DAC[][ 2 ] = { - { 61, 0 }, - { 94, 1 }, + { 51, 0 }, + { 73, 1 }, { 255, 255 } }; /* Analog Pin mappings and configurations */ @@ -297,16 +281,15 @@ XMC_ARD_DAC_t mapping_dac[] = const uint8_t NUM_ANALOG_OUTPUTS = ( sizeof( mapping_dac ) / sizeof( XMC_ARD_DAC_t ) ); #endif +//Result reg numbers are now equal to channel numbers XMC_ADC_t mapping_adc[] = { - //Result reg numbers are now equal to channel numbers {VADC, 0, VADC_G0, 0, 0, DISABLED}, {VADC, 1, VADC_G0, 0, 1, DISABLED}, {VADC, 2, VADC_G1, 1, 2, DISABLED}, {VADC, 3, VADC_G1, 1, 3, DISABLED}, {VADC, 0, VADC_G2, 2, 0, DISABLED}, {VADC, 1, VADC_G2, 2, 1, DISABLED}, - //Additional ADC channels starting here {VADC, 6, VADC_G2, 2, 6, DISABLED}, {VADC, 5, VADC_G2, 2, 5, DISABLED}, {VADC, 3, VADC_G2, 2, 3, DISABLED}, @@ -330,30 +313,46 @@ const uint8_t NUM_ANALOG_INPUTS = ( sizeof( mapping_adc ) / sizeof( XMC_ADC_t ) */ RingBuffer rx_buffer_0; RingBuffer tx_buffer_0; -#if (NUM_SERIAL > 1) -RingBuffer rx_buffer_1; -RingBuffer tx_buffer_1; -#endif -#ifdef SERIAL_HOSTPC XMC_UART_t XMC_UART_0 = { .channel = XMC_UART1_CH0, - .rx = { .port = (XMC_GPIO_PORT_t*)PORT0_BASE, + .rx = { +#ifdef SERIAL_HOSTPC + .port = (XMC_GPIO_PORT_t*)PORT0_BASE, .pin = (uint8_t)5 +#elif SERIAL_ONBOARD + .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)15 +#endif }, .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE }, - .tx = { .port = (XMC_GPIO_PORT_t*)PORT1_BASE, + .tx = { +#ifdef SERIAL_HOSTPC + .port = (XMC_GPIO_PORT_t*)PORT1_BASE, .pin = (uint8_t)15 +#elif SERIAL_ONBOARD + .port = (XMC_GPIO_PORT_t*)PORT2_BASE, + .pin = (uint8_t)14 +#endif }, - .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, + .tx_config = { +#ifdef SERIAL_HOSTPC + .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4, +#elif SERIAL_ONBOARD + .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, +#endif .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE }, +#ifdef SERIAL_HOSTPC .input_source_dx0 = (XMC_USIC_INPUT_t)USIC1_C0_DX0_P0_5, +#elif SERIAL_ONBOARD + .input_source_dx0 = (XMC_USIC_INPUT_t)USIC1_C0_DX0_P2_15, +#endif .input_source_dx1 = XMC_INPUT_INVALID, .input_source_dx2 = XMC_INPUT_INVALID, .input_source_dx3 = XMC_INPUT_INVALID, @@ -361,38 +360,9 @@ XMC_UART_t XMC_UART_0 = .irq_service_request = 0 }; -// Debug port +// Single Hardware Serial object for both UART interfaces HardwareSerial Serial( &XMC_UART_0, &rx_buffer_0, &tx_buffer_0 ); -#elif SERIAL_ONBOARD -XMC_UART_t XMC_UART_0 = - { - .channel = XMC_UART1_CH0, - .rx = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, - .pin = (uint8_t)15 - }, - .rx_config = { .mode = XMC_GPIO_MODE_INPUT_TRISTATE, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE - }, - .tx = { .port = (XMC_GPIO_PORT_t*)PORT2_BASE, - .pin = (uint8_t)14 - }, - .tx_config = { .mode = (XMC_GPIO_MODE_t) XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2, - .output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH, - .output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE - }, - .input_source_dx0 = (XMC_USIC_INPUT_t)USIC1_C0_DX0_P2_15, - .input_source_dx1 = XMC_INPUT_INVALID, - .input_source_dx2 = XMC_INPUT_INVALID, - .input_source_dx3 = XMC_INPUT_INVALID, - .irq_num = USIC0_5_IRQn, - .irq_service_request = 0 - }; - -// Debug port -HardwareSerial Serial( &XMC_UART_0, &rx_buffer_0, &tx_buffer_0 ); -#endif // Serial Interrupt and event handling #ifdef __cplusplus @@ -400,8 +370,6 @@ extern "C" { #endif void serialEventRun( ); void serialEvent( ) __attribute__((weak)); -void serialEvent1( ) __attribute__((weak)); - void serialEventRun( ) { @@ -410,28 +378,13 @@ if( serialEvent ) if( Serial.available( ) ) serialEvent( ); } -#if (NUM_SERIAL > 1) -if( serialEvent1 ) - { - if( Serial1.available( ) ) - serialEvent1( ); - } -#endif } - void USIC1_0_IRQHandler( ) { Serial.IrqHandler( ); } -#if (NUM_SERIAL > 1) -void USIC0_5_IRQHandler( void ) -{ -Serial1.IrqHandler(); -} -#endif - #ifdef __cplusplus } #endif @@ -439,9 +392,6 @@ Serial1.IrqHandler(); #ifdef __cplusplus extern HardwareSerial Serial; -#if (NUM_SERIAL > 1) -extern HardwareSerial Serial1; -#endif #endif /* cplusplus */ #endif diff --git a/variants/XMC4400/linker_script.ld b/variants/XMC4400/linker_script.ld old mode 100755 new mode 100644 diff --git a/variants/XMC4400/startup_XMC4400.S b/variants/XMC4400/startup_XMC4400.S old mode 100755 new mode 100644 diff --git a/variants/XMC4400/system_XMC4400.c b/variants/XMC4400/system_XMC4400.c old mode 100755 new mode 100644 diff --git a/variants/XMC4400/system_XMC4400.h b/variants/XMC4400/system_XMC4400.h old mode 100755 new mode 100644 diff --git a/variants/XMC4700/config/XMC4700_Radar_Baseboard/pins_arduino.h b/variants/XMC4700/config/XMC4700_Radar_Baseboard/pins_arduino.h index b32684a2..a7f36feb 100644 --- a/variants/XMC4700/config/XMC4700_Radar_Baseboard/pins_arduino.h +++ b/variants/XMC4700/config/XMC4700_Radar_Baseboard/pins_arduino.h @@ -36,7 +36,8 @@ // XMC_BOARD for stringifying into serial or other text outputs/logs // Note the actual name XMC and number MUST have a character between // to avoid issues with other defined macros e.g. XMC1100 -#define XMC_BOARD DEMO Radar BB XMC 4700 + +#define XMC_BOARD XMC 4700 Radar Baseboard /* On board LED is ON when digital output is 0, LOW, False, OFF */ #define XMC_LED_ON 0 @@ -65,8 +66,10 @@ extern const uint8_t NUM_ANALOG_OUTPUTS; // Board has two serial ports pre-assigned to debug and on-board -#define PWM4_TIMER_PERIOD (0x11EF) // Generate 490Hz @fCCU=144MHz -#define PWM8_TIMER_PERIOD (0x11EF) // Generate 490Hz @fCCU=144MHz +// Generate 490Hz @fCCU=144MHz +#define PWM4_TIMER_PERIOD (0x11EF) +// Generate 490Hz @fCCU=144MHz +#define PWM8_TIMER_PERIOD (0x11EF) #define PCLK 144000000u @@ -97,10 +100,14 @@ static const uint8_t SCK_SD = PIN_SPI_SCK_SD; #define A4 4 #define A5 5 -#define LED_RED 22 // LED Red channel -#define LED_GREEN 23 // LED Green channel -#define LED_BLUE 24 // LED Blue channel -#define BUTTON1 25 // Additional BUTTON1 +// LED Red channel +#define LED_RED 22 +// LED Green channel +#define LED_GREEN 23 +// LED Blue channel +#define LED_BLUE 24 +// Additional BUTTON1 +#define BUTTON1 25 #define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 32 ? 1 : NOT_AN_INTERRUPT)) @@ -151,7 +158,7 @@ const XMC_PORT_PIN_t mapping_port_pin[] = const uint8_t GND = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); const uint8_t NUM_DIGITAL = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) );; -#define INTERRUPT_USE_ERU + const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { /* 0 */ {XMC_ERU0, XMC_ERU_ETL_INPUT_A0, XMC_ERU_ETL_INPUT_B3, 2, 3, 0}, @@ -225,12 +232,8 @@ const uint8_t NUM_ANALOG_INPUTS = ( sizeof( mapping_adc ) / sizeof( XMC_ADC_t ) * * Serial 0 is Debug port * Serial 1 is on-board port - * - * See many XMC1x00 pins_arduino.h for proper way to handle HOSTPC -*/ -/* Following define gives REDFINITION Warning against the define for - INTERRUPT_USE_ERU above */ -#define SERIAL_USE_U1C1 + */ + RingBuffer rx_buffer_0; RingBuffer tx_buffer_0; diff --git a/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h b/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h index 2d214182..73a85240 100644 --- a/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h +++ b/variants/XMC4700/config/XMC4700_Relax_Kit/pins_arduino.h @@ -38,8 +38,8 @@ // to avoid issues with other defined macros e.g. XMC1100 #define XMC_BOARD XMC 4700 Relax Kit -/* On board LED is ON when digital output is 0, LOW, False, OFF */ -#define XMC_LED_ON 0 +/* On board LED is ON when digital output is 1, HIGH, TRUE, ON */ +#define XMC_LED_ON 1 // Following were defines now evaluated by compilation as const variables // After definitions of associated mapping arrays @@ -64,8 +64,10 @@ extern const uint8_t NUM_ANALOG_OUTPUTS; // Board has two serial ports pre-assigned to debug and on-board -#define PWM4_TIMER_PERIOD (0x11EF) // Generate 490Hz @fCCU=144MHz -#define PWM8_TIMER_PERIOD (0x11EF) // Generate 490Hz @fCCU=144MHz +// Generate 490Hz @fCCU=144MHz +#define PWM4_TIMER_PERIOD (0x11EF) +// Generate 490Hz @fCCU=144MHz +#define PWM8_TIMER_PERIOD (0x11EF) #define PCLK 144000000u @@ -96,33 +98,34 @@ static const uint8_t SCK_SD = PIN_SPI_SCK_SD; #define A4 4 #define A5 5 //Additional ADC ports starting here -#define A6 6 // ADC G2CH6 on P15.6 -#define A7 7 // ADC G2CH5 on P15.5 -#define A8 8 // ADC G2CH3 on P15.3 -#define A9 9 // ADC G1CH7 on P14.15 -#define A10 10 // ADC G1CH5 on P14.13 -#define A11 11 // ADC G0CH7 on P14.7 -#define A12 12 // ADC G3CH7 on P15.15 -#define A13 13 // ADC G1CH1 on P14.9 -#define A14 14 // ADC G1CH0 on P14.8 -#define A15 15 // ADC G3CH6 on P15.14 -#define A16 16 // ADC G0CH6 on P14.6 -#define A17 17 // ADC G1CH4 on P14.12 -#define A18 18 // ADC G1CH6 on P14.14 -#define A19 19 // ADC G2CH2 on P15.2 -#define A20 20 // ADC G2CH4 on P15.4 -#define A21 21 // ADC G2CH7 on P15.7 -// ADC G3CH0 on P15.8 not available -// ADC G3CH1 on P15.9 not available -// ADC G3CH4 on P15.12 button -// ADC G3CH5 on P15.13 button - - -#define LED1 24 // Additional LED1 -#define LED2 25 // Additional LED2 -#define LED_BUILTIN LED1 //Standard Arduino LED: Uses LED1 -#define BUTTON1 26 // Additional BUTTON1 -#define BUTTON2 27 // Additional BUTTON2 +#define A6 6 +#define A7 7 +#define A8 8 +#define A9 9 +#define A10 10 +#define A11 11 +#define A12 12 +#define A13 13 +#define A14 14 +#define A15 15 +#define A16 16 +#define A17 17 +#define A18 18 +#define A19 19 +#define A20 20 +#define A21 21 +// ADC G3CH0 on P15.8 not available +// ADC G3CH1 on P15.9 not available +// ADC G3CH4 on P15.12 button +// ADC G3CH5 on P15.13 button + + +#define LED1 24 +#define LED2 25 +#define LED_BUILTIN LED1 + +#define BUTTON1 26 +#define BUTTON2 27 #define digitalPinToInterrupt(p) ((p) == 2 ? 0 : ((p) == 3 ? 1 : NOT_AN_INTERRUPT)) @@ -130,9 +133,9 @@ static const uint8_t SCK_SD = PIN_SPI_SCK_SD; // Mapping of digital pins and comments /*** IMPORTANT NOTE - Extra entry at Arduino pin 23 is PLACEHOLDER - Duplicate wrong entry, but removing would mean changing many other - documents and reducing many pins for defines by 1 + Extra entries at Arduino pin 23 & 14 are PLACEHOLDERS + Invalid pin assignments, but removing would mean changing many other + documents and pins defines -> might break legacy code. ***/ const XMC_PORT_PIN_t mapping_port_pin[] = { @@ -150,7 +153,7 @@ const XMC_PORT_PIN_t mapping_port_pin[] = /* 11 */ {XMC_GPIO_PORT3, 8}, // SPI-MOSI / PWM41-2 / PWM5 P3.8 /* 12 */ {XMC_GPIO_PORT3, 7}, // SPI-MISO P3.7 /* 13 */ {XMC_GPIO_PORT3, 9}, // SPI-SCK P3.9 - /* 14 */ {XMC_GPIO_PORT2, 3}, // AREF TODO: P2.3 + /* 14 */ {XMC_GPIO_PORT2, 3}, // --- Note: DUMMY pin assignment, to prevent incompatibility of legacy code! INVALID --- /* 15 */ {XMC_GPIO_PORT3, 15}, // I2C Data / Address SDA / A4 P3.15 (Hardwired to A4) /* 16 */ {XMC_GPIO_PORT0, 13}, // I2C Clock SCL / A5 P0.13 (Hardwired to A5) /* 17 */ {XMC_GPIO_PORT14, 0}, // A0 / ADC Input P14.0 (INPUT ONLY) @@ -173,79 +176,79 @@ const XMC_PORT_PIN_t mapping_port_pin[] = /* 34 */ {XMC_GPIO_PORT1, 4}, // USB Debug RX P1.4 /* 35 */ {XMC_GPIO_PORT1, 5}, // USB Debug TX P1.5 - //Additional pins for port X1 starting here - /* 36 */ {XMC_GPIO_PORT3, 4}, // PWM42-2 / PWM12 P3.4 - /* 37 */ {XMC_GPIO_PORT0, 5}, // I2C_1 SDA // SPI_4 MOSI P0.5 - /* 38 */ {XMC_GPIO_PORT0, 3}, // PWM80-2 / PWM10 P0.3 - /* 39 */ {XMC_GPIO_PORT0, 1}, // PWM80-1 / PWM9 P0.1 - /* 40 */ {XMC_GPIO_PORT0, 10}, // P0.10 - /* 41 */ {XMC_GPIO_PORT3, 2}, // P3.2 - /* 42 */ {XMC_GPIO_PORT3, 1}, // P3.1 - /* 43 */ {XMC_GPIO_PORT15, 6}, // A6 / ADC Input P15.6 (INPUT ONLY) - /* 44 */ {XMC_GPIO_PORT15, 5}, // A7 / ADC Input P15.5 (INPUT ONLY) - /* 45 */ {XMC_GPIO_PORT15, 3}, // A8 / ADC Input P15.3 (INPUT ONLY) - /* 46 */ {XMC_GPIO_PORT14, 15}, // A9 / ADC Input P14.15 (INPUT ONLY) - /* 47 */ {XMC_GPIO_PORT14, 13}, // A10 / ADC Input P14.13 (INPUT ONLY) - /* 48 */ {XMC_GPIO_PORT14, 7}, // A11 / ADC Input P14.7 (INPUT ONLY) - /* 49 */ {XMC_GPIO_PORT15, 15}, // A12 / ADC Input P15.15 (INPUT ONLY) - /* 50 */ {XMC_GPIO_PORT14, 9}, // DAC0 // A13 / ADC Input P14.9 - /* 51 */ {XMC_GPIO_PORT2, 13}, // P2.13 - /* 52 */ {XMC_GPIO_PORT5, 10}, // P5.10 - /* 53 */ {XMC_GPIO_PORT5, 11}, // PWM80-0 / PWM6 P5.11 - /* 54 */ {XMC_GPIO_PORT1, 14}, // P1.14 - /* 55 */ {XMC_GPIO_PORT14, 8}, // DAC1 // A14 / ADC Input P14.8 - /* 56 */ {XMC_GPIO_PORT15, 14}, // A15 / ADC Input P15.14 (INPUT ONLY) - /* 57 */ {XMC_GPIO_PORT14, 6}, // A16 / ADC Input P14.6 (INPUT ONLY) - /* 58 */ {XMC_GPIO_PORT14, 12}, // A17 / ADC Input P14.12 (INPUT ONLY) - /* 59 */ {XMC_GPIO_PORT14, 14}, // A18 / ADC Input P14.14 (INPUT ONLY) - /* 60 */ {XMC_GPIO_PORT15, 2}, // A19 / ADC Input P15.2 (INPUT ONLY) - /* 61 */ {XMC_GPIO_PORT15, 4}, // A20 / ADC Input P15.4 (INPUT ONLY) - /* 62 */ {XMC_GPIO_PORT15, 7}, // A21 / ADC Input P15.7 (INPUT ONLY) - /* 63 */ {XMC_GPIO_PORT3, 0}, // PWM42-0 / PWM7 P3.0 - /* 64 */ {XMC_GPIO_PORT0, 9}, // PWM80-1 / PWM8 P0.9 - /* 65 */ {XMC_GPIO_PORT0, 0}, // P0.0 - /* 66 */ {XMC_GPIO_PORT0, 2}, // P0.2 - /* 67 */ {XMC_GPIO_PORT0, 4}, // SPI_4 MISO P0.4 - /* 68 */ {XMC_GPIO_PORT0, 6}, // PWM80-3 / PWM11 P0.6 - /* 69 */ {XMC_GPIO_PORT0, 11}, // I2C_1 SCL // SPI_4 SCLK P0.11 - - //Additional pins for port X2 starting here - /* 70 */ {XMC_GPIO_PORT3, 13}, // SPI_2 SCLK P3.13 - /* 71 */ {XMC_GPIO_PORT3, 11}, // SPI_2 MOSI P3.11 - /* 72 */ {XMC_GPIO_PORT0, 14}, // PWM40-1 / PWM21 P0.14 - /* 73 */ {XMC_GPIO_PORT3, 14}, // P3.14 - /* 74 */ {XMC_GPIO_PORT0, 7}, // P0.7 - /* 75 */ {XMC_GPIO_PORT1, 2}, // P1.2 - /* 76 */ {XMC_GPIO_PORT6, 1}, // P6.1 - /* 77 */ {XMC_GPIO_PORT5, 3}, // P5.3 - /* 78 */ {XMC_GPIO_PORT6, 5}, // PWM43-0 / PWM17 P6.5 - /* 79 */ {XMC_GPIO_PORT1, 15}, // PWM81-0 / PWM16 P1.15 - /* 80 */ {XMC_GPIO_PORT5, 1}, // SPI_3 MOSI P5.1 - /* 81 */ {XMC_GPIO_PORT5, 3}, // PWM81-2 / PWM15 P5.3 - /* 82 */ {XMC_GPIO_PORT5, 5}, // PWM81-1 / PWM14 P5.5 - /* 83 */ {XMC_GPIO_PORT5, 7}, // PWM81-0 / PWM13 P5.7 - /* 84 */ {XMC_GPIO_PORT2, 6}, // P2.6 - /* 85 */ {XMC_GPIO_PORT5, 6}, // P5.6 - /* 86 */ {XMC_GPIO_PORT5, 4}, // P5.4 - /* 87 */ {XMC_GPIO_PORT5, 2}, // P5.2 - /* 88 */ {XMC_GPIO_PORT5, 0}, // SPI_3 MISO P5.0 - /* 89 */ {XMC_GPIO_PORT6, 6}, // P6.6 - /* 90 */ {XMC_GPIO_PORT6, 4}, // PWM43-1 / PWM18 P6.4 - /* 91 */ {XMC_GPIO_PORT6, 2}, // PWM43-3 / PWM19 P6.2 - /* 92 */ {XMC_GPIO_PORT6, 0}, // P6.0 - /* 93 */ {XMC_GPIO_PORT0, 8}, // SPI_3 SCLK P0.8 - /* 94 */ {XMC_GPIO_PORT3, 3}, // P3.3 - /* 95 */ {XMC_GPIO_PORT0, 15}, // PWM40-0 / PWM20 P0.15 - /* 96 */ {XMC_GPIO_PORT0, 12}, // PWM40-3 / PWM22 P0.12 - /* 97 */ {XMC_GPIO_PORT3, 12} // ECAT0.P1_LINK_ACT P3.12 + //Additional pins for port X1 starting here + /* 36 */ {XMC_GPIO_PORT3, 4}, // PWM42-2 / PWM12 P3.4 X1-1 + /* 37 */ {XMC_GPIO_PORT0, 5}, // I2C_1 SDA // SPI_4 MOSI P0.5 X1-3 + /* 38 */ {XMC_GPIO_PORT0, 3}, // PWM80-2 / PWM10 P0.3 X1-5 + /* 39 */ {XMC_GPIO_PORT0, 1}, // PWM80-1 / PWM9 P0.1 X1-7 + /* 40 */ {XMC_GPIO_PORT0, 10}, // P0.10 X1-9 + /* 41 */ {XMC_GPIO_PORT3, 2}, // P3.2 X1-11 + /* 42 */ {XMC_GPIO_PORT3, 1}, // P3.1 X1-13 + /* 43 */ {XMC_GPIO_PORT15, 6}, // A6 / ADC Input P15.6 X1-15 + /* 44 */ {XMC_GPIO_PORT15, 5}, // A7 / ADC Input P15.5 X1-17 + /* 45 */ {XMC_GPIO_PORT15, 3}, // A8 / ADC Input P15.3 X1-19 + /* 46 */ {XMC_GPIO_PORT14, 15}, // A9 / ADC Input P14.15 X1-21 + /* 47 */ {XMC_GPIO_PORT14, 13}, // A10 / ADC Input P14.13 X1-23 + /* 48 */ {XMC_GPIO_PORT14, 7}, // A11 / ADC Input P14.7 X1-25 + /* 49 */ {XMC_GPIO_PORT15, 15}, // A12 / ADC Input P15.15 X1-27 + /* 50 */ {XMC_GPIO_PORT14, 9}, // DAC0 // A13 / ADC Input P14.9 X1-29 + /* 51 */ {XMC_GPIO_PORT2, 13}, // P2.13 X1-31 + /* 52 */ {XMC_GPIO_PORT5, 10}, // P5.10 X1-33 + /* 53 */ {XMC_GPIO_PORT5, 11}, // PWM80-0 / PWM6 P5.11 X1-34 + /* 54 */ {XMC_GPIO_PORT1, 14}, // P1.14 X1-32 + /* 55 */ {XMC_GPIO_PORT14, 8}, // DAC1 // A14 / ADC Input P14.8 X1-30 + /* 56 */ {XMC_GPIO_PORT15, 14}, // A15 / ADC Input P15.14 X1-28 + /* 57 */ {XMC_GPIO_PORT14, 6}, // A16 / ADC Input P14.6 X1-26 + /* 58 */ {XMC_GPIO_PORT14, 12}, // A17 / ADC Input P14.12 X1-24 + /* 59 */ {XMC_GPIO_PORT14, 14}, // A18 / ADC Input P14.14 X1-22 + /* 60 */ {XMC_GPIO_PORT15, 2}, // A19 / ADC Input P15.2 X1-20 + /* 61 */ {XMC_GPIO_PORT15, 4}, // A20 / ADC Input P15.4 X1-18 + /* 62 */ {XMC_GPIO_PORT15, 7}, // A21 / ADC Input P15.7 X1-16 + /* 63 */ {XMC_GPIO_PORT3, 0}, // PWM42-0 / PWM7 P3.0 X1-14 + /* 64 */ {XMC_GPIO_PORT0, 9}, // PWM80-1 / PWM8 P0.9 X1-12 + /* 65 */ {XMC_GPIO_PORT0, 0}, // P0.0 X1-10 + /* 66 */ {XMC_GPIO_PORT0, 2}, // P0.2 X1-8 + /* 67 */ {XMC_GPIO_PORT0, 4}, // SPI_4 MISO P0.4 X1-6 + /* 68 */ {XMC_GPIO_PORT0, 6}, // PWM80-3 / PWM11 P0.6 X1-4 + /* 69 */ {XMC_GPIO_PORT0, 11}, // I2C_1 SCL // SPI_4 SCLK P0.11 X1-2 + + //Additional pins for port X2 starting here + /* 70 */ {XMC_GPIO_PORT3, 13}, // SPI_2 SCLK P3.13 X2-1 + /* 71 */ {XMC_GPIO_PORT3, 11}, // SPI_2 MOSI P3.11 X2-3 + /* 72 */ {XMC_GPIO_PORT0, 14}, // PWM40-1 / PWM21 P0.14 X2-5 + /* 73 */ {XMC_GPIO_PORT3, 14}, // P3.14 X2-7 + /* 74 */ {XMC_GPIO_PORT0, 7}, // P0.7 X2-9 + /* 75 */ {XMC_GPIO_PORT1, 2}, // P1.2 X2-11 + /* 76 */ {XMC_GPIO_PORT6, 1}, // P6.1 X2-13 + /* 77 */ {XMC_GPIO_PORT5, 3}, // P5.3 X2-15 + /* 78 */ {XMC_GPIO_PORT6, 5}, // PWM43-0 / PWM17 P6.5 X2-17 + /* 79 */ {XMC_GPIO_PORT1, 15}, // PWM81-0 / PWM16 P1.15 X2-19 + /* 80 */ {XMC_GPIO_PORT5, 1}, // SPI_3 MOSI P5.1 X2-21 + /* 81 */ {XMC_GPIO_PORT5, 3}, // PWM81-2 / PWM15 P5.3 X2-23 + /* 82 */ {XMC_GPIO_PORT5, 5}, // PWM81-1 / PWM14 P5.5 X2-25 + /* 83 */ {XMC_GPIO_PORT5, 7}, // PWM81-0 / PWM13 P5.7 X2-27 + /* 84 */ {XMC_GPIO_PORT2, 6}, // P2.6 X2-28 + /* 85 */ {XMC_GPIO_PORT5, 6}, // P5.6 X2-26 + /* 86 */ {XMC_GPIO_PORT5, 4}, // P5.4 X2-24 + /* 87 */ {XMC_GPIO_PORT5, 2}, // P5.2 X2-22 + /* 88 */ {XMC_GPIO_PORT5, 0}, // SPI_3 MISO P5.0 X2-20 + /* 89 */ {XMC_GPIO_PORT6, 6}, // P6.6 X2-18 + /* 90 */ {XMC_GPIO_PORT6, 4}, // PWM43-1 / PWM18 P6.4 X2-16 + /* 91 */ {XMC_GPIO_PORT6, 2}, // PWM43-3 / PWM19 P6.2 X2-14 + /* 92 */ {XMC_GPIO_PORT6, 0}, // P6.0 X2-12 + /* 93 */ {XMC_GPIO_PORT0, 8}, // SPI_3 SCLK P0.8 X2-10 + /* 94 */ {XMC_GPIO_PORT3, 3}, // P3.3 X2-8 + /* 95 */ {XMC_GPIO_PORT0, 15}, // PWM40-0 / PWM20 P0.15 X2-6 + /* 96 */ {XMC_GPIO_PORT0, 12}, // PWM40-3 / PWM22 P0.12 X2-4 + /* 97 */ {XMC_GPIO_PORT3, 12} // ECAT0.P1_LINK_ACT P3.12 X2-2 }; const uint8_t GND = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) ); const uint8_t NUM_DIGITAL = ( sizeof( mapping_port_pin ) / sizeof( XMC_PORT_PIN_t ) );; const XMC_PIN_INTERRUPT_t mapping_interrupt[] = { - /* 0 */ {CCU40, CCU40_CC43, 3, 0, CCU40_IN3_P1_0}, - /* 1 */ {CCU40, CCU40_CC42, 2, 1, CCU40_IN2_P1_1} + /* 0 */ {CCU40, CCU40_CC43, 3, 0, CCU40_IN3_P1_0}, + /* 1 */ {CCU40, CCU40_CC42, 2, 1, CCU40_IN2_P1_1} }; const uint8_t NUM_INTERRUPT = ( sizeof( mapping_interrupt ) / sizeof( XMC_PIN_INTERRUPT_t ) ); @@ -274,15 +277,14 @@ XMC_PWM4_t mapping_pwm4[] = {CCU40, CCU40_CC42, 2, mapping_port_pin[3], P1_1_AF_CCU40_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 3 P1.1 {CCU41, CCU41_CC40, 0, mapping_port_pin[10], P3_10_AF_CCU41_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 10 P3.10 {CCU41, CCU41_CC42, 2, mapping_port_pin[11], P3_8_AF_CCU41_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 11 P3.8 - //additional pwm outputs starting here - {CCU40, CCU40_CC40, 0, mapping_port_pin[95], P0_15_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 95 P0.15 - {CCU40, CCU40_CC41, 1, mapping_port_pin[72], P0_14_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 72 P0.14 - {CCU40, CCU40_CC43, 3, mapping_port_pin[96], P0_12_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 96 P0.12 - {CCU42, CCU42_CC40, 0, mapping_port_pin[63], P3_0_AF_CCU42_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 63 P3.0 - {CCU42, CCU42_CC42, 2, mapping_port_pin[36], P3_4_AF_CCU42_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 36 P3.4 - {CCU43, CCU43_CC40, 0, mapping_port_pin[78], P6_5_AF_CCU43_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 78 P6.5 - {CCU43, CCU43_CC41, 1, mapping_port_pin[90], P6_4_AF_CCU43_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 90 P6.4 - {CCU43, CCU43_CC43, 3, mapping_port_pin[91], P6_2_AF_CCU43_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 91 P6.2 + {CCU40, CCU40_CC40, 0, mapping_port_pin[95], P0_15_AF_CCU40_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 95 P0.15 + {CCU40, CCU40_CC41, 1, mapping_port_pin[72], P0_14_AF_CCU40_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 72 P0.14 + {CCU40, CCU40_CC43, 3, mapping_port_pin[96], P0_12_AF_CCU40_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 96 P0.12 + {CCU42, CCU42_CC40, 0, mapping_port_pin[63], P3_0_AF_CCU42_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 63 P3.0 + {CCU42, CCU42_CC42, 2, mapping_port_pin[36], P3_4_AF_CCU42_OUT2, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 36 P3.4 + {CCU43, CCU43_CC40, 0, mapping_port_pin[78], P6_5_AF_CCU43_OUT0, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 78 P6.5 + {CCU43, CCU43_CC41, 1, mapping_port_pin[90], P6_4_AF_CCU43_OUT1, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED}, // PWM disabled 90 P6.4 + {CCU43, CCU43_CC43, 3, mapping_port_pin[91], P6_2_AF_CCU43_OUT3, XMC_CCU4_SLICE_PRESCALER_64, PWM4_TIMER_PERIOD, DISABLED} // PWM disabled 91 P6.2 }; const uint8_t NUM_PWM4 = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ); @@ -308,16 +310,15 @@ XMC_PWM8_t mapping_pwm8[] = {CCU81, CCU81_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[5], P2_12_AF_CCU81_OUT33, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 5 P2.12 {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[6], P2_11_AF_CCU80_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 6 P2.11 {CCU81, CCU81_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[9], P1_11_AF_CCU81_OUT11, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 9 P1.11 - //additional pwm outputs starting here - {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[53], P5_11_AF_CCU80_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 53 P5.11 - {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[39], P0_1_AF_CCU80_OUT11, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 39 P0.1 - {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[64], P0_9_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 64 P0.9 - {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[38], P0_3_AF_CCU80_OUT20, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 38 P0.3 - {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[68], P0_6_AF_CCU80_OUT30, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 68 P0.6 - {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[79], P1_15_AF_CCU81_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 79 P1.15 - {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[83], P5_7_AF_CCU81_OUT02, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 83 P5.7 - {CCU81, CCU81_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[82], P5_5_AF_CCU81_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 82 P5.5 - {CCU81, CCU81_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[81], P5_3_AF_CCU81_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED} // PWM disabled 81 P5.3 + {CCU80, CCU80_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[53], P5_11_AF_CCU80_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 53 P5.11 + {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[39], P0_1_AF_CCU80_OUT11, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 39 P0.1 + {CCU80, CCU80_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[64], P0_9_AF_CCU80_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 64 P0.9 + {CCU80, CCU80_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[38], P0_3_AF_CCU80_OUT20, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 38 P0.3 + {CCU80, CCU80_CC83, 3, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[68], P0_6_AF_CCU80_OUT30, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 68 P0.6 + {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_1, mapping_port_pin[79], P1_15_AF_CCU81_OUT00, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 79 P1.15 + {CCU81, CCU81_CC80, 0, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[83], P5_7_AF_CCU81_OUT02, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 83 P5.7 + {CCU81, CCU81_CC81, 1, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[82], P5_5_AF_CCU81_OUT12, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED}, // PWM disabled 82 P5.5 + {CCU81, CCU81_CC82, 2, XMC_CCU8_SLICE_COMPARE_CHANNEL_2, mapping_port_pin[81], P5_3_AF_CCU81_OUT22, XMC_CCU8_SLICE_PRESCALER_64, PWM8_TIMER_PERIOD, DISABLED} // PWM disabled 81 P5.3 }; const uint8_t NUM_PWM8 = ( sizeof( mapping_pwm8 ) / sizeof( XMC_PWM8_t ) ); const uint8_t NUM_PWM = ( sizeof( mapping_pwm4 ) / sizeof( XMC_PWM4_t ) ) @@ -331,38 +332,37 @@ const uint8_t mapping_pin_DAC[][ 2 ] = { { 255, 255 } }; XMC_ARD_DAC_t mapping_dac[] = { - {XMC_DAC0, 1, 12}, - {XMC_DAC0, 0, 12} + {XMC_DAC0, 1, 12}, + {XMC_DAC0, 0, 12} }; const uint8_t NUM_ANALOG_OUTPUTS = ( sizeof( mapping_dac ) / sizeof( XMC_ARD_DAC_t ) ); #endif +//Result reg numbers are now equal to channel numbers XMC_ADC_t mapping_adc[] = { - //Result reg numbers are now equal to channel numbers - {VADC, 0, VADC_G0, 0, 0, DISABLED}, + {VADC, 0, VADC_G0, 0, 0, DISABLED}, {VADC, 1, VADC_G0, 0, 1, DISABLED}, {VADC, 2, VADC_G1, 1, 2, DISABLED}, {VADC, 3, VADC_G1, 1, 3, DISABLED}, {VADC, 0, VADC_G2, 2, 0, DISABLED}, {VADC, 1, VADC_G2, 2, 1, DISABLED}, - //Additional ADC channels starting here - {VADC, 6, VADC_G2, 2, 6, DISABLED}, - {VADC, 5, VADC_G2, 2, 5, DISABLED}, - {VADC, 3, VADC_G2, 2, 3, DISABLED}, - {VADC, 7, VADC_G1, 1, 7, DISABLED}, - {VADC, 5, VADC_G1, 1, 5, DISABLED}, - {VADC, 7, VADC_G0, 0, 7, DISABLED}, - {VADC, 7, VADC_G3, 3, 7, DISABLED}, - {VADC, 1, VADC_G1, 1, 1, DISABLED}, - {VADC, 0, VADC_G1, 1, 0, DISABLED}, - {VADC, 6, VADC_G3, 3, 6, DISABLED}, - {VADC, 6, VADC_G0, 0, 6, DISABLED}, - {VADC, 4, VADC_G1, 1, 4, DISABLED}, - {VADC, 6, VADC_G1, 1, 6, DISABLED}, - {VADC, 2, VADC_G2, 2, 2, DISABLED}, - {VADC, 4, VADC_G2, 2, 4, DISABLED}, - {VADC, 7, VADC_G2, 2, 7, DISABLED} + {VADC, 6, VADC_G2, 2, 6, DISABLED}, + {VADC, 5, VADC_G2, 2, 5, DISABLED}, + {VADC, 3, VADC_G2, 2, 3, DISABLED}, + {VADC, 7, VADC_G1, 1, 7, DISABLED}, + {VADC, 5, VADC_G1, 1, 5, DISABLED}, + {VADC, 7, VADC_G0, 0, 7, DISABLED}, + {VADC, 7, VADC_G3, 3, 7, DISABLED}, + {VADC, 1, VADC_G1, 1, 1, DISABLED}, + {VADC, 0, VADC_G1, 1, 0, DISABLED}, + {VADC, 6, VADC_G3, 3, 6, DISABLED}, + {VADC, 6, VADC_G0, 0, 6, DISABLED}, + {VADC, 4, VADC_G1, 1, 4, DISABLED}, + {VADC, 6, VADC_G1, 1, 6, DISABLED}, + {VADC, 2, VADC_G2, 2, 2, DISABLED}, + {VADC, 4, VADC_G2, 2, 4, DISABLED}, + {VADC, 7, VADC_G2, 2, 7, DISABLED} }; const uint8_t NUM_ANALOG_INPUTS = ( sizeof( mapping_adc ) / sizeof( XMC_ADC_t ) );