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JackyJia73JackyJia73
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Merge pull request ChibiOS#395 from qmk-arterytek/f415_patch
Patch update for AT32F415
1 parent 91aefa4 commit 9a4d1a4

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11 files changed

+669
-721
lines changed

11 files changed

+669
-721
lines changed

‎os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -204,4 +204,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
204204
* @}
205205
*/
206206

207-
/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
207+
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/

‎os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h

+3-8
Original file line numberDiff line numberDiff line change
@@ -470,10 +470,7 @@ typedef struct
470470
{
471471
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
472472
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
473-
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
474-
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
475-
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
476-
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
473+
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
477474
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
478475
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
479476
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
@@ -696,9 +693,7 @@ typedef struct
696693

697694
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
698695
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
699-
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
700-
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
701-
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
696+
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
702697
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */
703698

704699
#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -10494,4 +10489,4 @@ typedef struct
1049410489

1049510490
#endif /* __AT32F415Cx_H */
1049610491

10497-
/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
10492+
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/

‎os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h

+3-8
Original file line numberDiff line numberDiff line change
@@ -469,10 +469,7 @@ typedef struct
469469
{
470470
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
471471
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
472-
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
473-
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
474-
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
475-
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
472+
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
476473
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
477474
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
478475
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
@@ -694,9 +691,7 @@ typedef struct
694691

695692
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
696693
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
697-
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
698-
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
699-
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
694+
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
700695
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */
701696

702697
#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -10444,4 +10439,4 @@ typedef struct
1044410439

1044510440
#endif /* __AT32F415Kx_H */
1044610441

10447-
/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
10442+
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/

‎os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h

+3-8
Original file line numberDiff line numberDiff line change
@@ -472,10 +472,7 @@ typedef struct
472472
{
473473
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
474474
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
475-
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
476-
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
477-
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
478-
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
475+
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
479476
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
480477
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
481478
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
@@ -700,9 +697,7 @@ typedef struct
700697

701698
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
702699
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
703-
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
704-
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
705-
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
700+
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
706701
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */
707702

708703
#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -10537,4 +10532,4 @@ typedef struct
1053710532

1053810533
#endif /* __AT32F415Rx_H */
1053910534

10540-
/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
10535+
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/

‎os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -109,4 +109,4 @@ extern void SystemCoreClockUpdate(void);
109109
* @}
110110
*/
111111

112-
/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
112+
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/

‎os/hal/boards/AT_START_F415/board.h

+1-3
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,6 @@
173173
* PA0 - Normal input (GPIOA_BUTTON)
174174
* PA2 - Alternate output (GPIOA_ARD_D1, GPIOA_USART2_TX)
175175
* PA3 - Normal input (GPIOA_ARD_D0, GPIOA_USART2_RX)
176-
* PA13 - Pull-up input (GPIOA_SWDIO)
177176
* PA14 - Pull-down input (GPIOA_SWCLK)
178177
*/
179178
#define VAL_GPIOACFGLR 0x88884B84 /* PA7...PA0 */
@@ -182,8 +181,6 @@
182181

183182
/*
184183
* Port B setup.
185-
* Everything input with pull-up except:
186-
* PB3 - Pull-up input (GPIOB_SWO)
187184
*/
188185
#define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */
189186
#define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */
@@ -203,6 +200,7 @@
203200

204201
/*
205202
* Port D setup.
203+
* Everything input with pull-up except:
206204
* PD0 - Normal input (GPIOD_OSC_IN).
207205
* PD1 - Normal input (GPIOD_OSC_OUT).
208206
*/

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