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pci: add device enumeration code
Add probe_pci, probe_pci_bus, and init_pci functions. init_pci is called from kernel_start to setup the PCI subsystem. In turn, init_pci calls probe_pci, which initializes the host bridge and then recursively enumerates the rest of the PCI devices on the system by calling probe_pci_bus. Each device's basic config space is stored in the pcidev_t structure, along with a pointer to the device's parent bridge and a list_head_t node. When a device is found, it is added to the global pci_list structure for later reference. Signed-off-by: Connor Davis <[email protected]>
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‎common/pci.c

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/*
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* Copyright © 2022 Amazon.com, Inc. or its affiliates.
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* All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <list.h>
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#include <mm/slab.h>
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#include <pci.h>
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#include <pci_cfg.h>
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#include <string.h>
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static list_head_t pci_list = LIST_INIT(pci_list);
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static inline uint8_t pci_dev_hdr_type(pcidev_t *dev) {
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return dev->hdr & PCI_HDR_TYPE;
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}
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static inline bool pci_dev_is_multifunc(pcidev_t *dev) {
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return ((dev->hdr & PCI_HDR_MULTIFUNC) != 0);
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}
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static pcidev_t *probe_pci_dev(uint8_t bus, uint8_t dev, uint8_t func, uint32_t device_vendor) {
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uint32_t cfg_val;
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pcidev_t *new_dev = kzalloc(sizeof(*new_dev));
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if (NULL == new_dev)
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return NULL;
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new_dev->segment = 0;
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new_dev->bus = bus;
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new_dev->dev = dev;
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new_dev->func = func;
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new_dev->vendor_id = PCI_VENDOR(device_vendor);
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new_dev->device_id = PCI_DEVICE(device_vendor);
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cfg_val = pci_cfg_read(bus, dev, func, PCI_REG_COMMAND);
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new_dev->command = PCI_COMMAND(cfg_val);
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new_dev->status = PCI_STATUS(cfg_val);
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cfg_val = pci_cfg_read(bus, dev, func, PCI_REG_CLASS);
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new_dev->class = PCI_CLASS(cfg_val);
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new_dev->subclass = PCI_SUBCLASS(cfg_val);
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cfg_val = pci_cfg_read(bus, dev, func, PCI_REG_HDR);
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new_dev->hdr = PCI_HDR(cfg_val);
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if (new_dev->status & PCI_STATUS_CAP_LIST)
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new_dev->cap_ptr = pci_cfg_read8(bus, dev, func, PCI_REG_CAP_PTR);
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return new_dev;
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}
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static void probe_pci_bus(uint8_t bus, uint8_t start_dev, pcidev_t *bridge) {
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for (uint8_t dev = start_dev; dev < PCI_NR_DEV; dev++) {
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for (uint8_t func = 0; func < PCI_NR_FUNC; func++) {
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pcidev_t *new_dev;
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uint32_t cfg_val;
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cfg_val = pci_cfg_read(bus, dev, func, PCI_REG_VENDOR);
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if (!PCI_DEV_EXISTS(cfg_val)) {
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continue;
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}
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new_dev = probe_pci_dev(bus, dev, func, cfg_val);
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BUG_ON(!new_dev);
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new_dev->bridge = bridge;
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snprintf(&new_dev->bdf_str[0], sizeof(new_dev->bdf_str), "%02x:%1x.%1x", bus,
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dev, func);
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list_add_tail(&new_dev->list, &pci_list);
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if (pci_dev_hdr_type(new_dev) == PCI_HDR_TYPE_PCI_BRIDGE) {
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uint8_t secondary, subordinate;
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cfg_val = pci_cfg_read(bus, dev, func, PCI_REG_BUS);
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secondary = PCI_SEC_BUS(cfg_val);
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subordinate = PCI_SUB_BUS(cfg_val);
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for (uint8_t b = secondary; b <= subordinate; b++) {
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probe_pci_bus(b, 0, new_dev);
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}
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}
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if (!pci_dev_is_multifunc(new_dev))
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break;
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}
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}
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}
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static void probe_pci(void) {
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pcidev_t *host_bridge;
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uint32_t cfg_val;
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uint32_t class_reg;
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const uint8_t bus = 0;
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const uint8_t dev = 0;
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const uint8_t func = 0;
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const uint32_t vendor_reg = pci_cfg_read(bus, dev, func, PCI_REG_VENDOR);
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if (!PCI_DEV_EXISTS(vendor_reg)) {
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printk("pci: non-existent host bridge @ 00.0.0\n");
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return;
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}
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class_reg = pci_cfg_read(bus, dev, func, PCI_REG_CLASS);
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if (PCI_CLASS(class_reg) != PCI_CLASS_BRIDGE && PCI_SUBCLASS(class_reg) != PCI_SUBCLASS_HOST_BRIDGE) {
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printk("pci: expected host bridge class code @ 00.0.0\n");
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return;
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}
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/* Found the host bridge, initialize it */
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host_bridge = kzalloc(sizeof(*host_bridge));
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BUG_ON(!host_bridge);
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host_bridge->segment = 0;
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host_bridge->vendor_id = PCI_VENDOR(vendor_reg);
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host_bridge->device_id = PCI_DEVICE(vendor_reg);
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cfg_val = pci_cfg_read(bus, dev, func, PCI_REG_COMMAND);
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host_bridge->command = PCI_COMMAND(cfg_val);
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host_bridge->status = PCI_STATUS(cfg_val);
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host_bridge->class = PCI_CLASS_BRIDGE;
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host_bridge->subclass = PCI_SUBCLASS_HOST_BRIDGE;
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host_bridge->bridge = NULL;
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strncpy(&host_bridge->bdf_str[0], "00:0.0", sizeof(host_bridge->bdf_str));
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list_add_tail(&host_bridge->list, &pci_list);
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/* Probe the rest of bus 0 */
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probe_pci_bus(0, 1, host_bridge);
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return;
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}
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void init_pci(void) {
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pcidev_t *dev;
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printk("Initializing PCI\n");
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probe_pci();
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list_for_each_entry (dev, &pci_list, list) {
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printk("pci: found device at %s\n", &dev->bdf_str[0]);
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}
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}

‎common/setup.c

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@@ -34,6 +34,7 @@
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#include <multiboot.h>
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#include <page.h>
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#include <pagetable.h>
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#include <pci.h>
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#include <percpu.h>
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#include <real_mode.h>
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#include <sched.h>
@@ -290,6 +291,8 @@ void __noreturn __text_init kernel_start(uint32_t multiboot_magic,
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init_ioapic();
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init_pci();
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/* Initialize console input */
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uart_input_init(get_bsp_cpu_id());
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‎include/pci.h

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/*
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* Copyright © 2022 Amazon.com, Inc. or its affiliates.
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* All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16+
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef KTF_PCI_H
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#define KTF_PCI_H
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#include <list.h>
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#define PCI_NR_BUS 256
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#define PCI_NR_DEV 32
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#define PCI_NR_FUNC 8
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#define PCI_VENDOR_MASK 0x0000FFFF
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#define PCI_VENDOR_INVALID 0xFFFF
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#define PCI_DEVICE_MASK 0xFFFF0000
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#define PCI_DEVICE_SHIFT 16
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#define PCI_COMMAND_MASK 0x0000FFFF
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#define PCI_STATUS_MASK 0xFFFF0000
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#define PCI_STATUS_SHIFT 16
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#define PCI_STATUS_CAP_LIST (1U << 4)
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#define PCI_CLASS_MASK 0xFF000000
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#define PCI_CLASS_SHIFT 24
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_SUBCLASS_MASK 0x00FF0000
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#define PCI_SUBCLASS_SHIFT 16
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#define PCI_SUBCLASS_HOST_BRIDGE 0x0
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#define PCI_HDR_MASK 0x00FF0000
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#define PCI_HDR_SHIFT 16
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#define PCI_HDR_TYPE 0x7F
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#define PCI_HDR_TYPE_NORMAL 0x00
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#define PCI_HDR_TYPE_PCI_BRIDGE 0x01
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#define PCI_HDR_MULTIFUNC 0x80
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#define PCI_SEC_BUS_MASK 0x0000FF00
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#define PCI_SEC_BUS_SHIFT 8
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#define PCI_SUB_BUS_MASK 0x00FF0000
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#define PCI_SUB_BUS_SHIFT 16
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#define PCI_REG_VENDOR 0x0
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#define PCI_REG_COMMAND 0x1
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#define PCI_REG_CLASS 0x2
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#define PCI_REG_HDR 0x3
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#define PCI_REG_BUS 0x6
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#define PCI_REG_CAP_PTR 0xD
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#define PCI_VENDOR(cfg_reg0) (cfg_reg0 & PCI_VENDOR_MASK)
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#define PCI_DEVICE(cfg_reg0) ((cfg_reg0 & PCI_DEVICE_MASK) >> PCI_DEVICE_SHIFT)
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#define PCI_COMMAND(cfg_reg1) (cfg_reg1 & PCI_COMMAND_MASK)
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#define PCI_STATUS(cfg_reg1) ((cfg_reg1 & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT)
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#define PCI_CLASS(cfg_reg2) ((cfg_reg2 & PCI_CLASS_MASK) >> PCI_CLASS_SHIFT)
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#define PCI_SUBCLASS(cfg_reg2) ((cfg_reg2 & PCI_SUBCLASS_MASK) >> PCI_SUBCLASS_SHIFT)
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#define PCI_HDR(cfg_reg3) ((cfg_reg3 & PCI_HDR_MASK) >> PCI_HDR_SHIFT)
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#define PCI_SEC_BUS(cfg_reg6) ((cfg_reg6 & PCI_SEC_BUS_MASK) >> PCI_SEC_BUS_SHIFT)
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#define PCI_SUB_BUS(cfg_reg6) ((cfg_reg6 & PCI_SUB_BUS_MASK) >> PCI_SUB_BUS_SHIFT)
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#define PCI_DEV_EXISTS(cfg_reg0) (PCI_VENDOR(cfg_reg0) != PCI_VENDOR_INVALID)
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struct pcidev {
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list_head_t list;
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uint32_t segment : 16;
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uint32_t bus : 8;
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uint32_t dev : 5;
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uint32_t func : 3;
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command;
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uint16_t status;
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uint8_t subclass;
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uint8_t class;
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uint8_t hdr;
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uint8_t cap_ptr;
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struct pcidev *bridge;
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char bdf_str[7];
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};
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typedef struct pcidev pcidev_t;
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extern void init_pci(void);
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#endif /* KTF_PCI_H */

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