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6502_Emu_CMOS.inc
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;
; 6502 EMULATOR include
;
; C M O S c o r e a.k.a. 65C02
;
; Copyright (C) 2013-2018 Klaus Dormann
;
; This program is free software: you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation, either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
;
;
.set core_version = 840
#define core_string "65C02" ;identify CMOS core in version message
;*****************************************************************
;
; 6502 emulation disassembly table
;
;*****************************************************************
;addressing modes
.equ op_s = 0b0000000 ;single (implied) - TAX
.equ op_a = 0b0010000 ;absolute - LDA abs
.equ op_x = 0b0010001 ;absolute indexed X - LDA abs,x
.equ op_y = 0b0010010 ;absolute indexed Y - LDA abs,y
.equ op_i = 0b1010011 ;absolute indirect - JMP (abs)
.equ op_m = 0b0101000 ;immediate - LDA #
.equ op_r = 0b0011000 ;relative to PC - BEQ rel
.equ op_z = 0b0001000 ;zero page - LDA zp
.equ op_zxi = 0b1001100 ;zero page indexed X indirect LDA (zp,x)
.equ op_zx = 0b0001001 ;zero page indexed X - LDA zp,x
.equ op_zy = 0b0001010 ;zero page indexed Y - LDA zp,y
.equ op_ziy = 0b1001101 ;zero page indidrect indexed Y - LDA (zp),y
.equ op_sa = 0b0000110 ;single accumulator - ASL A
; additional CMOS addressing modes
.equ op_zi = 0b1001011 ;zero page indidrect - LDA (zp)
.equ op_xi = 0b1010100 ;absolute indexed X indirect - JMP (abs,x)
.equ op_bz = 0b1101000 ;bitnum, zero page - RMB bit,zp
.equ op_bzr = 0b1101111 ;bitnum, zero page, relative - BBR bit,zp,rel
; 0b00_____ no prefix
; 0b01_____ # - immediate
; 0b10_____ ( - opening indirect
; 0b11_____ bitnumber, - SMB, RMB, BBS, BBR
; 0b__00___ no data - implied
; 0b__01___ 1 Byte - zero page or immediate
; 0b__10___ 2 Bytes - absolute
; 0b__11___ 1 Byte relative - calculated absolute
; 0b____000 no suffix
; 0b____001 ,X - indexed X
; 0b____010 ,Y - indexed Y
; 0b____011 ) - closing indirect
; 0b____100 ,X) - indexed X indirect
; 0b____101 ),Y - indirect indexed Y
; 0b____110 A - implied accumulator
; 0b____111 ,1 Byte relative - calculated absolute (BBS, BBR)
dis_opcode: .db "BRK",op_s
.db "ORA",op_zxi
.db "NOP",op_z
.db "NOP",op_s
.db "TSB",op_z
.db "ORA",op_z
.db "ASL",op_z
.db "RMB",op_bz
.db "PHP",op_s
.db "ORA",op_m
.db "ASL",op_sa
.db "NOP",op_s
.db "TSB",op_a
.db "ORA",op_a
.db "ASL",op_a
.db "BBR",op_bzr
.db "BPL",op_r
.db "ORA",op_ziy
.db "ORA",op_zi
.db "NOP",op_s
.db "TRB",op_z
.db "ORA",op_zx
.db "ASL",op_zx
.db "RMB",op_bz
.db "CLC",op_s
.db "ORA",op_y
.db "INC",op_sa
.db "NOP",op_s
.db "TRB",op_a
.db "ORA",op_x
.db "ASL",op_x
.db "BBR",op_bzr
.db "JSR",op_a
.db "AND",op_zxi
.db "NOP",op_z
.db "NOP",op_s
.db "BIT",op_z
.db "AND",op_z
.db "ROL",op_z
.db "RMB",op_bz
.db "PLP",op_s
.db "AND",op_m
.db "ROL",op_sa
.db "NOP",op_s
.db "BIT",op_a
.db "AND",op_a
.db "ROL",op_a
.db "BBR",op_bzr
.db "BMI",op_r
.db "AND",op_ziy
.db "AND",op_zi
.db "NOP",op_s
.db "BIT",op_zx
.db "AND",op_zx
.db "ROL",op_zx
.db "RMB",op_bz
.db "SEC",op_s
.db "AND",op_y
.db "DEC",op_sa
.db "NOP",op_s
.db "BIT",op_x
.db "AND",op_x
.db "ROL",op_x
.db "BBR",op_bzr
.db "RTI",op_s
.db "EOR",op_zxi
.db "NOP",op_z
.db "NOP",op_s
.db "NOP",op_z
.db "EOR",op_z
.db "LSR",op_z
.db "RMB",op_bz
.db "PHA",op_s
.db "EOR",op_m
.db "LSR",op_sa
.db "NOP",op_s
.db "JMP",op_a
.db "EOR",op_a
.db "LSR",op_a
.db "BBR",op_bzr
.db "BVC",op_r
.db "EOR",op_ziy
.db "EOR",op_zi
.db "NOP",op_s
.db "NOP",op_z
.db "EOR",op_zx
.db "LSR",op_zx
.db "RMB",op_bz
.db "CLI",op_s
.db "EOR",op_y
.db "PHY",op_s
.db "NOP",op_s
.db "NOP",op_a
.db "EOR",op_x
.db "LSR",op_x
.db "BBR",op_bzr
.db "RTS",op_s
.db "ADC",op_zxi
.db "NOP",op_z
.db "NOP",op_s
.db "STZ",op_z
.db "ADC",op_z
.db "ROR",op_z
.db "RMB",op_bz
.db "PLA",op_s
.db "ADC",op_m
.db "ROR",op_sa
.db "NOP",op_s
.db "JMP",op_i
.db "ADC",op_a
.db "ROR",op_a
.db "BBR",op_bzr
.db "BVS",op_r
.db "ADC",op_ziy
.db "ADC",op_zi
.db "NOP",op_s
.db "STZ",op_zx
.db "ADC",op_zx
.db "ROR",op_zx
.db "RMB",op_bz
.db "SEI",op_s
.db "ADC",op_y
.db "PLY",op_s
.db "NOP",op_s
.db "JMP",op_xi
.db "ADC",op_x
.db "ROR",op_x
.db "BBR",op_bzr
.db "BRA",op_r
.db "STA",op_zxi
.db "NOP",op_z
.db "NOP",op_s
.db "STY",op_z
.db "STA",op_z
.db "STX",op_z
.db "SMB",op_bz
.db "DEY",op_s
.db "BIT",op_m
.db "TXA",op_s
.db "NOP",op_s
.db "STY",op_a
.db "STA",op_a
.db "STX",op_a
.db "BBS",op_bzr
.db "BCC",op_r
.db "STA",op_ziy
.db "STA",op_zi
.db "NOP",op_s
.db "STY",op_zx
.db "STA",op_zx
.db "STX",op_zy
.db "SMB",op_bz
.db "TYA",op_s
.db "STA",op_y
.db "TXS",op_s
.db "NOP",op_s
.db "STZ",op_a
.db "STA",op_x
.db "STZ",op_x
.db "BBS",op_bzr
.db "LDY",op_m
.db "LDA",op_zxi
.db "LDX",op_m
.db "NOP",op_s
.db "LDY",op_z
.db "LDA",op_z
.db "LDX",op_z
.db "SMB",op_bz
.db "TAY",op_s
.db "LDA",op_m
.db "TAX",op_s
.db "NOP",op_s
.db "LDY",op_a
.db "LDA",op_a
.db "LDX",op_a
.db "BBS",op_bzr
.db "BCS",op_r
.db "LDA",op_ziy
.db "LDA",op_zi
.db "NOP",op_s
.db "LDY",op_zx
.db "LDA",op_zx
.db "LDX",op_zy
.db "SMB",op_bz
.db "CLV",op_s
.db "LDA",op_y
.db "TSX",op_s
.db "NOP",op_s
.db "LDY",op_x
.db "LDA",op_x
.db "LDX",op_y
.db "BBS",op_bzr
.db "CPY",op_m
.db "CMP",op_zxi
.db "NOP",op_z
.db "NOP",op_s
.db "CPY",op_z
.db "CMP",op_z
.db "DEC",op_z
.db "SMB",op_bz
.db "INY",op_s
.db "CMP",op_m
.db "DEX",op_s
.db "WAI",op_s
.db "CPY",op_a
.db "CMP",op_a
.db "DEC",op_a
.db "BBS",op_bzr
.db "BNE",op_r
.db "CMP",op_ziy
.db "CMP",op_zi
.db "NOP",op_s
.db "NOP",op_z
.db "CMP",op_zx
.db "DEC",op_zx
.db "SMB",op_bz
.db "CLD",op_s
.db "CMP",op_y
.db "PHX",op_s
.db "STP",op_s
.db "NOP",op_a
.db "CMP",op_x
.db "DEC",op_x
.db "BBS",op_bzr
.db "CPX",op_m
.db "SBC",op_zxi
.db "NOP",op_z
.db "NOP",op_s
.db "CPX",op_z
.db "SBC",op_z
.db "INC",op_z
.db "SMB",op_bz
.db "INX",op_s
.db "SBC",op_m
.db "NOP",op_s
.db "NOP",op_s
.db "CPX",op_a
.db "SBC",op_a
.db "INC",op_a
.db "BBS",op_bzr
.db "BEQ",op_r
.db "SBC",op_ziy
.db "SBC",op_zi
.db "NOP",op_s
.db "NOP",op_z
.db "SBC",op_zx
.db "INC",op_zx
.db "SMB",op_bz
.db "SED",op_s
.db "SBC",op_y
.db "PLX",op_s
.db "NOP",op_s
.db "NOP",op_a
.db "SBC",op_x
.db "INC",op_x
.db "BBS",op_bzr
;*****************************************************************
;
; 6 5 0 2 e m u l a t i o n m a c r o s
;
;*****************************************************************
;
; op_decode
;
; opcode fetch and decode, prefetch low operand
.macro op_decode
out abushi,pch ;opcode fetch
out abuslo,pcl
sei ;allow emulation INT, NMI
adiw pch:pcl,1 ;pc -> op low
cli
wait_data_valid 4 ;240 minimum @ 16MHz
in opcode,dbusin
out abushi,pch ;operand address low prefetch
out abuslo,pcl
wait_data_valid 6 ;360ns minimum @ 16MHz
adiw pch:pcl,1 ;pc -> op high
ijmp ;execute opcode
.endmacro
;op decode after single, opcode already fetched
.macro op_decode_single
sei ;allow emulation INT, NMI
out abushi,pch ;operand address low prefetch
out abuslo,pcl
cli
wait_data_valid 6 ;360ns minimum @ 16MHz
adiw pch:pcl,1 ;pc -> op high
ijmp ;execute opcode
.endmacro
; address generate relative
.macro adgen_r
rjmp no_branch ;condition false
.ifndef BRA_r
.equ BRA_r = pc
.endif
in operand,dbusin
clr a ;expand sign bit
sbrc operand,7 ;negative?
dec a
add pcl,operand ;set new PC
adc pch,a
no_branch: op_decode
.endmacro
; address generate absolute
.macro adgen_a
in oplow,dbusin
out abushi,pch ;operand high address fetch
out abuslo,pcl
adiw pch:pcl,1 ;pc -> next instruction
cbr flags,(1<<op_ind) ;operand address is direct
wait_data_valid 3 ;180ns minimum @ 16MHz
in ophigh,dbusin
.endmacro
; address generate abs,X
.macro adgen_x ;@0 = op_label xxx_
.equ @0x = pc
in oplow,dbusin
out abushi,pch ;operand high address fetch
out abuslo,pcl
adiw pch:pcl,1 ;pc -> next instruction
cbr flags,(1<<op_ind) ;operand address is direct
add oplow,regx
wait_data_valid 4 ;240ns minimum @ 16MHz
in ophigh,dbusin
adc ophigh,zero
rjmp @0o ;fetch operand
.endmacro
; address generate abs,Y
.macro adgen_y ;@0 = op_label xxx_
.equ @0y = pc
in oplow,dbusin
out abushi,pch ;operand high address fetch
out abuslo,pcl
adiw pch:pcl,1 ;pc -> next instruction
cbr flags,(1<<op_ind) ;operand address is direct
add oplow,regy
wait_data_valid 4 ;240ns minimum @ 16MHz
in ophigh,dbusin
adc ophigh,zero
rjmp @0o ;fetch operand
.endmacro
;address generate (ZP) indirect
.macro adgen_zi ;@0 = op_label xxx_
.equ @0zi = pc
in oplow,dbusin
out abushi,zero ;indirect low address fetch
out abuslo,oplow
inc oplow
sbr flags,(1<<op_ind) ;operand address is indirect
wait_data_valid 2 ;120ns minimum @ 16MHz
in a,dbusin
out abuslo,oplow ;indirect high address fetch
mov oplow,a
wait_data_valid 1 ;60ns minimum @ 16MHz
in ophigh,dbusin
rjmp @0o
.endmacro
;address generate (ZP,X) indexed indirect
.macro adgen_zxi ;@0 = op_label xxx_
.equ @0zxi = pc
in oplow,dbusin
add oplow,regx
out abushi,zero ;indirect low address fetch
out abuslo,oplow
inc oplow
sbr flags,(1<<op_ind) ;operand address is indirect
wait_data_valid 2 ;120ns minimum @ 16MHz
in a,dbusin
out abuslo,oplow ;indirect high address fetch
mov oplow,a
wait_data_valid 1 ;60ns minimum @ 16MHz
in ophigh,dbusin
rjmp @0o
.endmacro
;address generate (ZP),Y indirect indexed
.macro adgen_ziy ;@0 = op_label xxx_
.equ @0ziy = pc
in oplow,dbusin
out abushi,zero ;indirect low address fetch
out abuslo,oplow
inc oplow
sbr flags,(1<<op_ind) ;operand address is indirect
wait_data_valid 2 ;120ns minimum @ 16MHz
in a,dbusin
out abuslo,oplow ;indirect high address fetch
mov oplow,a
add oplow,regy
wait_data_valid 2 ;120ns minimum @ 16MHz
in ophigh,dbusin
adc ophigh,zero
rjmp @0o
.endmacro
;address generate ZP,X and operand fetch
.macro adgen_zx ;@0 = op_label xxx_
.equ @0zx = pc
in oplow,dbusin
add oplow,regx
out abushi,zero ;operand fetch
out abuslo,oplow
wait_data_valid 3 ;180ns minimum @ 16MHz
clr ophigh
rjmp @0m
.endmacro
;address generate ZP,Y and operand fetch
.macro adgen_zy ;@0 = op_label xxx_
.equ @0zy = pc
in oplow,dbusin
add oplow,regy
out abushi,zero ;operand fetch
out abuslo,oplow
wait_data_valid 3 ;180ns minimum @ 16MHz
clr ophigh
rjmp @0m
.endmacro
;address generate ZP absolute and operand fetch
.macro adgen_z ;@0 = op_label xxx_
.equ @0z = pc
in oplow,dbusin
out abushi,zero ;operand fetch
out abuslo,oplow
wait_data_valid 3 ;180ns minimum @ 16MHz
clr ophigh
rjmp @0m
.endmacro
; operand fetch from memory
.macro op_fetch
out abushi,ophigh ;operand fetch
out abuslo,oplow
.ifdef iomap
wait_data_valid 3 ;180ns minimum @ 16MHz
cpi ophigh,iomap ;internal io?
brne skip_IO
rcall ioread ;ioread returns data in operand
rjmp pc+2 ;skip reading from dbus
.else
wait_data_valid 0 ;0ns minimum @ 16MHz
.endif
skip_IO:
.endmacro
; operand fetch from memory for modify op (extended memory address lock)
.macro op_fetch_modify
out abushi,ophigh ;operand fetch
out abuslo,oplow
.ifdef iomap
wait_data_valid 3 ;180ns minimum @ 16MHz
cpi ophigh,iomap ;internal io?
brne skip_IO
rcall iomodify ;ioread returns data in operand
rjmp pc+2 ;skip reading from dbus
.else
wait_data_valid 0 ;0ns minimum @ 16MHz
.endif
skip_IO:
.endmacro
; register fetch from memory
.macro reg_fetch ;@0 = register
out abushi,ophigh ;register fetch
out abuslo,oplow
.ifdef iomap
wait_data_valid 3 ;180ns minimum @ 16MHz
cpi ophigh,iomap ;internal io?
brne skip_IO
rcall ioread ;ioread returns data in operand
mov @0,operand
rjmp pc+2 ;skip reading from dbus
.else
wait_data_valid 0 ;0ns minimum @ 16MHz
.endif
skip_IO:
.endmacro
;flag generating macro
.macro flags_gen_nz ;@0 = register
out sreg,stat ;keep C
tst @0 ;generate NZ
in stat,sreg ;save NZ, keep C
.endmacro
;IRQ enable/disable
.macro IRQ_restore ;sets IRQ according to I-flag
.ifdef irq_dis_real ;+7 if enabled, +5 if disabled
sbrs stat2,2 ;IRQ disabled?
rjmp IRQ_rest_ena
ldi a,IRQ_dis
out ibus,a
out timsk,one ;only TOV0 (single step) stays enabled
ldi a,0b11000 ;no USART interrupts, only RX & TX enable
rjmp IRQ_rest_exit
IRQ_rest_ena:
ldi a,IRQ_ena ;enable IRQ
out ibus,a
lds a,timer_ena ;enable timers interrupts
out timsk,a
lds a,usart_ena ;enable usart interrupts
IRQ_rest_exit:
out ucsrb,a
.else
ldi a,IRQ_ena
sbrc stat2,2 ;disable if I-flag set
ldi a,IRQ_dis
out ibus,a
.endif
.endmacro
; store modified operand to memory
.macro store_modify ;write to previous read address
.ifdef iomap ;test internal I/O
cpi ophigh,iomap
breq do_io
.endif
.ifdef rommap ;test write-protect
cpi ophigh,rommap
brsh skip_store
.endif
out cbus,writemem ;WE, ~OE
out dbusout,operand ;precharge write
out dbusddr,allon ;output data valid
out cbus,clear ;~WE / write cycle ends 180ns/16MHz
out dbusddr,zero ;data hold ends after 60ns
out cbus,readmem ;OE / read mode back on
skip_store:
op_decode ;next instruction
.ifdef iomap
do_io: rjmp iowrite
.endif
.endmacro
;address generate store ZP,X
.macro adgen_s_zx ;@0 = op_label xxx_
.equ @0zx = pc
in oplow,dbusin
add oplow,regx
out abushi,zero ;operand fetch
out abuslo,oplow
rjmp @0m
.endmacro
;address generate store ZP,Y
.macro adgen_s_zy ;@0 = op_label xxx_
.equ @0zy = pc
in oplow,dbusin
add oplow,regy
out abushi,zero ;operand fetch
out abuslo,oplow
rjmp @0m
.endmacro
;address generate store ZP absolute
.macro adgen_s_z ;@0 = op_label xxx_
.equ @0z = pc
in oplow,dbusin
out abushi,zero
out abuslo,oplow
rjmp @0m
.endmacro
; store register
.macro store_reg ;@0 = register, @1 = zp_entry STx_m
out abushi,ophigh
out abuslo,oplow
.ifdef iomap ;test internal I/O
cpi ophigh,iomap
breq do_io
.endif
.ifdef rommap ;test write-protect
cpi ophigh,rommap
brsh skip_store
.endif
.equ @1 = pc
out cbus,writemem ;WE, ~OE
out dbusout,@0 ;precharge write
out dbusddr,allon ;output data valid
out cbus,clear ;~WE / write cycle ends 180ns/16MHz
out dbusddr,zero ;data hold ends after 60ns
out cbus,readmem ;OE / read mode back on
skip_store:
op_decode ;next instruction
.ifdef iomap
do_io: mov operand,@0
rjmp iowrite
.endif
.endmacro
;fetch zp operand for BBR and set bitmask
.macro fetch_z_BBR ;@0 = bit number
in oplow,dbusin
out abushi,zero ;ZP operand fetch
out abuslo,oplow
wait_data_valid 3 ;180ns minimum @ 16MHz
ldi a,1<<@0 ;set bitmask
rjmp BBR_o
.endmacro
;fetch zp operand for BBS and set bitmask
.macro fetch_z_BBS ;@0 = bit number
in oplow,dbusin
out abushi,zero ;ZP operand fetch
out abuslo,oplow
wait_data_valid 3 ;180ns minimum @ 16MHz
ldi a,1<<@0 ;set bitmask
rjmp BBS_o
.endmacro
;fetch zp operand for RMB and set bitmask
.macro fetch_z_RMB ;@0 = bit number
in oplow,dbusin
out abushi,zero ;ZP operand fetch
out abuslo,oplow
wait_data_valid 3 ;180ns minimum @ 16MHz
ldi a,~(1<<@0) ;set bitmask
rjmp RMB_o
.endmacro
;fetch zp operand for SMB and set bitmask
.macro fetch_z_SMB ;@0 = bit number
in oplow,dbusin
out abushi,zero ;ZP operand fetch
out abuslo,oplow
wait_data_valid 3 ;180ns minimum @ 16MHz
ldi a,1<<@0 ;set bitmask
rjmp SMB_o
.endmacro
;*****************************************************************
;
; 6 5 0 2 e m u l a t i o n
;
;*****************************************************************
;
; ***** IRQ pin low interrupt *****
;
IRQ:
rupt_dma_mmu 0 ;handle DMA save & MMU restore
out abushi,allon ;new PC high fetch from irq vector
out abuslo,allon
ldi zl,0xfe ;preload vector low
ldi a,IRQ_dis
out ibus,a
.ifdef irq_dis_real ;+3
out timsk,one ;only TOV0 (single step) stays enabled
ldi a,0b11000 ;no USART interrupts, only RX & TX enable
out ucsrb,a
.endif
;status merge while we are waiting for data
mov a,stat ;merge status in 6502 format
andi a,0b11 ;------ZC
wait_data_valid 5 ;300ns minimum @ 16MHz
in ophigh,dbusin
out abuslo,zl ;new PC low fetch from irq vector
;status merge while we are waiting for data
bst stat,2 ;<----<
bld a,7 ;N-------
or a,stat2 ;-V1BDI--
sbr stat2,0b100 ;I=1 (IRQ disabled)
cbr stat2,0b1000 ;D=0 (clear decimal mode)
ldi oc_tabh,high(oc_tab)
wait_data_valid 6 ;360ns minimum @ 16MHz
in oplow,dbusin
out abushi,one ;push pch
out abuslo,spointer
dec spointer
out cbus,writemem ;WE, ~OE
out dbusout,pch ;precharge write
out dbusddr,allon ;output data valid
out cbus,clear ;~WE / write cycle ends 180ns/16MHz
out abuslo,spointer ;push pcl
dec spointer
out cbus,writemem ;WE
out dbusout,pcl ;write
out cbus,clear ;~WE / write cycle ends 120ns/16MHz
out abuslo,spointer ;push status
dec spointer
out cbus,writemem ;WE
out dbusout,a ;write
out cbus,clear ;~WE / write cycle ends 120ns/16MHz
out dbusddr,zero ;data hold ends after 60ns
out cbus,readmem ;OE / read mode back on
movw pcl,oplow ;load new PC
ldi a,low(ramend) ;discard AVR return address
out spl,a
op_decode ;next instruction
;
; ***** NMI pin high to low edge interrupt *****
;
NMI:
rupt_dma_mmu 0 ;handle DMA save & MMU restore
ldi zl,0xfb ;vector high first
out abushi,allon ;new PC high fetch from irq vector
out abuslo,zl
ldi zl,0xfa ;preload vector low
ldi a,IRQ_dis
out ibus,a
.ifdef irq_dis_real ;+3
out timsk,one ;only TOV0 (single step) stays enabled
ldi a,0b11000 ;no USART interrupts, only RX & TX enable
out ucsrb,a
.endif
;status merge while we are waiting for data
mov a,stat ;merge status in 6502 format
andi a,0b11 ;------ZC
wait_data_valid 5 ;300ns minimum @ 16MHz
in ophigh,dbusin
out abuslo,zl ;new PC low fetch from irq vector
;status merge while we are waiting for data
bst stat,2 ;<----<
bld a,7 ;N-------
or a,stat2 ;-V1BDI--
sbr stat2,0b100 ;I=1 (IRQ disabled)
cbr stat2,0b1000 ;D=0 (clear decimal mode)
ldi oc_tabh,high(oc_tab)
wait_data_valid 6 ;360ns minimum @ 16MHz
in oplow,dbusin
out abushi,one ;push pch
out abuslo,spointer
dec spointer
out cbus,writemem ;WE, ~OE
out dbusout,pch ;precharge write
out dbusddr,allon ;output data valid
out cbus,clear ;~WE / write cycle ends 180ns/16MHz
out abuslo,spointer ;push pcl
dec spointer
out cbus,writemem ;WE
out dbusout,pcl ;write
out cbus,clear ;~WE / write cycle ends 120ns/16MHz
out abuslo,spointer ;push status
dec spointer
out cbus,writemem ;WE
out dbusout,a ;write
out cbus,clear ;~WE / write cycle ends 120ns/16MHz
out dbusddr,zero ;data hold ends after 60ns
out cbus,readmem ;OE / read mode back on
movw pcl,oplow ;load new PC
ldi a,low(ramend) ;discard AVR return address
out spl,a
op_decode ;next instruction
;
; opcode template
;
; operand adressing modes:
; a absolute - LDA abs
; x absolute indexed X - LDA abs,x
; y absolute indexed Y - LDA abs,y
; i absolute indirect - JMP (abs)
; s single (implied) - TAX
; m immediate - LDA #
; r relative to PC - BEQ rel
; z zero page - LDA zp
; zxi zero page indexed X indirect - LDA (zp,x)
; zx zero page indexed X - LDA zp,x
; zy zero page indexed Y - LDA zp,y
; ziy zero page indirect indexed Y - LDA (zp),y
; additional CMOS addressing modes
; zi zero page indirect - LDA (zp)
; xi absolute indexed X indirect - JMP (abs,x)
; zr zero page, relative - BBRbit zp,rel
;
; adressing mode is added as suffix to the original opcode
; examples: LDA_ziy, BEQ_r, TAX_s, JMP_a
;*****************************************************************
;
; Implied adressing instructions
; Register, Stack
;
;*****************************************************************
; opcode: ASL A
ASL_s: in opcode,dbusin ;next opcode
lsl rega ;AVR emulated OP
in stat,sreg ;save NZC
op_decode_single ;next instruction
; opcode: CLC
CLC_s: in opcode,dbusin ;next opcode
cbr stat,1 ;AVR emulated OP
op_decode_single ;next instruction
; opcode: CLD
CLD_s: in opcode,dbusin ;next opcode
cbr stat2,0b1000 ;AVR emulated OP
ldi oc_tabh,high(oc_tab)
op_decode_single ;next instruction
; opcode: CLI
CLI_s: in opcode,dbusin ;next opcode
cbr stat2,0b100
ldi a,IRQ_ena
out ibus,a
.ifdef irq_dis_real ;+6
lds a,timer_ena ;enable timers interrupts
out timsk,a
lds a,usart_ena ;enable usart interrupts
out ucsrb,a
.endif
op_decode_single ;next instruction
; opcode: CLV
CLV_s: in opcode,dbusin ;next opcode
cbr stat2,0b1000000 ;AVR emulated OP
op_decode_single ;next instruction
; opcode: DEC A
DEC_s: in opcode,dbusin ;next opcode
out sreg,stat ;keep C
dec rega ;AVR emulated OP
in stat,sreg ;save NZ, keep C
op_decode_single ;next instruction
; opcode: DEX
DEX_s: in opcode,dbusin ;next opcode
out sreg,stat ;keep C
dec regx ;AVR emulated OP
in stat,sreg ;save NZ, keep C
op_decode_single ;next instruction
; opcode: DEX
DEY_s: in opcode,dbusin ;next opcode
out sreg,stat ;keep C
dec regy ;AVR emulated OP
in stat,sreg ;save NZ, keep C
op_decode_single ;next instruction
; opcode: INC A
INC_s: in opcode,dbusin ;next opcode
out sreg,stat ;keep C
inc rega ;AVR emulated OP
in stat,sreg ;save NZ, keep C
op_decode_single ;next instruction
; opcode: INX
INX_s: in opcode,dbusin ;next opcode
out sreg,stat ;keep C
inc regx ;AVR emulated OP
in stat,sreg ;save NZ, keep C
op_decode_single ;next instruction
; opcode: INY
INY_s: in opcode,dbusin ;next opcode
out sreg,stat ;keep C
inc regy ;AVR emulated OP
in stat,sreg ;save NZ, keep C
op_decode_single ;next instruction
; opcode: LSR A
LSR_s: in opcode,dbusin ;next opcode
lsr rega ;AVR emulated OP
in stat,sreg ;save NZC
op_decode_single ;next instruction
; opcode: NOP
; additional NOPs in the CMOS core replace invalid opcodes
NOP38_s: wait_ns 2000,30 ;3 byte, 8 6502 cycles
ldi a,10 ;burn 30 cycles
NOP_delay: dec a
brne NOP_delay
NOP34_s: wait_ns 500,4 ;3 byte, 4 6502 cycles
adiw pch:pcl,1
rjmp NOP23_s
NOP24_s: wait_ns 500,0 ;2 byte, 4 6502 cycles
NOP23_s: wait_ns 500,0 ;2 byte, 3 6502 cycles
NOP22_s: wait_ns 1000,15 ;2 byte, 2 6502 cycles