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6502_Emu_IO.inc
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;
; 6502 EMULATOR include
; I/O page (iomap) address decode & emulated I/O
;
; Copyright (C) 2013-2018 Klaus Dormann
;
; This program is free software: you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation, either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
;
.set io_version = 840
;*****************************************************************
;
; IO macros
;
;*****************************************************************
;I/O address least significant nibble address decode
;
;@0 = table of 16 addresses for decoded nibble (0x0 - 0xf)
.macro io_adr_dec
.if (@0 & 0xff) > 0xf0
.error "Address decode table @0 crosses a page boundary!"
.endif
ldi zh,high(@0) ;register address decode
mov zl,oplow ;lower byte
andi zl,0xf ;lower 4 bits
addi zl,low(@0) ;add offset
ijmp ;address specific code
.endmacro
;macro set IO select pin
;
;@0 = io_strobe pin direct (1-3) or extended (10-17, 20-27, 30-37)
.macro set_io_select
out cbus,clear ;turn off -OE to RAM
.set io_select = @0
.if io_select > 3 ;generate strobe
.set io_select = io_select -10
.if io_select < 8
ldi b,ios1_default ;precharge IO-select register
.set io_strobe_pol = !((ios1_default >> io_select) & 1)
.set io_sel_direct = 6 ;bit to enable extension register
.else
.set io_select = io_select -10
.if io_select < 8
ldi b,ios2_default ;precharge IO-select register
.set io_strobe_pol = !((ios2_default >> io_select) & 1)
.set io_sel_direct = 7 ;bit to enable extension register
.else
.set io_select = io_select -10
ldi b,ios3_default ;precharge IO-select register
.set io_strobe_pol = !((ios3_default >> io_select) & 1)
.set io_sel_direct = 2 ;bit to enable extension register
.endif
.endif
out abushi,b
sbi cbus,io_sel_direct ;make register transparent
.else
.set io_sel_direct = 0
.if (io_select == 3) ;translate to pin
.set io_select = 2
.else
.set io_select = io_select + 5
.endif
.endif
.endmacro
;macro set IO selectpin and keep reset pin low
;
;@0 io_strobe pin direct (1-3) or extended (10-17, 20-27, 30-37)
.macro set_io_reset
out cbus,clear ;turn off -OE to RAM
.set io_select = @0
.if io_select > 3 ;generate strobe
.set io_select = io_select -10
.if io_select < 8
ldi b,ios1_default ;precharge IO-select register
.set io_strobe_pol = !((ios1_default >> io_select) & 1)
.set io_sel_direct = 6 ;bit to enable extension register
.else
.set io_select = io_select -10
.if io_select < 8
ldi b,ios2_default ;precharge IO-select register
.set io_strobe_pol = !((ios2_default >> io_select) & 1)
.set io_sel_direct = 7 ;bit to enable extension register
.else
.set io_select = io_select -10
ldi b,ios3_default ;precharge IO-select register
.set io_strobe_pol = !((ios3_default >> io_select) & 1)
.set io_sel_direct = 2 ;bit to enable extension register
.endif
.endif
.ifdef io_reset_pin
.if (@0 & 0x30) == (io_reset_pin & 0x30)
cbr b,(1 << (io_reset_pin & 7))
.endif
.endif
out abushi,b
sbi cbus,io_sel_direct ;make register transparent
.else
.set io_sel_direct = 0
.if (io_select == 3) ;translate to pin
.set io_select = 2
.else
.set io_select = io_select + 5
.endif
.endif
.endmacro
;macro prepare IO select pin
;use with make_io_select, precharges yl & yh with strobe
;
;@0 = io_strobe pin direct (1-3) or extended (10-17, 20-27, 30-37)
.macro prep_io_select
.set io_select = @0
.if io_select > 3 ;generate strobe
.set io_select = io_select -10
.if io_select < 8
ldi b,ios1_default ;precharge IO-select register
ldi yl,ios1_default^(1<<io_select)
.set io_strobe_pol = !((ios1_default >> io_select) & 1)
.set io_sel_direct = 6 ;bit to enable extension register
.else
.set io_select = io_select -10
.if io_select < 8
ldi b,ios2_default ;precharge IO-select register
ldi yl,ios2_default^(1<<io_select)
.set io_strobe_pol = !((ios2_default >> io_select) & 1)
.set io_sel_direct = 7 ;bit to enable extension register
.else
.set io_select = io_select -10
ldi b,ios3_default ;precharge IO-select register
ldi yl,ios3_default^(1<<io_select)
.set io_strobe_pol = !((ios3_default >> io_select) & 1)
.set io_sel_direct = 2 ;bit to enable extension register
.endif
.endif
ldi yh,0x30|(1<<io_sel_direct)
.else
.set io_sel_direct = 0
.if (io_select == 3) ;translate to pin
.set io_select = 2
.else
.set io_select = io_select + 5
.endif
ldi yh,0x30|(1<<io_select)
.endif
.endmacro
;macro make IO select pin
;
.macro make_io_select
.if (io_sel_direct > 0)
out abushi,yl
.endif
out cbus,yh
.endmacro
;macro enable IO select pin
;
.macro ena_io_select
.if (io_sel_direct > 0)
.if io_strobe_pol
sbi abushi,io_select ;strobe high
.else
cbi abushi,io_select ;strobe low
.endif
.else
sbi cbus,io_select ;strobe high
.endif
.endmacro
;macro disable IO select pin
;
.macro dis_io_select
.if (io_sel_direct > 0)
out abushi,b ;end strobe
.else
out cbus,clear ;end strobe
.endif
.endmacro
;macro disable SPI select pin
;
.macro dis_spi_select
.if (io_sel_direct > 0)
out abushi,b ;end strobe if io extension
.endif
;must be followed by
; out cbus,{readmem|clear}
.endmacro
;macro SPI wait for spdr complete
;
.macro wait_spi
wait_spdr:
sbis spsr,spif
rjmp wait_spdr
.endmacro
;macro out @0 to SPI and wait for spdr complete
;
.macro out_spi
out spdr,@0
wait_spdr:
sbis spsr,spif
rjmp wait_spdr
.endmacro
;macro in @0 from SPI and wait for data ready
;
.macro in_spi
out spdr,allon
wait_spdr:
sbis spsr,spif
rjmp wait_spdr
in @0,spdr
.endmacro
;macro parallel read
;
;@0 minimum read strobe in ns, max 800ns
; maximum time to data valid is @0 -1/2 clock, -32ns
.macro par_rd
sbi abuslo,7 ;generate R/-W if needed
ena_io_select
wait_ns @0,1
dis_io_select
in operand,dbusin ;data latched during previous cycle
out cbus,readmem ;IO-select off & read mode back on
ldi oc_tabh,high(oc_tab) ;restore zh as opcode table
sbrc stat2,3 ;test decimal flag
ldi oc_tabh,high(oc_tabd)
ret
.endmacro
;macro parallel write
;
;@0 minimum write strobe duration in ns, max 800ns
.macro par_wrt
cbi abuslo,7 ;generate R/-W if needed
out dbusout,operand ;precharge data to be written
out dbusddr,allon ;data write mode
ena_io_select
wait_ns @0,1
dis_io_select
out dbusddr,zero ;data hold ends
.endmacro
;parallel pre read macro - data to a, no return
;
;@0 minimum read strobe in ns, max 800ns
; maximum time to data valid is @0 -1/2 clock, -32ns
.macro par_pre_rd
sbi abuslo,7 ;generate R/-W
ena_io_select
wait_ns @0,1
dis_io_select
in a,dbusin ;data latched during previous cycle
.endmacro
;phase 2 synchronisation macro
; next instruction after macro is at tcnt=7, OC2=1
;
; you are here | at end of macro
; _ _ _ _ _ _ _V_ _ _
; Phi2 _ _| |_ _ _ _ _ _ _ _|
;
; tcnt 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1
;
; 500ns/phase, 62.5ns/count
.macro phi2_sync
phi2_syncloop:
in zl,tcnt2
sbic pind,7 ;wait for phi2 low
rjmp phi2_syncloop
clr zh
subi zl,low(-phi2_synctable) ;calculate offset cycles
sbci zh,high(-phi2_synctable)
ijmp
; .if (PC & 0xff) > 0xf8 ;keep table on same page - avoid adc zh,zero
; .org (PC + 0x100) & 0xff00
; .endif
phi2_synctable: ;delay -1 cycle for each count in tcnt
nop ;0/1 - tcnt=0/OC2=1
nop ;1/1
nop ;2/1
nop ;3/1
nop ;4/1
nop ;5/1
nop ;6/1
; next 7/1 - output to next cycle, input from previous cycle
.endmacro
.macro nop2 ;2 cycle nop
rjmp pc+1
.endmacro
;macro phase 2 synchronized read
;
;
; data latched 1/2 clock ahead of IN +
; address valid + |
; after sync + | |
; | | _ _ _ _ _ _ _ _ _ _ _ _ | _ _
; chip select _ _|_ _|_ _| | |_ _
; _ _ _ _V_ | _ _ _ _ _ _ _ V
; Phi2 |_V_ _ _ _ _ _ _| |_ _ _ _
;
; tcnt 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
;
.macro phi2_rd
phi2_sync
sbi abuslo,7 ;7/1 generate R/-W - tcnt=7/OC2=1
ena_io_select ;1/0 CS strobe >300ns before phi2
nop2 ;3/0
nop2 ;5/0
nop2 ;7/0
nop2 ;1/1
nop2 ;3/1
ldi oc_tabh,high(oc_tab) ;5/1 restore zh as opcode table
sbrc stat2,3 ;6/1 test decimal flag
ldi oc_tabh,high(oc_tabd) ;7/1
in operand,dbusin ;0/0 input latched at 7/1 +30ns
dis_io_select ;1/0 end strobe 125ns after phi2 te
out cbus,readmem ;IO-select off & read mode back on
ret
.endmacro
;macro phase 2 synchronized write
;
; output data valid +
; address valid + |
; after sync + | |
; | | _ _ _ _ _ _ _|_ _ _ _ _ _ _
; chip select _ _|_ _|_ _| | |_ _ _
; _ _ _ _V_ | _ _V_ _ _ _ _ _
; Phi2 |_V_ _ _ _ _ _ _| |_ _ _ _
;
; tcnt 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
;
.macro phi2_wrt
phi2_sync
cbi abuslo,7 ;7/1 generate R/-W - tcnt=7/OC2=1
ena_io_select ;1/0 CS strobe high >300ns before phi2
nop2 ;3/0
nop2 ;5/0
nop ;7/0
out dbusout,operand ;0/1 precharge data to be written
out dbusddr,allon ;1/1 write data valid 125 ns after phi2 le
nop2 ;2/1
nop ;4/1
ldi oc_tabh,high(oc_tab) ;5/1 restore zh as opcode table
sbrc stat2,3 ;6/1 test decimal flag
ldi oc_tabh,high(oc_tabd) ;7/1
dis_io_select ;0/0 end strobe 60ns after phi2 te
out dbusddr,zero ;data hold ends
rjmp iw_exit2 ;next instruction
.endmacro
;*** IO subrocessor ***
;
;macro nibble read from IO subprocessor
.macro nib_rd
ena_io_select ;begin CS strobe
sbi abuslo,3 ;generate R/-W
nib_rd_nak:
;xx.x clocks after ACK raised
; delayed to xx.x + 3 max
sbis dbusin,7 ; 2.5 wait for ACK
rjmp nib_rd_nak ; --- loop on -ACK
out aloddr,zero ; 3.5! set input (3.5 - 6.5 after ACK)
dis_io_select ; 4.5 end CS strobe
ldi oc_tabh,high(oc_tab) ; 5.5 restore zh as opcode table
sbrc stat2,3 ; 7.5 test decimal flag
ldi oc_tabh,high(oc_tabd) ; 7.5
nop ; 8.5
nop ; 9.5
in a,aloin ;10.5! read high nibble (9 - 12 after ACK)
swap a ;11.5
andi a,0xf0 ;12.5
mov operand,a ;13.5
nop ;14.5
in a,aloin ;15.5! read low nibble (14 - 17 after ACK)
andi a,0xf ;16.5
or operand,a ;17.5
out aloddr,allon ;18.5! set output (18.5 - 21.5 after ACK)
out cbus,readmem ;set read mode back on
ret
.endmacro
;macro nibble write to IO subprocessor
.macro nib_wrt
ena_io_select ;begin CS strobe
cbi abuslo,3 ;generate R/-W
swap operand
ldi oc_tabh,high(oc_tab) ;restore zh as opcode table
nib_wrt_nak:
;xx.x clocks after ACK raised
; delayed to xx.x + 3 max
sbis dbusin,7 ; 2.5 wait for ACK
rjmp nib_wrt_nak ; --- loop on -ACK
out abuslo,operand ; 3.5! output operand high (3.5 - 6.5 after ACK)
dis_io_select ; 4.5 end CS strobe
swap operand ; 5.5
sbrc stat2,3 ; 7.5 test decimal flag
ldi oc_tabh,high(oc_tabd) ;7.5
out abuslo,operand ; 8.5! output operand low (8.5 - 11.5 after ACK)
rjmp iw_exit2
.endmacro
;macro subprocessor reset
.macro nib_rs
iosub_det_retry:
PrintStr_far iosub_msg
ldi a,iomap ;identify io subprocessor
call PrintHex
ldi a,low(iosub_adr)
call PrintHex
call space
; sbic dbusin,7 ;test ACK low
; rjmp iosub_det_fail
ldi a,3 ;write io register address (r/-w = 0, address = 3)
out abuslo,a
clr c ;timeout counter
ena_io_select ;begin CS strobe
iosub_det_waitack:
dec c
breq iosub_det_fail
sbis dbusin,7 ;wait for ACK
rjmp iosub_det_waitack
iosub_det_waitackend:
dec c
brne iosub_det_wait
iosub_det_fail:
dis_io_select
out cbus,clear ;end exp. reg. select
PrintStr_far iosub_fail
iosub_det_halt:
sbis ucsra,rxc ;retry on escape
rjmp iosub_det_halt
in a,udr
cpi a,27
brne iosub_det_halt
rjmp iosub_det_retry
iosub_det_wait:
sbic dbusin,7 ;wait for -ACK
rjmp iosub_det_waitackend
;actual reset starts here
ldi a,5 ;write ios_aad with wdtcr address
out abuslo,a
ldi a,wdtcr
iosub_rs_wdt:
ena_io_select ;begin CS strobe
nop
swap a
nib_wrt_nak:
sbis dbusin,7 ; 2.5 wait for ACK
rjmp nib_wrt_nak ; --- loop on -ACK
out abuslo,a ; 3.5! output operand high (3.5 - 6.5 after ACK)
dis_io_select ; 4.5 end CS strobe
swap a ; 5.5
nop ; 6.5
nop ; 7.5
out abuslo,a ; 8.5! output operand low (8.5 - 11.5 after ACK)
cpi a,wdtcr
ldi a,7 ;write ios_xr with reset command (63)
nop
nop
out abuslo,a
ldi a,63
breq iosub_rs_wdt
ldi a,'V' ;get version from subprocessor
call PrintChr
nib_rd_ver:
ena_io_select ;begin CS strobe
nib_rd_ack:
ldi a,8+6 ;read data register
out abuslo,a
nib_rd_nak:
;xx.x clocks after ACK raised
; delayed to xx.x + 3 max
sbis dbusin,7 ; 2.5 wait for ACK
rjmp nib_rd_nak ; --- loop on -ACK
out aloddr,zero ; 3.5! set input (3.5 - 6.5 after ACK)
dis_io_select ; 4.5 end CS strobe
ldi oc_tabh,high(oc_tab) ; 5.5 restore zh as opcode table
sbrc stat2,3 ; 7.5 test decimal flag
ldi oc_tabh,high(oc_tabd) ; 7.5
nop ; 8.5
nop ; 9.5
in a,aloin ;10.5! read high nibble (9 - 12 after ACK)
swap a ;11.5
andi a,0xf0 ;12.5
mov d,a ;13.5
nop ;14.5
in a,aloin ;15.5! read low nibble (14 - 17 after ACK)
andi a,0xf ;16.5
or a,d ;17.5
out aloddr,allon ;18.5! set output (18.5 - 21.5 after ACK)
tst a ;end of string?
breq nib_rs_exit
call PrintChr
rjmp nib_rd_ver
nib_rs_exit:
out cbus,clear ;end exp. reg. select
ret
.ifndef iosub_msg
.equ iosub_msg = pc
.db 13,10,"IO subprocessor @ ",0,0
.equ iosub_fail = pc
.db "failed, cannot continue!",0,0
.endif
.endmacro
;****************************************************************
;
; Begin IO address decode after load, store or modify instruction
;
;****************************************************************
;address decode for higher nibble of internally mapped address
iomodify:
sbr flags,(1<<modify) ;lock extended memory address until rewrite
ioread:
ldi zh,high(ior_tab)
mov zl,oplow ;lower byte
andi zl,0xf0 ;upper 4 bits
swap zl ;to low position
addi zl,low(ior_tab) ;add offset
ijmp ;address specific code
;address decode for higher nibble of internally mapped address
iowrite:
ldi zh,high(iow_tab)
mov zl,oplow ;lower address byte
andi zl,0xf0 ;upper 4 bits
swap zl ;to low position
addi zl,low(iow_tab) ;add offset
ijmp ;address specific code
;**************************************************************
;
; IO RESET
;
;**************************************************************
io_reset:
cli
out timsk,zero ;no timer interrupts for reset delays
ldi a,0b00000101 ;timer 0 ctc off, clock / 1024
out tccr0,a
call rs_IO_ext ;reset IO extension registers
;*** custom IO resets go here ***
rcall t1_rs ;reset timer 1
rcall irq_rs ;reset interrupts & flags
rcall mmu_rs ;reset MMU
rcall lcd_rs ;reset character LCD
rcall spi_rs ;reset SPI bus
rcall i2c_rs ;reset I2C bus
; spi reset with IO expansion select reset (as early as possible)
io_modules_reset ;defined by a macro in 6502_Emu_config.inc
;end of reset sequence - restore t0, end HW reset strobe
out tcnt0,zero ;timer 0 init
ldi a,ten_ms
out ocr0,a
ldi a,0b00001101 ;timer 0 ctc, clock / 1024
out tccr0,a
out tcnt0,zero
.ifdef io_reset_pin
ldi a,10 ;wait 100ms
do reset_delay
in c,tifr
sbrs c,ocf0
ifs reset_10ms_expired
ldi b,(1 << ocf0)
out tifr,b ;clear flag
dec a ;next 10ms
exiteq reset_delay
end reset_10ms_expired
loop reset_delay
set_io_select io_reset_pin
out cbus,clear
.endif
out tcnt0,zero ;restart t0
out tifr,allon ;clear all timer flags
ldi a,0b11 ;t0 compare match & overflow interrupt enable
out timsk,a
sts timer_ena,a
out cbus,readmem ;OE / read mode back on
sei
ret
.ifdef mmu_sel
;*****************************************************************
;
;Memory Managment Unit
;
; the MMU maps 4 16k address segments to 16 32k RAM elements
; RAM elements are divided into 2 halves to match the segment size
; segment | 0 | 1 | 2 | 3 |
; address |0000-3FFF|4000-7FFF|8000-BFFF|C000-FFFF|
; element | lower | upper | lower | upper |
; default | 0 | 0 | 1 | 1 |
mmu_rd:
andi oplow,0b11 ;mask lower address bits
addi oplow,low(mmu_emu)
ldi ophigh,high(mmu_emu)
ld operand,opointer ;read saved MMU RAM element
ldi oc_tabh,high(oc_tab) ;restore zh as opcode table
sbrc stat2,3 ;test decimal flag
ldi oc_tabh,high(oc_tabd)
ret
mmu_wrt:
andi oplow,0b11 ;mask lower address bits
addi oplow,low(mmu_emu) ;set RAM shadow
ldi ophigh,high(mmu_emu)
st opointer,operand ;save MMU RAM element
set_io_select mmu_sel
par_wrt 60
rjmp iw_exit ;next instruction
/*
mmu_rs: ;reset to default banks = 0 0 1 1
clr operand ;1st RAM element 0
clr a ;1st address segment
ldi zl,low(mmu_emu) ;1st RAM shadow
ldi zh,high(mmu_emu)
sts mmu_sync,allon ;monitor MMU = emulator MMU
set_io_reset mmu_sel
rcall mmu_rs_seg ;segment 0 - RAM element 0 low
rcall mmu_rs_seg ;segment 1 - RAM element 0 high
inc operand ;RAM element 1
rcall mmu_rs_seg ;segment 2 - RAM element 1 low
;segment 3 - RAM element 1 high
mmu_rs_seg: ;reset one segment
st z+,operand ;write RAM shadow
out abuslo,a ;write bank switch register
par_wrt 60
inc a ;next address segment
ret
*/
mmu_rs: ;soft reset to current emulator banks
clr a ;1st address segment
ldi zl,low(mmu_emu) ;1st RAM shadow
ldi zh,high(mmu_emu)
sts mmu_sync,allon ;monitor MMU = emulator MMU
set_io_reset mmu_sel
do mmu_rs_el
ld operand,z+ ;read RAM shadow
out abuslo,a ;write bank switch register
par_wrt 60
inc a ;next address segment
cpi a,4
loopne mmu_rs_el
ret
.endif
.ifdef lcd_sel
;*****************************************************************
;
;character LCD IO
;
; LCD address pin 7 (0=write, 1=read), pin 0 (0=cmd/busy, 1=data)
; automatic busy scan for address 0 & 1 if lcd responded during reset
; raw access at 2 & 3
lcd_rd: ;referenced from ior_tab = address
set_io_select lcd_sel
lds a,lcd_flags ;lcd responded during reset?
tst a
ifne_and lcd_rd_scan
sbrc oplow,1 ;address 0 or 1 / not 2 or 3?
ifs lcd_rd_scan ;scan busy flag
cbi abuslo,0 ;status register
par_pre_rd 450
sbrc a,7 ;test status busy
rjmp ir_retry ;on busy
out abuslo,oplow ;back to original address
ldi a,32 ;delay 96 cycles = 6µs
do lcd_rd_adr ;for older hd44780 requiring
dec a ;extra time after busy
loopne lcd_rd_adr ;to increment RAM address
end lcd_rd_scan
par_rd 450 ;450ns enable strobe
lcd_wrt: ;referenced from iow_tab = address
set_io_select lcd_sel
lds a,lcd_flags ;lcd responded during reset?
tst a
ifne_and lcd_wrt_scan
sbrc oplow,1 ;address 0 or 1 / not 2 or 3?
ifs lcd_wrt_scan ;scan busy flag
cbi abuslo,0 ;status register
par_pre_rd 450
sbrc a,7 ;test status busy
rjmp iw_retry ;on busy
out abuslo,oplow ;back to original address
ldi a,32 ;delay 96 cycles = 6µs
do lcd_wrt_adr ; for older hd44780 requiring
dec a ; extra time after busy
loopne lcd_wrt_adr ; to increment RAM address
end lcd_wrt_scan
par_wrt 450 ;450ns enable strobe
rjmp iw_exit ;next instruction
lcd_rs:
; character LCD - check presence
ldi a,0x30 ;reset LCD 8-bit mode
mov operand,a
out abuslo,zero ;-w & -rs (write command)
sts lcd_flags,allon ;set lcd usable
set_io_reset lcd_sel ;select lcd strobe
ldi a,0x15 ;15ms power up delay
rcall lcd_rs_force ;write 8-bit mode
ldi a,0xbf ;4.1ms delay
rcall lcd_rs_force ;repeat write 8-bit mode
ldi a,0xfd ;100µs delay
rcall lcd_rs_force ;repeat write 8-bit mode
;continue init checking busy
ldi zl,low(lcd_init<<1)
ldi zh,high(lcd_init<<1)
ldi oplow,0 ;command register
do lcd_rs_init
lpm a,z+
tst a ;end of string?
exiteq lcd_rs_init
cpi a,0xff ;switch to data register?
ifeq lcd_rs_text
ldi oplow,1
else lcd_rs_text
rcall lcd_rs_wrt
end lcd_rs_text
loop lcd_rs_init
ldi oplow,0 ;verify text on LCD
ldi a,0x80 ;cursor position 0
rcall lcd_rs_wrt
ldi zl,low((lcd_init<<1)+5)
ldi zh,high((lcd_init<<1)+5)
ldi oplow,1
do lcd_rs_readback
rcall lcd_rs_rd
lpm a,z+
tst a
exiteq lcd_rs_readback
cp a,operand
ifne lcd_rs_rd_fail
sts lcd_flags,zero
end lcd_rs_rd_fail
loop lcd_rs_readback
lds a,lcd_flags ;message, if LCD failed
tst a
ifeq lcd_rs_fail
PrintStr_far lcd_fail
end lcd_rs_fail
ret
lcd_init: ;8 bit bus, 2 display lines
; ;display on, cursor off
; ; ;clear & home position
; ; ; ;position increment, no shift
; ; ; ; ;switch to data (internal)
.db 0x38,0xc,1,6,0xff,core_string," Emu V",version,0
lcd_fail: .db 13,10,"LCD reset failed",0,0
; subroutines for lcd reset - keep within io_select for lcd
lcd_rs_force: ;delayed forced write to lcd
out tcnt0,a
do rs_lcd_delay
in a,tcnt0
tst a
loopne rs_lcd_delay
rjmp lcd_rs_fwrt
lcd_rs_wrt: ;write to lcd with timeout on busy
out tcnt0,zero
mov operand,a
cbi abuslo,0 ;set status register
do lcd_rs_busy
in a,tcnt0 ;busy timeout?
cpi a,0x9c ;>10ms?
ifeq lcd_rs_timeout
sts lcd_flags,zero
ret
end lcd_rs_timeout
par_pre_rd 450
sbrc a,7 ;test status busy
loop lcd_rs_busy
ldi a,32 ;delay 96 cycles = 6µs
do lcd_rs_adr ; for older hd44780 requiring
dec a ; extra time after busy
loopne lcd_rs_adr ; to increment RAM address
lcd_rs_fwrt:
out abuslo,oplow ;set register
par_wrt 450 ;write with 450ns strobe
ret
lcd_rs_rd: ;read from lcd with timeout on busy
out tcnt0,zero
cbi abuslo,0 ;set status register
do lcd_rs_rd_busy
in a,tcnt0 ;busy timeout?
cpi a,0x9c ;>10ms?
ifeq lcd_rs_rd_timeout
sts lcd_flags,zero
ret
end lcd_rs_rd_timeout
par_pre_rd 450
sbrc a,7 ;test status busy
loop lcd_rs_rd_busy
ldi a,32 ;delay 96 cycles = 6µs
do lcd_rs_rd_adr ; for older hd44780 requiring
dec a ; extra time after busy
loopne lcd_rs_rd_adr ; to increment RAM address
out abuslo,oplow ;set register
par_pre_rd 450 ;read with 450ns strobe
mov operand,a
ret
.endif
;*****************************************************************
;
; emulated 6551 ACIA - data register only
;
; ACIA is not available, when the debugger is using the RS232 interface
; use exit command (X) to enable ACIA, use break to return to the debugger
;
;data register, TX on write, RX on read both with 256 byte FIFO buffer
acia_rx:
lds a,irq_flag
cbr a,0b01000000 ;clear rdrf
lds c,irq_mask ;other interrupts pending & enabled?
and c,a
ifeq rx_irq_clear
.ifdef ena_diag
lds c,selftest
sbrs c,0 ;forced IRQ by selftest
.endif
cbi cbusddr,3 ;clear IRQ
end rx_irq_clear
clr operand ;default response
sbrc flags,deb_on ;acia disconnected?
ifs acia_rx_ena
lds c,rx_fill ;precharge rx level
.ifdef irq_dis_real
sbrs stat2,2 ;interrupts disabled?
ifs acia_rx_bypass
sbis ucsra,udre ;UDR available?
ifs_and acia_rx_tx
lds d,tx_fill ;empty buffer?
tst d
ifne acia_rx_tx
ldi xh,high(tx_buf)
lds xl,tx_inx ;calc output index
sub xl,d
ld b,x ;load from fifo head
out udr,b
dec d ;update pointer
ifeq acia_rx_tx_empty
ldi b,usart_txi_dis ;tx buffer now empty
out ucsrb,b
sts usart_ena,b
end acia_rx_tx_empty
sts tx_fill,d
end acia_rx_tx
lds b,irq_mask ;check TDRE IRQ enabled
andi b,0b10000000
ifne acia_rx_tx_int_ena
sbi cbusddr,3 ;set IRQ
end acia_rx_tx_int_ena
lds b,irq_flag
sbr b,0b10000000 ;set TDRE
sts irq_flag,b ;store status
tst c ;buffer empty?
ifeq acia_rx_direct
sbic ucsra,rxc ;data waiting in UDR?
in operand,udr ;read direct if disabled & buffer empty
end acia_rx_direct
end acia_rx_bypass
.endif
tst c ;buffer empty?
ifne acia_rx_empty
lds xl,rx_inx ;prepare address to read rx fifo
ldi xh,high(rx_buf)
sub xl,c
ld operand,x ;read
dec c ;update pointer
sts rx_fill,c
ifne acia_rx_more
lds b,irq_mask ;check acia irq enabled
andi b,0b01000000 ;RDRF IRQ enabled ?
ifne acia_rx_int
sbi cbusddr,3 ;set IRQ
end acia_rx_int
sbr a,0b01000000 ;set rdrf - more rx data
end acia_rx_more
.ifdef flowlo
mov i,c
cpi i,flowlo ;buffer lower watermark?
iflo acia_flow
lds i,flow_cmd
cpi i,0x91 ;xon done?
ifne acia_send_xon
ldi i,0x11 ;post xon pending
sts flow_cmd,i
ldi i,usart_txi_ena ;notify transmitter
out ucsrb,i
.ifdef irq_dis_real
sts usart_ena,i
.endif
end acia_send_xon
end acia_flow
.endif
end acia_rx_empty
sts irq_flag,a
end acia_rx_ena
ldi oc_tabh,high(oc_tab) ;restore zh as opcode table
sbrc stat2,3 ;test decimal flag
ldi oc_tabh,high(oc_tabd)
ret
acia_tx:
lds c,tx_fill ;precharge level
.ifdef irq_dis_real
sbrs stat2,2 ;interrupts disabled?
ifs_and acia_tx_bypass
sbis ucsra,udre ;UDR empty?
ifs acia_tx_bypass
cbr flags,(1<<deb_on) ;force connect
tst c ;data in buffer
ifne acia_tx_filled
ldi xh,high(tx_buf)
lds xl,tx_inx ;calc output index
sub xl,c
ld d,x ;load from fifo head
out udr,d
dec c
else acia_tx_filled
out udr,operand ;direct output
rjmp iw_exit
end acia_tx_filled
end acia_tx_bypass
.endif
sbrc flags,deb_on ;acia connected?
iw_retry_ext:
rjmp iw_retry ;disconnected - loop until buffer is available
inc c ;space in buffer ?
breq iw_retry_ext ;full - loop until buffer is available
lds a,irq_flag
cbr a,0b10000000 ;clear tdre
lds d,irq_mask ;other interrupts pending & enabled?
and d,a
ifeq tx_irq_clear
.ifdef ena_diag
lds d,selftest
sbrs d,0 ;forced IRQ by selftest
.endif
cbi cbusddr,3 ;clear IRQ
end tx_irq_clear
ldi i,usart_txi_ena ;notify transmitter
out ucsrb,i
.ifdef irq_dis_real
sts usart_ena,i
.endif
lds xl,tx_inx ;load pointer
ldi xh,high(tx_buf)
st x+,operand ;send data to fifo
sts tx_inx,xl ;save index
sts tx_fill,c
inc c ;more tx fifo available?
ifne acia_tx_more
lds b,irq_mask ;TDRE IRQ enabled
andi b,0b10000000
ifne acia_tx_int
sbi cbusddr,3 ;set IRQ
end acia_tx_int
sbr a,0b10000000 ;set tdre - tx buffer available
end acia_tx_more
sts irq_flag,a