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dpu_musebox.hwh
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue May 9 17:57:19 2023" VIVADOVERSION="2022.1">
<SYSTEMINFO ARCH="zynquplus" BOARD="xilinx.com:k26c:part0:1.3" DEVICE="xck26" NAME="design_1" PACKAGE="sfvc784" SPEEDGRADE="-2LV"/>
<EXTERNALPORTS>
<PORT CLKFREQUENCY="25000000" DIR="I" NAME="CLK_IN_gem" SIGIS="clk" SIGNAME="External_Ports_CLK_IN_gem">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_wiz_0" PORT="clk_in1"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="gpio_rtl_tri_o" RIGHT="0" SIGIS="undef" SIGNAME="axi_gpio_0_gpio_io_o">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_gpio_0" PORT="gpio_io_o"/>
</CONNECTIONS>
</PORT>
</EXTERNALPORTS>
<EXTERNALINTERFACES>
<BUSINTERFACE BUSNAME="axi_gpio_0_GPIO" NAME="gpio_rtl" TYPE="INITIATOR">
<PORTMAPS>
<PORTMAP LOGICAL="TRI_O" PHYSICAL="gpio_rtl_tri_o"/>
</PORTMAPS>
</BUSINTERFACE>
</EXTERNALINTERFACES>
<MODULES>
<MODULE COREREVISION="0" FULLNAME="/DPUCZDX8G_1" HWVERSION="1.0" INSTANCE="DPUCZDX8G_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="DPUCZDX8G" VLNV="xilinx.com:RTLKernel:DPUCZDX8G:1.0">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="" INTERFACE="S_AXI_CONTROL" NAME="reg0" RANGE="0x1000" USAGE="register"/>
</ADDRESSBLOCKS>
<PARAMETERS>
<PARAMETER NAME="DSP48_VER" VALUE="DSP48E2"/>
<PARAMETER NAME="S_AXI_FREQ_MHZ" VALUE="200"/>
<PARAMETER NAME="M_AXI_FREQ_MHZ" VALUE="200"/>
<PARAMETER NAME="AWRLEN_BW" VALUE="8"/>
<PARAMETER NAME="AWRUSER_BW" VALUE="1"/>
<PARAMETER NAME="AWRLOCK_BW" VALUE="1"/>
<PARAMETER NAME="GP_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP0_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP1_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP2_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP3_ID_BW" VALUE="6"/>
<PARAMETER NAME="HP_DATA_BW" VALUE="128"/>
<PARAMETER NAME="SYS_IP_VER" VALUE="0x00000040"/>
<PARAMETER NAME="SYS_IP_TYPE" VALUE="0x00000001"/>
<PARAMETER NAME="SIZE_REGMAP_SIZE" VALUE="0x0000006B"/>
<PARAMETER NAME="SYS_REGMAP_VER" VALUE="2"/>
<PARAMETER NAME="TIME_YEAR" VALUE="22"/>
<PARAMETER NAME="TIME_MONTH" VALUE="5"/>
<PARAMETER NAME="TIME_DAY" VALUE="14"/>
<PARAMETER NAME="TIME_HOUR" VALUE="14"/>
<PARAMETER NAME="TIME_QUARTER" VALUE="2"/>
<PARAMETER NAME="GIT_COMMIT_ID" VALUE="0x4772D51"/>
<PARAMETER NAME="GIT_COMMIT_TIME" VALUE="2022051323"/>
<PARAMETER NAME="VER_IP_REV" VALUE="0x00000000"/>
<PARAMETER NAME="VER_TARGET" VALUE="0x141"/>
<PARAMETER NAME="ARCH_HP_BW" VALUE="3"/>
<PARAMETER NAME="ARCH_DATA_BW" VALUE="1"/>
<PARAMETER NAME="ARCH_IMG_BKGRP" VALUE="2"/>
<PARAMETER NAME="ARCH_PP" VALUE="8"/>
<PARAMETER NAME="ARCH_ICP" VALUE="16"/>
<PARAMETER NAME="ARCH_OCP" VALUE="16"/>
<PARAMETER NAME="RAM_DEPTH_MEAN" VALUE="1"/>
<PARAMETER NAME="RAM_DEPTH_BIAS" VALUE="3"/>
<PARAMETER NAME="RAM_DEPTH_WGT" VALUE="3"/>
<PARAMETER NAME="RAM_DEPTH_IMG" VALUE="3"/>
<PARAMETER NAME="UBANK_IMG_N" VALUE="5"/>
<PARAMETER NAME="UBANK_WGT_N" VALUE="17"/>
<PARAMETER NAME="UBANK_BIAS" VALUE="1"/>
<PARAMETER NAME="DBANK_IMG_N" VALUE="0"/>
<PARAMETER NAME="DBANK_WGT_N" VALUE="0"/>
<PARAMETER NAME="DBANK_BIAS" VALUE="0"/>
<PARAMETER NAME="LOAD_AUGM" VALUE="1"/>
<PARAMETER NAME="LOAD_IMG_MEAN" VALUE="0"/>
<PARAMETER NAME="LOAD_PARALLEL" VALUE="2"/>
<PARAMETER NAME="CONV_LEAKYRELU" VALUE="1"/>
<PARAMETER NAME="CONV_RELU6" VALUE="1"/>
<PARAMETER NAME="CONV_WR_PARALLEL" VALUE="1"/>
<PARAMETER NAME="CONV_DSP_CASC_MAX" VALUE="4"/>
<PARAMETER NAME="CONV_DSP_ACCU_ENA" VALUE="1"/>
<PARAMETER NAME="SAVE_PARALLEL" VALUE="2"/>
<PARAMETER NAME="ELEW_PARALLEL" VALUE="4"/>
<PARAMETER NAME="ALU_LEAKYRELU" VALUE="0"/>
<PARAMETER NAME="ALU_PARALLEL" VALUE="4"/>
<PARAMETER NAME="MISC_WR_PARALLEL" VALUE="1"/>
<PARAMETER NAME="DNNDK_PRINT" VALUE="xrt test"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_DPUCZDX8G_1_0"/>
<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
<PARAMETER NAME="C_BASEADDR" VALUE="0xB0000000"/>
<PARAMETER NAME="C_HIGHADDR" VALUE="0xB0000FFF"/>
</PARAMETERS>
<PORTS>
<PORT DIR="O" LEFT="39" NAME="M_AXI_GP0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_GP0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_arlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_arready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_arvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="39" NAME="M_AXI_GP0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_GP0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_GP0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_awlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_awready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_GP0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_awvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_bready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_bvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="M_AXI_GP0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_rlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_rready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_GP0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_rvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="M_AXI_GP0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_wlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_GP0_wready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_GP0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_GP0_wvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_GP0_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HPC0_FPD" PORT="S00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_aruser" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" LEFT="0" NAME="M_AXI_GP0_awuser" RIGHT="0" SIGIS="undef"/>
<PORT DIR="O" LEFT="39" NAME="M_AXI_HP0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_HP0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_HP0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP0_arlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_arready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_arvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="39" NAME="M_AXI_HP0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_HP0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_HP0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP0_awlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_awready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_awvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_bready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_HP0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_bvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="127" NAME="M_AXI_HP0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_rlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_rready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_HP0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_rvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="127" NAME="M_AXI_HP0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_wlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP0_wready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="M_AXI_HP0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP0_wvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP0_aruser" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_aruser">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_aruser"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP0_awuser" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP0_awuser">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP0_FPD" PORT="S00_AXI_awuser"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="39" NAME="M_AXI_HP2_araddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_HP2_arburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP2_arcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_HP2_arlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP2_arlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP2_arprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP2_arqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP2_arready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP2_arsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP2_arvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="39" NAME="M_AXI_HP2_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="M_AXI_HP2_awburst" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awburst">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awburst"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP2_awcache" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awcache">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awcache"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="7" NAME="M_AXI_HP2_awlen" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awlen">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awlen"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP2_awlock" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awlock">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awlock"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP2_awprot" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awprot">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awprot"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="M_AXI_HP2_awqos" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awqos">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awqos"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP2_awready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="2" NAME="M_AXI_HP2_awsize" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awsize">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awsize"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP2_awvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP2_bready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_HP2_bresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP2_bvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="127" NAME="M_AXI_HP2_rdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP2_rlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_rlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_rlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP2_rready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="1" NAME="M_AXI_HP2_rresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP2_rvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="127" NAME="M_AXI_HP2_wdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP2_wlast" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_wlast">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_wlast"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="M_AXI_HP2_wready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="15" NAME="M_AXI_HP2_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="M_AXI_HP2_wvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP2_aruser" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_aruser">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_aruser"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="0" NAME="M_AXI_HP2_awuser" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_M_AXI_HP2_awuser">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_S_AXI_HP1_FPD" PORT="S00_AXI_awuser"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="11" NAME="S_AXI_CONTROL_araddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_araddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_araddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_CONTROL_arready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_arready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_arready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_CONTROL_arvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_arvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_arvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="11" NAME="S_AXI_CONTROL_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_awaddr">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_awaddr"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_CONTROL_awready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_awready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_awready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_CONTROL_awvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_awvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_awvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_CONTROL_bready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_bready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_bready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S_AXI_CONTROL_bresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_bresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_bresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_CONTROL_bvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_bvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_bvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="31" NAME="S_AXI_CONTROL_rdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_rdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_rdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_CONTROL_rready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_rready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_rready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="1" NAME="S_AXI_CONTROL_rresp" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_rresp">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_rresp"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_CONTROL_rvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_rvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_rvalid"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="31" NAME="S_AXI_CONTROL_wdata" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_wdata">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_wdata"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="S_AXI_CONTROL_wready" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_wready">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_wready"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" LEFT="3" NAME="S_AXI_CONTROL_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_wstrb">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_wstrb"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="S_AXI_CONTROL_wvalid" SIGIS="undef" SIGNAME="DPUCZDX8G_1_S_AXI_CONTROL_wvalid">
<CONNECTIONS>
<CONNECTION INSTANCE="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" PORT="M00_AXI_wvalid"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="200000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_wiz_0_clk_out2">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_wiz_0" PORT="clk_out2"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="400000000" DIR="I" NAME="ap_clk_2" SIGIS="clk" SIGNAME="clk_wiz_0_clk_out3">
<CONNECTIONS>
<CONNECTION INSTANCE="clk_wiz_0" PORT="clk_out3"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="ap_rst_n_2" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_2_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="proc_sys_reset_2" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="proc_sys_reset_1_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="proc_sys_reset_1" PORT="peripheral_aresetn"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" NAME="interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="DPUCZDX8G_1_M_AXI_GP0" DATAWIDTH="32" NAME="M_AXI_GP0" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
<PARAMETER NAME="FREQ_HZ" VALUE="200000000"/>
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
<PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="HAS_BURST" VALUE="1"/>
<PARAMETER NAME="HAS_LOCK" VALUE="1"/>
<PARAMETER NAME="HAS_PROT" VALUE="1"/>
<PARAMETER NAME="HAS_CACHE" VALUE="1"/>
<PARAMETER NAME="HAS_QOS" VALUE="1"/>
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_clk_wiz_0_0_clk_out1"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_GP0_awaddr"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="M_AXI_GP0_awlen"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="M_AXI_GP0_awsize"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="M_AXI_GP0_awburst"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="M_AXI_GP0_awlock"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="M_AXI_GP0_awcache"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_GP0_awprot"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="M_AXI_GP0_awqos"/>
<PORTMAP LOGICAL="AWUSER" PHYSICAL="M_AXI_GP0_awuser"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_GP0_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_GP0_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_GP0_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_GP0_wstrb"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="M_AXI_GP0_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_GP0_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_GP0_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_GP0_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_GP0_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_GP0_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_GP0_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="M_AXI_GP0_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="M_AXI_GP0_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="M_AXI_GP0_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="M_AXI_GP0_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="M_AXI_GP0_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_GP0_arprot"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="M_AXI_GP0_arqos"/>
<PORTMAP LOGICAL="ARUSER" PHYSICAL="M_AXI_GP0_aruser"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_GP0_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_GP0_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_GP0_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_GP0_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="M_AXI_GP0_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_GP0_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_GP0_rready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="DPUCZDX8G_1_M_AXI_HP0" DATAWIDTH="128" NAME="M_AXI_HP0" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
<PARAMETER NAME="FREQ_HZ" VALUE="200000000"/>
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
<PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="HAS_BURST" VALUE="1"/>
<PARAMETER NAME="HAS_LOCK" VALUE="1"/>
<PARAMETER NAME="HAS_PROT" VALUE="1"/>
<PARAMETER NAME="HAS_CACHE" VALUE="1"/>
<PARAMETER NAME="HAS_QOS" VALUE="1"/>
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_clk_wiz_0_0_clk_out1"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_HP0_awaddr"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="M_AXI_HP0_awlen"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="M_AXI_HP0_awsize"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="M_AXI_HP0_awburst"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="M_AXI_HP0_awlock"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="M_AXI_HP0_awcache"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_HP0_awprot"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="M_AXI_HP0_awqos"/>
<PORTMAP LOGICAL="AWUSER" PHYSICAL="M_AXI_HP0_awuser"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_HP0_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_HP0_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_HP0_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_HP0_wstrb"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="M_AXI_HP0_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_HP0_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_HP0_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_HP0_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_HP0_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_HP0_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_HP0_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="M_AXI_HP0_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="M_AXI_HP0_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="M_AXI_HP0_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="M_AXI_HP0_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="M_AXI_HP0_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_HP0_arprot"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="M_AXI_HP0_arqos"/>
<PORTMAP LOGICAL="ARUSER" PHYSICAL="M_AXI_HP0_aruser"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_HP0_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_HP0_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_HP0_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_HP0_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="M_AXI_HP0_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_HP0_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_HP0_rready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="DPUCZDX8G_1_M_AXI_HP2" DATAWIDTH="128" NAME="M_AXI_HP2" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
<PARAMETER NAME="FREQ_HZ" VALUE="200000000"/>
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
<PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="HAS_BURST" VALUE="1"/>
<PARAMETER NAME="HAS_LOCK" VALUE="1"/>
<PARAMETER NAME="HAS_PROT" VALUE="1"/>
<PARAMETER NAME="HAS_CACHE" VALUE="1"/>
<PARAMETER NAME="HAS_QOS" VALUE="1"/>
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_clk_wiz_0_0_clk_out1"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="M_AXI_HP2_awaddr"/>
<PORTMAP LOGICAL="AWLEN" PHYSICAL="M_AXI_HP2_awlen"/>
<PORTMAP LOGICAL="AWSIZE" PHYSICAL="M_AXI_HP2_awsize"/>
<PORTMAP LOGICAL="AWBURST" PHYSICAL="M_AXI_HP2_awburst"/>
<PORTMAP LOGICAL="AWLOCK" PHYSICAL="M_AXI_HP2_awlock"/>
<PORTMAP LOGICAL="AWCACHE" PHYSICAL="M_AXI_HP2_awcache"/>
<PORTMAP LOGICAL="AWPROT" PHYSICAL="M_AXI_HP2_awprot"/>
<PORTMAP LOGICAL="AWQOS" PHYSICAL="M_AXI_HP2_awqos"/>
<PORTMAP LOGICAL="AWUSER" PHYSICAL="M_AXI_HP2_awuser"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="M_AXI_HP2_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="M_AXI_HP2_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="M_AXI_HP2_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="M_AXI_HP2_wstrb"/>
<PORTMAP LOGICAL="WLAST" PHYSICAL="M_AXI_HP2_wlast"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="M_AXI_HP2_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="M_AXI_HP2_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="M_AXI_HP2_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="M_AXI_HP2_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="M_AXI_HP2_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="M_AXI_HP2_araddr"/>
<PORTMAP LOGICAL="ARLEN" PHYSICAL="M_AXI_HP2_arlen"/>
<PORTMAP LOGICAL="ARSIZE" PHYSICAL="M_AXI_HP2_arsize"/>
<PORTMAP LOGICAL="ARBURST" PHYSICAL="M_AXI_HP2_arburst"/>
<PORTMAP LOGICAL="ARLOCK" PHYSICAL="M_AXI_HP2_arlock"/>
<PORTMAP LOGICAL="ARCACHE" PHYSICAL="M_AXI_HP2_arcache"/>
<PORTMAP LOGICAL="ARPROT" PHYSICAL="M_AXI_HP2_arprot"/>
<PORTMAP LOGICAL="ARQOS" PHYSICAL="M_AXI_HP2_arqos"/>
<PORTMAP LOGICAL="ARUSER" PHYSICAL="M_AXI_HP2_aruser"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="M_AXI_HP2_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="M_AXI_HP2_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="M_AXI_HP2_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="M_AXI_HP2_rresp"/>
<PORTMAP LOGICAL="RLAST" PHYSICAL="M_AXI_HP2_rlast"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="M_AXI_HP2_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="M_AXI_HP2_rready"/>
</PORTMAPS>
</BUSINTERFACE>
<BUSINTERFACE BUSNAME="axi_ic_zynq_ultra_ps_e_0_M_AXI_HPM1_FPD_M00_AXI" DATAWIDTH="32" NAME="S_AXI_CONTROL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
<PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
<PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
<PARAMETER NAME="FREQ_HZ" VALUE="200000000"/>
<PARAMETER NAME="ID_WIDTH" VALUE="0"/>
<PARAMETER NAME="ADDR_WIDTH" VALUE="12"/>
<PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
<PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
<PARAMETER NAME="HAS_BURST" VALUE="0"/>
<PARAMETER NAME="HAS_LOCK" VALUE="0"/>
<PARAMETER NAME="HAS_PROT" VALUE="0"/>
<PARAMETER NAME="HAS_CACHE" VALUE="0"/>
<PARAMETER NAME="HAS_QOS" VALUE="0"/>
<PARAMETER NAME="HAS_REGION" VALUE="0"/>
<PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
<PARAMETER NAME="HAS_BRESP" VALUE="1"/>
<PARAMETER NAME="HAS_RRESP" VALUE="1"/>
<PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
<PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
<PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
<PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
<PARAMETER NAME="PHASE" VALUE="0.0"/>
<PARAMETER NAME="CLK_DOMAIN" VALUE="design_1_clk_wiz_0_0_clk_out1"/>
<PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
<PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
<PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
<PARAMETER NAME="INSERT_VIP" VALUE="0"/>
<PORTMAPS>
<PORTMAP LOGICAL="AWADDR" PHYSICAL="S_AXI_CONTROL_awaddr"/>
<PORTMAP LOGICAL="AWVALID" PHYSICAL="S_AXI_CONTROL_awvalid"/>
<PORTMAP LOGICAL="AWREADY" PHYSICAL="S_AXI_CONTROL_awready"/>
<PORTMAP LOGICAL="WDATA" PHYSICAL="S_AXI_CONTROL_wdata"/>
<PORTMAP LOGICAL="WSTRB" PHYSICAL="S_AXI_CONTROL_wstrb"/>
<PORTMAP LOGICAL="WVALID" PHYSICAL="S_AXI_CONTROL_wvalid"/>
<PORTMAP LOGICAL="WREADY" PHYSICAL="S_AXI_CONTROL_wready"/>
<PORTMAP LOGICAL="BRESP" PHYSICAL="S_AXI_CONTROL_bresp"/>
<PORTMAP LOGICAL="BVALID" PHYSICAL="S_AXI_CONTROL_bvalid"/>
<PORTMAP LOGICAL="BREADY" PHYSICAL="S_AXI_CONTROL_bready"/>
<PORTMAP LOGICAL="ARADDR" PHYSICAL="S_AXI_CONTROL_araddr"/>
<PORTMAP LOGICAL="ARVALID" PHYSICAL="S_AXI_CONTROL_arvalid"/>
<PORTMAP LOGICAL="ARREADY" PHYSICAL="S_AXI_CONTROL_arready"/>
<PORTMAP LOGICAL="RDATA" PHYSICAL="S_AXI_CONTROL_rdata"/>
<PORTMAP LOGICAL="RRESP" PHYSICAL="S_AXI_CONTROL_rresp"/>
<PORTMAP LOGICAL="RVALID" PHYSICAL="S_AXI_CONTROL_rvalid"/>
<PORTMAP LOGICAL="RREADY" PHYSICAL="S_AXI_CONTROL_rready"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE ADDRESSBLOCK="HPC0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
<MEMRANGE ADDRESSBLOCK="HP0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HP0" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
<MEMRANGE ADDRESSBLOCK="HP1_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HP2" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HP1_FPD"/>
<MEMRANGE ADDRESSBLOCK="HPC0_LPS_OCM" BASENAME="C_BASEADDR" BASEVALUE="0xFF000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_GP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
<MEMRANGE ADDRESSBLOCK="HP0_LPS_OCM" BASENAME="C_BASEADDR" BASEVALUE="0xFF000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HP0" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_HP0_FPD"/>
<MEMRANGE ADDRESSBLOCK="HP1_LPS_OCM" BASENAME="C_BASEADDR" BASEVALUE="0xFF000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HP2" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_HP1_FPD"/>
</MEMORYMAP>
<PERIPHERALS>
<PERIPHERAL INSTANCE="zynq_ultra_ps_e_0"/>
</PERIPHERALS>
</MODULE>
<MODULE COREREVISION="7" FULLNAME="/axcache_0xe" HWVERSION="1.1" INSTANCE="axcache_0xe" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
<DOCUMENTS/>
<PARAMETERS>
<PARAMETER NAME="CONST_WIDTH" VALUE="4"/>
<PARAMETER NAME="CONST_VAL" VALUE="0xE"/>
<PARAMETER NAME="Component_Name" VALUE="design_1_axcache_0xe_0"/>