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boot.cpp
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/****************************************************************************
* Copyright (c) 2014 by Michael Blandford. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
* Other Authors:
* - Andre Bernet
* - Bertrand Songis
* - Bryan J. Rentoul (Gruvin)
* - Cameron Weeks
* - Erez Raviv
* - Jean-Pierre Parisy
* - Karl Szmutny
* - Michal Hlavinka
* - Pat Mackenzie
* - Philip Moss
* - Rob Thomson
* - Romolo Manfredini
* - Thomas Husterer
*
****************************************************************************/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#ifdef PCBSKY
#include "AT91SAM3S4.h"
#include "core_cm3.h"
#endif
#ifdef PCBX9D
#include "stm32f2xx.h"
#include "stm32f2xx_flash.h"
#include "i2c_ee.h"
#include "hal.h"
#include "timers.h"
extern "C" {
#include "usb_dcd_int.h"
#include "usb_bsp.h"
#include "usbd_desc.h"
#include "usbd_msc_core.h"
#include "usbd_usr.h"
}
#endif
#ifdef PCB9XT
#define P9XT_DEBUG 1
#include "stm32f2xx.h"
#include "stm32f2xx_flash.h"
#include "hal.h"
#include "timers.h"
#include "mega64.h"
extern "C" {
#include "usb_dcd_int.h"
#include "usb_bsp.h"
#include "usbd_desc.h"
#include "usbd_msc_core.h"
#include "usbd_usr.h"
}
#endif
#if defined(PCBX12D) || defined(PCBX10)
#include "stm32f4xx.h"
#include "stm32f4xx_flash.h"
#include "timers.h"
#include "stm32f4xx_rcc.h"
extern "C" {
#include "usb_dcd_int.h"
#include "usb_bsp.h"
#include "usbd_desc.h"
#include "usbd_msc_core.h"
#include "usbd_usr.h"
}
#endif
#include "radio.h"
#ifndef PCBSKY
#include "hal.h"
#endif
#include "lcd.h"
#include "ff.h"
#include "diskio.h"
#include "drivers.h"
#include "logicio.h"
__attribute__ ((section(".version"), used))
// Temp edit to force a push
const uint8_t Version[] =
{
'B', 'O', 'O', 'T', '3', '3'
} ;
__attribute__ ((section(".text"), used))
#if defined(REV9E) || defined(PCBX7) || defined(PCBSKY) || defined(PCBX12D) || defined(PCBX9LITE) || defined(PCBX10)
extern void init_rotary_encoder() ;
extern void checkRotaryEncoder() ;
#endif
extern void usbPluggedIn( uint16_t allowSD ) ;
#ifdef PCBSKY
extern uint16_t usbLunStat() ;
#endif
#ifdef PCBSKY
uint32_t LastResult ;
#endif
#ifdef PCBSKY
extern void usbMassStorage( void ) ;
#endif
void createFat( uint32_t flashSize ) ;
#if defined(PCBX12D) || defined(PCBX10)
#define POWER_STATE_OFF 0
#define POWER_STATE_START 1
#define POWER_STATE_RUNNING 2
#define POWER_STATE_STOPPING 3
#define POWER_STATE_STOPPED 4
uint8_t PowerState = POWER_STATE_OFF ;
uint32_t check_soft_power()
{
uint32_t switchValue ;
#if defined(PCBT16)
switchValue = ~GPIOPWR->IDR & PIN_PWR_STATUS ;
#else
switchValue = GPIOPWR->IDR & PIN_PWR_STATUS ;
#endif
switch ( PowerState )
{
case POWER_STATE_OFF :
default :
PowerState = POWER_STATE_START ;
return POWER_ON ;
break ;
case POWER_STATE_START :
if ( !switchValue )
{
PowerState = POWER_STATE_RUNNING ;
}
return POWER_ON ;
break ;
case POWER_STATE_RUNNING :
if ( switchValue )
{
PowerState = POWER_STATE_STOPPING ;
return POWER_X9E_STOP ;
}
return POWER_ON ;
break ;
case POWER_STATE_STOPPING :
if ( !switchValue )
{
PowerState = POWER_STATE_STOPPED ;
return POWER_OFF ;
}
return POWER_X9E_STOP ;
break ;
case POWER_STATE_STOPPED :
return POWER_OFF ;
break ;
}
}
extern "C" void pwrOff(void) ;
void soft_power_off()
{
pwrOff() ;
}
#endif
// states
#define ST_MENU 0
#define ST_START 1
#define ST_DIR_CHECK 2
#define ST_OPEN_DIR 3
#define ST_FILE_LIST 4
#define ST_FLASH_CHECK 5
#define ST_FLASHING 6
#define ST_FLASH_DONE 7
#define ST_LOAD_APP 8
#define ST_USB 10
#define ST_REBOOT 11
#define ST_WRITE_EEPROM 12
#define MENU_NOTHING 0
#define MENU_EXIT 1
#define MENU_FLASH 2
#define MENU_RUNAPP 3
#define MENU_EEPROM 4
#define UPDATE_TYPE_FLASH 0
#define UPDATE_TYPE_RUNAPP 1
#define UPDATE_TYPE_EEPROM 2
/*----------------------------------------------------------------------------
* Local variables
*----------------------------------------------------------------------------*/
uint32_t FirmwareSize ;
uint32_t Master_frequency ;
volatile uint8_t Tenms ;
uint8_t EE_timer ;
uint8_t USBcounter ;
uint8_t SDcardDisabled ;
volatile uint16_t BlinkCounter ;
extern uint32_t sd_card_ready( void ) ;
uint8_t UpdateItem ;
TCHAR FlashFilename[60] ;
FATFS g_FATFS ;
FIL FlashFile ;
DIR Dj ;
FILINFO Finfo ;
TCHAR Filenames[8][50] ;
uint32_t FileSize[20] ;
uint32_t FnStartIndex ;
uint32_t Valid ;
uint8_t FIleExtension[4] ;
uint32_t FlashSize ;
uint32_t FlashBlocked = 1 ;
uint32_t LockBits ;
#ifdef PCBSKY
uint32_t Block_buffer[1024] __attribute__((section(".overlaydata"), aligned(32))) ;
#else
uint32_t Block_buffer[1024] ;
#endif
UINT BlockCount ;
#ifdef PCBSKY
uint32_t ChipId ;
#endif
#if ( defined(PCBSKY) || defined(PCB9XT) )
extern int32_t EblockAddress ;
#endif
extern uint32_t EepromBlocked ;
extern void init_spi( void ) ;
extern void writeBlock( void ) ;
#ifdef PCBX9D
void I2C_EE_BufferWrite(uint8_t* pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) ;
#endif
extern uint16_t WatchdogTimer ;
extern void b_putEvent( register uint8_t evt) ;
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
void __set_MSP(uint32_t mainStackPointer) ;
#ifdef PCBSKY
// Starts TIMER0 at full speed (MCK/2) for delay timing
// @ 36MHz this is 18MHz
// This was 6 MHz, we may need to slow it to TIMER_CLOCK2 (MCK/8=4.5 MHz)
void start_timer0()
{
register Tc *ptc ;
PMC->PMC_PCER0 |= 0x00800000L ; // Enable peripheral clock to TC0
ptc = TC0 ; // Tc block 0 (TC0-2)
ptc->TC_BCR = 0 ; // No sync
ptc->TC_BMR = 2 ;
ptc->TC_CHANNEL[0].TC_CMR = 0x00008001 ; // Waveform mode MCK/8 for 36MHz osc.(Upset be write below)
ptc->TC_CHANNEL[0].TC_RC = 0xFFF0 ;
ptc->TC_CHANNEL[0].TC_RA = 0 ;
ptc->TC_CHANNEL[0].TC_CMR = 0x00008040 ; // 0000 0000 0000 0000 1000 0000 0100 0000, stop at regC, 18MHz
ptc->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger)
}
void stop_timer0( void )
{
TC0->TC_CHANNEL[0].TC_CCR = TC_CCR0_CLKDIS ; // Disable clock
}
void delay2ms()
{
TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger)
while ( TC0->TC_CHANNEL[0].TC_CV < 36000 ) // 2mS, Value depends on MCK/2 (used 18MHz)
{
// Wait
}
}
void delayNus( uint16_t time )
{
time *= 18 ; // Value depends on MCK/2 (used 18MHz)
TC0->TC_CHANNEL[0].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger)
while ( TC0->TC_CHANNEL[0].TC_CV < time ) // "time" uS, Value depends on MCK/2 (used 18MHz)
{
// Wait
}
}
#endif
static uint32_t PowerUpDelay ;
static bool usbPlugged(void)
{
if ( PowerUpDelay < 100 ) // 1000 mS
{
return 0 ;
}
#ifdef PCBSKY
return PIOC->PIO_PDSR & 0x02000000 ;
#endif
#if ( defined(PCBX9D) || defined(PCB9XT) )
return GPIOA->IDR & 0x0200 ;
#endif
#if defined(PCBX12D) || defined(PCBX10)
return GPIOA->IDR & 0x0200 ;
#endif
}
#if ( defined(PCBX9D) || defined(PCB9XT) || defined(PCBX12D) ) || defined(PCBX10)
extern "C" {
USB_OTG_CORE_HANDLE USB_OTG_dev;
void OTG_FS_IRQHandler(void)
{
USBD_OTG_ISR_Handler (&USB_OTG_dev);
}
}
static void usbInit()
{
USB_OTG_BSP_Init(&USB_OTG_dev);
}
static void usbStart()
{
USBD_Init(&USB_OTG_dev, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_MSC_cb, &USR_cb);
}
#endif
#if ( defined(PCBX9D) || defined(PCB9XT) )
uint32_t isFirmwareStart( uint32_t *block )
{
if ( ( block[0] & 0xFFFC0000 ) != 0x20000000 )
{
if ( ( block[0] & 0xFFFC0000 ) != 0x10000000 )
{
return 0 ;
}
}
if ( ( block[1] & 0xFFF00000 ) != 0x08000000 )
{
return 0 ;
}
if ( ( block[2] & 0xFFF00000 ) != 0x08000000 )
{
return 0 ;
}
return 1 ;
}
#endif
#if defined(PCBX12D) || defined(PCBX10)
uint32_t isFirmwareStart( uint32_t *block )
{
if ( ( block[0] & 0xFFF00000 ) != 0x20000000 )
{
if ( ( block[0] & 0xFFF00000 ) != 0x10000000 )
{
return 0 ;
}
}
if ( ( block[1] & 0xFFC00000 ) != 0x08000000 )
{
return 0 ;
}
if ( ( block[2] & 0xFFC00000 ) != 0x08000000 )
{
return 0 ;
}
return 1 ;
}
#endif
#ifdef PCBSKY
uint32_t isFirmwareStart( uint32_t *block )
{
if ( ChipId & 0x0080 )
{
if ( ( block[0] & 0xFFFC3000 ) != 0x20000000 )
{
return 0 ;
}
}
else
{
if ( ( block[0] & 0xFFFE3000 ) != 0x20000000 )
{
return 0 ;
}
}
if ( ( block[1] & 0xFFF80000 ) != 0x00400000 )
{
return 0 ;
}
if ( ( block[2] & 0xFFF80000 ) != 0x00400000 )
{
return 0 ;
}
return 1 ;
}
#endif
#ifdef PCBSKY
uint32_t (*IAP_Function)(uint32_t, uint32_t) ;
uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes
{
uint32_t FlashSectorNum ;
uint32_t flash_cmd = 0 ;
uint32_t i ;
uint32_t size ;
// uint32_t flash_status = 0;
// uint32_t EFCIndex = 0; // 0:EEFC0, 1: EEFC1
/* Initialize the function pointer (retrieve function address from NMI vector) */
if ( ( (uint32_t) address == 0x00408000 ) || ( (uint32_t) address == 0x00407000 ) )
{
if ( isFirmwareStart( buffer) )
{
FlashBlocked = 0 ;
}
// else
// {
// FlashBlocked = 1 ;
// }
}
if ( (uint32_t) address < 0x00407000 )
{
FlashBlocked = 1 ;
return 1 ;
}
if ( FlashBlocked )
{
return 1 ;
}
IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ;
FlashSectorNum = (uint32_t) address ;
if ( ChipId & 0x0080 )
{
size = 128 ;
FlashSectorNum >>= 9 ; // page size is 512 bytes
FlashSectorNum &= 1023 ; // max page number
}
else
{
// Always initialise this here, setting a default doesn't seem to work
size = 64 ;
FlashSectorNum >>= 8 ; // page size is 256 bytes
FlashSectorNum &= 2047 ; // max page number
}
/* Send data to the sector here */
for ( i = 0 ; i < size ; i += 1 )
{
*address++ = *buffer++ ;
}
if ( ChipId & 0x0080 )
{
if ( ( FlashSectorNum & 7 ) == 0 )
{
flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | 0x00000100 | 0x07 ; //AT91C_MC_FCMD_EPA = erase (8) pages
__disable_irq() ;
/* Call the IAP function with appropriate command */
i = IAP_Function( 0, flash_cmd ) ;
__enable_irq() ;
}
flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | 0x01 ; //AT91C_MC_FCMD_WP = write page
}
else
{
/* build the command to send to EEFC */
flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) | 0x03 ; //AT91C_MC_FCMD_EWP
}
__disable_irq() ;
/* Call the IAP function with appropriate command */
i = IAP_Function( 0, flash_cmd ) ;
__enable_irq() ;
return i ;
}
uint32_t readLockBits()
{
// Always initialise this here, setting a default doesn't seem to work
IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ;
uint32_t flash_cmd = (0x5A << 24) | 0x0A ; //AT91C_MC_FCMD_GLB ;
__disable_irq() ;
(void) IAP_Function( 0, flash_cmd ) ;
__enable_irq() ;
return EFC->EEFC_FRR ;
}
void clearLockBits()
{
uint32_t i ;
uint32_t flash_cmd = 0 ;
// Always initialise this here, setting a default doesn't seem to work
IAP_Function = (uint32_t (*)(uint32_t, uint32_t)) *(( uint32_t *)0x00800008) ;
for ( i = 0 ; i < 16 ; i += 1 )
{
flash_cmd = (0x5A << 24) | ((128*i) << 8) | 0x09 ; //AT91C_MC_FCMD_CLB ;
__disable_irq() ;
/* Call the IAP function with appropriate command */
(void) IAP_Function( 0, flash_cmd ) ;
__enable_irq() ;
}
}
#endif
void interrupt10ms()
{
BlinkCounter += 7 ;
Tenms |= 1 ; // 10 mS has passed
per10ms() ;
}
#ifdef PCBSKY
void init10msTimer()
{
register Tc *ptc ;
register uint32_t timer ;
PMC->PMC_PCER0 |= 0x02000000L ; // Enable peripheral clock to TC2
timer = Master_frequency / 12800 ; // MCK/128 and 100 Hz
ptc = TC0 ; // Tc block 0 (TC0-2)
ptc->TC_BCR = 0 ; // No sync
ptc->TC_BMR = 0 ;
ptc->TC_CHANNEL[2].TC_CMR = 0x00008000 ; // Waveform mode
ptc->TC_CHANNEL[2].TC_RC = timer ; // 10 Hz
ptc->TC_CHANNEL[2].TC_RA = timer >> 1 ;
ptc->TC_CHANNEL[2].TC_CMR = 0x0009C003 ; // 0000 0000 0000 1001 1100 0000 0000 0011
// MCK/128, set @ RA, Clear @ RC waveform
ptc->TC_CHANNEL[2].TC_CCR = 5 ; // Enable clock and trigger it (may only need trigger)
NVIC_EnableIRQ(TC2_IRQn) ;
TC0->TC_CHANNEL[2].TC_IER = TC_IER0_CPCS ;
}
extern "C" void TC2_IRQHandler()
{
register uint32_t dummy;
/* Clear status bit to acknowledge interrupt */
dummy = TC0->TC_CHANNEL[2].TC_SR;
(void) dummy ; // Discard value - prevents compiler warning
interrupt10ms() ;
}
#endif
#if ( defined(PCBX9D) || defined(PCB9XT) || defined(PCBX12D) ) || defined(PCBX10)
void init10msTimer()
{
// Timer14
RCC->APB1ENR |= RCC_APB1ENR_TIM14EN ; // Enable clock
TIM14->ARR = 9999 ; // 10mS
TIM14->PSC = (Peri1_frequency*Timer_mult1) / 1000000 - 1 ; // 1uS from 12MHz
TIM14->CCER = 0 ;
TIM14->CCMR1 = 0 ;
TIM14->EGR = 0 ;
TIM14->CR1 = 5 ;
TIM14->DIER |= 1 ;
NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn) ;
}
extern "C" void TIM8_TRG_COM_TIM14_IRQHandler()
{
TIM14->SR &= ~TIM_SR_UIF ;
interrupt10ms() ;
}
void init_hw_timer()
{
// Timer13
RCC->APB1ENR |= RCC_APB1ENR_TIM13EN ; // Enable clock
TIM13->ARR = 65535 ;
TIM13->PSC = (Peri1_frequency*Timer_mult1) / 10000000 - 1 ; // 0.1uS from 12MHz
TIM13->CCER = 0 ;
TIM13->CCMR1 = 0 ;
TIM13->EGR = 0 ;
TIM13->CR1 = 1 ;
}
// delay in units of 0.1 uS up to 6.5535 mS
void hw_delay( uint16_t time )
{
TIM13->CNT = 0 ;
TIM13->EGR = 1 ; // Re-start counter
while ( TIM13->CNT < time )
{
// wait
}
}
//After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
//Flash memory against possible unwanted operations due, for example, to electric
//disturbances. The following sequence is used to unlock this register:
//1. Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
//2. Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)
//Any wrong sequence will return a bus error and lock up the FLASH_CR register until the
//next reset.
//The FLASH_CR register can be locked again by software by setting the LOCK bit in the
//FLASH_CR register.
void unlockFlash()
{
FLASH->KEYR = 0x45670123 ;
FLASH->KEYR = 0xCDEF89AB ;
}
void waitFlashIdle()
{
while (FLASH->SR & FLASH_FLAG_BSY)
{
wdt_reset() ;
}
}
#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
void eraseSector( uint32_t sector )
{
waitFlashIdle() ;
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_PSIZE_WORD ;
FLASH->CR &= SECTOR_MASK;
FLASH->CR |= FLASH_CR_SER | (sector<<3) ;
FLASH->CR |= FLASH_CR_STRT;
/* Wait for operation to be completed */
waitFlashIdle() ;
/* if the erase operation is completed, disable the SER Bit */
FLASH->CR &= (~FLASH_CR_SER);
FLASH->CR &= SECTOR_MASK;
}
uint32_t program( uint32_t *address, uint32_t *buffer ) // size is 256 bytes
{
uint32_t i ;
#if defined(PCBX12D) || defined(PCBX10)
if ( (uint32_t) address == 0x08020000 )
#else
if ( (uint32_t) address == 0x08008000 )
#endif
{
if ( isFirmwareStart( buffer) )
{
FlashBlocked = 0 ;
}
else
{
FlashBlocked = 1 ;
}
}
if ( FlashBlocked )
{
return 1 ;
}
#if defined(PCBX12D) || defined(PCBX10)
if ( (uint32_t) address < 0x08020000 )
#else
if ( (uint32_t) address < 0x08008000 )
#endif
{
FlashBlocked = 1 ;
return 1 ;
}
#if defined(PCBX12D) || defined(PCBX10)
if ( (uint32_t) address == 0x08020000 )
{
eraseSector( 5 ) ;
}
if ( (uint32_t) address == 0x08040000 )
{
eraseSector( 6 ) ;
}
if ( (uint32_t) address == 0x08060000 )
{
eraseSector( 7 ) ;
}
if ( (uint32_t) address == 0x08080000 )
{
eraseSector( 8 ) ;
}
if ( (uint32_t) address == 0x080A0000 )
{
eraseSector( 9 ) ;
}
if ( (uint32_t) address == 0x080C0000 )
{
eraseSector( 10 ) ;
}
if ( (uint32_t) address == 0x080E0000 )
{
eraseSector( 11 ) ;
}
if ( (uint32_t) address == 0x08100000 )
{
eraseSector( 16 ) ;
}
if ( (uint32_t) address == 0x08104000 )
{
eraseSector( 17 ) ;
}
if ( (uint32_t) address == 0x08108000 )
{
eraseSector( 18 ) ;
}
if ( (uint32_t) address == 0x0810C000 )
{
eraseSector( 19 ) ;
}
if ( (uint32_t) address == 0x08110000 )
{
eraseSector( 20 ) ;
}
if ( (uint32_t) address == 0x08120000 )
{
eraseSector( 21 ) ;
}
if ( (uint32_t) address == 0x08140000 )
{
eraseSector( 22 ) ;
}
if ( (uint32_t) address == 0x08160000 )
{
eraseSector( 23 ) ;
}
if ( (uint32_t) address == 0x08180000 )
{
eraseSector( 24 ) ;
}
if ( (uint32_t) address == 0x081A0000 )
{
eraseSector( 25 ) ;
}
if ( (uint32_t) address == 0x081C0000 )
{
eraseSector( 26 ) ;
}
if ( (uint32_t) address == 0x081E0000 )
{
eraseSector( 27 ) ;
}
#else
if ( (uint32_t) address == 0x08008000 )
{
eraseSector( 2 ) ;
}
if ( (uint32_t) address == 0x0800C000 )
{
eraseSector( 3 ) ;
}
if ( (uint32_t) address == 0x08010000 )
{
eraseSector( 4 ) ;
}
if ( (uint32_t) address == 0x08020000 )
{
eraseSector( 5 ) ;
}
if ( (uint32_t) address == 0x08040000 )
{
eraseSector( 6 ) ;
}
if ( (uint32_t) address == 0x08060000 )
{
eraseSector( 7 ) ;
}
if ( (uint32_t) address == 0x08080000 )
{
eraseSector( 8 ) ;
}
if ( (uint32_t) address == 0x080A0000 )
{
eraseSector( 9 ) ;
}
if ( (uint32_t) address == 0x080C0000 )
{
eraseSector( 10 ) ;
}
if ( (uint32_t) address == 0x080E0000 )
{
eraseSector( 11 ) ;
}
#endif
// Now program the 256 bytes
for (i = 0 ; i < 64 ; i += 1 )
{
/* Device voltage range supposed to be [2.7V to 3.6V], the operation will
be done by word */
// Wait for last operation to be completed
waitFlashIdle() ;
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_PSIZE_WORD;
FLASH->CR |= FLASH_CR_PG;
*address = *buffer ;
/* Wait for operation to be completed */
waitFlashIdle() ;
FLASH->CR &= (~FLASH_CR_PG);
/* Check the written value */
if ( *address != *buffer )
{
/* Flash content doesn't match SRAM content */
return 2 ;
}
/* Increment FLASH destination address */
address += 1 ;
buffer += 1 ;
}
return 0 ;
}
#endif
uint8_t *cpystr( uint8_t *dest, uint8_t *source )
{
while ( (*dest++ = *source++) )
;
return dest - 1 ;
}
FRESULT readBinDir( DIR *dj, FILINFO *fno )
{
FRESULT fr ;
uint32_t loop ;
do
{
loop = 0 ;
fr = f_readdir ( dj, fno ) ; // First entry
if ( fr != FR_OK || fno->fname[0] == 0 )
{
break ;
}
if ( *fno->lfname == 0 )
{
cpystr( (uint8_t *)fno->lfname, (uint8_t *)fno->fname ) ; // Copy 8.3 name
}
int32_t len = strlen(fno->lfname) - 4 ;
if ( len < 0 )
{
loop = 1 ;
}
if ( fno->lfname[len] != '.' )
{
loop = 1 ;
}
if ( ( fno->lfname[len+1] & ~0x20 ) != FIleExtension[0] )
{
loop = 1 ;
}
if ( ( fno->lfname[len+2] & ~0x20 ) != FIleExtension[1] )
{
loop = 1 ;
}
if ( ( fno->lfname[len+3] & ~0x20 ) != FIleExtension[2] )
{
loop = 1 ;
}
} while ( loop ) ;
return fr ;
}
uint32_t fillNames( uint32_t index )
{
uint32_t i ;
FRESULT fr ;
Finfo.lfname = Filenames[0] ;
Finfo.lfsize = 48 ;
fr = f_readdir ( &Dj, 0 ) ; // rewind
fr = f_readdir ( &Dj, &Finfo ) ; // Skip .
fr = f_readdir ( &Dj, &Finfo ) ; // Skip ..
i = 0 ;
while ( i <= index )
{
fr = readBinDir( &Dj, &Finfo ) ; // First entry
FileSize[0] = Finfo.fsize ;
i += 1 ;
if ( fr == FR_NO_FILE)
{
return 0 ;
}
}
for ( i = 1 ; i < 7 ; i += 1 )
{
Finfo.lfname = Filenames[i] ;
fr = readBinDir( &Dj, &Finfo ) ; // First entry
FileSize[i] = Finfo.fsize ;
if ( fr != FR_OK || Finfo.fname[0] == 0 )
{
break ;
}
}
return i ;
}
FRESULT openFirmwareFile( uint32_t index )
{
cpystr( cpystr( (uint8_t *)FlashFilename, (uint8_t *)"\\firmware\\" ), (uint8_t *)Filenames[index] ) ;