diff --git a/targets/arm/mikroe/common/include/flatten_me.h b/targets/arm/mikroe/common/include/flatten_me.h new file mode 100644 index 0000000000..446641823e --- /dev/null +++ b/targets/arm/mikroe/common/include/flatten_me.h @@ -0,0 +1,71 @@ +/**************************************************************************** +** +** Copyright (C) MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file flatten_me.h + * @brief mikroSDK code flattener level selection. + */ + +#ifndef __FLATTEN_ME_H__ +#define __FLATTEN_ME_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Flattening levels. + * @ref FLATTEN_ME_LEVEL_NONE - no code flattening done. + * @ref FLATTEN_ME_LEVEL_LOW - flatten only HAL_LL APIs. + * @ref FLATTEN_ME_LEVEL_MID - flatten only HAL_LL and HAL APIs. + * @ref FLATTEN_ME_LEVEL_HIGH - flatten all layered APIs (HAL_LL, HAL and DRV). + */ +#define FLATTEN_ME_LEVEL_NONE (0) +#define FLATTEN_ME_LEVEL_LOW (1) +#define FLATTEN_ME_LEVEL_MID (2) +#define FLATTEN_ME_LEVEL_HIGH (3) + +// Flatten code or not? +#define FLATTEN_ME + +// Flatten level selection. +#define FLATTEN_ME_LEVEL FLATTEN_ME_LEVEL_HIGH + +#ifdef __cplusplus +} +#endif + +#endif // __FLATTEN_ME_H__ diff --git a/targets/arm/mikroe/common/include/mcu_definitions/TOSHIBA/TMPM4KNF10AFG/mcu_definitions.h b/targets/arm/mikroe/common/include/mcu_definitions/TOSHIBA/TMPM4KNF10AFG/mcu_definitions.h index 466bece8b5..be0281f0a0 100644 --- a/targets/arm/mikroe/common/include/mcu_definitions/TOSHIBA/TMPM4KNF10AFG/mcu_definitions.h +++ b/targets/arm/mikroe/common/include/mcu_definitions/TOSHIBA/TMPM4KNF10AFG/mcu_definitions.h @@ -92,7 +92,67 @@ //EOF I2C //UART +/* ====== UART0 ====== */ +/* RX */ +#define UART0_RX_PC0_FR2 +#define UART0_RX_PC1_FR1 +#define UART0_RX_PN0_FR2 +#define UART0_RX_PN1_FR1 +/* TX */ +#define UART0_TX_PC1_FR2 +#define UART0_TX_PC0_FR1 +#define UART0_TX_PN1_FR2 +#define UART0_TX_PN0_FR1 +/* CTS */ +#define UART0_CTS_PD2_FR1 +#define UART0_CTS_PN2_FR1 +/* RTS */ +#define UART0_RTS_PD3_FR1 +#define UART0_RTS_PV1_FR1 +/* ====== UART1 ====== */ +/* RX */ +#define UART1_RX_PC4_FR2 +#define UART1_RX_PC5_FR1 +#define UART1_RX_PU5_FR2 +#define UART1_RX_PU6_FR1 +/* TX */ +#define UART1_TX_PC5_FR2 +#define UART1_TX_PC4_FR1 +#define UART1_TX_PU6_FR2 +#define UART1_TX_PU5_FR1 +/* CTS */ +#define UART1_CTS_PU4_FR1 +/* RTS */ +#define UART1_RTS_PU3_FR1 +/* ====== UART2 ====== */ +/* RX */ +#define UART2_RX_PF0_FR2 /* PF0 and PF1 are used for SWD by reset */ +#define UART2_RX_PF1_FR1 +#define UART2_RX_PU0_FR2 +#define UART2_RX_PU1_FR1 +/* TX */ +#define UART2_TX_PF1_FR2 +#define UART2_TX_PF0_FR1 +#define UART2_TX_PU1_FR2 +#define UART2_TX_PU0_FR1 +/* ====== UART3 ====== */ +/* RX */ +#define UART3_RX_PF3_FR2 +#define UART3_RX_PF4_FR1 +#define UART3_RX_PF6_FR2 +#define UART3_RX_PF7_FR1 +/* TX */ +#define UART3_TX_PF4_FR2 +#define UART3_TX_PF3_FR1 +#define UART3_TX_PF7_FR2 +#define UART3_TX_PF6_FR1 + #define UART_MODULE_COUNT 4 + +#define UART_MODULE_0 0 +#define UART_MODULE_1 1 +#define UART_MODULE_2 2 +#define UART_MODULE_3 3 //EOF UART //SPI @@ -269,6 +329,22 @@ //EOF GPIO //IVT_TABLE +#define UART0_RX_NVIC 60 /* INTSC0RX */ +#define UART0_TX_NVIC 61 /* INTSC0TX */ +#define UART0_ERR_NVIC 62 /* INTSC0ERR */ + +#define UART1_RX_NVIC 63 /* INTSC1RX */ +#define UART1_TX_NVIC 64 /* INTSC1TX */ +#define UART1_ERR_NVIC 65 /* INTSC1ERR */ + +#define UART2_RX_NVIC 66 /* INTSC2RX */ +#define UART2_TX_NVIC 67 /* INTSC2TX */ +#define UART2_ERR_NVIC 68 /* INTSC2ERR */ + +#define UART3_RX_NVIC 69 /* INTSC3RX */ +#define UART3_TX_NVIC 70 /* INTSC3TX */ +#define UART3_ERR_NVIC 71 /* INTSC3ERR */ + //EOF IVT_TABLE diff --git a/targets/arm/mikroe/core/include/hal_ll_core_defines.h b/targets/arm/mikroe/core/include/hal_ll_core_defines.h index 00d5143e14..8e540824b4 100644 --- a/targets/arm/mikroe/core/include/hal_ll_core_defines.h +++ b/targets/arm/mikroe/core/include/hal_ll_core_defines.h @@ -430,7 +430,7 @@ extern "C"{ #define NVIC_IPR ((NVIC_IPR_Type *) 0xE000E400UL) - #define hal_ll_core_irq(irq_val) (1 << (irq_val & HAL_LL_CORE_IRQ_MASK)) + #define hal_ll_core_irq(irq_val) (1 << irq_val) #define hal_ll_core_pri(irq_pri) (irq_pri << 4) #define HAL_LL_CORE_IRQ_MASK 0x1F @@ -457,6 +457,64 @@ extern "C"{ #define HAL_LL_CORE_NVIC_SCB_SHPR2 (( uint32_t * )0xE000ED1C) #define HAL_LL_CORE_NVIC_SCB_SHPR3 (( uint32_t * )0xE000ED20) #endif +#elif defined(toshiba) + #if defined(__cortex_m4__) + typedef enum + { + HAL_LL_IVT_PRIORITY_LEVEL_0 = 0, + HAL_LL_IVT_PRIORITY_LEVEL_1, + HAL_LL_IVT_PRIORITY_LEVEL_2, + HAL_LL_IVT_PRIORITY_LEVEL_3, + HAL_LL_IVT_PRIORITY_LEVEL_4, + HAL_LL_IVT_PRIORITY_LEVEL_5, + HAL_LL_IVT_PRIORITY_LEVEL_6, + HAL_LL_IVT_PRIORITY_LEVEL_7, + HAL_LL_IVT_PRIORITY_LEVEL_8, + HAL_LL_IVT_PRIORITY_LEVEL_9, + HAL_LL_IVT_PRIORITY_LEVEL_10, + HAL_LL_IVT_PRIORITY_LEVEL_11, + HAL_LL_IVT_PRIORITY_LEVEL_12, + HAL_LL_IVT_PRIORITY_LEVEL_13, + HAL_LL_IVT_PRIORITY_LEVEL_14, + HAL_LL_IVT_PRIORITY_LEVEL_15 + } hal_ll_core_irq_priority_levels; + + /* Eksterni NVIC indeks = IRQn - 16 */ + #define hal_ll_core_irq(irq_val) (( irq_val - 16 )) + + /* Maske i konstante */ + #define HAL_LL_CORE_IRQ_MASK 0x1F + #define HAL_LL_CORE_LOW_NIBBLE 0xFUL + #define HAL_LL_CORE_HIGH_NIBBLE 0xF0UL + #define HAL_LL_CORE_IVT_INT_MEM_MANAGE 4 + #define HAL_LL_CORE_IVT_INT_BUS_FAULT 5 + #define HAL_LL_CORE_IVT_INT_USAGE_FAULT 6 + #define HAL_LL_CORE_IVT_INT_SYS_TICK 15 + #define HAL_LL_CORE_IVT_TICKINT_BIT 1 + #define HAL_LL_CORE_IVT_MEMFAULTENA_BIT 16 + #define HAL_LL_CORE_IVT_BUSFAULTENA_BIT 17 + #define HAL_LL_CORE_IVT_USGFAULTENA_BIT 18 + + /* SCB / SysTick / NVIC (ARM standardna mapa registara) */ + #define HAL_LL_CORE_SCB_SHCRS (( uint32_t * )0xE000ED24) + #define HAL_LL_CORE_STK_CTRL (( uint32_t * )0xE000E010) + + #define HAL_LL_CORE_NVIC_ISER_0 (( uint32_t * )0xE000E100) + #define HAL_LL_CORE_NVIC_ISER_1 (( uint32_t * )0xE000E104) + #define HAL_LL_CORE_NVIC_ISER_2 (( uint32_t * )0xE000E108) + #define HAL_LL_CORE_NVIC_ISER_3 (( uint32_t * )0xE000E10C) + + #define HAL_LL_CORE_NVIC_ICER_0 (( uint32_t * )0xE000E180) + #define HAL_LL_CORE_NVIC_ICER_1 (( uint32_t * )0xE000E184) + #define HAL_LL_CORE_NVIC_ICER_2 (( uint32_t * )0xE000E188) + #define HAL_LL_CORE_NVIC_ICER_3 (( uint32_t * )0xE000E18C) + + #define HAL_LL_CORE_NVIC_IPR_0 (( uint32_t * )0xE000E400) /* IPR lutka (8b po IRQ, gornjih 4 bita efektivno) */ + + #define HAL_LL_CORE_NVIC_SCB_SHPR1 (( uint32_t * )0xE000ED18) + #define HAL_LL_CORE_NVIC_SCB_SHPR2 (( uint32_t * )0xE000ED1C) + #define HAL_LL_CORE_NVIC_SCB_SHPR3 (( uint32_t * )0xE000ED20) + #endif #endif #ifdef __cplusplus diff --git a/targets/arm/mikroe/core/src/toshiba/m4/hal_ll_core_port.c b/targets/arm/mikroe/core/src/toshiba/m4/hal_ll_core_port.c index 5aae06e490..f5f9daebae 100644 --- a/targets/arm/mikroe/core/src/toshiba/m4/hal_ll_core_port.c +++ b/targets/arm/mikroe/core/src/toshiba/m4/hal_ll_core_port.c @@ -48,15 +48,93 @@ void hal_ll_core_port_nvic_enable_irq( uint8_t IRQn ) { // TODO - Define function behaviour. + /* Sistemski izuzeci */ + switch ( IRQn ) + { + case HAL_LL_CORE_IVT_INT_MEM_MANAGE: + set_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_MEMFAULTENA_BIT ); + break; + case HAL_LL_CORE_IVT_INT_BUS_FAULT: + set_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_BUSFAULTENA_BIT ); + break; + case HAL_LL_CORE_IVT_INT_USAGE_FAULT: + set_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_USGFAULTENA_BIT ); + break; + case HAL_LL_CORE_IVT_INT_SYS_TICK: + set_reg_bit( HAL_LL_CORE_STK_CTRL, HAL_LL_CORE_IVT_TICKINT_BIT ); + break; + default: + break; + } + + uint32_t bank = (uint32_t)IRQn >> 5; // div 32 + uint32_t bit = (uint32_t)IRQn & 0x1Fu; //mod 32 + volatile uint32_t *reg; + + if (bank == 0u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_0; + else if (bank == 1u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_1; + else if (bank == 2u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_2; + else reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_3; + + *reg = (1u << bit); /* write-1-to-enable */ } void hal_ll_core_port_nvic_disable_irq( uint8_t IRQn ) { // TODO - Define function behaviour. + switch ( IRQn ) + { + case HAL_LL_CORE_IVT_INT_MEM_MANAGE: + clear_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_MEMFAULTENA_BIT ); + break; + case HAL_LL_CORE_IVT_INT_BUS_FAULT: + clear_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_BUSFAULTENA_BIT ); + break; + case HAL_LL_CORE_IVT_INT_USAGE_FAULT: + clear_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_USGFAULTENA_BIT ); + break; + case HAL_LL_CORE_IVT_INT_SYS_TICK: + clear_reg_bit( HAL_LL_CORE_STK_CTRL, HAL_LL_CORE_IVT_TICKINT_BIT ); + break; + default: + break; + } + + uint32_t bank = (uint32_t)IRQn >> 5; + uint32_t bit = (uint32_t)IRQn & 0x1Fu; + volatile uint32_t *reg; + + if (bank == 0u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_0; + else if (bank == 1u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_1; + else if (bank == 2u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_2; + else reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_3; + + *reg = (1u << bit); /* write-1-to-disable */ } void hal_ll_core_port_nvic_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority ) { // TODO - Define function behaviour. + uintptr_t *reg; + uint8_t tmp_shift; + + if ( IRQn > 15 ) + { + reg = HAL_LL_CORE_NVIC_IPR_0 + ( ( hal_ll_core_irq( IRQn ) ) >> 2 ); + tmp_shift = ( ( ( hal_ll_core_irq( IRQn ) ) % 4 ) << 3 ) + 4; + } else if ( ( IRQn > 3 ) & ( IRQn <= 15 ) ) { + reg = HAL_LL_CORE_NVIC_SCB_SHPR1 + ( IRQn / 4 ) - 1; + tmp_shift = ( ( IRQn % 4 ) << 3 ) + 4; + } else { + return; + } + + if ( IRQn_priority & HAL_LL_CORE_LOW_NIBBLE ) { + *reg &= ~( HAL_LL_CORE_LOW_NIBBLE << tmp_shift ); + *reg |= ( uint32_t )IRQn_priority << tmp_shift; + } else { + *reg &= ~( HAL_LL_CORE_LOW_NIBBLE << tmp_shift ); + *reg |= ( uint32_t )IRQn_priority << ( tmp_shift - 4 ); + } } // ------------------------------------------------------------------------- END diff --git a/targets/arm/mikroe/toshiba/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h b/targets/arm/mikroe/toshiba/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h index 7c3b3a60ae..74ad758157 100644 --- a/targets/arm/mikroe/toshiba/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h +++ b/targets/arm/mikroe/toshiba/include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h @@ -101,17 +101,20 @@ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_sck_map[] = { /*!< SPI MISO pins. */ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_miso_map[] = { #ifdef SPI_MODULE_0 - #ifdef SPI0_MISO_PA3_AF1 - {GPIO_PA3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1}, + #ifdef SPI0_MISO_PA2_AF1 + {GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1}, #endif - #ifdef SPI0_MISO_PC4_AF3 - {GPIO_PC4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3}, + #ifdef SPI0_MISO_PC3_AF3 + {GPIO_PC3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3}, #endif #endif #ifdef SPI_MODULE_1 #ifdef SPI1_MISO_PG4_AF1 {GPIO_PG4, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF1}, #endif + #ifdef SPI1_MISO_PV1_AF2 + {GPIO_PV1, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF2}, + #endif #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; @@ -119,20 +122,17 @@ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_miso_map[] = { /*!< SPI MOSI pins. */ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_mosi_map[] = { #ifdef SPI_MODULE_0 - #ifdef SPI0_MOSI_PA2_AF1 - {GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1}, + #ifdef SPI0_MOSI_PA3_AF1 + {GPIO_PA3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1}, #endif - #ifdef SPI0_MOSI_PC3_AF3 - {GPIO_PC3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3}, + #ifdef SPI0_MOSI_PC4_AF3 + {GPIO_PC4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3}, #endif #endif #ifdef SPI_MODULE_1 #ifdef SPI1_MOSI_PG5_AF1 {GPIO_PG5, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF1}, #endif - #ifdef SPI1_MOSI_PV1_AF2 - {GPIO_PV1, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF2}, - #endif #endif {HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC} }; diff --git a/targets/arm/mikroe/toshiba/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h b/targets/arm/mikroe/toshiba/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h index 369dbf260d..9d4e6fcbac 100644 --- a/targets/arm/mikroe/toshiba/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h +++ b/targets/arm/mikroe/toshiba/include/tim/hal_ll_tim_pin_map/implementation_1/hal_ll_tim_pin_map.h @@ -87,49 +87,105 @@ typedef struct { hal_ll_pin_name_t pin; hal_ll_base_addr_t base; uint8_t af; - hal_ll_tim_pin_type_t module_index; + hal_ll_pin_name_t module_index; hal_ll_tim_pin_type_t pin_type; } hal_ll_tim_pin_map_t; /*! chA (FR4) - { GPIO_PA4, HAL_LL_TIM0_BASE_ADDR, 4, 0, HAL_LL_TIM_PIN_B }, // PA4 -> chB (FR4) - { GPIO_PA3, HAL_LL_TIM0_BASE_ADDR, 5, 0, HAL_LL_TIM_PIN_C }, // PA3 -> chC (FR5) - + #ifdef TIM_MODULE_0 + #ifdef TIM0_CHA_PA3_FR4 + { GPIO_PA3, HAL_LL_TIM0_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM0_CHB_PA4_FR4 + { GPIO_PA4, HAL_LL_TIM0_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_PIN_B }, + #endif + #ifdef TIM0_CHC_PA3_FR5 + { GPIO_PA3, HAL_LL_TIM0_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_0), HAL_LL_TIM_PIN_C }, + #endif + #endif // ===== T32A1 ===== - { GPIO_PF4, HAL_LL_TIM1_BASE_ADDR, 4, 1, HAL_LL_TIM_PIN_A }, // PF4 -> chA (FR4) - { GPIO_PV0, HAL_LL_TIM1_BASE_ADDR, 4, 1, HAL_LL_TIM_PIN_B }, // PV0 -> chB (FR4) - { GPIO_PF4, HAL_LL_TIM1_BASE_ADDR, 5, 1, HAL_LL_TIM_PIN_C }, // PF4 -> chC (FR5) - + #ifdef TIM_MODULE_1 + #ifdef TIM1_CHA_PF4_FR4 + { GPIO_PF4, HAL_LL_TIM1_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM1_CHB_PV0_FR4 + { GPIO_PV0, HAL_LL_TIM1_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_PIN_B }, + #endif + #ifdef TIM1_CHC_PF4_FR5 + { GPIO_PF4, HAL_LL_TIM1_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_1), HAL_LL_TIM_PIN_C }, + #endif + #endif // ===== T32A2 ===== - { GPIO_PC1, HAL_LL_TIM2_BASE_ADDR, 5, 2, HAL_LL_TIM_PIN_A }, // PC1 -> chA (FR5) - { GPIO_PU2, HAL_LL_TIM2_BASE_ADDR, 4, 2, HAL_LL_TIM_PIN_A }, // PU2 -> chA (FR4) - { GPIO_PD1, HAL_LL_TIM2_BASE_ADDR, 4, 2, HAL_LL_TIM_PIN_B }, // PD1 -> chB (FR4) - { GPIO_PU4, HAL_LL_TIM2_BASE_ADDR, 4, 2, HAL_LL_TIM_PIN_B }, // PU4 -> chB (FR4) - { GPIO_PC1, HAL_LL_TIM2_BASE_ADDR, 6, 2, HAL_LL_TIM_PIN_C }, // PC1 -> chC (FR6) - { GPIO_PU2, HAL_LL_TIM2_BASE_ADDR, 5, 2, HAL_LL_TIM_PIN_C }, // PU2 -> chC (FR5) - + #ifdef TIM_MODULE_2 + #ifdef TIM2_CHA_PC1_FR5 + { GPIO_PC1, HAL_LL_TIM2_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM2_CHA_PU2_FR4 + { GPIO_PU2, HAL_LL_TIM2_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM2_CHB_PD1_FR4 + { GPIO_PD1, HAL_LL_TIM2_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_B }, + #endif + #ifdef TIM2_CHB_PU4_FR4 + { GPIO_PU4, HAL_LL_TIM2_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_B }, + #endif + #ifdef TIM2_CHC_PC1_FR6 + { GPIO_PC1, HAL_LL_TIM2_BASE_ADDR, 6, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_C }, + #endif + #ifdef TIM2_CHC_PU2_FR5 + { GPIO_PU2, HAL_LL_TIM2_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_2), HAL_LL_TIM_PIN_C }, + #endif + #endif // ===== T32A3 ===== - { GPIO_PC2, HAL_LL_TIM3_BASE_ADDR, 5, 3, HAL_LL_TIM_PIN_A }, // PC2 -> chA (FR5) - { GPIO_PE2, HAL_LL_TIM3_BASE_ADDR, 4, 3, HAL_LL_TIM_PIN_A }, // PE2 -> chA (FR4) - { GPIO_PC3, HAL_LL_TIM3_BASE_ADDR, 5, 3, HAL_LL_TIM_PIN_B }, // PC3 -> chB (FR5) - { GPIO_PE6, HAL_LL_TIM3_BASE_ADDR, 4, 3, HAL_LL_TIM_PIN_B }, // PE6 -> chB (FR4) - { GPIO_PC2, HAL_LL_TIM3_BASE_ADDR, 6, 3, HAL_LL_TIM_PIN_C }, // PC2 -> chC (FR6) - { GPIO_PE2, HAL_LL_TIM3_BASE_ADDR, 5, 3, HAL_LL_TIM_PIN_C }, // PE2 -> chC (FR5) - + #ifdef TIM_MODULE_3 + #ifdef TIM3_CHA_PC2_FR5 + { GPIO_PC2, HAL_LL_TIM3_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM3_CHA_PE2_FR4 + { GPIO_PE2, HAL_LL_TIM3_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM3_CHB_PC3_FR5 + { GPIO_PC3, HAL_LL_TIM3_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_PIN_B }, + #endif + #ifdef TIM3_CHB_PE6_FR4 + { GPIO_PE6, HAL_LL_TIM3_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_PIN_B }, + #endif + #ifdef TIM3_CHC_PC2_FR6 + { GPIO_PC2, HAL_LL_TIM3_BASE_ADDR, 6, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_PIN_C }, + #endif + #ifdef TIM3_CHC_PE2_FR5 + { GPIO_PE2, HAL_LL_TIM3_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_3), HAL_LL_TIM_PIN_C }, + #endif + #endif // ===== T32A4 ===== - { GPIO_PG2, HAL_LL_TIM4_BASE_ADDR, 4, 4, HAL_LL_TIM_PIN_A }, // PG2 -> chA (FR4) - { GPIO_PG3, HAL_LL_TIM4_BASE_ADDR, 4, 4, HAL_LL_TIM_PIN_B }, // PG3 -> chB (FR4) - { GPIO_PG2, HAL_LL_TIM4_BASE_ADDR, 5, 4, HAL_LL_TIM_PIN_C }, // PG2 -> chC (FR5) - + #ifdef TIM_MODULE_4 + #ifdef TIM4_CHA_PG2_FR4 + { GPIO_PG2, HAL_LL_TIM4_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM4_CHB_PG3_FR4 + { GPIO_PG3, HAL_LL_TIM4_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_PIN_B }, + #endif + #ifdef TIM4_CHC_PG2_FR5 + { GPIO_PG2, HAL_LL_TIM4_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_4), HAL_LL_TIM_PIN_C }, + #endif + #endif // ===== T32A5 ===== - { GPIO_PF1, HAL_LL_TIM5_BASE_ADDR, 4, 5, HAL_LL_TIM_PIN_A }, // PF1 -> chA (FR4) - { GPIO_PN1, HAL_LL_TIM5_BASE_ADDR, 4, 5, HAL_LL_TIM_PIN_A }, // PN1 -> chA (FR4) - { GPIO_PF1, HAL_LL_TIM5_BASE_ADDR, 5, 5, HAL_LL_TIM_PIN_C }, // PF1 -> chC (FR5) - { GPIO_PN1, HAL_LL_TIM5_BASE_ADDR, 5, 5, HAL_LL_TIM_PIN_C }, // PN1 -> chC (FR5) - + #ifdef TIM_MODULE_5 + #ifdef TIM5_CHA_PF1_FR4 + { GPIO_PF1, HAL_LL_TIM5_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM5_CHA_PN1_FR4 + { GPIO_PN1, HAL_LL_TIM5_BASE_ADDR, 4, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_PIN_A }, + #endif + #ifdef TIM5_CHC_PF1_FR5 + { GPIO_PF1, HAL_LL_TIM5_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_PIN_C }, + #endif + #ifdef TIM5_CHC_PN1_FR5 + { GPIO_PN1, HAL_LL_TIM5_BASE_ADDR, 5, hal_ll_tim_module_num(TIM_MODULE_5), HAL_LL_TIM_PIN_C }, + #endif + #endif { HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC, HAL_LL_PIN_NC } }; diff --git a/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart.h b/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart.h index c9e7cb1e93..048b78bc12 100644 --- a/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart.h +++ b/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart.h @@ -41,6 +41,8 @@ * @brief API for UART HAL LOW LEVEL layer. */ + + #ifndef _HAL_LL_UART_H_ #define _HAL_LL_UART_H_ @@ -50,6 +52,12 @@ extern "C"{ #endif +/* CGFSYSMENA bitovi za UART kanale (1 = supply, 0 = stop) */ +#define CGFSYSMENA_IPMENA_UART0_BIT 21 /* UART ch0, 1 po resetu */ +#define CGFSYSMENA_IPMENA_UART1_BIT 22 /* UART ch1, 0 po resetu */ +#define CGFSYSMENA_IPMENA_UART2_BIT 23 /* UART ch2, 0 po resetu */ +#define CGFSYSMENA_IPMENA_UART3_BIT 24 /* UART ch3, 0 po resetu */ + /** * @brief Interrupt request type enum. */ diff --git a/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h b/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h index 9bc5b7d6c5..2d38606a6a 100644 --- a/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h +++ b/targets/arm/mikroe/toshiba/include/uart/hal_ll_uart_pin_map/implementation_1/hal_ll_uart_pin_map.h @@ -41,74 +41,107 @@ * @brief UART HAL LOW LEVEL PIN MAPS. */ + #ifndef _HAL_LL_UART_PIN_MAP_H_ #define _HAL_LL_UART_PIN_MAP_H_ #ifdef __cplusplus -extern "C"{ +extern "C" { #endif #include "hal_ll_pin_names.h" -/*!< @brief Macro defining `weak` attribute */ + /*!< @brief Macro defining `weak` attribute */ #define __weak __attribute__((weak)) /*!< @brief Helper macro for getting adequate module index number */ -#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +//#define hal_ll_uart_module_num(_module_num) (_module_num - 1) +#define hal_ll_uart_module_num(_module_num) (_module_num ) + /*!< @brief UART module base addresses */ #ifdef UART_MODULE_0 -static const hal_ll_base_addr_t HAL_LL_UART0_BASE_ADDRESS = 0x40070000UL; + static const hal_ll_base_addr_t HAL_LL_UART0_BASE_ADDRESS = 0x400CE000UL; #endif #ifdef UART_MODULE_1 -static const hal_ll_base_addr_t HAL_LL_UART1_BASE_ADDRESS = 0x40070020UL; + static const hal_ll_base_addr_t HAL_LL_UART1_BASE_ADDRESS = 0x400CE400UL; #endif #ifdef UART_MODULE_2 -static const hal_ll_base_addr_t HAL_LL_UART2_BASE_ADDRESS = 0x40070040UL; + static const hal_ll_base_addr_t HAL_LL_UART2_BASE_ADDRESS = 0x400CE800UL; #endif #ifdef UART_MODULE_3 -static const hal_ll_base_addr_t HAL_LL_UART3_BASE_ADDRESS = 0x40070060UL; -#endif -#ifdef UART_MODULE_4 -static const hal_ll_base_addr_t HAL_LL_UART4_BASE_ADDRESS = 0x40070080UL; -#endif -#ifdef UART_MODULE_5 -static const hal_ll_base_addr_t HAL_LL_UART5_BASE_ADDRESS = 0x400700A0UL; -#endif -#ifdef UART_MODULE_6 -static const hal_ll_base_addr_t HAL_LL_UART6_BASE_ADDRESS = 0x400700C0UL; -#endif -#ifdef UART_MODULE_7 -static const hal_ll_base_addr_t HAL_LL_UART7_BASE_ADDRESS = 0x400700E0UL; -#endif -#ifdef UART_MODULE_8 -static const hal_ll_base_addr_t HAL_LL_UART8_BASE_ADDRESS = 0x40070100UL; -#endif -#ifdef UART_MODULE_9 -static const hal_ll_base_addr_t HAL_LL_UART9_BASE_ADDRESS = 0x40070120UL; + static const hal_ll_base_addr_t HAL_LL_UART3_BASE_ADDRESS = 0x400CEC00UL; #endif -/*!< @brief UART pin structure. */ -typedef struct { - uint8_t module_index; - hal_ll_pin_name_t pin; - hal_ll_base_addr_t base; - uint8_t af; -} hal_ll_uart_pin_map_t; + /*!< @brief UART pin structure. */ + typedef struct { + uint8_t module_index; + hal_ll_pin_name_t pin; + hal_ll_base_addr_t base; + uint8_t af; + } hal_ll_uart_pin_map_t; -/*!< UART TX Pins. */ -static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { - // TODO - Define pin mappings here! + /*!< UART TX Pins. */ + static const hal_ll_uart_pin_map_t hal_ll_uart_tx_map[] = { + // TODO - Define pin mappings here! + #ifdef UART_MODULE_0 + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 1 }, + #endif + #ifdef UART_MODULE_1 + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 1 }, + #endif + #ifdef UART_MODULE_2 + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 1 }, + #endif + #ifdef UART_MODULE_3 + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 1 }, + #endif - {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} -}; + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + }; -/*!< UART RX Pins. */ -static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { - // TODO - Define pin mappings here! + /*!< UART RX Pins. */ + static const hal_ll_uart_pin_map_t hal_ll_uart_rx_map[] = { + // TODO - Define pin mappings here! + #ifdef UART_MODULE_0 + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC0, HAL_LL_UART0_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PC1, HAL_LL_UART0_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN0, HAL_LL_UART0_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_0), GPIO_PN1, HAL_LL_UART0_BASE_ADDRESS, 1 }, + #endif + #ifdef UART_MODULE_1 + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC4, HAL_LL_UART1_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PC5, HAL_LL_UART1_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU5, HAL_LL_UART1_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_1), GPIO_PU6, HAL_LL_UART1_BASE_ADDRESS, 1 }, + #endif + #ifdef UART_MODULE_2 + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF0, HAL_LL_UART2_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PF1, HAL_LL_UART2_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU0, HAL_LL_UART2_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_2), GPIO_PU1, HAL_LL_UART2_BASE_ADDRESS, 1 }, + #endif + #ifdef UART_MODULE_3 + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF3, HAL_LL_UART3_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF4, HAL_LL_UART3_BASE_ADDRESS, 1 }, + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF6, HAL_LL_UART3_BASE_ADDRESS, 2 }, + { hal_ll_uart_module_num(UART_MODULE_3), GPIO_PF7, HAL_LL_UART3_BASE_ADDRESS, 1 }, + #endif - {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} -}; + {HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC} + }; #ifdef __cplusplus } diff --git a/targets/arm/mikroe/toshiba/src/adc/implementation_1/hal_ll_adc.c b/targets/arm/mikroe/toshiba/src/adc/implementation_1/hal_ll_adc.c index 3959fd4be6..b7bf2dcba2 100644 --- a/targets/arm/mikroe/toshiba/src/adc/implementation_1/hal_ll_adc.c +++ b/targets/arm/mikroe/toshiba/src/adc/implementation_1/hal_ll_adc.c @@ -70,18 +70,38 @@ #define HAL_LL_CG_ADCKEN1_BIT 17 #define HAL_LL_CG_ADCKEN2_BIT 18 #define HAL_LL_MOD0_DACON 0x01 +#define HAL_LL_MOD0_RCUT 0x02 #define HAL_LL_CR0_ADEN 0x80 #define HAL_LL_CR0_SGL 0x02 #define HAL_LL_ST_SNGF 0x04 #define HAL_LL_MOD1_CONVERSION_CFG 0x00306122 #define HAL_LL_MOD2_CONVERSION_CFG 0x00000000 #define HAL_LL_CLK_EXAZ0 0x00000008U -#define HAL_LL_EXAZSEL_MASK 0x0C +#define HAL_LL_EXAZSEL_MASK 0xffffffff #define HAL_LL_TSET_SW_SINGLE_MODE 0b10 #define HAL_LL_TSET_MODE_SHIFT 5 #define HAL_LL_ADC_CHANNEL_MASK 0x1F #define HAL_LL_ADC_RESULT_SHIFT 4 #define HAL_LL_ADC_RESULT_MASK 0x0FFF +#define NO_DMA_REQUEST 0x00000000 + +#define ADCLK_140_MHz 140000000 +#define ADCLK_110_MHz 110000000 +#define ADCLK_70_MHz 70000000 + + +#define MOD1_40MHZ 0x00306122u /* SCLK=40MHz, conv?0.96µs */ +#define MOD1_30MHZ 0x00308012u /* SCLK=30MHz, conv?0.91µs */ +#define MOD1_20MHZ 0x00104011u /* SCLK=20MHz, conv?1.09µs */ +#define MOD2_ALL 0x00000000u + +#define EXAZ_m1 0x0u +#define EXAZ_m2 0x1u +#define VADCLK_DIV4 0x0u +#define VADCLK_DIV8 0x1u + + + // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief Local handle list. */ @@ -393,7 +413,7 @@ hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) { // Get the channel number uint8_t channel = hal_ll_adc_hw_specifics_map_local->channel; - if ( 0xFF == channel ) { + if ( HAL_LL_ADC_CHANNEL_NC == channel ) { return HAL_LL_ADC_WRONG_CHANNEL; } @@ -401,21 +421,16 @@ hal_ll_err_t hal_ll_adc_read( handle_t *handle, uint16_t *readDatabuf ) { base->cr0 = HAL_LL_CR0_ADEN | HAL_LL_CR0_SGL; // Wait for conversion to start - while ( !( base->st & HAL_LL_ST_SNGF ) ); + while ( !( read_reg_bits( &base->st, HAL_LL_ST_SNGF ) ) ); - // Wait for conversion to complete - while ( ( base->st & HAL_LL_ST_SNGF ) ); - uint32_t result_reg = 0; - if ( HAL_LL_ADC_CHANNEL_2 == channel ) { // AINC02 - result_reg = base->reg[ 4 ]; - } else if ( HAL_LL_ADC_CHANNEL_3 == channel ) { // AINC03 - result_reg = base->reg[ 5 ]; - } else { - result_reg = base->reg[ 1 ]; - } + // Wait for conversion to complete + while ( ( read_reg_bits( &base->st, HAL_LL_ST_SNGF ) ) ); + + // since ADxTSET0 was used to configure AIN and single conversion in hw_init() => result is stored in ADxREG0 + uint32_t result_reg = read_reg( &base->reg[ 0 ] ); - // Extract 12-bit result + // Extract 12-bit result, toshiba adc is exclusively 12bit *readDatabuf = (uint16_t) ( ( result_reg >> HAL_LL_ADC_RESULT_SHIFT ) & HAL_LL_ADC_RESULT_MASK ); return HAL_LL_ADC_SUCCESS; @@ -505,7 +520,7 @@ static void hal_ll_adc_hw_init( hal_ll_adc_hw_specifics_map_t *map ) { uint8_t port = hal_ll_gpio_port_get_port_index( map->pin ); - set_reg_bit( &hal_ll_cg_reg->fsysmena, port ); // Enable clock for port J + set_reg_bit( &hal_ll_cg_reg->fsysmena, port ); // Enable port clock switch ( map->module_index ) { #ifdef ADC_MODULE_0 @@ -533,34 +548,62 @@ static void hal_ll_adc_hw_init( hal_ll_adc_hw_specifics_map_t *map ) { uint8_t ain_mask = map->channel; - // MOD0: Enable ADC (DACON=1), low-power off (RCUT=0) - base->mod0 = HAL_LL_MOD0_DACON; // DACON = 1 - - // Wait 3 �s after DACON=1 for stabilization - Delay_us( 3 ); - - // Configure CLK with proper values: VADCLK=000 (SCLK=ADCLK/4=40MHz), EXAZ0=0001 (~0.96�s) - base->clk = HAL_LL_CLK_EXAZ0; - base->mod1 = HAL_LL_MOD1_CONVERSION_CFG; // AD conversion time 0.96�s at SCLK=40MHz - base->mod2 = HAL_LL_MOD2_CONVERSION_CFG; - - // Clear EXAZSEL for channels to use EXAZ0 setting - base->exazsel &= ~HAL_LL_EXAZSEL_MASK; - - // TRGS=0b10 (SW single), ENINT=0, channel in bits 0-4 - uint32_t tset_value = ( HAL_LL_TSET_SW_SINGLE_MODE << HAL_LL_TSET_MODE_SHIFT ) - | ( ain_mask & HAL_LL_ADC_CHANNEL_MASK ); - - if ( HAL_LL_ADC_CHANNEL_2 == ain_mask ) { // AINC02 - base->tset[ 4 ] = tset_value; - } else if ( HAL_LL_ADC_CHANNEL_3 == ain_mask ) { // AINC03 - base->tset[ 5 ] = tset_value; + base->mod0 = HAL_LL_MOD0_DACON; // enable adc + base->mod0 &= ~HAL_LL_MOD0_RCUT; // normal operation (no lower power opeation) + + CG_ClocksTypeDef cg; + CG_GetClocksFrequency( &cg ); + uint32_t adclk_hz = cg.CG_FT0M_Frequency; + + uint32_t mod1, vadclk, exaz; + + // clear CRO, necessary for certain registers to be configured + clear_reg_bits( &base->cr0, HAL_LL_CR0_ADEN ); + + /* + * this is calculated based on a table 2.50 in product information page 71/108 + * ADCLK and SCLK combinations in the table provide conversion time around 1us + * SCLK must not be higher than 40MHZ => rferance manual page 31 + */ + if (adclk_hz >= ADCLK_140_MHz) { + /* use 160/40 MHz combination from table */ + vadclk = VADCLK_DIV4; + exaz = EXAZ_m2; + mod1 = MOD1_40MHZ; + } else if (adclk_hz >= ADCLK_110_MHz) { + /* use 120/30 MHz combination from table */ + vadclk = VADCLK_DIV4; + exaz = EXAZ_m1; + mod1 = MOD1_30MHZ; + } else if (adclk_hz >= ADCLK_70_MHz) { + /* use 80/20 MHz combination from table */ + vadclk = VADCLK_DIV4; + exaz = EXAZ_m1; + mod1 = MOD1_20MHZ; } else { - base->tset[ 1 ] = tset_value; + /* fallback, make sure SCLK is in allowed range */ + vadclk = VADCLK_DIV8; + exaz = EXAZ_m1; + mod1 = MOD1_20MHZ; } + // configuring these registers is allwoed only if CRO = 0 + write_reg( &base->mod1, mod1 ); + write_reg( &base->mod2, MOD2_ALL ); + base->clk = (vadclk << 0) | (exaz << 3) | (exaz << 8); + + // choose EXAZ0 as setting for AIN sampling time for all channels + clear_reg_bits( &base->exazsel, HAL_LL_EXAZSEL_MASK ); + + // set analog in pin and single conversion + uint32_t tset_value = ( HAL_LL_TSET_SW_SINGLE_MODE << HAL_LL_TSET_MODE_SHIFT ) + | ( ain_mask & HAL_LL_ADC_CHANNEL_MASK ); + + write_reg( &base->tset[0], tset_value ); + // Disable DMA requests - base->cr1 = 0x00000000; + write_reg( &base->cr1, NO_DMA_REQUEST ); + } static void hal_ll_adc_init( hal_ll_adc_hw_specifics_map_t *map ) { diff --git a/targets/arm/mikroe/toshiba/src/gpio/implementation_1/hal_ll_gpio_port.c b/targets/arm/mikroe/toshiba/src/gpio/implementation_1/hal_ll_gpio_port.c index fbce43befb..492cee115c 100644 --- a/targets/arm/mikroe/toshiba/src/gpio/implementation_1/hal_ll_gpio_port.c +++ b/targets/arm/mikroe/toshiba/src/gpio/implementation_1/hal_ll_gpio_port.c @@ -98,48 +98,78 @@ static const uint32_t hal_ll_gpio_port_base_arr[] = { #ifdef GPIO_PORTA_BASE GPIO_PORTA_BASE, +#else + 0, #endif #ifdef GPIO_PORTB_BASE GPIO_PORTB_BASE, +#else + 0, #endif #ifdef GPIO_PORTC_BASE GPIO_PORTC_BASE, +#else + 0, #endif #ifdef GPIO_PORTD_BASE GPIO_PORTD_BASE, +#else + 0, #endif #ifdef GPIO_PORTE_BASE GPIO_PORTE_BASE, +#else + 0, #endif #ifdef GPIO_PORTF_BASE GPIO_PORTF_BASE, +#else + 0, #endif #ifdef GPIO_PORTG_BASE GPIO_PORTG_BASE, +#else + 0, #endif #ifdef GPIO_PORTH_BASE GPIO_PORTH_BASE, +#else + 0, #endif #ifdef GPIO_PORTJ_BASE GPIO_PORTJ_BASE, +#else + 0, #endif #ifdef GPIO_PORTK_BASE GPIO_PORTK_BASE, +#else + 0, #endif #ifdef GPIO_PORTL_BASE GPIO_PORTL_BASE, +#else + 0, #endif #ifdef GPIO_PORTM_BASE GPIO_PORTM_BASE, +#else + 0, #endif #ifdef GPIO_PORTN_BASE GPIO_PORTN_BASE, +#else + 0, #endif #ifdef GPIO_PORTU_BASE GPIO_PORTU_BASE, +#else + 0, #endif #ifdef GPIO_PORTV_BASE - GPIO_PORTV_BASE + GPIO_PORTV_BASE, +#else + 0 #endif }; @@ -281,6 +311,12 @@ static void hal_ll_gpio_config( uint32_t *port, uint16_t pin_mask, uint32_t conf } return; // Exit early for flag-based configuration + }else if( config == GPIO_CFG_MODE_ANALOG_INPUT ){ + gpio_ptr->ie &= ~pin_mask; + gpio_ptr->cr &= ~pin_mask; + gpio_ptr->pdn &= ~pin_mask; + gpio_ptr->pup &= ~pin_mask; + gpio_ptr->od &= ~pin_mask; } } @@ -301,8 +337,6 @@ static void hal_ll_gpio_config_pin_alternate_enable( uint32_t module_pin, uint32 uint32_t mask = (uint32_t) ( 1 << pin_index ); - hal_ll_gpio_clock_enable( port_ptr ); - hal_ll_gpio_config( (uint32_t*)&port_ptr, mask, module_config ); // Clear all FR registers for this pin diff --git a/targets/arm/mikroe/toshiba/src/i2c/implementation_1/hal_ll_i2c_master.c b/targets/arm/mikroe/toshiba/src/i2c/implementation_1/hal_ll_i2c_master.c index 83ca0141be..a6560b8f97 100644 --- a/targets/arm/mikroe/toshiba/src/i2c/implementation_1/hal_ll_i2c_master.c +++ b/targets/arm/mikroe/toshiba/src/i2c/implementation_1/hal_ll_i2c_master.c @@ -64,7 +64,6 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define HAL_LL_I2C_MASTER_SPEED_100K (100000UL) #define HAL_LL_I2C_MASTER_SPEED_400K (400000UL) #define HAL_LL_I2C_MASTER_SPEED_1M (1000000UL) -#define HAL_LL_I2C_MASTER_SPEED_3M2 (3200000UL) #define HAL_LL_I2C_DEFAULT_PASS_COUNT (10000) @@ -76,10 +75,15 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define GPIO_CFG_I2C_SDA (GPIO_CFG_CR |\ GPIO_CFG_IE |\ GPIO_CFG_OD |\ - GPIO_CFG_PULL_UP) + GPIO_CFG_PULL_UP) -#define HAL_LL_CG_I2C0_BIT 25 -#define HAL_LL_CG_I2C1_BIT 26 + + +#define HAL_LL_CG_I2C0_BIT 25 +#define HAL_LL_CG_I2C1_BIT 26 +#define HAL_LL_I2C_CR1_ACK_BIT 4 +#define HAL_LL_I2C_OP_SREN_BIT 1 +#define HAL_LL_I2C_OP_MFACK_BIT 0 #define HAL_LL_I2C_CR1_BC_MASK 0xE0U #define HAL_LL_I2C_CR1_ACK_MASK 0x10U @@ -112,6 +116,10 @@ static volatile hal_ll_i2c_master_handle_register_t hal_ll_module_state[I2C_MODU #define HAL_LL_I2C_WRITE 0x00U #define HAL_LL_I2C_READ 0x01U +#define DUMMY_BYTE 0x00U + +#define UINT32_MAX 0xFFFFFFFFu + /*!< @brief I2C register structure */ typedef struct { uint32_t cr1; /* 0x0000 I2C control register 1 */ @@ -550,15 +558,15 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ // Wait for transmit end time_counter = map->timeout; - while ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_PIN_MASK ) { - if ( !time_counter-- ) { - hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; - return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + while ( read_reg_bits( &hal_ll_hw_reg->sr, HAL_LL_I2C_SR_PIN_MASK ) ) { + if ( !time_counter-- ) { + hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; + return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; + } } - } // Check for NACK - if ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_LRB_MASK ) { + if ( read_reg_bits( &hal_ll_hw_reg->sr, HAL_LL_I2C_SR_LRB_MASK ) ) { hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; return HAL_LL_I2C_MASTER_ERROR; } @@ -569,7 +577,7 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ // Wait for transmit end time_counter = map->timeout; - while ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_PIN_MASK ) { + while ( read_reg_bits( &hal_ll_hw_reg->sr, HAL_LL_I2C_SR_PIN_MASK ) ) { if ( !time_counter-- ) { hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; return HAL_LL_I2C_MASTER_TIMEOUT_WRITE; @@ -577,7 +585,7 @@ static hal_ll_err_t hal_ll_i2c_master_write_bare_metal( hal_ll_i2c_hw_specifics_ } // Check for NACK - if ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_LRB_MASK ) { + if ( read_reg_bits( &hal_ll_hw_reg->sr, HAL_LL_I2C_SR_LRB_MASK ) ) { hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; return HAL_LL_I2C_MASTER_ERROR; } @@ -603,7 +611,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m // For WRITE_THEN_READ mode, generate repeated start condition if ( mode == HAL_LL_I2C_MASTER_WRITE_THEN_READ ) { // Set repeated start request bit - hal_ll_hw_reg->op |= HAL_LL_I2C_OP_SREN_MASK; + set_reg_bit( &hal_ll_hw_reg->op, HAL_LL_I2C_OP_SREN_BIT ); // Send slave address + read bit hal_ll_hw_reg->dbr = (map->address << 1) | HAL_LL_I2C_READ; @@ -616,7 +624,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m // Wait for transmit end time_counter = map->timeout; - while ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_PIN_MASK ) { + while ( read_reg_bits( &hal_ll_hw_reg->sr, HAL_LL_I2C_SR_PIN_MASK ) ) { if ( !time_counter-- ) { hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; return HAL_LL_I2C_MASTER_TIMEOUT_READ; @@ -624,7 +632,7 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m } // Check for NACK - if ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_LRB_MASK ) { + if ( read_reg_bits( &hal_ll_hw_reg->sr, HAL_LL_I2C_SR_LRB_MASK ) ) { hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; return HAL_LL_I2C_MASTER_ERROR; } @@ -633,15 +641,15 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m for ( size_t i = 0; i < len_read_data; i++ ) { // If this is the last byte, announce NACK will be sent if ( i == len_read_data - 1 ) { - hal_ll_hw_reg->op |= HAL_LL_I2C_OP_MFACK_MASK; + set_reg_bit( &hal_ll_hw_reg->op, HAL_LL_I2C_OP_MFACK_BIT ); } // Start receive by writing dummy byte - hal_ll_hw_reg->dbr = 0x00U; + hal_ll_hw_reg->dbr = DUMMY_BYTE; // Wait for transmit end time_counter = map->timeout; - while ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_PIN_MASK ) { + while ( read_reg_bits( &hal_ll_hw_reg->sr, HAL_LL_I2C_SR_PIN_MASK ) ) { if ( !time_counter-- ) { hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; return HAL_LL_I2C_MASTER_TIMEOUT_READ; @@ -655,8 +663,8 @@ static hal_ll_err_t hal_ll_i2c_master_read_bare_metal( hal_ll_i2c_hw_specifics_m // Generate STOP condition hal_ll_hw_reg->cr2 = HAL_LL_I2C_STOP_CONDITION_MASK; - // Clear MFACK and SREN bits - hal_ll_hw_reg->op &= ~(HAL_LL_I2C_OP_MFACK_MASK | HAL_LL_I2C_OP_SREN_MASK); + // Clear OP_MFACK, writing 0 to OP_SREN is invalid, RM page 40 + clear_reg_bit( &hal_ll_hw_reg->op, HAL_LL_I2C_OP_MFACK_BIT); return HAL_LL_I2C_MASTER_SUCCESS; } @@ -714,6 +722,8 @@ static uint32_t hal_ll_i2c_get_speed( uint32_t bit_rate ) { return HAL_LL_I2C_MASTER_SPEED_1M; } } + + } static hal_ll_i2c_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { @@ -784,8 +794,7 @@ static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); uint16_t time_counter = map->timeout; - // Wait for bus to be free (BB = 0, meaning SCL = 1 & SDA = 1) - while ( hal_ll_hw_reg->sr & HAL_LL_I2C_SR_BB_MASK ) { + while ( read_reg_bits(&hal_ll_hw_reg->sr, HAL_LL_I2C_SR_BB_MASK ) ) { if ( !time_counter-- ) { return HAL_LL_I2C_MASTER_TIMEOUT_WAIT_IDLE; } @@ -797,11 +806,55 @@ static hal_ll_err_t hal_ll_i2c_master_wait_for_idle( hal_ll_i2c_hw_specifics_map static void hal_ll_i2c_calculate_speed( hal_ll_i2c_hw_specifics_map_t *map ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); - // Set default prescaler and SCK values for I2C speed configuration - // Set PRS = 2 (divide by 1) and SCK = 6 - hal_ll_hw_reg->prs = HAL_LL_I2C_PRESCALER_CFG; - hal_ll_hw_reg->cr1 = (hal_ll_hw_reg->cr1 & ~HAL_LL_I2C_CR1_SCK_MASK) | HAL_LL_I2C_CR1_SCK_CFG; -} + /* + * REG_PRS: [I2CxPRS] - preskaler p (1..32) + * REG_CR1: [I2CxCR1] - divisor n (0..7) + * Formula (DNF, NFSEL=0): fSCL = fsys / ( p * ( 2^(n+2) + 16 ) ) + */ + + // choose fsys from CG ( I2C is on FSYSM domain ) + CG_ClocksTypeDef cg; + CG_GetClocksFrequency(&cg); + uint32_t fsys_hz = cg.CG_FSYSM_Frequency; + + // default spped + uint32_t target = map->speed ? map->speed : HAL_LL_I2C_MASTER_SPEED_100K; + + uint32_t best_p = 1, best_n = 0; + uint32_t best_diff = UINT32_MAX; + uint32_t best_f = 0; + + // find the best combination (p,n) for a desired speed + for (uint32_t p = 1; p <= 32; p++) { + for (uint32_t n = 0; n <= 7; n++) { + uint32_t denom = p * (((uint32_t)1U << (n + 2U)) + 16U); + + uint32_t f = fsys_hz / denom; + uint32_t diff = (f > target) ? (f - target) : (target - f); + + if( (diff < best_diff) || ((diff == best_diff) && (f > best_f)) ){ + best_diff = diff; + best_p = p; + best_n = n; + best_f = f; + } + } + } + + // write (p,n) to PRSCK and SCK + uint32_t prs = hal_ll_hw_reg->prs; + prs &= ~HAL_LL_I2C_PRS_PRSCK_MASK; + prs |= (best_p & 0x1FU); + hal_ll_hw_reg->prs = prs; + + uint32_t cr1 = hal_ll_hw_reg->cr1; + cr1 &= ~HAL_LL_I2C_CR1_SCK_MASK; + cr1 |= (best_n & 0x07U); + hal_ll_hw_reg->cr1 = cr1; + + // updated the speed + map->speed = best_f; + } static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { hal_ll_i2c_base_handle_t *hal_ll_hw_reg = hal_ll_i2c_get_base_struct( map->base ); @@ -828,17 +881,18 @@ static void hal_ll_i2c_hw_init( hal_ll_i2c_hw_specifics_map_t *map ) { } /* I2C bus enable */ + // since cr2 is a WRITE ONLY register(RM page 36) ,functions from hal_ll_bit_control.h cannot be used. hal_ll_hw_reg->cr2 = HAL_LL_I2C_I2CM_SET_MASK; - /* ACK enable + 8-bit transfer length */ - hal_ll_hw_reg->cr1 |= HAL_LL_I2C_CR1_ACK_MASK; - hal_ll_hw_reg->cr1 &= ~HAL_LL_I2C_CR1_BC_MASK; + // ACK enable + 8-bit transfer length + set_reg_bit(&hal_ll_hw_reg->cr1, HAL_LL_I2C_CR1_ACK_BIT); + clear_reg_bits(&hal_ll_hw_reg->cr1, HAL_LL_I2C_CR1_BC_MASK); - /* Master/Transmitter default */ + // Master/Transmitter default hal_ll_hw_reg->cr2 = HAL_LL_I2C_MASTER_TRANSMITTER; - /* clear interrupt enable register - DMA not used */ - hal_ll_hw_reg->ie = 0; + // clear interrupt enable register - DMA not used + clear_reg(&hal_ll_hw_reg->ie); } static void hal_ll_i2c_init( hal_ll_i2c_hw_specifics_map_t *map ) { diff --git a/targets/arm/mikroe/toshiba/src/spi_master/implementation_1/hal_ll_spi_master.c b/targets/arm/mikroe/toshiba/src/spi_master/implementation_1/hal_ll_spi_master.c index 5c108d693f..adc215c4b2 100644 --- a/targets/arm/mikroe/toshiba/src/spi_master/implementation_1/hal_ll_spi_master.c +++ b/targets/arm/mikroe/toshiba/src/spi_master/implementation_1/hal_ll_spi_master.c @@ -81,11 +81,11 @@ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MOD #define HAL_LL_SPI_CR_ENABLE_BIT 0 // SPI GPIO configuration macros -#define GPIO_CFG_SPI_SCK ( GPIO_CFG_PORT_DIRECTION_OUTPUT | GPIO_CFG_PULL_UP ) +#define GPIO_CFG_SPI_SCK ( GPIO_CFG_PORT_DIRECTION_OUTPUT ) -#define GPIO_CFG_SPI_MISO ( GPIO_CFG_MODE_DIGITAL_INPUT ) +#define GPIO_CFG_SPI_MISO ( GPIO_CFG_MODE_DIGITAL_INPUT | GPIO_CFG_PULL_UP ) -#define GPIO_CFG_SPI_MOSI ( GPIO_CFG_PORT_DIRECTION_OUTPUT | GPIO_CFG_PULL_UP ) +#define GPIO_CFG_SPI_MOSI ( GPIO_CFG_PORT_DIRECTION_OUTPUT ) // CR0 register masks #define CR0_TSPIE_MASK 0x01 @@ -123,6 +123,8 @@ static volatile hal_ll_spi_master_handle_register_t hal_ll_module_state[ SPI_MOD #define CR0_TIDLE_POS 22 #define CR0_TIDLE_MASK 0x00C00000 +#define TSPI_MAX_SPEED 25000000UL + // Helper macros for frame count and TIDLE settings #define TSPI_CR1_FC_MSK 0xFF #define TSPI_CR1_FC( val ) ( ( (uint32_t) ( val ) << 0 ) & TSPI_CR1_FC_MSK ) @@ -584,137 +586,180 @@ static void hal_ll_spi_master_write_bare_metal( hal_ll_spi_master_base_handle_t if ( !write_data_buffer || !write_data_length ) { return; } + + // will be used for disposing of unwanted dr values static uint8_t clear_reg = 0; - while ( hal_ll_hw_reg->sr & SR_RLVL_MASK ) { + // flush rx fifo + while ( read_reg_bits( &hal_ll_hw_reg->sr, SR_RLVL_MASK ) ) { clear_reg = hal_ll_hw_reg->dr; } - + + // set frame count uint32_t reg = hal_ll_hw_reg->cr1 & ~TSPI_CR1_FC_MSK; reg |= TSPI_CR1_FC( write_data_length ); hal_ll_hw_reg->cr1 = reg; - + + /* + * since frame lenght is 8bits => TX FIFO has 8 stages ( RM 3.6.1.1 table 3.6) + * if write_data_length > 8, fully prefill the Tx FIFO and start the transfer + * before writing new data, make sure to clear recieved data to pervent RX FIFO getting blocked + */ if ( write_data_length > 8 ) { for ( size_t i = 0; i < 8; i++ ) { hal_ll_hw_reg->dr = write_data_buffer[i]; } - - hal_ll_hw_reg->cr1 |= CR1_TRXE_MASK; + + // start communication + set_reg_bits( &hal_ll_hw_reg->cr1, CR1_TRXE_MASK ); for ( size_t i = 8; i < write_data_length; i++ ) { - while ( ( ( hal_ll_hw_reg->sr & SR_TLVL_MASK ) >> 16 ) > 6 ) { + // shift by 16 since SR are bits 19:16 and wait untill there is a space in TX FIFO + // CR2 max value is 7 + while ( ( ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TLVL_MASK ) ) >> 16 ) > 6 ) { } - if (hal_ll_hw_reg->sr & SR_RLVL_MASK) { + if (read_reg_bits( &hal_ll_hw_reg->sr, SR_RLVL_MASK )) { clear_reg = hal_ll_hw_reg->dr; } hal_ll_hw_reg->dr = write_data_buffer[i]; } - } else { + } + // just prefill the TX FIFO with all the data from write_data_buffer and start transfer + else { for ( size_t i = 0; i < write_data_length; i++ ) { hal_ll_hw_reg->dr = write_data_buffer[i]; } - - hal_ll_hw_reg->cr1 |= CR1_TRXE_MASK; + + // start communication + set_reg_bits( &hal_ll_hw_reg->cr1, CR1_TRXE_MASK ); } - - while ( ( hal_ll_hw_reg->sr & SR_TFEMP_MASK ) == 0 ); - - hal_ll_hw_reg->cr1 &= ~CR1_TRXE_MASK; - - while ( hal_ll_hw_reg->sr & SR_TSPISUE_MASK ); + + // wait until TX FIFO becomes empty + while ( ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TFEMP_MASK ) ) == 0 ); + + //stop communication + clear_reg_bits( &hal_ll_hw_reg->cr1, CR1_TRXE_MASK ); + + // wait until modification is enabled again + while ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TSPISUE_MASK ) ); } static void hal_ll_spi_master_read_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *read_data_buffer, size_t read_data_length, uint8_t dummy_data ) { + + // will be used for disposing of unwanted dr values static uint8_t clear_reg = 0; if ( !read_data_buffer || !read_data_length ) { return; } - - while (hal_ll_hw_reg->sr & SR_RLVL_MASK) { + + // flush rx fifo + while (read_reg_bits( &hal_ll_hw_reg->sr, SR_RLVL_MASK )) { clear_reg = hal_ll_hw_reg->dr; } - + + // since its a fullduplex, data must also be sent(dummy data) and therefore frame conunt must be set uint32_t reg = hal_ll_hw_reg->cr1 & ~TSPI_CR1_FC_MSK; reg |= TSPI_CR1_FC( read_data_length ); hal_ll_hw_reg->cr1 = reg; - + + // prefill TX FIFO with dummy data, max 8 bytes for ( size_t i = 0; i < read_data_length && i < 8; i++ ) { hal_ll_hw_reg->dr = dummy_data; } - - hal_ll_hw_reg->cr1 |= CR1_TRXE_MASK; + + // start communication + set_reg_bits( &hal_ll_hw_reg->cr1, CR1_TRXE_MASK ); for ( size_t i = 0; i < read_data_length; i++ ) { - while ( ( hal_ll_hw_reg->sr & SR_RLVL_MASK ) == 0 ); + // wait until there is data in RX FIFO and read it + while ( ( read_reg_bits( &hal_ll_hw_reg->sr, SR_RLVL_MASK ) ) == 0 ); read_data_buffer[i] = hal_ll_hw_reg->dr; + // check if there is still data to be read if ( i + 8 < read_data_length ) { hal_ll_hw_reg->dr = dummy_data; } } - - hal_ll_hw_reg->cr1 &= ~CR1_TRXE_MASK; - - while ( hal_ll_hw_reg->sr & SR_TSPISUE_MASK ); + + //stop communication + clear_reg_bits( &hal_ll_hw_reg->cr1, CR1_TRXE_MASK ); + + // wait until modification is enabled again + while ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TSPISUE_MASK ) ); } static void hal_ll_spi_master_transfer_bare_metal( hal_ll_spi_master_base_handle_t *hal_ll_hw_reg, uint8_t *write_data_buffer, uint8_t *read_data_buffer, size_t data_length ) { + + // will be used for disposing of unwanted dr values static uint8_t clear_reg = 0; if ( !data_length ) { return; } - - while (hal_ll_hw_reg->sr & SR_RLVL_MASK) { + + // flush rx fifo + while ( read_reg_bits( &hal_ll_hw_reg->sr, SR_RLVL_MASK ) ) { clear_reg = hal_ll_hw_reg->dr; } - + + // set frame count uint32_t reg = hal_ll_hw_reg->cr1 & ~TSPI_CR1_FC_MSK; reg |= TSPI_CR1_FC( data_length ); hal_ll_hw_reg->cr1 = reg; - + + // calculate how many bytes TX FIFO will be prefilled with size_t initial_fill = ( data_length < 8 ) ? data_length : 8; + + // prefill TX FIFO with data from write_data_buffer or with 0x00 if write_data_buffer is NULL for ( size_t i = 0; i < initial_fill; i++ ) { uint8_t data = write_data_buffer ? write_data_buffer[i] : 0; hal_ll_hw_reg->dr = data; } - hal_ll_hw_reg->cr1 |= CR1_TRXE_MASK; - size_t tx_count = initial_fill; - size_t rx_count = 0; + size_t rx_count = 0; + + // start communication + set_reg_bits( &hal_ll_hw_reg->cr1, CR1_TRXE_MASK ); + // continue transfer until all data is received while ( rx_count < data_length ) { - while ( ( hal_ll_hw_reg->sr & SR_RLVL_MASK ) == 0 ); + + // wait until data is recieved in RX FIFO and read it + while ( ( read_reg_bits( &hal_ll_hw_reg->sr, SR_RLVL_MASK ) ) == 0 ); uint8_t received = hal_ll_hw_reg->dr; if ( read_data_buffer ) { read_data_buffer[rx_count] = received; } rx_count++; - - if ( tx_count < data_length && ( ( hal_ll_hw_reg->sr & SR_TLVL_MASK ) >> 16 ) <= 6 ) { + + // check if there is more data to be transfered and if there is an empty space in TX FIFO + if ( tx_count < data_length && ( ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TLVL_MASK ) ) >> 16 ) <= 6 ) { uint8_t data = write_data_buffer ? write_data_buffer[tx_count] : 0; hal_ll_hw_reg->dr = data; tx_count++; } } - - while ( ( hal_ll_hw_reg->sr & SR_TFEMP_MASK ) == 0 ) { - } - - hal_ll_hw_reg->cr1 &= ~CR1_TRXE_MASK; - - while ( hal_ll_hw_reg->sr & SR_TSPISUE_MASK ) { - } + + // wait until TX FIFO becomes empty + while ( ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TFEMP_MASK ) ) == 0 ); + + + //stop communication + clear_reg_bits( &hal_ll_hw_reg->cr1, CR1_TRXE_MASK ); + + // wait until modification is enabled again + while ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TSPISUE_MASK ) ); + } static hal_ll_pin_name_t hal_ll_spi_master_check_pins( hal_ll_pin_name_t sck_pin, @@ -847,7 +892,6 @@ static void hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_ #ifdef HAL_LL_CG_SPI0_BIT set_reg_bit( &hal_ll_cg_reg->fsysmena, HAL_LL_CG_SPI0_BIT ); // Enable clock for SPI0 module #endif - set_reg_bit( &hal_ll_hw_reg->cr0, HAL_LL_SPI_CR_ENABLE_BIT ); break; #endif #ifdef SPI_MODULE_1 @@ -855,7 +899,6 @@ static void hal_ll_spi_master_module_enable( hal_ll_spi_master_hw_specifics_map_ #ifdef HAL_LL_CG_SPI1_BIT set_reg_bit( &hal_ll_cg_reg->fsysmena, HAL_LL_CG_SPI1_BIT ); // Enable clock for SPI1 module #endif - set_reg_bit( &hal_ll_hw_reg->cr0, HAL_LL_SPI_CR_ENABLE_BIT ); break; #endif @@ -892,26 +935,52 @@ static void hal_ll_spi_master_set_bit_rate( hal_ll_spi_master_hw_specifics_map_t // Calculate baud rate setting based on desired speed // BR register formula: SPI_CLK = fsys / (2 * (BR + 1)) CG_ClocksTypeDef cg; - CG_GetClocksFrequency( &cg ); - - uint32_t desired_speed = map->speed; - uint32_t br_value; + CG_GetClocksFrequency(&cg); - if ( desired_speed == 0 ) { - desired_speed = HAL_LL_SPI_MASTER_SPEED_100K; - } + uint32_t f_phi_t0 = cg.CG_FT0M_Frequency; + uint32_t desired = map->speed ? map->speed : HAL_LL_SPI_MASTER_SPEED_100K; - br_value = ( cg.CG_FC_Frequency / ( 2 * desired_speed ) ) - 1; + // "When setting conditions, the transfer clock cannot exceed 25 MHz" -> RM page 23 + if (desired > TSPI_MAX_SPEED) desired = TSPI_MAX_SPEED; - if ( br_value > HAL_LL_SPI_MASTER_BR_REG_MAX_VALUE ) { - br_value = HAL_LL_SPI_MASTER_BR_REG_MAX_VALUE; + uint32_t best_brck = 0, best_brs = 0; + uint32_t best_err = 0xFFFFFFFFu; + + // prescaler x (BRCK): 1,2,4,...,512 and divisor N (BRS): 1..16 + const uint16_t brck_div_tbl[10] = {1,2,4,8,16,32,64,128,256,512}; + for (uint32_t i = 0; i < 10; i++) { + uint32_t x = brck_div_tbl[i]; + for (uint32_t N = 1; N <= 16; N++) { + uint32_t f = f_phi_t0 / (2u * x * N); + uint32_t err = (f > desired) ? (f - desired) : (desired - f); + if (err < best_err) { + best_err = err; + best_brck = i; + best_brs = (N == 16) ? 0 : N; // TSPIxBR : 0000 = 16 RM page 65 + } + } } - hal_ll_hw_reg->br = br_value; + // wait until modification is enabled again + while (hal_ll_hw_reg->sr & SR_TSPISUE_MASK); + + // create a bit field with calculate values + uint32_t br = ((best_brck & 0xFu) << 4) | (best_brs & 0xFu); + hal_ll_hw_reg->br = br; + + + // update the speed + uint32_t x = brck_div_tbl[best_brck]; + uint32_t N = (best_brs == 0) ? 16u : best_brs; + map->hw_actual_speed = f_phi_t0 / (2u * x * N); + + - map->hw_actual_speed = cg.CG_FC_Frequency / ( 2 * ( br_value + 1 ) ); } + +uint8_t SW_RESET_FLAG = 0; + static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map ) { hal_ll_spi_master_base_handle_t *hal_ll_hw_reg = (hal_ll_spi_master_base_handle_t *) map->base; hal_ll_cg_base_handle_t *hal_ll_cg_reg = (hal_ll_cg_base_handle_t *) HAL_LL_CG_BASE_ADDR; @@ -936,25 +1005,21 @@ static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map break; } - // Check if this is the init sequence by verifying module state - if ( !( hal_ll_hw_reg->cr0 & CR0_TSPIE_MASK ) ) { - // Module is not enabled, this is the init sequence - // Software reset sequence - this resets the SPI module - hal_ll_hw_reg->cr0 = CR0_SWRST10_MASK; - hal_ll_hw_reg->cr0 = CR0_SWRST01_MASK; - } else { - // Module already initialized, perform soft reset only if needed - if ( hal_ll_hw_reg->sr & SR_TSPISUE_MASK ) { - hal_ll_hw_reg->cr0 = CR0_SWRST10_MASK; - hal_ll_hw_reg->cr0 = CR0_SWRST01_MASK; - } - } - - hal_ll_hw_reg->cr0 |= CR0_TSPIE_MASK; - - while ( hal_ll_hw_reg->sr & SR_TSPISUE_MASK ); + // RM page 61 - Set CR0 = 1 (operation) then perform initialization and communications + set_reg_bits( &hal_ll_hw_reg->cr0, CR0_TSPIE_MASK ); - hal_ll_hw_reg->sectcr0 &= ~SECTCR0_SECT_MASK; + + // in case modification is not enbaled,enable it by doing a SW reset + if ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TSPISUE_MASK ) ) { + set_reg_bits( &hal_ll_hw_reg->cr0, CR0_SWRST10_MASK ); + set_reg_bits( &hal_ll_hw_reg->cr0, CR0_SWRST01_MASK ); + } + + // wait until modification is enabled + while ( read_reg_bits( &hal_ll_hw_reg->sr, SR_TSPISUE_MASK ) ); + + // choose frame mode + clear_reg_bits( &hal_ll_hw_reg->sectcr0, SECTCR0_SECT_MASK ); // Configure CR1: MASTER, SPI MODE, FULL DUPLEX, BURST FRAME transfer // Breaking down the bits: @@ -962,9 +1027,10 @@ static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map // - TSPIMS = 1 (SPI mode) // - TMMD = 01 (Full duplex) // - CSSEL = 01 (CS1) - // - FC = 5 (will be set dynamically during transfers) + // - FC will be set dynamically during transfers hal_ll_hw_reg->cr1 = HAL_LL_SPI_CR1_DEFAULT_CONFIG; - + + // set output value function control when TSPIxTXD idles to be low uint32_t reg = hal_ll_hw_reg->cr2 & ~CR0_TIDLE_MASK; reg |= TSPI_CR2_TIDLE( 2 ); hal_ll_hw_reg->cr2 = reg; @@ -1006,6 +1072,7 @@ static void hal_ll_spi_master_hw_init( hal_ll_spi_master_hw_specifics_map_t *map hal_ll_hw_reg->fmtr0 = fmtr0_val; } + static void hal_ll_spi_master_init( hal_ll_spi_master_hw_specifics_map_t *map ) { hal_ll_spi_master_module_enable( map, true ); diff --git a/targets/arm/mikroe/toshiba/src/tim/implementation_1/hal_ll_tim.c b/targets/arm/mikroe/toshiba/src/tim/implementation_1/hal_ll_tim.c index d4c6afe033..19b114fe00 100644 --- a/targets/arm/mikroe/toshiba/src/tim/implementation_1/hal_ll_tim.c +++ b/targets/arm/mikroe/toshiba/src/tim/implementation_1/hal_ll_tim.c @@ -155,6 +155,9 @@ static inline void hal_ll_cg_protect_close(void) { TSB_CG_PROTECT = HAL_LL_CG_PR #define T32A_RUN_RG0_EN HAL_LL_BIT(T32A_RUN_RG0_EN_POS) #define T32A_RUN_RG1_EN HAL_LL_BIT(T32A_RUN_RG1_EN_POS) +#define T32A_ENABLE_AND_START ( 0x00000003 ) +#define T32A_DISABLE_AND_STOP ( 0x00000004 ) + #define T32A_RUN_START_BOTH (T32A_RUN_RG0_EN | T32A_RUN_RG1_EN) #define T32A_RUN_STOP_ALL (0u) @@ -179,16 +182,22 @@ static inline void hal_ll_cg_protect_close(void) { TSB_CG_PROTECT = HAL_LL_CG_PR #define T32A_CR_PRESC_POS (CR_PRESCL_POS) #define T32A_CR_PRESC_MSK ( HAL_LL_MASK(3u, T32A_CR_PRESC_POS) ) #define T32A_CR_PRESC(V) ( (uint32_t)(V) << T32A_CR_PRESC_POS ) + +#define T32A_MOD32_mask (0x00000001 << 0) + + +#define UPDNC_mask (0x00000003 << 16) +#define PRSCLC_mask (0x00000007 << 28) +#define CLCK_mask (0x00000007 << 24) +#define RELDC_mask (0x00000007 << 8) +#define OCRC_mask (0x00000003 << 0) +#define OCRCMPC1_mask (0x00000003 << 2) +#define OCRCMPC0_mask (0x00000003 << 0) +#define RUNC_mask (0x00000001 << 0) +#define SFTSTAC_mask (0x00000001 << 1) +#define SFTSTPC_mask (0x00000001 << 2) -// typedef struct { -// uint32_t CG_FC_Frequency; -// uint32_t CG_FSYSH_Frequency; -// uint32_t CG_FSYSM_Frequency; -// uint32_t CG_FT0H_Frequency; -// uint32_t CG_FT0M_Frequency; -// } CG_ClocksTypeDef; - -// extern void CG_GetClocksFrequency(CG_ClocksTypeDef *CG_Clocks); + static inline uint32_t _tim_input_clk_hz(void) { CG_ClocksTypeDef clks; @@ -202,6 +211,9 @@ static inline uint32_t _tim_input_clk_hz(void) #define HAL_LL_TIM_OUTCR_CLEAR_RG0_SET_RG1 \ ( T32A_OUTCRx1_RG0(T32A_OUT_ACT_CLEAR) | T32A_OUTCRx1_RG1(T32A_OUT_ACT_SET) ) +#define HAL_LL_TIM_OUTCR_SET_RG0_CLEAR_RG1 \ + ( T32A_OUTCRx1_RG0(T32A_OUT_ACT_SET) | T32A_OUTCRx1_RG1(T32A_OUT_ACT_CLEAR) ) + // -------------------------------------------------------------- PRIVATE TYPES /*!< @brief TIM register structure. */ typedef struct @@ -212,59 +224,59 @@ typedef struct uint32_t _unused0[15]; /* 0x0004 - 0x003C : Reserved */ /* ==== Timer A Registers ==== */ - uint32_t runa; /* 0x0040 - Run Register A */ - uint32_t cra; /* 0x0044 - Counter Control Register A */ - uint32_t capcra; /* 0x0048 - Capture Control Register A */ - uint32_t outcra0; /* 0x004C - Output Control Register A0 */ - uint32_t outcra1; /* 0x0050 - Output Control Register A1 */ - uint32_t sta; /* 0x0054 - Status Register A */ - uint32_t ima; /* 0x0058 - Interrupt Mask Register A */ - uint32_t tmra; /* 0x005C - Counter Capture Register A */ - uint32_t relda; /* 0x0060 - Counter Reload Register A */ - uint32_t rga0; /* 0x0064 - Timer Register A0 */ - uint32_t rga1; /* 0x0068 - Timer Register A1 */ - uint32_t capa0; /* 0x006C - Capture Register A0 */ - uint32_t capa1; /* 0x0070 - Capture Register A1 */ - uint32_t dmaa; /* 0x0074 - DMA Request Enable Register A */ - uint32_t cpa0; /* 0x0078 - Compare Register A0 */ - uint32_t cpa1; /* 0x007C - Compare Register A1 */ + uint32_t runa; /* 0x0040 - Run Register A */ + uint32_t cra; /* 0x0044 - Counter Control Register A */ + uint32_t capcra; /* 0x0048 - Capture Control Register A */ + uint32_t outcra0; /* 0x004C - Output Control Register A0 */ + uint32_t outcra1; /* 0x0050 - Output Control Register A1 */ + uint32_t sta; /* 0x0054 - Status Register A */ + uint32_t ima; /* 0x0058 - Interrupt Mask Register A */ + uint32_t tmra; /* 0x005C - Counter Capture Register A */ + uint32_t relda; /* 0x0060 - Counter Reload Register A */ + uint32_t rga0; /* 0x0064 - Timer Register A0 */ + uint32_t rga1; /* 0x0068 - Timer Register A1 */ + uint32_t capa0; /* 0x006C - Capture Register A0 */ + uint32_t capa1; /* 0x0070 - Capture Register A1 */ + uint32_t dmaa; /* 0x0074 - DMA Request Enable Register A */ + uint32_t cpa0; /* 0x0078 - Compare Register A0 */ + uint32_t cpa1; /* 0x007C - Compare Register A1 */ /* ==== Timer B Registers ==== */ - uint32_t runb; /* 0x0080 - Run Register B */ - uint32_t crb; /* 0x0084 - Counter Control Register B */ - uint32_t capcrb; /* 0x0088 - Capture Control Register B */ - uint32_t outcrb0; /* 0x008C - Output Control Register B0 */ - uint32_t outcrb1; /* 0x0090 - Output Control Register B1 */ - uint32_t stb; /* 0x0094 - Status Register B */ - uint32_t imb; /* 0x0098 - Interrupt Mask Register B */ - uint32_t tmrb; /* 0x009C - Counter Capture Register B */ - uint32_t reldb; /* 0x00A0 - Counter Reload Register B */ - uint32_t rgb0; /* 0x00A4 - Timer Register B0 */ - uint32_t rgb1; /* 0x00A8 - Timer Register B1 */ - uint32_t capb0; /* 0x00AC - Capture Register B0 */ - uint32_t capb1; /* 0x00B0 - Capture Register B1 */ - uint32_t dmab; /* 0x00B4 - DMA Request Enable Register B */ - uint32_t cpb0; /* 0x00B8 - Compare Register B0 */ - uint32_t cpb1; /* 0x00BC - Compare Register B1 */ + uint32_t runb; /* 0x0080 - Run Register B */ + uint32_t crb; /* 0x0084 - Counter Control Register B */ + uint32_t capcrb; /* 0x0088 - Capture Control Register B */ + uint32_t outcrb0; /* 0x008C - Output Control Register B0 */ + uint32_t outcrb1; /* 0x0090 - Output Control Register B1 */ + uint32_t stb; /* 0x0094 - Status Register B */ + uint32_t imb; /* 0x0098 - Interrupt Mask Register B */ + uint32_t tmrb; /* 0x009C - Counter Capture Register B */ + uint32_t reldb; /* 0x00A0 - Counter Reload Register B */ + uint32_t rgb0; /* 0x00A4 - Timer Register B0 */ + uint32_t rgb1; /* 0x00A8 - Timer Register B1 */ + uint32_t capb0; /* 0x00AC - Capture Register B0 */ + uint32_t capb1; /* 0x00B0 - Capture Register B1 */ + uint32_t dmab; /* 0x00B4 - DMA Request Enable Register B */ + uint32_t cpb0; /* 0x00B8 - Compare Register B0 */ + uint32_t cpb1; /* 0x00BC - Compare Register B1 */ /* ==== Timer C Registers ==== */ - uint32_t runc; /* 0x00C0 - Run Register C */ - uint32_t crc; /* 0x00C4 - Counter Control Register C */ - uint32_t capcrc; /* 0x00C8 - Capture Control Register C */ - uint32_t outcrc0; /* 0x00CC - Output Control Register C0 */ - uint32_t outcrc1; /* 0x00D0 - Output Control Register C1 */ - uint32_t stc; /* 0x00D4 - Status Register C */ - uint32_t imc; /* 0x00D8 - Interrupt Mask Register C */ - uint32_t tmrc; /* 0x00DC - Counter Capture Register C */ - uint32_t reldc; /* 0x00E0 - Counter Reload Register C */ - uint32_t rgc0; /* 0x00E4 - Timer Register C0 */ - uint32_t rgc1; /* 0x00E8 - Timer Register C1 */ - uint32_t capc0; /* 0x00EC - Capture Register C0 */ - uint32_t capc1; /* 0x00F0 - Capture Register C1 */ - uint32_t dmac; /* 0x00F4 - DMA Request Enable Register C */ - uint32_t plscr; /* 0x00F8 - Pulse Count Control Register */ - uint32_t cpc0; /* 0x00FC - Compare Register C0 */ - uint32_t cpc1; /* 0x0100 - Compare Register C1 */ + uint32_t runc; /* 0x00C0 - Run Register C */ + uint32_t crc; /* 0x00C4 - Counter Control Register C */ + uint32_t capcrc; /* 0x00C8 - Capture Control Register C */ + uint32_t outcrc0; /* 0x00CC - Output Control Register C0 */ + uint32_t outcrc1; /* 0x00D0 - Output Control Register C1 */ + uint32_t stc; /* 0x00D4 - Status Register C */ + uint32_t imc; /* 0x00D8 - Interrupt Mask Register C */ + uint32_t tmrc; /* 0x00DC - Counter Capture Register C */ + uint32_t reldc; /* 0x00E0 - Counter Reload Register C */ + uint32_t rgc0; /* 0x00E4 - Timer Register C0 */ + uint32_t rgc1; /* 0x00E8 - Timer Register C1 */ + uint32_t capc0; /* 0x00EC - Capture Register C0 */ + uint32_t capc1; /* 0x00F0 - Capture Register C1 */ + uint32_t dmac; /* 0x00F4 - DMA Request Enable Register C */ + uint32_t plscr; /* 0x00F8 - Pulse Count Control Register */ + uint32_t cpc0; /* 0x00FC - Compare Register C0 */ + uint32_t cpc1; /* 0x0100 - Compare Register C1 */ } hal_ll_tim_base_handle_t; /*!< @brief TIM pin structure */ @@ -507,55 +519,99 @@ hal_ll_err_t hal_ll_tim_set_duty( handle_t *handle, float duty_ratio ) { low_level_handle = hal_ll_tim_get_handle; hal_ll_tim_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_tim_get_module_state_address); hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct(hal_ll_tim_hw_specifics_map_local->base); - hal_ll_tim_pin_type_t pin_type = hal_ll_tim_hw_specifics_map_local->config.pin_type; - if ( duty_ratio < HAL_LL_DUTY_RATIO_MIN ) duty_ratio = HAL_LL_DUTY_RATIO_MIN; - if ( duty_ratio > HAL_LL_DUTY_RATIO_MAX ) duty_ratio = HAL_LL_DUTY_RATIO_MAX ; - - uint32_t period = hal_ll_tim_hw_specifics_map_local->max_period; - if ( period == 0u ) { - switch (pin_type) { - case HAL_LL_TIM_PIN_A: - period = hal_ll_hw_reg->rga1; - break; - case HAL_LL_TIM_PIN_B: - period = hal_ll_hw_reg->rgb1; - break; -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - period = hal_ll_hw_reg->rgc1; - break; -#endif - default: return HAL_LL_TIM_WRONG_PIN; - } - if ( period == 0u ) period = 0xFFFFu; + // which channel is used A/B/C + hal_ll_tim_pin_type_t pin_type = hal_ll_tim_hw_specifics_map_local->config.pin_type; + + // Clamp duty_ratio between 0 and 1 + if (duty_ratio < HAL_LL_DUTY_RATIO_MIN) duty_ratio = HAL_LL_DUTY_RATIO_MIN; + if (duty_ratio > HAL_LL_DUTY_RATIO_MAX) duty_ratio = HAL_LL_DUTY_RATIO_MAX; + + // helper registers + struct tim_ch_regs_t{ + uint32_t *RUNx; + uint32_t *OUTCRx0; + uint32_t *OUTCRx1; + uint32_t *RGx0; + uint32_t *RGx1; + uint32_t *RELDx; + }ch; + + switch (pin_type) + { + case HAL_LL_TIM_PIN_A: + ch.RUNx = &hal_ll_hw_reg->runa; ch.OUTCRx0 = &hal_ll_hw_reg->outcra0; ch.OUTCRx1 = &hal_ll_hw_reg->outcra1; + ch.RGx0 = &hal_ll_hw_reg->rga0; ch.RGx1 = &hal_ll_hw_reg->rga1; ch.RELDx = &hal_ll_hw_reg->relda; + break; + case HAL_LL_TIM_PIN_B: + ch.RUNx = &hal_ll_hw_reg->runb; ch.OUTCRx0 = &hal_ll_hw_reg->outcrb0; ch.OUTCRx1 = &hal_ll_hw_reg->outcrb1; + ch.RGx0 = &hal_ll_hw_reg->rgb0; ch.RGx1 = &hal_ll_hw_reg->rgb1; ch.RELDx = &hal_ll_hw_reg->reldb; + break; + case HAL_LL_TIM_PIN_C: + ch.RUNx = &hal_ll_hw_reg->runc; ch.OUTCRx0 = &hal_ll_hw_reg->outcrc0; ch.OUTCRx1 = &hal_ll_hw_reg->outcrc1; + ch.RGx0 = &hal_ll_hw_reg->rgc0; ch.RGx1 = &hal_ll_hw_reg->rgc1; ch.RELDx = &hal_ll_hw_reg->reldc; + break; } - uint32_t top = period; - uint32_t compare; - if ( duty_ratio <= HAL_LL_DUTY_RATIO_MIN ) { - compare = 0u; - } else if ( duty_ratio >= HAL_LL_DUTY_RATIO_MAX ) { - compare = top; + uint32_t period = *ch.RGx1 - *ch.RELDx + 1; + if(period == 0) return HAL_LL_TIM_MODULE_ERROR; // Freq has not been set yet + + // RM page 56 => "Do not make any changes of [T32AxOUTCRC1] register while the [T32AxRUNC] = 1. " + const bool was_running = ((*ch.RUNx) & RUNC_mask) != 0; + if (was_running) { + *ch.RUNx |= SFTSTPC_mask; // stops counter + *ch.RUNx &= ~RUNC_mask; // disables the operation of timer + } + + + /* + * calculate high_ticks(must be rounded) + * period_ticks = RGx1 - RELDx + 1 + * duty = high_ticks / period_ticks + * high_ticks = duty * period_ticks + * RGx0 = RGx1 - high_ticks + 1 + */ + double ht = (double)period * (double)duty_ratio; + uint32_t high_ticks = (uint32_t)(ht + 0.5); + + if (high_ticks == 0u) { + // output should always be low => force it with OUTx0 + *ch.OUTCRx1 = 0u; // invalid capture/compare logic + uint32_t temp_reg = *ch.OUTCRx0 & ~OCRC_mask; + temp_reg |= (2 << 0 ); // 10b -> LOW + *ch.OUTCRx0 = temp_reg; // force out to be low + } else if (high_ticks >= period) { + // output should always be high => force it with OUTx0 + *ch.OUTCRx1 = 0u; + uint32_t temp_reg = *ch.OUTCRx0 & ~OCRC_mask; + temp_reg |= (1 << 0 ); // 01b -> HIGH + *ch.OUTCRx0 = temp_reg; //force out to be high } else { - compare = (uint32_t)((duty_ratio/HAL_LL_DUTY_RATIO_MAX) * (float)(top + HAL_LL_ONE_TICK ) + HAL_LL_ROUNDING_BIAS); - if (compare > 0u) compare--; + // calculate RGx0 based on the wanted duty_ratio + *ch.RGx0 = *ch.RGx1 - (high_ticks - 1u); + + // make sure output is low before the compare match + // uint32_t temp_reg = *ch.OUTCRx0 & ~OCRC_mask; + // temp_reg |= (2 << 0 ); // 10b -> LOW + // *ch.OUTCRx0 = temp_reg; // force out to be low + + // clear output when counter c1 + uint32_t temp_reg = *ch.OUTCRx1 & (~OCRCMPC1_mask); + temp_reg |= (2 << 2); + *ch.OUTCRx1 = temp_reg; + + //set output when counter reaches c0 + temp_reg = *ch.OUTCRx1 & (~OCRCMPC0_mask); + temp_reg |= (1 << 0); + *ch.OUTCRx1 = temp_reg; } - switch (pin_type) { - case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->rga0 = compare; - break; - case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->rgb0 = compare; - break; -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->rgc0 = compare; - break; -#endif - default: - return HAL_LL_TIM_WRONG_PIN; + + // load back the state that timer was in + if (was_running) { + *ch.RUNx |= RUNC_mask; + *ch.RUNx |= SFTSTAC_mask; } + return HAL_LL_TIM_SUCCESS; } @@ -570,13 +626,13 @@ hal_ll_err_t hal_ll_tim_start( handle_t *handle ) { switch ( pin_type ) { case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->runa = T32A_RUN_START_BOTH; + hal_ll_hw_reg->runa = T32A_ENABLE_AND_START; // enable operation for timer and start the conter break; case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->runb = T32A_RUN_START_BOTH; + hal_ll_hw_reg->runb = T32A_ENABLE_AND_START; break; case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->runc = T32A_RUN_START_BOTH; + hal_ll_hw_reg->runc = T32A_ENABLE_AND_START; break; default: return HAL_LL_TIM_WRONG_PIN; @@ -594,13 +650,13 @@ hal_ll_err_t hal_ll_tim_stop( handle_t *handle ) { switch ( hal_ll_tim_hw_specifics_map_local->config.pin_type ) { case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->runa = T32A_RUN_STOP_ALL; + hal_ll_hw_reg->runa = T32A_DISABLE_AND_STOP; // disable timer and stops the counter break; case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->runb = T32A_RUN_STOP_ALL; + hal_ll_hw_reg->runb = T32A_DISABLE_AND_STOP; break; case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->runc = T32A_RUN_STOP_ALL; + hal_ll_hw_reg->runc = T32A_DISABLE_AND_STOP; break; default: return HAL_LL_TIM_WRONG_PIN; @@ -707,10 +763,7 @@ static void hal_ll_tim_module_enable(hal_ll_tim_hw_specifics_map_t *map, bool ha default: break; } - (void)TSB_CG_FSYSMENA; - (void)TSB_CG_FSYSMENB; - - hal_ll_cg_protect_close(); + hal_ll_cg_protect_close(); } static uint32_t hal_ll_tim_clock_source() { @@ -740,92 +793,70 @@ static void hal_ll_tim_alternate_functions_set_state( hal_ll_tim_hw_specifics_ma static uint32_t hal_ll_tim_set_freq_bare_metal( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); - uint32_t tim_clk_hz = _tim_input_clk_hz(); -if ( tim_clk_hz == 0u ) { tim_clk_hz = HAL_LL_DEFAULT_TIM_CLK_HZ; } + uint32_t period; - uint32_t want_hz = map->freq_hz; - if ( 0u == want_hz ) { - want_hz = HAL_LL_DEFAULT_PWM_HZ; - } + CG_ClocksTypeDef cg; + CG_GetClocksFrequency(&cg); + uint32_t g_sysclk_hz = cg.CG_FT0M_Frequency; - static const struct { uint8_t prscl_bits; uint32_t div; } prs_tbl[] = { - { PRSCL_1_1, HAL_LL_DIV_1 }, - { PRSCL_1_2, HAL_LL_DIV_2 }, - { PRSCL_1_8, HAL_LL_DIV_8 }, - { PRSCL_1_32, HAL_LL_DIV_32 }, - { PRSCL_1_128, HAL_LL_DIV_128 }, - { PRSCL_1_256, HAL_LL_DIV_256 }, - { PRSCL_1_512, HAL_LL_DIV_512 }, - { PRSCL_1_1024, HAL_LL_DIV_1024 } - }; - - uint32_t top = 0; - uint8_t chosen_prs_bits = PRSCL_1_1; - uint32_t chosen_div = HAL_LL_DIV_1 ; - - for (size_t i = 0; i < sizeof(prs_tbl)/sizeof(prs_tbl[0]); ++i) { - uint32_t div = prs_tbl[i].div; - uint32_t ticks = (uint32_t)((tim_clk_hz + (want_hz/HAL_LL_ROUNDING_DIV)) / (want_hz * div)); - if (ticks >= HAL_LL_MIN_TICKS && T32A_COUNTER_RANGE <= 0x10000u) { - chosen_prs_bits = prs_tbl[i].prscl_bits; - chosen_div = div; - top = ticks - 1u; - break; - } + + // which channel is used A/B/C + hal_ll_tim_pin_type_t pin_type = map->config.pin_type; + + // helper registers + struct tim_ch_regs_t{ + uint32_t *RUNx; + uint32_t *OUTCRx0; + uint32_t *OUTCRx1; + uint32_t *RGx0; + uint32_t *RGx1; + uint32_t *RELDx; + }ch; + + switch (pin_type) + { + case HAL_LL_TIM_PIN_A: + ch.RUNx = &hal_ll_hw_reg->runa; ch.OUTCRx0 = &hal_ll_hw_reg->outcra0; ch.OUTCRx1 = &hal_ll_hw_reg->outcra1; + ch.RGx0 = &hal_ll_hw_reg->rga0; ch.RGx1 = &hal_ll_hw_reg->rga1; ch.RELDx = &hal_ll_hw_reg->relda; + break; + case HAL_LL_TIM_PIN_B: + ch.RUNx = &hal_ll_hw_reg->runb; ch.OUTCRx0 = &hal_ll_hw_reg->outcrb0; ch.OUTCRx1 = &hal_ll_hw_reg->outcrb1; + ch.RGx0 = &hal_ll_hw_reg->rgb0; ch.RGx1 = &hal_ll_hw_reg->rgb1; ch.RELDx = &hal_ll_hw_reg->reldb; + break; + case HAL_LL_TIM_PIN_C: + ch.RUNx = &hal_ll_hw_reg->runc; ch.OUTCRx0 = &hal_ll_hw_reg->outcrc0; ch.OUTCRx1 = &hal_ll_hw_reg->outcrc1; + ch.RGx0 = &hal_ll_hw_reg->rgc0; ch.RGx1 = &hal_ll_hw_reg->rgc1; ch.RELDx = &hal_ll_hw_reg->reldc; + break; } - if (top == 0u) { - chosen_prs_bits = PRSCL_1_1024; - chosen_div = HAL_LL_DIV_1024; - uint32_t ticks = (uint32_t)((tim_clk_hz + (want_hz/HAL_LL_ROUNDING_DIV)) / (want_hz * chosen_div)); - if (ticks < HAL_LL_MIN_TICKS) ticks = HAL_LL_MIN_TICKS; - if (ticks > T32A_COUNTER_RANGE) ticks = T32A_COUNTER_RANGE; - top = ticks - HAL_LL_ONE_TICK; + // RM page 56 => "Do not make any changes of [T32AxOUTCRC1] register while the [T32AxRUNC] = 1. " + const bool was_running = ((*ch.RUNx) & RUNC_mask) != 0; + if (was_running) { + *ch.RUNx |= SFTSTPC_mask; // stops counter + *ch.RUNx &= ~RUNC_mask; // disables the operation of timer } + + /* + * period_ticks = RGx1 - RELDx + 1 + * T_pwm = period_ticks * T_clk, Tclk = 1/g_sysclk_hz, T_pwm = 1/map->freq_hz + * 1/map->freq_hz = ( RGx1 - RELDx + 1 ) / g_sysclk_hz + * RGx1 = ( g_sysclk_hz/map->freq_hz ) + RELDx - 1 + */ + *ch.RGx1 = (g_sysclk_hz/map->freq_hz) - 1 + *ch.RELDx; + + + // load back the state that timer was in + if (was_running) { + *ch.RUNx |= RUNC_mask; + *ch.RUNx |= SFTSTAC_mask; + } + + // calculate period_ticks based on updated RGx1 + uint32_t period_ticks = g_sysclk_hz/map->freq_hz; -volatile uint32_t *cr_reg = NULL; - -switch ( map->config.pin_type ) { - case HAL_LL_TIM_PIN_A: - cr_reg = &hal_ll_hw_reg->cra; - break; - case HAL_LL_TIM_PIN_B: - cr_reg = &hal_ll_hw_reg->crb; - break; -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - cr_reg = &hal_ll_hw_reg->crc; - break; -#endif - default: - break; -} + return period_ticks; -if (cr_reg != NULL) { - *cr_reg = (*cr_reg & ~T32A_CR_PRESC_MSK) | T32A_CR_PRESC(chosen_prs_bits); -} - switch ( map->config.pin_type ) { - case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->relda = 0u; - hal_ll_hw_reg->rga1 = top; - if (hal_ll_hw_reg->rga0 > top) hal_ll_hw_reg->rga0 = top / HAL_LL_DIV_2; - break; - case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->reldb = 0u; - hal_ll_hw_reg->rgb1 = top; - if (hal_ll_hw_reg->rgb0 > top) hal_ll_hw_reg->rgb0 = top / HAL_LL_DIV_2; - break; -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->reldc = 0u; - hal_ll_hw_reg->rgc1 = top; - if (hal_ll_hw_reg->rgc0 > top) hal_ll_hw_reg->rgc0 = top / HAL_LL_DIV_2; - break; -#endif - default: break; - } - return top; } @@ -833,105 +864,56 @@ static uint32_t hal_ll_tim_hw_init( hal_ll_tim_hw_specifics_map_t *map ) { hal_ll_tim_base_handle_t *hal_ll_hw_reg = hal_ll_tim_get_base_struct( map->base ); hal_ll_tim_pin_type_t pin_type = map->config.pin_type; - switch ( pin_type ) { - case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->runa = T32A_RUN_STOP_ALL; - break; - case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->runb = T32A_RUN_STOP_ALL; - break; -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->runc = T32A_RUN_STOP_ALL; - break; -#endif - default: - return 0u; + // helper registers + struct tim_ch_regs_t{ + uint32_t *RUNx; + uint32_t *OUTCRx0; + uint32_t *OUTCRx1; + uint32_t *CRx; + uint32_t *RELDx; + uint32_t *RGx0; + }ch; + + switch (pin_type) + { + case HAL_LL_TIM_PIN_A: + ch.RUNx = &hal_ll_hw_reg->runa; ch.OUTCRx0 = &hal_ll_hw_reg->outcra0; ch.OUTCRx1 = &hal_ll_hw_reg->outcra1; + ch.CRx = &hal_ll_hw_reg->cra; ch.RELDx = &hal_ll_hw_reg->relda; ch.RGx0 = &hal_ll_hw_reg->rga0; + hal_ll_hw_reg->mod &= ~T32A_MOD32_mask; + break; + case HAL_LL_TIM_PIN_B: + ch.RUNx = &hal_ll_hw_reg->runb; ch.OUTCRx0 = &hal_ll_hw_reg->outcrb0; ch.OUTCRx1 = &hal_ll_hw_reg->outcrb1; + ch.CRx = &hal_ll_hw_reg->crb; ch.RELDx = &hal_ll_hw_reg->reldb; ch.RGx0 = &hal_ll_hw_reg->rgb0; + hal_ll_hw_reg->mod &= ~T32A_MOD32_mask; + break; + case HAL_LL_TIM_PIN_C: + ch.RUNx = &hal_ll_hw_reg->runc; ch.OUTCRx0 = &hal_ll_hw_reg->outcrc0; ch.OUTCRx1 = &hal_ll_hw_reg->outcrc1; + ch.CRx = &hal_ll_hw_reg->crc; ch.RELDx = &hal_ll_hw_reg->reldc; ch.RGx0 = &hal_ll_hw_reg->rgc0; + hal_ll_hw_reg->mod |= T32A_MOD32_mask; + break; } - const uint32_t clk = hal_ll_tim_clock_source(); - const uint32_t prscl = PRSCL_1_1; - - switch ( pin_type ) { - case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->cra = - ( RELD_MATCH_B1 << T32A_CR_RELD_POS ) | - ( UPDN_UP_COUNT << T32A_CR_UPDN_POS ) | - ( WBF_DIS << T32A_CR_WBF_POS ) | - ( clk << T32A_CR_CLK_POS ) | - ( prscl << T32A_CR_PRESC_POS ); - hal_ll_hw_reg->relda = 0u; - break; - - case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->crb = - ( RELD_MATCH_B1 << T32A_CR_RELD_POS ) | - ( UPDN_UP_COUNT << T32A_CR_UPDN_POS ) | - ( WBF_DIS << T32A_CR_WBF_POS ) | - ( clk << T32A_CR_CLK_POS ) | - ( prscl << T32A_CR_PRESC_POS ); - hal_ll_hw_reg->reldb = 0u; - break; - -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->crc = - ( RELD_MATCH_B1 << T32A_CR_RELD_POS ) | - ( UPDN_UP_COUNT << T32A_CR_UPDN_POS ) | - ( WBF_DIS << T32A_CR_WBF_POS ) | - ( clk << T32A_CR_CLK_POS ) | - ( prscl << T32A_CR_PRESC_POS ); - hal_ll_hw_reg->reldc = 0u; - break; -#endif - default: - return 0u; - } + const uint32_t clk = hal_ll_tim_clock_source(); - /* Clear on RGA0, Set on RGA1; status clear */ - switch ( pin_type ) { - case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->outcra0 = 0x00u; - hal_ll_hw_reg->outcra1 = HAL_LL_TIM_OUTCR_CLEAR_RG0_SET_RG1; /* Clear on RGA0, Set on RGA1 */ - hal_ll_hw_reg->sta = 0xFFu; /* clear status */ - break; + *ch.CRx = + ( RELD_MATCH_B1 << T32A_CR_RELD_POS ) | // reload when counter matches tiemr register C1 + ( UPDN_UP_COUNT << T32A_CR_UPDN_POS ) | // up counting + ( WBF_DIS << T32A_CR_WBF_POS ) | // disable double buffering + ( clk << T32A_CR_CLK_POS ) | // sets prescaler as a count clock + ( PRSCL_1_1 << T32A_CR_PRESC_POS ); // prescaler division ratio = 1/1 - case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->outcrb0 = 0x00u; - hal_ll_hw_reg->outcrb1 = HAL_LL_TIM_OUTCR_CLEAR_RG0_SET_RG1; /* Clear on RGB0, Set on RGB1 */ - hal_ll_hw_reg->stb = 0xFFu; /* clear status */ - break; + *ch.RELDx = 0u; // set default reload value to 0 -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->outcrc0 = 0x00u; - hal_ll_hw_reg->outcrc1 = HAL_LL_TIM_OUTCR_CLEAR_RG0_SET_RG1; /* Clear on RGC0, Set on RGC1 */ - hal_ll_hw_reg->stc = 0xFFu; /* clear status */ - break; -#endif + *ch.OUTCRx0 = 0x00u; // clear output + *ch.OUTCRx1 = HAL_LL_TIM_OUTCR_SET_RG0_CLEAR_RG1; // set on C0 clear on C1 - default: - return 0u; - } + uint32_t period = hal_ll_tim_set_freq_bare_metal( map ); - uint32_t top = hal_ll_tim_set_freq_bare_metal( map ); - if ( top == 0u ) { top = 0xFFFFu; } + // dividing with 0 protection + if ( period == 0u ) { period = 0xFFFFu; } - switch ( pin_type ) { - case HAL_LL_TIM_PIN_A: - hal_ll_hw_reg->rga0 = top / HAL_LL_DIV_2; - break; - case HAL_LL_TIM_PIN_B: - hal_ll_hw_reg->rgb0 = top / HAL_LL_DIV_2; - break; -#ifdef HAL_LL_TIM_PIN_C - case HAL_LL_TIM_PIN_C: - hal_ll_hw_reg->rgc0 = top / HAL_LL_DIV_2; - break; -#endif - default: return 0u; - } - return top; + return period; + } diff --git a/targets/arm/mikroe/toshiba/src/uart/implementation_1/hal_ll_uart.c b/targets/arm/mikroe/toshiba/src/uart/implementation_1/hal_ll_uart.c index 486aceacf6..e772782aa7 100644 --- a/targets/arm/mikroe/toshiba/src/uart/implementation_1/hal_ll_uart.c +++ b/targets/arm/mikroe/toshiba/src/uart/implementation_1/hal_ll_uart.c @@ -48,8 +48,11 @@ #include "hal_ll_core_defines.h" #include "hal_ll_uart_pin_map.h" -/*!< @brief Local handle list */ -static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_COUNT ] = { (handle_t *)NULL, (handle_t *)NULL, false }; +#include "hal_ll_core_defines.h" +#include "hal_ll_bit_control.h" + + /*!< @brief Local handle list */ +static volatile hal_ll_uart_handle_register_t hal_ll_module_state[UART_MODULE_COUNT] = { (handle_t*)NULL, (handle_t*)NULL, false }; // ------------------------------------------------------------- PRIVATE MACROS /*!< @brief Helper macro for getting hal_ll_module_state address. */ @@ -62,11 +65,138 @@ static volatile hal_ll_uart_handle_register_t hal_ll_module_state[ UART_MODULE_C #define hal_ll_uart_get_base_from_hal_handle ((hal_ll_uart_hw_specifics_map_t *)((hal_ll_uart_handle_register_t *)\ (((hal_ll_uart_handle_register_t *)(handle))->hal_ll_uart_handle))->hal_ll_uart_handle)->base -/*!< @brief UART HW register structure. */ + + +/*!< @brief Macros used for calculating actual baud rate value and error value */ +#define HAL_LL_UART_ACCEPTABLE_ERROR (float)1.0 +#define HAL_LL_UART_CLK (hal_ll_uart_get_clock_speed()) +#define hal_ll_uart_real_baud_rate(_N) ( (uint32_t)( (HAL_LL_UART_CLK) / (16UL * (uint32_t)(_N)) ) ) +#define hal_ll_baud_rate_register_divider(_baud) ( (uint16_t)( ((HAL_LL_UART_CLK) + (8UL*(uint32_t)(_baud))) / (16UL*(uint32_t)(_baud)) ) ) +#define hal_ll_uart_get_baud_error(_baud_real,_baud) (((float)(abs(_baud_real - _baud)) / _baud) * 100) + + +/*======================= BRD =============================*/ +#define UART_BRD_BRN_POS 0 +#define UART_BRD_BRN_MASK (0X0000FFFF << UART_BRD_BRN_POS) +#define UART_BRD_BRK_POS 16 +#define UART_BRD_BRK_MASK (0X0000003F << UART_BRD_BRK_POS) +#define UART_BRD_KEN_BIT 23 + + +/*======================= CR0 =============================*/ +#define UART_CR0_SM_POS 0 +#define UART_CR0_SM_MASK (0X00000003 << UART_CR0_SM_POS) +#define UART_CR0_DATA_BITS_7 (0x00000000 << UART_CR0_SM_POS) +#define UART_CR0_DATA_BITS_8 (0x00000001 << UART_CR0_SM_POS) +#define UART_CR0_DATA_BITS_9 (0x00000002 << UART_CR0_SM_POS) +#define UART_CR0_STOP_BIT_POS 4 +#define UART_CR0_PARITY_BIT 3 +#define UART_CR0_PARITY_ENABLE_BIT 2 + +/*======================= SR =============================*/ +#define UART_SR_SUE_POS 31 +#define UART_SR_TXRUN_MASK (0x00000001 << 15) + + + + +#define UART_SR_TLVL_POS (8u) // TLVL[11:8] +#define UART_SR_TLVL_MASK (0xFu << UART_SR_TLVL_POS) +#define UART_SR_RLVL_POS (0u) // RLVL[3:0] +#define UART_SR_RLVL_MASK (0xFu << UART_SR_RLVL_POS) + +#define UART_SR_TXFF_MASK (0X00000001 << 13) +#define UART_SR_RXFF_MASK (0X00000001 << 5) +#define UART_SR_TXEND_MASK (0X00000001 << 14) +#define UART_SR_RXEND_MASK (0X00000001 << 6) + +#define UART_SR_TXFF_BIT (13) +#define UART_SR_RXFF_BIT (5) + + + + +/*======================= TRANS =============================*/ +#define UART_TRANS_TXE_BIT 1 +#define UART_TRANS_RXE_BIT 0 + +/*======================= CR1 =============================*/ +#define UART_CR1_INTTXFE_MASK (0X00000001 << 7) +#define UART_CR1_INTRXFE_MASK (0X00000001 << 5) +#define UART_CR1_INTTXWE_MASK (0X00000001 << 6) +#define UART_CR1_INTRXWE_MASK (0X00000001 << 4) + +#define UART_CR1_INTTXFE_BIT (7) +#define UART_CR1_INTRXFE_BIT (5) + +/*======================= SWRST =============================*/ +#define UART_SWRST_MASK (0X00000003 << 0) +#define UART_SWRST_MASK_10 (0x00000002) +#define UART_SWRST_MASK_01 (0x00000001) + +/*======================= CLK =============================*/ +#define UART_CLK_PRSEL_0 (0x00000000) + +/*======================= CR1 =============================*/ +#define UART_CR1_TIL_POS 12 +#define UART_CR1_RIL_POS 8 + +#define UART_CR1_TIL_000_SHIFTED (0x00000000 << UART_CR1_TIL_POS) +#define UART_CR1_TIL_001_SHIFTED (0x00000001 << UART_CR1_TIL_POS) +#define UART_CR1_RIL_001_SHIFTED (0x00000001 << UART_CR1_RIL_POS) + +#define UART_CR1_TIL_MASK (0x00000007 << UART_CR1_TIL_POS) +#define UART_CR1_RIL_MASK (0x00000007 << UART_CR1_RIL_POS) + +#define UART_FIFOCLR_RFCLR_BIT 1 +#define UART_FIFOCLR_TFCLR_BIT 0 + + +#define write_reg8(reg8_ptr, val8) (*(volatile uint8_t *)(reg8_ptr) = (uint8_t)(val8)) +#define read_reg8(reg8_ptr) (*(volatile uint8_t *)(reg8_ptr)) + +static volatile uint8_t s_tx_prime_pending[4]; + + + + +#define write_field_reg(reg, mask, value_shifted) do { \ + uint32_t _r = read_reg(reg); \ + _r = ((_r & ~mask) | ((value_shifted) & (mask))); \ + write_reg(reg,_r); \ + } while(0) + + +/* ove dve su dodate fje */ +/*!< @brief Macro used for interrupt status register flag check + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_status_flags(_handle,_flag) (((hal_ll_uart_base_handle_t *)_handle)->CR1 & _flag) + + /*!< @brief Macro used for module interrupt source check. + * Used in interrupt handlers. + */ +#define hal_ll_uart_get_interrupt_source(_handle,_bit) (((hal_ll_uart_base_handle_t *)_handle)->SR & _bit) + + + + /*!< @brief UART HW register structure. */ typedef struct { // TODO - Define the UART registers here! + volatile uint32_t SWRST; /* UART Software Reset Register */ + volatile uint32_t CR0; /* UART Control Register 0 */ + volatile uint32_t CR1; /* UART Control Register 1 */ + volatile uint32_t CLK; /* UART Clock Control Register */ + volatile uint32_t BRD; /* UART Baud Rate Register */ + volatile uint32_t TRANS; /* UART Transfer Enable Register */ + volatile uint32_t DR; /* UART Data Register */ + volatile uint32_t SR; /* UART Status Register */ + volatile uint32_t FIFOCLR; /* UART FIFO Clear Register */ + volatile uint32_t ERR; } hal_ll_uart_base_handle_t; + + /*!< @brief UART baud rate structure. */ typedef struct { uint32_t baud; @@ -107,36 +237,20 @@ typedef enum { // ------------------------------------------------------------------ VARIABLES /*!< @brief UART hardware specific info. */ -static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_COUNT + 1 ] = { +/* ovde su defaultne vrednosti poput af = 0 i pin_name = HAL_LL_PIN_NC, to ce se posle popunjavati */ + +static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[UART_MODULE_COUNT + 1] = { #ifdef UART_MODULE_0 - {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_0 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART0_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_0), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {9600, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_1 - {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_1 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART1_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_1), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_2 - {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_2 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART2_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_2), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif #ifdef UART_MODULE_3 - {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_3 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, - #endif - #ifdef UART_MODULE_4 - {HAL_LL_UART4_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_4 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, - #endif - #ifdef UART_MODULE_5 - {HAL_LL_UART5_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_5 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, - #endif - #ifdef UART_MODULE_6 - {HAL_LL_UART6_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_6 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, - #endif - #ifdef UART_MODULE_7 - {HAL_LL_UART7_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_7 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, - #endif - #ifdef UART_MODULE_8 - {HAL_LL_UART8_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_8 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, - #endif - #ifdef UART_MODULE_9 - {HAL_LL_UART9_BASE_ADDRESS, hal_ll_uart_module_num( UART_MODULE_9 ), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, + {HAL_LL_UART3_BASE_ADDRESS, hal_ll_uart_module_num(UART_MODULE_3), {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {115200, 0}, HAL_LL_UART_PARITY_DEFAULT, HAL_LL_UART_STOP_BITS_DEFAULT, HAL_LL_UART_DATA_BITS_DEFAULT}, #endif {HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, {HAL_LL_PIN_NC, 0, HAL_LL_PIN_NC, 0}, {0, 0}, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR, HAL_LL_MODULE_ERROR} @@ -144,13 +258,16 @@ static hal_ll_uart_hw_specifics_map_t hal_ll_uart_hw_specifics_map[ UART_MODULE_ /*!< @brief UART hardware specific info. */ /*!< @brief Global handle variables used in functions. */ -static volatile hal_ll_uart_handle_register_t *low_level_handle; -static volatile hal_ll_uart_hw_specifics_map_t *hal_ll_uart_hw_specifics_map_local; +static volatile hal_ll_uart_handle_register_t* low_level_handle; +static volatile hal_ll_uart_hw_specifics_map_t* hal_ll_uart_hw_specifics_map_local; /*!< @brief Global interrupt handlers used in functions. */ static hal_ll_uart_isr_t irq_handler; static handle_t objects[UART_MODULE_COUNT]; + + + // ---------------------------------------------- PRIVATE FUNCTION DECLARATIONS /** * @brief Check if pins are adequate. @@ -167,7 +284,7 @@ static handle_t objects[UART_MODULE_COUNT]; * Returns pre-defined module index from pin maps, if pins * are adequate. */ -static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ); +static hal_ll_pin_name_t hal_ll_uart_check_pins(hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id* index_list, hal_ll_uart_handle_register_t* handle_map); /** * @brief Maps new-found module specific values. @@ -181,7 +298,7 @@ static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_l * * @return None */ -static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ); +static void hal_ll_uart_map_pins(uint8_t module_index, hal_ll_uart_pin_id* index_list); /** * @brief Sets UART pin alternate function state. @@ -196,8 +313,9 @@ static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *inde * * @return void None. */ -static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); +static void hal_ll_uart_alternate_functions_set_state(hal_ll_uart_hw_specifics_map_t* map, bool hal_ll_state); +static void hal_ll_uart_tx_af_set(hal_ll_uart_hw_specifics_map_t* map, bool enable_tx_af, bool tx_as_input); /** * @brief Get local hardware specific map. * @@ -210,7 +328,7 @@ static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_ * Returns pre-defined map index address based on handle value, * if handle is adequate. */ -static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); +static hal_ll_uart_hw_specifics_map_t* hal_ll_get_specifics(handle_t handle); /** * @brief Enable clock for UART module on hardware level. @@ -223,7 +341,7 @@ static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ); * * @return void None. */ -static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ); +static void hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_t* map, bool hal_ll_state); /** * @brief Finds UART module index. @@ -236,7 +354,7 @@ static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal * @return uint8_t Module number. * Returns values from 0 to 9. */ -static uint8_t hal_ll_uart_find_index( handle_t *handle ); +static uint8_t hal_ll_uart_find_index(handle_t* handle); /** * @brief Get UART module clock speed. @@ -245,7 +363,7 @@ static uint8_t hal_ll_uart_find_index( handle_t *handle ); * * @return uint32_t UART source clock speed in Hz. */ -static uint32_t hal_ll_uart_get_clock_speed( void ); +static uint32_t hal_ll_uart_get_clock_speed(void); /** * @brief Clears UART registers. @@ -259,7 +377,7 @@ static uint32_t hal_ll_uart_get_clock_speed( void ); * * @return void None. */ -static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); +static void hal_ll_uart_clear_regs(hal_ll_uart_base_handle_t* hal_ll_hw_reg); /** * @brief Sets desired stop bits. @@ -271,7 +389,7 @@ static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ); * * @return void None. */ -static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); +static void hal_ll_uart_set_stop_bits_bare_metal(hal_ll_uart_hw_specifics_map_t* map); /** * @brief Sets desired data bits. @@ -283,7 +401,7 @@ static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t * * @return void None. */ -static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); +static void hal_ll_uart_set_data_bits_bare_metal(hal_ll_uart_hw_specifics_map_t* map); /** * @brief Sets desired parity. @@ -295,7 +413,7 @@ static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t * * @return void None. */ -static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ); +static void hal_ll_uart_set_parity_bare_metal(hal_ll_uart_hw_specifics_map_t* map); /** * @brief Sets module clock value. @@ -304,11 +422,11 @@ static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *m * clock gate. * * @param[in] hal_ll_hw_reg - UART HW register structure. - * @param[in] pin_state - true(enable clock) / false(disable clock) + * @param[in] pin_state - true(enable `) / false(disable clock) * * @return void None. */ -static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); +static void hal_ll_uart_set_module(hal_ll_uart_base_handle_t* hal_ll_hw_reg, hal_ll_uart_state_t pin_state); /** * @brief Sets module TX line state. @@ -321,7 +439,7 @@ static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, ha * * @return void None. */ -static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); +static void hal_ll_uart_set_transmitter(hal_ll_uart_base_handle_t* hal_ll_hw_reg, hal_ll_uart_state_t pin_state); /** * @brief Sets module RX line state. @@ -334,7 +452,7 @@ static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_re * * @return void None. */ -static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ); +static void hal_ll_uart_set_receiver(hal_ll_uart_base_handle_t* hal_ll_hw_reg, hal_ll_uart_state_t pin_state); /** * @brief Initialize UART module. @@ -347,7 +465,7 @@ static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, * * @return void None. */ -static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); +static void hal_ll_uart_init(hal_ll_uart_hw_specifics_map_t* map); /** * @brief Initialize UART module on the hardware level. @@ -369,104 +487,104 @@ static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ); * * @return void None. */ -static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ); +static void hal_ll_uart_hw_init(hal_ll_uart_hw_specifics_map_t* map); // ------------------------------------------------ PUBLIC FUNCTION DEFINITIONS -hal_ll_err_t hal_ll_uart_register_handle( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t *handle_map, uint8_t *hal_module_id ) { - hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = {HAL_LL_PIN_NC,HAL_LL_PIN_NC}; +hal_ll_err_t hal_ll_uart_register_handle(hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_handle_register_t* handle_map, uint8_t* hal_module_id) { + hal_ll_uart_pin_id index_list[UART_MODULE_COUNT] = { HAL_LL_PIN_NC,HAL_LL_PIN_NC }; uint16_t pin_check_result; // Check if pins are valid. - if ( (pin_check_result = hal_ll_uart_check_pins( tx_pin, rx_pin, &index_list, handle_map )) == HAL_LL_PIN_NC ) { + if ((pin_check_result = hal_ll_uart_check_pins(tx_pin, rx_pin, &index_list, handle_map)) == HAL_LL_PIN_NC) { return HAL_LL_UART_WRONG_PINS; }; - if ( (hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || - (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin) ) + if ((hal_ll_uart_hw_specifics_map[pin_check_result].pins.tx_pin.pin_name != tx_pin) || + (hal_ll_uart_hw_specifics_map[pin_check_result].pins.rx_pin.pin_name != rx_pin)) { - hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], false ); + hal_ll_uart_alternate_functions_set_state(&hal_ll_uart_hw_specifics_map[pin_check_result], false); - hal_ll_uart_map_pins( pin_check_result, &index_list ); + hal_ll_uart_map_pins(pin_check_result, &index_list); - hal_ll_uart_alternate_functions_set_state( &hal_ll_uart_hw_specifics_map[ pin_check_result ], true ); + hal_ll_uart_alternate_functions_set_state(&hal_ll_uart_hw_specifics_map[pin_check_result], true); handle_map[pin_check_result].init_ll_state = false; } *hal_module_id = pin_check_result; - hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t*)&hal_ll_uart_hw_specifics_map[pin_check_result].base; - handle_map[pin_check_result].hal_ll_uart_handle = (handle_t *)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; + handle_map[pin_check_result].hal_ll_uart_handle = (handle_t*)&hal_ll_module_state[pin_check_result].hal_ll_uart_handle; return HAL_LL_UART_SUCCESS; } -hal_ll_err_t hal_ll_module_configure_uart( handle_t *handle ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); - hal_ll_uart_handle_register_t *hal_handle = ( hal_ll_uart_handle_register_t * )*handle; +hal_ll_err_t hal_ll_module_configure_uart(handle_t* handle) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_handle_register_t* hal_handle = (hal_ll_uart_handle_register_t*)*handle; uint8_t pin_check_result = hal_ll_uart_hw_specifics_map_local->module_index; - hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); - hal_ll_module_state[pin_check_result].hal_ll_uart_handle = ( handle_t * )&hal_ll_uart_hw_specifics_map[pin_check_result].base; + hal_ll_module_state[pin_check_result].hal_ll_uart_handle = (handle_t*)&hal_ll_uart_hw_specifics_map[pin_check_result].base; hal_ll_module_state[pin_check_result].init_ll_state = true; hal_handle->init_ll_state = true; return HAL_LL_UART_SUCCESS; } -hal_ll_err_t hal_ll_uart_set_baud( handle_t *handle, uint32_t baud ) { +hal_ll_err_t hal_ll_uart_set_baud(handle_t* handle, uint32_t baud) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); low_level_handle->init_ll_state = false; hal_ll_uart_hw_specifics_map_local->baud_rate.baud = baud; - hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); low_level_handle->init_ll_state = true; return hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud; } -hal_ll_err_t hal_ll_uart_set_parity( handle_t *handle, hal_ll_uart_parity_t parity ) { +hal_ll_err_t hal_ll_uart_set_parity(handle_t* handle, hal_ll_uart_parity_t parity) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); low_level_handle->init_ll_state = false; hal_ll_uart_hw_specifics_map_local->parity = parity; - hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); low_level_handle->init_ll_state = true; return HAL_LL_UART_SUCCESS; } -hal_ll_err_t hal_ll_uart_set_stop_bits( handle_t *handle, hal_ll_uart_stop_bits_t stop_bit ) { +hal_ll_err_t hal_ll_uart_set_stop_bits(handle_t* handle, hal_ll_uart_stop_bits_t stop_bit) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); low_level_handle->init_ll_state = false; hal_ll_uart_hw_specifics_map_local->stop_bit = stop_bit; - hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); low_level_handle->init_ll_state = true; return HAL_LL_UART_SUCCESS; } -hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_t data_bit ) { +hal_ll_err_t hal_ll_uart_set_data_bits(handle_t* handle, hal_ll_uart_data_bits_t data_bit) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - // Chips using this implementation do not support 7 bit data. - if ( ( data_bit < HAL_LL_UART_DATA_BITS_7 ) || ( data_bit > HAL_LL_UART_DATA_BITS_9 ) ) { + + if ((data_bit < HAL_LL_UART_DATA_BITS_7) || (data_bit > HAL_LL_UART_DATA_BITS_9)) { return HAL_LL_UART_MODULE_ERROR; } @@ -474,26 +592,26 @@ hal_ll_err_t hal_ll_uart_set_data_bits( handle_t *handle, hal_ll_uart_data_bits_ hal_ll_uart_hw_specifics_map_local->data_bit = data_bit; - hal_ll_uart_init( hal_ll_uart_hw_specifics_map_local ); + hal_ll_uart_init(hal_ll_uart_hw_specifics_map_local); low_level_handle->init_ll_state = true; return HAL_LL_UART_SUCCESS; } -void hal_ll_uart_close( handle_t *handle ) { +void hal_ll_uart_close(handle_t* handle) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - if( low_level_handle->hal_ll_uart_handle != NULL ) { - hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_local, true ); - hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_local, false ); + if (low_level_handle->hal_ll_uart_handle != NULL) { + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, true); + hal_ll_uart_alternate_functions_set_state(hal_ll_uart_hw_specifics_map_local, false); - hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_RX ); - hal_ll_uart_irq_disable( handle, HAL_LL_UART_IRQ_TX ); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_RX); + hal_ll_uart_irq_disable(handle, HAL_LL_UART_IRQ_TX); - hal_ll_uart_clear_regs( hal_ll_uart_hw_specifics_map_local->base ); - hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_local, false ); + hal_ll_uart_clear_regs(hal_ll_uart_hw_specifics_map_local->base); + hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_local, false); hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_name = HAL_LL_PIN_NC; hal_ll_uart_hw_specifics_map_local->pins.tx_pin.pin_af = 0; @@ -504,7 +622,7 @@ void hal_ll_uart_close( handle_t *handle ) { hal_ll_uart_hw_specifics_map_local->baud_rate.real_baud = 0; irq_handler = NULL; - objects[ hal_ll_uart_find_index( handle ) ] = NULL; + objects[hal_ll_uart_find_index(handle)] = NULL; low_level_handle->hal_ll_uart_handle = NULL; low_level_handle->hal_drv_uart_handle = NULL; @@ -513,101 +631,357 @@ void hal_ll_uart_close( handle_t *handle ) { } } -void hal_ll_uart_register_irq_handler( handle_t *handle, hal_ll_uart_isr_t handler, handle_t obj ){ +void hal_ll_uart_register_irq_handler(handle_t* handle, hal_ll_uart_isr_t handler, handle_t obj) { irq_handler = handler; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); - objects[ hal_ll_uart_find_index( handle ) ] = obj; + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + objects[hal_ll_uart_find_index(handle)] = obj; } -void hal_ll_uart_irq_enable( handle_t *handle, hal_ll_uart_irq_t irq ) { + +uint8_t clear_af = 0; + +void hal_ll_uart_irq_enable(handle_t* handle, hal_ll_uart_irq_t irq) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)hal_ll_uart_hw_specifics_map_local->base; - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; // TODO - Define the function behavior here! + /* SR_SUE must be set to 0 before modifing CR1 -> done in hw_init */ + switch (irq) { + + case HAL_LL_UART_IRQ_RX: + set_reg_bit(&hal_ll_hw_reg->CR1, UART_CR1_INTRXFE_BIT); + switch (hal_ll_uart_hw_specifics_map_local->module_index) { + #ifdef UART_MODULE_0 + case hal_ll_uart_module_num(UART_MODULE_0): hal_ll_core_enable_irq(UART0_RX_NVIC); break; + #endif + #ifdef UART_MODULE_1 + case hal_ll_uart_module_num(UART_MODULE_1): hal_ll_core_enable_irq(UART1_RX_NVIC); break; + #endif + #ifdef UART_MODULE_2 + case hal_ll_uart_module_num(UART_MODULE_2): hal_ll_core_enable_irq(UART2_RX_NVIC); break; + #endif + #ifdef UART_MODULE_3 + case hal_ll_uart_module_num(UART_MODULE_3): hal_ll_core_enable_irq(UART3_RX_NVIC); break; + #endif + default: break; + } + break; + + case HAL_LL_UART_IRQ_TX: + set_reg_bit(&hal_ll_hw_reg->CR1, UART_CR1_INTTXFE_BIT); + + switch (hal_ll_uart_hw_specifics_map_local->module_index) { + #ifdef UART_MODULE_0 + case hal_ll_uart_module_num(UART_MODULE_0): hal_ll_core_enable_irq(UART0_TX_NVIC); break; + #endif + #ifdef UART_MODULE_1 + case hal_ll_uart_module_num(UART_MODULE_1): hal_ll_core_enable_irq(UART1_TX_NVIC); break; + #endif + #ifdef UART_MODULE_2 + case hal_ll_uart_module_num(UART_MODULE_2): hal_ll_core_enable_irq(UART2_TX_NVIC); break; + #endif + #ifdef UART_MODULE_3 + case hal_ll_uart_module_num(UART_MODULE_3): hal_ll_core_enable_irq(UART3_TX_NVIC); break; + #endif + default: break; + } + + + /* + * INTTXFE interrupt is edge-triggered (TLVL -> ≤TIL),not level-triggered ! + * in the beggining TLVL = 0 (fifo empty) and TIL = 0 (default) + * so interrupt will not be triggered until TIL is set to 1 (or more) + * therefor we need to set TIL to 1 using dummy byte so the interrupt can be triggered + * once the dummy byte is sent from FIFO to shift reg and TLVL becomes 0 again + + * in order to mask dummy byte on terminal we will set TX pin as input and disable af + * once the dummy byte is fully sent we will set TX pin as output and enable af + * a new function hal_ll_uart_tx_af_set() is created for this purpose because + * hal_ll_uart_alternate_functions_set_state() affects RX pin as well + + * the kick start with dummy byte is done only once at the beginning of the transmission + * this condition is checked with TXRUN and TLVL flag in SR register + * TXRUN = 0 & TLVL = 0 (transmission is not operating and fifo empty) -> send dummy byte + * after that the interrupt will be triggered each time TLVL becomes ≤ TIL (1 or more) + */ + + // RM page 33 => transmission complete and the transmit FIFO empty + if ( ((read_reg(&hal_ll_hw_reg->SR) & UART_SR_TXRUN_MASK) == 0u) && + (((read_reg(&hal_ll_hw_reg->SR) & UART_SR_TLVL_MASK) >> UART_SR_TLVL_POS) == 0u) ) { + + // set TX as input and disable af to avoid the dummy byte on terminal + hal_ll_uart_tx_af_set(hal_ll_uart_hw_specifics_map_local, false, true); + + // send dummy byte to cause condtiion for interrupt + write_reg8(&hal_ll_hw_reg->DR, 0x00); + + // allow transmition + set_reg_bit(&hal_ll_hw_reg->TRANS, UART_TRANS_TXE_BIT); + + // make sure dummy is fully sent before setting tx af and output pin on again: + // wait untill transmission is complete + while ((read_reg(&hal_ll_hw_reg->SR) & UART_SR_TXEND_MASK) == 0u) {;} + // W1C flag + write_reg(&hal_ll_hw_reg->SR, UART_SR_TXEND_MASK); + //MORA OVO,wait untill transmition is not operating + while ((read_reg(&hal_ll_hw_reg->SR) & UART_SR_TXRUN_MASK) != 0u) {;} + // wait until fifo is empty, MORA I OVO + while (((read_reg(&hal_ll_hw_reg->SR) & UART_SR_TLVL_MASK) >> UART_SR_TLVL_POS) != 0u) {;} + + // set tx as output and endable af + hal_ll_uart_tx_af_set(hal_ll_uart_hw_specifics_map_local, true, false); + } + + + default: + break; + } + + + } -void hal_ll_uart_irq_disable( handle_t *handle, hal_ll_uart_irq_t irq ) { +void hal_ll_uart_irq_disable(handle_t* handle, hal_ll_uart_irq_t irq) { low_level_handle = hal_ll_uart_get_handle; - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)hal_ll_uart_hw_specifics_map_local->base; // TODO - Define the function behavior here! + switch (irq) { + + case HAL_LL_UART_IRQ_RX: + clear_reg_bit(&hal_ll_hw_reg->CR1, UART_CR1_INTRXFE_BIT); + switch (hal_ll_uart_hw_specifics_map_local->module_index) { + #ifdef UART_MODULE_0 + case hal_ll_uart_module_num(UART_MODULE_0): hal_ll_core_disable_irq(UART0_RX_NVIC); break; + #endif + #ifdef UART_MODULE_1 + case hal_ll_uart_module_num(UART_MODULE_1): hal_ll_core_disable_irq(UART1_RX_NVIC); break; + #endif + #ifdef UART_MODULE_2 + case hal_ll_uart_module_num(UART_MODULE_2): hal_ll_core_disable_irq(UART2_RX_NVIC); break; + #endif + #ifdef UART_MODULE_3 + case hal_ll_uart_module_num(UART_MODULE_3): hal_ll_core_disable_irq(UART3_RX_NVIC); break; + #endif + default: break; + } + break; + + case HAL_LL_UART_IRQ_TX: + clear_reg_bit(&hal_ll_hw_reg->CR1, UART_CR1_INTTXFE_BIT); + switch (hal_ll_uart_hw_specifics_map_local->module_index) { + #ifdef UART_MODULE_0 + case hal_ll_uart_module_num(UART_MODULE_0): hal_ll_core_disable_irq(UART0_TX_NVIC); break; + #endif + #ifdef UART_MODULE_1 + case hal_ll_uart_module_num(UART_MODULE_1): hal_ll_core_disable_irq(UART1_TX_NVIC); break; + #endif + #ifdef UART_MODULE_2 + case hal_ll_uart_module_num(UART_MODULE_2): hal_ll_core_disable_irq(UART2_TX_NVIC); break; + #endif + #ifdef UART_MODULE_3 + case hal_ll_uart_module_num(UART_MODULE_3): hal_ll_core_disable_irq(UART3_TX_NVIC); break; + #endif + default: break; + } + + + + break; + + default: + break; + } } -void hal_ll_uart_write( handle_t *handle, uint8_t wr_data ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; +void hal_ll_uart_write(handle_t* handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)hal_ll_uart_hw_specifics_map_local->base; // TODO - Define the function behavior here! + /* TRANS_TXE must be set beforehand -> it is set in set_transiver() */ + + write_reg8(&hal_ll_hw_reg->DR, wr_data); + + + } -void hal_ll_uart_write_polling( handle_t *handle, uint8_t wr_data ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t * )hal_ll_uart_hw_specifics_map_local->base; +void hal_ll_uart_write_polling(handle_t* handle, uint8_t wr_data) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)hal_ll_uart_hw_specifics_map_local->base; // TODO - Define the function behavior here! + //check weather there isspace in TX FIFO for another data,if not then wait until there is + while (((read_reg(&hal_ll_hw_reg->SR) & UART_SR_TLVL_MASK) >> UART_SR_TLVL_POS) >= 8u) { /* Wait for space in the transmit buffer */ } + + // enable tramsition, since its not enabled in hw_init() anymore + set_reg_bit(&hal_ll_hw_reg->TRANS, UART_TRANS_TXE_BIT); + write_reg8(&hal_ll_hw_reg->DR, wr_data); + } -uint8_t hal_ll_uart_read( handle_t *handle ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t * )hal_ll_uart_hw_specifics_map_local->base; +uint8_t hal_ll_uart_read(handle_t* handle) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)hal_ll_uart_hw_specifics_map_local->base; + + while (((read_reg(&hal_ll_hw_reg->SR) & UART_SR_RLVL_MASK) >> UART_SR_RLVL_POS) == 0u) {/* wait (RX FIFO empty) */ } + // TODO - Define the function behavior here! + return (read_reg8(&hal_ll_hw_reg->DR)); } -uint8_t hal_ll_uart_read_polling( handle_t *handle ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); - hal_ll_uart_base_handle_t *hal_ll_hw_reg = ( hal_ll_uart_base_handle_t *)hal_ll_uart_hw_specifics_map_local->base; +uint8_t hal_ll_uart_read_polling(handle_t* handle) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)hal_ll_uart_hw_specifics_map_local->base; // TODO - Define the function behavior here! + //check if a data has been recieved to RX FIFO,if yes read it,if not then wait + while (((read_reg(&hal_ll_hw_reg->SR) & UART_SR_RLVL_MASK) >> UART_SR_RLVL_POS) == 0u) {/* wait (RX FIFO empty) */ } + + + return (read_reg8(&hal_ll_hw_reg->DR)); } // ------------------------------------------------------------- DEFAULT EXCEPTION HANDLERS // TODO - Define the ISRs behaviors here! +#ifdef UART_MODULE_0 +void INTSC0RX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART0_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART0_BASE_ADDRESS, UART_CR1_INTRXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART0_BASE_ADDRESS, UART_SR_RXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_RXFF_MASK); /* W1C */ + //set_reg_bit(HAL_LL_UART0_BASE_ADDRESS->SR, UART_SR_RXFF_BIT) - > ne moze ovako jer bi eventualno upisao 1 u druge W1C bite tj obrisao ih + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_0)], HAL_LL_UART_IRQ_RX); + } + } +} +void INTSC0TX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART0_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART0_BASE_ADDRESS, UART_CR1_INTTXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART0_BASE_ADDRESS, UART_SR_TXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_TXFF_MASK); + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_0)], HAL_LL_UART_IRQ_TX); + } + } +} +#endif + +#ifdef UART_MODULE_1 +void INTSC1RX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART1_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART1_BASE_ADDRESS, UART_CR1_INTRXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART1_BASE_ADDRESS, UART_SR_RXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_RXFF_MASK); /* W1C */ + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_1)], HAL_LL_UART_IRQ_RX); + } + } +} +void INTSC1TX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART1_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART1_BASE_ADDRESS, UART_CR1_INTTXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART1_BASE_ADDRESS, UART_SR_TXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_TXFF_MASK); + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_1)], HAL_LL_UART_IRQ_TX); + } + } +} +#endif + +#ifdef UART_MODULE_2 +void INTSC2RX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART2_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART2_BASE_ADDRESS, UART_CR1_INTRXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART2_BASE_ADDRESS, UART_SR_RXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_RXFF_MASK); /* W1C */ + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_2)], HAL_LL_UART_IRQ_RX); + //write_reg(&hal_ll_hw_reg->SR, UART_SR_RXFF_MASK); + } + } +} +void INTSC2TX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART2_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART2_BASE_ADDRESS, UART_CR1_INTTXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART2_BASE_ADDRESS, UART_SR_TXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_TXFF_MASK); // MORA PRVO W1C PA IRQ_HANDLER + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_2)], HAL_LL_UART_IRQ_TX); + //write_reg(&hal_ll_hw_reg->SR, UART_SR_TXFF_MASK); + + } + } +} +#endif + +#ifdef UART_MODULE_3 +void INTSC3RX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART3_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART3_BASE_ADDRESS, UART_CR1_INTRXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART3_BASE_ADDRESS, UART_SR_RXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_RXFF_MASK); /* W1C */ + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_3)], HAL_LL_UART_IRQ_RX); + } + } +} +void INTSC3TX_Handler(void) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = (hal_ll_uart_base_handle_t*)HAL_LL_UART3_BASE_ADDRESS; + if (hal_ll_uart_get_status_flags(HAL_LL_UART3_BASE_ADDRESS, UART_CR1_INTTXFE_MASK)) { + if ((hal_ll_uart_get_interrupt_source(HAL_LL_UART3_BASE_ADDRESS, UART_SR_TXFF_MASK))) { + write_reg(&hal_ll_hw_reg->SR, UART_SR_TXFF_MASK); + irq_handler(objects[hal_ll_uart_module_num(UART_MODULE_3)], HAL_LL_UART_IRQ_TX); + } + } +} +#endif + // ----------------------------------------------- PRIVATE FUNCTION DEFINITIONS -static uint8_t hal_ll_uart_find_index( handle_t *handle ) { - hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics( hal_ll_uart_get_module_state_address ); +static uint8_t hal_ll_uart_find_index(handle_t* handle) { + hal_ll_uart_hw_specifics_map_local = hal_ll_get_specifics(hal_ll_uart_get_module_state_address); - if( hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR ) { + if (hal_ll_uart_hw_specifics_map_local->base != HAL_LL_MODULE_ERROR) { return hal_ll_uart_hw_specifics_map_local->module_index; - } else { + } + else { return NULL; } } -static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id *index_list, hal_ll_uart_handle_register_t *handle_map ) { - static const uint16_t tx_map_size = ( sizeof( hal_ll_uart_tx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); - static const uint16_t rx_map_size = ( sizeof( hal_ll_uart_rx_map ) / sizeof( hal_ll_uart_pin_map_t ) ); +static hal_ll_pin_name_t hal_ll_uart_check_pins(hal_ll_pin_name_t tx_pin, hal_ll_pin_name_t rx_pin, hal_ll_uart_pin_id* index_list, hal_ll_uart_handle_register_t* handle_map) { + static const uint16_t tx_map_size = (sizeof(hal_ll_uart_tx_map) / sizeof(hal_ll_uart_pin_map_t)); + static const uint16_t rx_map_size = (sizeof(hal_ll_uart_rx_map) / sizeof(hal_ll_uart_pin_map_t)); uint8_t hal_ll_module_id = 0; uint8_t index_counter = 0; uint16_t tx_index; uint16_t rx_index; - if (( HAL_LL_PIN_NC == tx_pin ) || ( HAL_LL_PIN_NC == rx_pin )) { + if ((HAL_LL_PIN_NC == tx_pin) || (HAL_LL_PIN_NC == rx_pin)) { return HAL_LL_PIN_NC; } - for ( tx_index = 0; tx_index < tx_map_size; tx_index++ ) { - if ( hal_ll_uart_tx_map[ tx_index ].pin == tx_pin ) { - for ( rx_index = 0; rx_index < rx_map_size; rx_index++ ) { - if ( hal_ll_uart_rx_map[ rx_index ].pin == rx_pin ) { - if ( hal_ll_uart_tx_map[ tx_index ].base == hal_ll_uart_rx_map[ rx_index ].base ) { + for (tx_index = 0; tx_index < tx_map_size; tx_index++) { + if (hal_ll_uart_tx_map[tx_index].pin == tx_pin) { + for (rx_index = 0; rx_index < rx_map_size; rx_index++) { + if (hal_ll_uart_rx_map[rx_index].pin == rx_pin) { + if (hal_ll_uart_tx_map[tx_index].base == hal_ll_uart_rx_map[rx_index].base) { // Get module number. - hal_ll_module_id = hal_ll_uart_tx_map[ tx_index ].module_index; + hal_ll_module_id = hal_ll_uart_tx_map[tx_index].module_index; // Map pin names. index_list[hal_ll_module_id].pin_tx = tx_index; index_list[hal_ll_module_id].pin_rx = rx_index; // Check if module is taken. - if ( NULL == handle_map[ hal_ll_module_id ].hal_drv_uart_handle ) { + if (NULL == handle_map[hal_ll_module_id].hal_drv_uart_handle) { return hal_ll_module_id; - } else if ( UART_MODULE_COUNT == ++index_counter ) { + } + else if (UART_MODULE_COUNT == ++index_counter) { return --index_counter; } } @@ -616,19 +990,20 @@ static hal_ll_pin_name_t hal_ll_uart_check_pins( hal_ll_pin_name_t tx_pin, hal_l } } - if ( index_counter ) { + if (index_counter) { return hal_ll_module_id; - } else { + } + else { return HAL_LL_PIN_NC; } } -static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { - uint8_t hal_ll_module_count = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_uart_handle_register_t )); - static uint8_t hal_ll_module_error = sizeof( hal_ll_module_state ) / ( sizeof( hal_ll_uart_handle_register_t )); +static hal_ll_uart_hw_specifics_map_t* hal_ll_get_specifics(handle_t handle) { + uint8_t hal_ll_module_count = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); + static uint8_t hal_ll_module_error = sizeof(hal_ll_module_state) / (sizeof(hal_ll_uart_handle_register_t)); - while( hal_ll_module_count-- ) { - if ( hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base ) { + while (hal_ll_module_count--) { + if (hal_ll_uart_get_base_from_hal_handle == hal_ll_uart_hw_specifics_map[hal_ll_module_count].base) { return &hal_ll_uart_hw_specifics_map[hal_ll_module_count]; } } @@ -636,11 +1011,47 @@ static hal_ll_uart_hw_specifics_map_t *hal_ll_get_specifics( handle_t handle ) { return &hal_ll_uart_hw_specifics_map[hal_ll_module_error]; } -static void hal_ll_uart_set_clock( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { +static void hal_ll_uart_set_clock(hal_ll_uart_hw_specifics_map_t* map, bool hal_ll_state) { // TODO - Define the function behavior here! + uint32_t* sysma_addr = (uint32_t*)HAL_LL_CG_BASE_FSYSMENA_ADDR; + uint32_t* protect_addr = (uint32_t*)HAL_LL_CG_BASE_PROTECT_ADDR; + + set_reg_bits(protect_addr, 0xC1); + + + + switch (map->module_index) + { +#ifdef UART_MODULE_0 + case (hal_ll_uart_module_num(UART_MODULE_0)): + (hal_ll_state == true) ? (set_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART0_BIT)) : (clear_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART0_BIT)); + break; +#endif + +#ifdef UART_MODULE_1 + case (hal_ll_uart_module_num(UART_MODULE_1)): + (hal_ll_state == true) ? (set_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART1_BIT)) : (clear_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART1_BIT)); + break; +#endif + +#ifdef UART_MODULE_2 + case (hal_ll_uart_module_num(UART_MODULE_2)): + (hal_ll_state == true) ? (set_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART2_BIT)) : (clear_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART2_BIT)); + break; +#endif + +#ifdef UART_MODULE_3 + case (hal_ll_uart_module_num(UART_MODULE_3)): + (hal_ll_state == true) ? (set_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART3_BIT)) : (clear_reg_bit(sysma_addr, CGFSYSMENA_IPMENA_UART3_BIT)); + break; +#endif + + default: + break; + } } -static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *index_list ) { +static void hal_ll_uart_map_pins(uint8_t module_index, hal_ll_uart_pin_id* index_list) { // Map new pins. hal_ll_uart_hw_specifics_map[module_index].pins.tx_pin.pin_name = hal_ll_uart_tx_map[index_list[module_index].pin_tx].pin; hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_name = hal_ll_uart_rx_map[index_list[module_index].pin_rx].pin; @@ -649,93 +1060,231 @@ static void hal_ll_uart_map_pins( uint8_t module_index, hal_ll_uart_pin_id *inde hal_ll_uart_hw_specifics_map[module_index].pins.rx_pin.pin_af = hal_ll_uart_rx_map[index_list[module_index].pin_rx].af; } -static void hal_ll_uart_alternate_functions_set_state( hal_ll_uart_hw_specifics_map_t *map, bool hal_ll_state ) { +static void hal_ll_uart_alternate_functions_set_state(hal_ll_uart_hw_specifics_map_t* map, bool hal_ll_state) { module_struct module; uint32_t uart_config = 0; - if (( map->pins.rx_pin.pin_name != HAL_LL_PIN_NC ) && - ( map->pins.tx_pin.pin_name != HAL_LL_PIN_NC )) + if ((map->pins.rx_pin.pin_name != HAL_LL_PIN_NC) && + (map->pins.tx_pin.pin_name != HAL_LL_PIN_NC)) { - module.pins[0] = VALUE( map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af ); - module.pins[1] = VALUE( map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af ); + module.pins[0] = VALUE(map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af); + module.pins[1] = VALUE(map->pins.rx_pin.pin_name, map->pins.rx_pin.pin_af); module.pins[2] = GPIO_MODULE_STRUCT_END; + - module.configs[ 0 ] = uart_config; - module.configs[ 1 ] = uart_config; - module.configs[ 2 ] = GPIO_MODULE_STRUCT_END; + module.configs[0] = GPIO_CFG_CR; + module.configs[1] = GPIO_CFG_MODE_DIGITAL_INPUT; + module.configs[2] = GPIO_MODULE_STRUCT_END; - hal_ll_gpio_module_struct_init( &module, hal_ll_state ); + hal_ll_gpio_module_struct_init(&module, hal_ll_state); } } -static void hal_ll_uart_set_baud_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); + +static void hal_ll_uart_tx_af_set(hal_ll_uart_hw_specifics_map_t* map, bool enable_tx_af, bool tx_as_input) { + module_struct m; + // samo TX pin! + m.pins[0] = VALUE(map->pins.tx_pin.pin_name, map->pins.tx_pin.pin_af); + m.pins[1] = GPIO_MODULE_STRUCT_END; + + // ako maskiramo dummy: stavi TX kao digital input da linija miruje dok FIFO ?alje dummy + m.configs[0] = tx_as_input ? GPIO_CFG_MODE_DIGITAL_INPUT : GPIO_CFG_CR; + m.configs[1] = GPIO_MODULE_STRUCT_END; + + hal_ll_gpio_module_struct_init(&m, enable_tx_af); +} + + + +static void hal_ll_uart_set_baud_bare_metal(hal_ll_uart_hw_specifics_map_t* map) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); // TODO - Define the function behavior here! + uint16_t baud_rate_register_divider = hal_ll_baud_rate_register_divider(map->baud_rate.baud); + uint32_t real_baud_rate = hal_ll_uart_real_baud_rate(baud_rate_register_divider); + + // If error greater than specified, cancel setting baud rate. + if (HAL_LL_UART_ACCEPTABLE_ERROR < hal_ll_uart_get_baud_error(real_baud_rate, map->baud_rate.baud)) { + map->baud_rate.real_baud = hal_ll_uart_get_baud_error(real_baud_rate, map->baud_rate.baud); + } + else { + map->baud_rate.real_baud = real_baud_rate; + + /*SR_SUE must be set to 0 before this reg BRD can be modified - > done in uart_hw_init*/ + + /* set N divider in UARTxBRD_BRN[15:0] */ + write_field_reg(&hal_ll_hw_reg->BRD, UART_BRD_BRN_MASK, baud_rate_register_divider << UART_BRD_BRN_POS); + + /* set K fractions in UARTxBRD_BRK[21:16], setting UARTxBRD_KEN = 0 -> disable K fractions, its disabled by default */ + write_field_reg(&hal_ll_hw_reg->BRD, UART_BRD_BRK_MASK, 0 << UART_BRD_BRK_POS); + clear_reg_bit(&hal_ll_hw_reg->BRD, UART_BRD_KEN_BIT); + + } } -static uint32_t hal_ll_uart_get_clock_speed( void ) { +static uint32_t hal_ll_uart_get_clock_speed(void) { // TODO - Define the function behavior here! + return (uint32_t)40000000; //80000000 } -static void hal_ll_uart_set_stop_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); +static void hal_ll_uart_set_stop_bits_bare_metal(hal_ll_uart_hw_specifics_map_t* map) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); // TODO - Define the function behavior here! + /* SR_SUE must be set to 0 before this reg CR0 can be modified - > done in uart_hw_init */ + switch (map->stop_bit) + { + case HAL_LL_UART_STOP_BITS_ONE: + clear_reg_bit(&hal_ll_hw_reg->CR0, UART_CR0_STOP_BIT_POS); + break; + case HAL_LL_UART_STOP_BITS_TWO: + set_reg_bit(&hal_ll_hw_reg->CR0, UART_CR0_STOP_BIT_POS); + break; + + default: + break; + } } -static void hal_ll_uart_set_data_bits_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); +static void hal_ll_uart_set_data_bits_bare_metal(hal_ll_uart_hw_specifics_map_t* map) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); // TODO - Define the function behavior here! + /* SR_SUE must be set to 0 before this reg CR0 can be modified - > done in uart_hw_init */ + switch (map->data_bit) + { + case HAL_LL_UART_DATA_BITS_7: + write_field_reg(&hal_ll_hw_reg->CR0, UART_CR0_SM_MASK, UART_CR0_DATA_BITS_7); + break; + + case HAL_LL_UART_DATA_BITS_8: + write_field_reg(&hal_ll_hw_reg->CR0, UART_CR0_SM_MASK, UART_CR0_DATA_BITS_8); + break; + + case HAL_LL_UART_DATA_BITS_9: + write_field_reg(&hal_ll_hw_reg->CR0, UART_CR0_SM_MASK, UART_CR0_DATA_BITS_9); + break; + + default: + break; + } + } -static void hal_ll_uart_set_parity_bare_metal( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_base_handle_t *hal_ll_hw_reg = hal_ll_uart_get_base_struct( map->base ); +static void hal_ll_uart_set_parity_bare_metal(hal_ll_uart_hw_specifics_map_t* map) { + hal_ll_uart_base_handle_t* hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); // TODO - Define the function behavior here! + /* SR_SUE must be set to 0 before this reg CR0 can be modified - > done in uart_hw_init */ + switch (map->parity) + { + case HAL_LL_UART_PARITY_NONE: + clear_reg_bit(&hal_ll_hw_reg->CR0, UART_CR0_PARITY_ENABLE_BIT); + break; + case HAL_LL_UART_PARITY_EVEN: + set_reg_bit(&hal_ll_hw_reg->CR0, UART_CR0_PARITY_ENABLE_BIT); + set_reg_bit(&hal_ll_hw_reg->CR0, UART_CR0_PARITY_BIT); + break; + case HAL_LL_UART_PARITY_ODD: + set_reg_bit(&hal_ll_hw_reg->CR0, UART_CR0_PARITY_ENABLE_BIT); + clear_reg_bit(&hal_ll_hw_reg->CR0, UART_CR0_PARITY_BIT); + break; + + default: + break; + } } -static void hal_ll_uart_set_module( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { +static void hal_ll_uart_set_module(hal_ll_uart_base_handle_t* hal_ll_hw_reg, hal_ll_uart_state_t pin_state) { // TODO - Define the function behavior here! + hal_ll_hw_reg->CLK = UART_CLK_PRSEL_0; + } -static void hal_ll_uart_set_transmitter( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { +static void hal_ll_uart_set_transmitter(hal_ll_uart_base_handle_t* hal_ll_hw_reg, hal_ll_uart_state_t pin_state) { // TODO - Define the function behavior here! + switch (pin_state) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit(&hal_ll_hw_reg->TRANS, UART_TRANS_TXE_BIT); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit(&hal_ll_hw_reg->TRANS, UART_TRANS_TXE_BIT); + break; + + default: + break; + } } -static void hal_ll_uart_set_receiver( hal_ll_uart_base_handle_t *hal_ll_hw_reg, hal_ll_uart_state_t pin_state ) { +static void hal_ll_uart_set_receiver(hal_ll_uart_base_handle_t* hal_ll_hw_reg, hal_ll_uart_state_t pin_state) { // TODO - Define the function behavior here! + switch (pin_state) + { + case HAL_LL_UART_DISABLE: + clear_reg_bit(&hal_ll_hw_reg->TRANS, UART_TRANS_RXE_BIT); + break; + + case HAL_LL_UART_ENABLE: + set_reg_bit(&hal_ll_hw_reg->TRANS, UART_TRANS_RXE_BIT); + break; + + default: + break; + } } -static void hal_ll_uart_clear_regs( hal_ll_uart_base_handle_t *hal_ll_hw_reg ) { +static void hal_ll_uart_clear_regs(hal_ll_uart_base_handle_t* hal_ll_hw_reg) { // TODO - Define the function behavior here! + write_reg(&hal_ll_hw_reg->FIFOCLR, (1u<TRANS); + } -static void hal_ll_uart_hw_init( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_clear_regs( map->base ); +int transmitter_set = 0; + +static void hal_ll_uart_hw_init(hal_ll_uart_hw_specifics_map_t* map) { - hal_ll_uart_set_data_bits_bare_metal( map ); + + // The sequence of the write of "10" and the next write of "01" generates the software reset. => is "0" => + //The registers can be updated. + // ovo clearuje TXE i RXE + hal_ll_uart_base_handle_t* hal_ll_hw_reg = hal_ll_uart_get_base_struct(map->base); + write_field_reg(&hal_ll_hw_reg->SWRST, UART_SWRST_MASK, UART_SWRST_MASK_10); + write_field_reg(&hal_ll_hw_reg->SWRST, UART_SWRST_MASK, UART_SWRST_MASK_01); - hal_ll_uart_set_parity_bare_metal( map ); + write_field_reg(&hal_ll_hw_reg->CR1, UART_CR1_TIL_MASK, UART_CR1_TIL_000_SHIFTED); + write_field_reg(&hal_ll_hw_reg->CR1, UART_CR1_RIL_MASK, UART_CR1_RIL_001_SHIFTED); - hal_ll_uart_set_stop_bits_bare_metal( map ); + hal_ll_uart_clear_regs(map->base); - hal_ll_uart_set_baud_bare_metal( map ); - hal_ll_uart_set_transmitter( map->base, HAL_LL_UART_ENABLE ); + hal_ll_uart_set_module(map->base, HAL_LL_UART_ENABLE); - hal_ll_uart_set_receiver( map->base, HAL_LL_UART_ENABLE ); + + hal_ll_uart_set_baud_bare_metal(map); + hal_ll_uart_set_data_bits_bare_metal(map); + hal_ll_uart_set_parity_bare_metal(map); + hal_ll_uart_set_stop_bits_bare_metal(map); - hal_ll_uart_set_module( map->base, HAL_LL_UART_ENABLE ); + + + //hal_ll_uart_set_transmitter(map->base, HAL_LL_UART_ENABLE); + + hal_ll_uart_set_receiver(map->base, HAL_LL_UART_ENABLE); + + } -static void hal_ll_uart_init( hal_ll_uart_hw_specifics_map_t *map ) { - hal_ll_uart_set_clock( map, true ); - hal_ll_uart_alternate_functions_set_state( map, true ); - hal_ll_uart_hw_init( map ); +static void hal_ll_uart_init(hal_ll_uart_hw_specifics_map_t* map) { + hal_ll_uart_set_clock(map, true); + + hal_ll_uart_alternate_functions_set_state(map, true); + + hal_ll_uart_hw_init(map); } // ------------------------------------------------------------------------- END