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vcodec_service.c
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vcodec_service.c
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/**
* Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
* author: chenhengming, [email protected]
* Alpha Lin, [email protected]
* Jung Zhao, [email protected]
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
#include <linux/compat.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/uaccess.h>
#include <linux/debugfs.h>
#include <linux/pm_runtime.h>
#include <linux/iopoll.h>
#include <linux/dma-buf.h>
#include <video/rk_vpu_service.h>
/* Definitions not present in mainline kernels - Myy */
#define RK_IO_ADDRESS(x) IOMEM(0xFED00000 + x)
#define RK_GRF_VIRT RK_IO_ADDRESS(0x00010000)
#define RK312X_GRF_SOC_CON1 0x00144
int rockchip_pmu_idle_request(struct device *dev, bool idle);
/* --- */
#include "vcodec_hw_info.h"
#include "vcodec_hw_vpu.h"
#include "vcodec_hw_rkv.h"
#include "vcodec_hw_vpu2.h"
#include "vcodec_service.h"
#include "vcodec_iommu_dma.h"
/*
* debug flag usage:
* +------+-------------------+
* | 8bit | 24bit |
* +------+-------------------+
* 0~23 bit is for different information type
* 24~31 bit is for information print format
*/
#define DEBUG_POWER 0x00000001
#define DEBUG_CLOCK 0x00000002
#define DEBUG_IRQ_STATUS 0x00000004
#define DEBUG_IOMMU 0x00000008
#define DEBUG_IOCTL 0x00000010
#define DEBUG_FUNCTION 0x00000020
#define DEBUG_REGISTER 0x00000040
#define DEBUG_EXTRA_INFO 0x00000080
#define DEBUG_TIMING 0x00000100
#define DEBUG_TASK_INFO 0x00000200
#define DEBUG_SET_REG 0x00001000
#define DEBUG_GET_REG 0x00002000
#define DEBUG_PPS_FILL 0x00004000
#define DEBUG_IRQ_CHECK 0x00008000
#define DEBUG_CACHE_32B 0x00010000
#define PRINT_FUNCTION 0x80000000
#define PRINT_LINE 0x40000000
#define MHZ (1000 * 1000)
#define SIZE_REG(reg) ((reg) * 4)
#define VCODEC_CLOCK_ENABLE 1
#define EXTRA_INFO_MAGIC 0x4C4A46
static int debug;
module_param(debug, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(debug, "bit switch for vcodec_service debug information");
/*
* hardware information organization
*
* In order to support multiple hardware with different version the hardware
* information is organized as follow:
*
* 1. First, index hardware by register size / position.
* These information is fix for each hardware and do not relate to runtime
* work flow. It only related to resource allocation.
* Descriptor: struct vpu_hw_info
*
* 2. Then, index hardware by runtime configuration
* These information is related to runtime setting behave including enable
* register, irq register and other key control flag
* Descriptor: struct vpu_task_info
*
* 3. Final, on iommu case the fd translation is required
* Descriptor: struct vpu_trans_info
*/
enum VPU_FREQ {
VPU_FREQ_200M,
VPU_FREQ_266M,
VPU_FREQ_300M,
VPU_FREQ_400M,
VPU_FREQ_500M,
VPU_FREQ_600M,
VPU_FREQ_DEFAULT,
VPU_FREQ_BUT,
};
struct extra_info_elem {
u32 index;
u32 offset;
};
struct extra_info_for_iommu {
u32 magic;
u32 cnt;
struct extra_info_elem elem[20];
};
static const struct vcodec_info vcodec_info_set[] = {
{
.hw_id = VPU_ID_8270,
.hw_info = &hw_vpu_8270,
.task_info = task_vpu,
.trans_info = trans_vpu,
},
{
.hw_id = VPU_ID_4831,
.hw_info = &hw_vpu_4831,
.task_info = task_vpu,
.trans_info = trans_vpu,
},
{
.hw_id = VPU_DEC_ID_9190,
.hw_info = &hw_vpu_9190,
.task_info = task_vpu,
.trans_info = trans_vpu,
},
{
.hw_id = HEVC_ID,
.hw_info = &hw_rkhevc,
.task_info = task_rkv,
.trans_info = trans_rkv,
},
{
.hw_id = RKV_DEC_ID,
.hw_info = &hw_rkvdec,
.task_info = task_rkv,
.trans_info = trans_rkv,
},
{
.hw_id = VPU2_ID,
.hw_info = &hw_vpu2,
.task_info = task_vpu2,
.trans_info = trans_vpu2,
},
{
.hw_id = RKV_DEC_ID2,
.hw_info = &hw_rkvdec,
.task_info = task_rkv,
.trans_info = trans_rkv,
},
};
/* Both VPU1 and VPU2 */
static const struct vcodec_device_info vpu_device_info = {
.device_type = VCODEC_DEVICE_TYPE_VPUX,
.name = "vpu-service",
};
static const struct vcodec_device_info vpu_combo_device_info = {
.device_type = VCODEC_DEVICE_TYPE_VPUC,
.name = "vpu-combo",
};
static const struct vcodec_device_info hevc_device_info = {
.device_type = VCODEC_DEVICE_TYPE_HEVC,
.name = "hevc-service",
};
static const struct vcodec_device_info rkvd_device_info = {
.device_type = VCODEC_DEVICE_TYPE_RKVD,
.name = "rkvdec",
};
#define DEBUG
#ifdef DEBUG
#define vpu_debug_func(type, fmt, args...) \
do { \
if (unlikely(debug & type)) { \
pr_info("%s:%d: " fmt, \
__func__, __LINE__, ##args); \
} \
} while (0)
#define vpu_debug(type, fmt, args...) \
do { \
if (unlikely(debug & type)) { \
pr_info(fmt, ##args); \
} \
} while (0)
#else
#define vpu_debug_func(level, fmt, args...)
#define vpu_debug(level, fmt, args...)
#endif
#define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
#define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
#define vpu_err(fmt, args...) \
pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
struct vpu_device {
atomic_t irq_count_codec;
atomic_t irq_count_pp;
unsigned int iosize;
u32 *regs;
};
enum VCODEC_RUNNING_MODE {
VCODEC_RUNNING_MODE_NONE = -1,
VCODEC_RUNNING_MODE_VPU,
VCODEC_RUNNING_MODE_HEVC,
VCODEC_RUNNING_MODE_RKVDEC
};
struct vcodec_mem_region {
struct list_head srv_lnk;
struct list_head reg_lnk;
struct list_head session_lnk;
/* virtual address for iommu */
dma_addr_t iova;
unsigned long len;
void *hdl;
u32 reg_idx;
};
/* struct for process session which connect to vpu */
struct vpu_session {
enum VPU_CLIENT_TYPE type;
/* a linked list of data so we can access them for debugging */
struct list_head list_session;
/* a linked list of register data waiting for process */
struct list_head waiting;
/* a linked list of register data in processing */
struct list_head running;
/* a linked list of register data processed */
struct list_head done;
wait_queue_head_t wait;
pid_t pid;
atomic_t task_running;
/* The buffer pool for this session */
struct vcodec_dma_session *dma;
};
/* struct for process register set */
struct vpu_reg {
enum VPU_CLIENT_TYPE type;
enum VPU_FREQ freq;
struct vpu_session *session;
struct vpu_subdev_data *data;
struct vpu_task_info *task;
const struct vpu_trans_info *trans;
/* link to vpu service session */
struct list_head session_link;
/* link to register set list */
struct list_head status_link;
unsigned long size;
struct list_head mem_region_list;
u32 dec_base;
u32 *reg;
};
struct vpu_subdev_data {
struct cdev cdev;
dev_t dev_t;
struct class *cls;
struct device *child_dev;
int irq_enc;
int irq_dec;
struct vpu_service_info *pservice;
u32 *regs;
enum VCODEC_RUNNING_MODE mode;
struct list_head lnk_service;
struct device *dev;
struct vpu_device enc_dev;
struct vpu_device dec_dev;
enum VPU_HW_ID hw_id;
struct vpu_hw_info *hw_info;
struct vpu_task_info *task_info;
const struct vpu_trans_info *trans_info;
u32 reg_size;
struct work_struct set_work;
struct iommu_domain *domain;
struct vcodec_iommu_info *iommu_info;
};
struct vpu_service_info {
/* struct wake_lock wake_lock;*/
struct delayed_work power_off_work;
/* struct wake_lock set_wake_lock;*/
struct workqueue_struct *set_workq;
ktime_t last; /* record previous power-on time */
/* vpu service structure global lock */
struct mutex lock;
/* link to link_reg in struct vpu_reg */
struct list_head waiting;
/* link to link_reg in struct vpu_reg */
struct list_head running;
/* link to link_reg in struct vpu_reg */
struct list_head done;
/* link to list_session in struct vpu_session */
struct list_head session;
atomic_t total_running;
atomic_t enabled;
atomic_t power_on_cnt;
atomic_t power_off_cnt;
atomic_t service_on;
struct mutex shutdown_lock;
/*
* FIXME: if someone call iommu translate function during vpu_reset,
* it may cause system core dump without any message. we suggest
* modify iommu driver to avoid this situation. before that,
* this is a temporary solution.
*/
struct mutex reset_lock;
struct vpu_reg *reg_codec;
struct vpu_reg *reg_pproc;
struct vpu_reg *reg_resev;
struct vpu_dec_config dec_config;
struct vpu_enc_config enc_config;
bool auto_freq;
bool bug_dec_addr;
atomic_t freq_status;
bool secure_isr;
bool secure_irq_status;
atomic_t secure_mode;
wait_queue_head_t *wait_secure_isr;
struct clk *aclk_vcodec;
struct clk *hclk_vcodec;
struct clk *clk_core;
struct clk *clk_cabac;
struct clk *pd_video;
#ifdef CONFIG_RESET_CONTROLLER
struct reset_control *rst_a;
struct reset_control *rst_h;
struct reset_control *rst_v;
struct reset_control *rst_core;
struct reset_control *rst_cabac;
struct reset_control *rst_niu_a;
struct reset_control *rst_niu_h;
#endif
struct device *dev;
u32 irq_status;
atomic_t reset_request;
struct list_head mem_region_list;
enum vcodec_device_id dev_id;
enum VCODEC_RUNNING_MODE curr_mode;
u32 prev_mode;
struct delayed_work simulate_work;
u32 mode_bit;
u32 mode_ctrl;
u32 *reg_base;
u32 ioaddr;
struct regmap *grf;
u32 *grf_base;
char *name;
u32 subcnt;
struct list_head subdev_list;
u32 alloc_type;
};
#ifdef CONFIG_COMPAT
struct compat_vpu_request {
compat_uptr_t req;
u32 size;
};
#endif
#define VDPU_SOFT_RESET_REG 101
#define VDPU_CLEAN_CACHE_REG 516
#define VEPU_CLEAN_CACHE_REG 772
#define HEVC_CLEAN_CACHE_REG 260
#define VPU_REG_ENABLE(base, reg) writel_relaxed(1, base + reg)
#define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
#define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
#define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
#define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
#define VPU_POWER_OFF_DELAY (4 * HZ) /* 4s */
#define VPU_TIMEOUT_DELAY (2 * HZ) /* 2s */
static void *vcodec_get_drv_data(struct platform_device *pdev);
static void reg_deinit(struct vpu_subdev_data *data, struct vpu_reg *reg);
static void vpu_service_power_on(struct vpu_subdev_data *data,
struct vpu_service_info *pservice);
static void time_record(struct vpu_task_info *task, int is_end)
{
if (unlikely(debug & DEBUG_TIMING) && task)
do_gettimeofday((is_end) ? (&task->end) : (&task->start));
}
static void time_diff(struct vpu_task_info *task)
{
vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
(task->end.tv_sec - task->start.tv_sec) * 1000 +
(task->end.tv_usec - task->start.tv_usec) / 1000);
}
static inline int try_reset_assert(struct reset_control *rst)
{
if (rst)
return reset_control_assert(rst);
return -EINVAL;
}
static inline int try_reset_deassert(struct reset_control *rst)
{
if (rst)
return reset_control_deassert(rst);
return -EINVAL;
}
static inline int grf_combo_switch(const struct vpu_subdev_data *data)
{
struct vpu_service_info *pservice = data->pservice;
int bits;
u32 raw = 0;
bits = 1 << pservice->mode_bit;
#ifdef CONFIG_MFD_SYSCON
if (pservice->grf) {
regmap_read(pservice->grf, pservice->mode_ctrl, &raw);
if (data->mode == VCODEC_RUNNING_MODE_HEVC)
regmap_write(pservice->grf, pservice->mode_ctrl,
raw | bits | (bits << 16));
else
regmap_write(pservice->grf, pservice->mode_ctrl,
(raw & (~bits)) | (bits << 16));
} else if (pservice->grf_base) {
u32 *grf_base = pservice->grf_base;
raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
if (data->mode == VCODEC_RUNNING_MODE_HEVC)
writel_relaxed(raw | bits | (bits << 16),
grf_base + pservice->mode_ctrl / 4);
else
writel_relaxed((raw & (~bits)) | (bits << 16),
grf_base + pservice->mode_ctrl / 4);
} else {
vpu_err("no grf resource define, switch decoder failed\n");
return -EINVAL;
}
#else
if (pservice->grf_base) {
u32 *grf_base = pservice->grf_base;
raw = readl_relaxed(grf_base + pservice->mode_ctrl / 4);
if (data->mode == VCODEC_RUNNING_MODE_HEVC)
writel_relaxed(raw | bits | (bits << 16),
grf_base + pservice->mode_ctrl / 4);
else
writel_relaxed((raw & (~bits)) | (bits << 16),
grf_base + pservice->mode_ctrl / 4);
} else {
vpu_err("no grf resource define, switch decoder failed\n");
return -EINVAL;
}
#endif
return 0;
}
static void vcodec_enter_mode(struct vpu_subdev_data *data)
{
struct vpu_service_info *pservice = data->pservice;
if (pservice->subcnt < 2 || pservice->mode_ctrl == 0)
return;
if (pservice->curr_mode == data->mode)
return;
vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
if (grf_combo_switch(data))
return;
pservice->prev_mode = pservice->curr_mode;
pservice->curr_mode = data->mode;
}
static void vcodec_exit_mode(struct vpu_subdev_data *data)
{
/*
* In case of VPU Combo, it require HW switch its running mode
* before the other HW component start work. set current HW running
* mode to none, can ensure HW switch to its reqired mode properly.
*/
data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
}
static int vpu_get_clk(struct vpu_service_info *pservice)
{
#if VCODEC_CLOCK_ENABLE
struct device *dev = pservice->dev;
switch (pservice->dev_id) {
case VCODEC_DEVICE_ID_HEVC:
/* We won't regard the power domain as clocks at 4.4 */
pservice->pd_video = devm_clk_get(dev, "pd_hevc");
if (IS_ERR(pservice->pd_video)) {
pservice->pd_video = NULL;
dev_dbg(dev, "failed on clk_get pd_hevc\n");
}
case VCODEC_DEVICE_ID_COMBO:
case VCODEC_DEVICE_ID_RKVDEC:
pservice->clk_cabac = devm_clk_get(dev, "clk_cabac");
if (IS_ERR(pservice->clk_cabac)) {
dev_err(dev, "failed on clk_get clk_cabac\n");
pservice->clk_cabac = NULL;
}
pservice->clk_core = devm_clk_get(dev, "clk_core");
if (IS_ERR(pservice->clk_core)) {
dev_err(dev, "failed on clk_get clk_core\n");
pservice->clk_core = NULL;
/* The VDPU and AVSD combo doesn't need those clocks */
if (pservice->dev_id == VCODEC_DEVICE_ID_RKVDEC)
return -1;
}
case VCODEC_DEVICE_ID_VPU:
pservice->aclk_vcodec = devm_clk_get(dev, "aclk_vcodec");
if (IS_ERR(pservice->aclk_vcodec)) {
dev_err(dev, "failed on clk_get aclk_vcodec\n");
pservice->aclk_vcodec = NULL;
return -1;
}
pservice->hclk_vcodec = devm_clk_get(dev, "hclk_vcodec");
if (IS_ERR(pservice->hclk_vcodec)) {
dev_err(dev, "failed on clk_get hclk_vcodec\n");
pservice->hclk_vcodec = NULL;
return -1;
}
if (pservice->pd_video == NULL) {
pservice->pd_video = devm_clk_get(dev, "pd_video");
if (IS_ERR(pservice->pd_video)) {
pservice->pd_video = NULL;
dev_dbg(dev, "do not have pd_video\n");
}
}
break;
default:
break;
}
return 0;
#else
return 0;
#endif
}
static void _vpu_reset(struct vpu_subdev_data *data)
{
struct vpu_service_info *pservice = data->pservice;
unsigned long rate = 0;
dev_info(pservice->dev, "resetting...\n");
WARN_ON(pservice->reg_codec != NULL);
WARN_ON(pservice->reg_pproc != NULL);
WARN_ON(pservice->reg_resev != NULL);
pservice->reg_codec = NULL;
pservice->reg_pproc = NULL;
pservice->reg_resev = NULL;
#ifdef CONFIG_RESET_CONTROLLER
rockchip_pmu_idle_request(pservice->dev, true);
rate = clk_get_rate(pservice->aclk_vcodec);
/*
* Some old platforms can't run at 300MHZ, they don't request
* decrease the frequency at resetting either. It is safe to
* keep here in 200 MHZ.
*/
clk_set_rate(pservice->aclk_vcodec, 200 * MHZ);
try_reset_assert(pservice->rst_niu_a);
try_reset_assert(pservice->rst_niu_h);
try_reset_assert(pservice->rst_v);
try_reset_assert(pservice->rst_a);
try_reset_assert(pservice->rst_h);
try_reset_assert(pservice->rst_core);
try_reset_assert(pservice->rst_cabac);
udelay(5);
try_reset_deassert(pservice->rst_niu_h);
try_reset_deassert(pservice->rst_niu_a);
try_reset_deassert(pservice->rst_v);
try_reset_deassert(pservice->rst_h);
try_reset_deassert(pservice->rst_a);
try_reset_deassert(pservice->rst_core);
try_reset_deassert(pservice->rst_cabac);
rockchip_pmu_idle_request(pservice->dev, false);
clk_set_rate(pservice->aclk_vcodec, rate);
vcodec_iommu_detach(data->iommu_info);
vcodec_iommu_attach(data->iommu_info);
dev_info(pservice->dev, "reset done\n");
#endif
}
static void vpu_reset(struct vpu_subdev_data *data)
{
struct vpu_service_info *pservice = data->pservice;
mutex_lock(&pservice->reset_lock);
_vpu_reset(data);
mutex_unlock(&pservice->reset_lock);
atomic_set(&pservice->reset_request, 0);
dev_info(pservice->dev, "reset done\n");
}
static void vpu_service_session_clear(struct vpu_subdev_data *data,
struct vpu_session *session)
{
struct vpu_reg *reg, *n;
list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
reg_deinit(data, reg);
}
list_for_each_entry_safe(reg, n, &session->running, session_link) {
reg_deinit(data, reg);
}
list_for_each_entry_safe(reg, n, &session->done, session_link) {
reg_deinit(data, reg);
}
}
static void vpu_service_clear(struct vpu_subdev_data *data)
{
struct vpu_reg *reg, *n;
struct vpu_session *session, *s;
struct vpu_service_info *pservice = data->pservice;
list_for_each_entry_safe(reg, n, &pservice->waiting, status_link) {
reg_deinit(reg->data, reg);
}
/* wake up session wait event to prevent the timeout hw reset
* during reboot procedure.
*/
list_for_each_entry_safe(session, s,
&pservice->session, list_session)
wake_up(&session->wait);
}
static void vpu_service_power_off(struct vpu_service_info *pservice)
{
int total_running;
int ret = atomic_add_unless(&pservice->enabled, -1, 0);
if (!ret)
return;
total_running = atomic_read(&pservice->total_running);
if (total_running) {
pr_alert("alert: power off when %d task running!!\n",
total_running);
mdelay(50);
pr_alert("alert: delay 50 ms for running task\n");
}
dev_dbg(pservice->dev, "power off...\n");
pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
pm_runtime_put(pservice->dev);
#if VCODEC_CLOCK_ENABLE
if (pservice->pd_video)
clk_disable_unprepare(pservice->pd_video);
if (pservice->hclk_vcodec)
clk_disable_unprepare(pservice->hclk_vcodec);
if (pservice->aclk_vcodec)
clk_disable_unprepare(pservice->aclk_vcodec);
if (pservice->clk_core)
clk_disable_unprepare(pservice->clk_core);
if (pservice->clk_cabac)
clk_disable_unprepare(pservice->clk_cabac);
#endif
atomic_add(1, &pservice->power_off_cnt);
/* wake_unlock(&pservice->wake_lock);*/
dev_dbg(pservice->dev, "power off done\n");
}
static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
{
queue_delayed_work(system_wq, &pservice->power_off_work,
VPU_POWER_OFF_DELAY);
}
static void vpu_power_off_work(struct work_struct *work_s)
{
struct delayed_work *dlwork = container_of(work_s,
struct delayed_work, work);
struct vpu_service_info *pservice = container_of(dlwork,
struct vpu_service_info, power_off_work);
if (mutex_trylock(&pservice->lock)) {
vpu_service_power_off(pservice);
mutex_unlock(&pservice->lock);
} else {
/* Come back later if the device is busy... */
vpu_queue_power_off_work(pservice);
}
}
static void vpu_service_power_on(struct vpu_subdev_data *data,
struct vpu_service_info *pservice)
{
int ret;
ktime_t now = ktime_get();
if (ktime_to_ns(ktime_sub(now, pservice->last)) > NSEC_PER_SEC ||
atomic_read(&pservice->power_on_cnt)) {
/* NSEC_PER_SEC */
cancel_delayed_work_sync(&pservice->power_off_work);
vpu_queue_power_off_work(pservice);
pservice->last = now;
}
ret = atomic_add_unless(&pservice->enabled, 1, 1);
if (!ret)
return;
dev_dbg(pservice->dev, "power on\n");
#define BIT_VCODEC_CLK_SEL (1<<10)
if (of_machine_is_compatible("rockchip,rk3126"))
writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1)
| BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
#if VCODEC_CLOCK_ENABLE
if (pservice->aclk_vcodec)
clk_prepare_enable(pservice->aclk_vcodec);
if (pservice->hclk_vcodec)
clk_prepare_enable(pservice->hclk_vcodec);
if (pservice->clk_core)
clk_prepare_enable(pservice->clk_core);
if (pservice->clk_cabac)
clk_prepare_enable(pservice->clk_cabac);
if (pservice->pd_video)
clk_prepare_enable(pservice->pd_video);
#endif
pm_runtime_get_sync(pservice->dev);
udelay(5);
atomic_add(1, &pservice->power_on_cnt);
// wake_lock(&pservice->wake_lock);
}
static inline bool reg_check_interlace(struct vpu_reg *reg)
{
u32 type = (reg->reg[3] & (1 << 23));
return (type > 0);
}
static inline enum VPU_DEC_FMT reg_check_fmt(struct vpu_reg *reg)
{
enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] >> 28) & 0xf);
return type;
}
static inline int reg_probe_width(struct vpu_reg *reg)
{
int width_in_mb = reg->reg[4] >> 23;
return width_in_mb * 16;
}
static inline int reg_probe_hevc_y_stride(struct vpu_reg *reg)
{
int y_virstride = reg->reg[8];
return y_virstride;
}
static dma_addr_t vcodec_fd_to_iova(struct vpu_subdev_data *data,
struct vpu_session *session,
struct vpu_reg *reg, int fd)
{
struct vcodec_mem_region *mem_region;
dma_addr_t iova;
iova = vcodec_dma_import_fd(session->dma, fd);
if (IS_ERR_VALUE(iova)) {
vpu_err("can't access dma-buf %d\n", fd);
return -EINVAL;
}
mem_region = kzalloc(sizeof(*mem_region), GFP_KERNEL);
if (mem_region == NULL) {
vpu_err("allocate memory for iommu memory region failed\n");
vcodec_dma_release_fd(session->dma, fd);
return -ENOMEM;
}
mem_region->hdl = (void *)(long)fd;
mem_region->iova = iova;
INIT_LIST_HEAD(&mem_region->reg_lnk);
list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
return mem_region->iova;
}
/*
* NOTE: rkvdec/rkhevc put scaling list address in pps buffer hardware will read
* it by pps id in video stream data.
*
* So we need to translate the address in iommu case. The address data is also
* 10bit fd + 22bit offset mode.
* Because userspace decoder do not give the pps id in the register file sets
* kernel driver need to translate each scaling list address in pps buffer which
* means 256 pps for H.264, 64 pps for H.265.
*
* In order to optimize the performance kernel driver ask userspace decoder to
* set all scaling list address in pps buffer to the same one which will be used
* on current decoding task. Then kernel driver can only translate the first
* address then copy it all pps buffer.
*/
static int fill_scaling_list_pps(struct vpu_subdev_data *data,
struct vpu_reg *reg, int fd,
int offset, int count,
int pps_info_size,
int sub_addr_offset)
{
struct dma_buf *dmabuf = NULL;
void *vaddr = NULL;
u8 *pps = NULL;
u32 base = sub_addr_offset;
u32 scaling_fd = 0;
u32 scaling_offset;
int ret = 0;
dmabuf = dma_buf_get(fd);
if (IS_ERR_OR_NULL(dmabuf)) {
dev_err(data->dev, "invliad pps buffer\n");
return -ENOENT;
}
/* See commit 831e9da7dc5c22fd2a5fb64e999f6e077a4338c3 */
ret = dma_buf_begin_cpu_access(dmabuf, DMA_FROM_DEVICE);
if (ret) {
dev_err(data->dev, "can't access the pps buffer\n");
return ret;
}
vaddr = dma_buf_vmap(dmabuf);
if (!vaddr) {
dev_err(data->dev, "can't access the pps buffer\n");
return -EIO;
}
pps = vaddr + offset;
memcpy(&scaling_offset, pps + base, sizeof(scaling_offset));
scaling_offset = le32_to_cpu(scaling_offset);
scaling_fd = scaling_offset & 0x3ff;
scaling_offset = scaling_offset >> 10;
if (scaling_fd > 0) {
int i = 0;
dma_addr_t tmp = vcodec_fd_to_iova(data, reg->session, reg,
scaling_fd);
if (IS_ERR_VALUE(tmp))
return tmp;
tmp += scaling_offset;
tmp = cpu_to_le32(tmp);
/* Fill the scaling list address in each pps entries */
for (i = 0; i < count; i++, base += pps_info_size)
memcpy(pps + base, &tmp, sizeof(tmp));
}
dma_buf_vunmap(dmabuf, vaddr);
/* See commit 831e9da7dc5c22fd2a5fb64e999f6e077a4338c3 */
dma_buf_end_cpu_access(dmabuf, DMA_FROM_DEVICE);
dma_buf_put(dmabuf);
return 0;
}
static int vcodec_bufid_to_iova(struct vpu_subdev_data *data,
struct vpu_session *session,
const u8 *tbl,
int size, struct vpu_reg *reg,
struct extra_info_for_iommu *ext_inf)
{
struct vpu_service_info *pservice = data->pservice;
struct vpu_task_info *task = reg->task;
enum FORMAT_TYPE type;
int offset = 0;
int ret = 0;
int i;
if (tbl == NULL || size <= 0) {
dev_err(pservice->dev, "input arguments invalidate\n");
return -EINVAL;
}
if (task->get_fmt) {
type = task->get_fmt(reg->reg);
} else {
dev_err(pservice->dev, "invalid task with NULL get_fmt\n");
return -EINVAL;
}
for (i = 0; i < size; i++) {
int usr_fd = reg->reg[tbl[i]] & 0x3FF;
dma_addr_t iova = 0;
/* if userspace do not set the fd at this register, skip */
if (usr_fd == 0)
continue;
/*
* special offset scale case
*
* This translation is for fd + offset translation.
* One register has 32bits. We need to transfer both buffer file
* handle and the start address offset so we packet file handle
* and offset together using below format.
*
* 0~9 bit for buffer file handle range 0 ~ 1023
* 10~31 bit for offset range 0 ~ 4M
*
* But on 4K case the offset can be larger the 4M
* So on H.264 4K vpu/vpu2 decoder we scale the offset by 16
* But MPEG4 will use the same register for colmv and it do not
* need scale.
*
* RKVdec do not have this issue.
*/
if ((type == FMT_H264D || type == FMT_VP9D) &&
task->reg_dir_mv > 0 && task->reg_dir_mv == tbl[i])
offset = reg->reg[tbl[i]] >> 10 << 4;