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JackController.syr
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JackController.syr
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.03 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.03 secs
-->
Reading design: JackController.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "JackController.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "JackController"
Output Format : NGC
Target Device : xc6slx45-3-fgg484
---- Source Options
Top Module Name : JackController
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/nabav/Workspace/JackController/Jack_Controller_Main_State_Machine.vhd" into library work
Parsing entity <Jack_Controller_Main_State_Machine>.
Parsing architecture <Behavioral> of entity <jack_controller_main_state_machine>.
Parsing VHDL file "/home/nabav/Workspace/JackController/Frame_Transmitter.vhd" into library work
Parsing entity <Frame_Transmitter>.
Parsing architecture <Behavioral> of entity <frame_transmitter>.
Parsing VHDL file "/home/nabav/Workspace/JackController/Frame_Receiver.vhd" into library work
Parsing entity <Frame_Receiver>.
Parsing architecture <Behavioral> of entity <frame_receiver>.
Parsing VHDL file "/home/nabav/Workspace/JackController/Debounce.vhd" into library work
Parsing entity <Debounce>.
Parsing architecture <Behavioral> of entity <debounce>.
Parsing VHDL file "/home/nabav/Workspace/JackController/JackController.vhd" into library work
Parsing entity <JackController>.
Parsing architecture <Behavioral> of entity <jackcontroller>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <JackController> (architecture <Behavioral>) from library <work>.
Elaborating entity <Frame_Transmitter> (architecture <Behavioral>) from library <work>.
Elaborating entity <Debounce> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <Frame_Receiver> (architecture <Behavioral>) from library <work>.
Elaborating entity <Jack_Controller_Main_State_Machine> (architecture <Behavioral>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <JackController>.
Related source file is "/home/nabav/Workspace/JackController/JackController.vhd".
Summary:
no macro.
Unit <JackController> synthesized.
Synthesizing Unit <Frame_Transmitter>.
Related source file is "/home/nabav/Workspace/JackController/Frame_Transmitter.vhd".
Found 1-bit register for signal <TX_RS485>.
Found 1-bit register for signal <Tx_Busy>.
Found 6-bit register for signal <bit_number>.
Found 3-bit register for signal <bus_hold_counter>.
Found 3-bit register for signal <state>.
Found 1-bit register for signal <Tx_Buffer<39>>.
Found 1-bit register for signal <Tx_Buffer<38>>.
Found 1-bit register for signal <Tx_Buffer<37>>.
Found 1-bit register for signal <Tx_Buffer<36>>.
Found 1-bit register for signal <Tx_Buffer<35>>.
Found 1-bit register for signal <Tx_Buffer<34>>.
Found 1-bit register for signal <Tx_Buffer<33>>.
Found 1-bit register for signal <Tx_Buffer<32>>.
Found 1-bit register for signal <Tx_Buffer<31>>.
Found 1-bit register for signal <Tx_Buffer<30>>.
Found 1-bit register for signal <Tx_Buffer<29>>.
Found 1-bit register for signal <Tx_Buffer<28>>.
Found 1-bit register for signal <Tx_Buffer<27>>.
Found 1-bit register for signal <Tx_Buffer<26>>.
Found 1-bit register for signal <Tx_Buffer<25>>.
Found 1-bit register for signal <Tx_Buffer<24>>.
Found 1-bit register for signal <Tx_Buffer<23>>.
Found 1-bit register for signal <Tx_Buffer<22>>.
Found 1-bit register for signal <Tx_Buffer<21>>.
Found 1-bit register for signal <Tx_Buffer<20>>.
Found 1-bit register for signal <Tx_Buffer<19>>.
Found 1-bit register for signal <Tx_Buffer<18>>.
Found 1-bit register for signal <Tx_Buffer<17>>.
Found 1-bit register for signal <Tx_Buffer<16>>.
Found 1-bit register for signal <Tx_Buffer<15>>.
Found 1-bit register for signal <Tx_Buffer<14>>.
Found 1-bit register for signal <Tx_Buffer<13>>.
Found 1-bit register for signal <Tx_Buffer<12>>.
Found 1-bit register for signal <Tx_Buffer<11>>.
Found 1-bit register for signal <Tx_Buffer<10>>.
Found 1-bit register for signal <Tx_Buffer<9>>.
Found 1-bit register for signal <Tx_Buffer<8>>.
Found 1-bit register for signal <Frame_Tx_FSM.Tx_Start_old>.
Found 6-bit register for signal <baudrate_prescaler_counter>.
INFO:Xst:1799 - State hold_bus_idle is never reached in FSM <state>.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 12 |
| Inputs | 5 |
| Outputs | 4 |
| Clock | clk (rising_edge) |
| Power Up State | idle |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 6-bit adder for signal <baudrate_prescaler_counter[5]_GND_7_o_add_1_OUT> created at line 38.
Found 3-bit adder for signal <bus_hold_counter[2]_GND_7_o_add_17_OUT> created at line 81.
Found 6-bit subtractor for signal <GND_7_o_GND_7_o_sub_13_OUT<5:0>> created at line 72.
Found 8-bit adder for signal <_n0162> created at line 25.
Found 8-bit adder for signal <_n0163> created at line 25.
Found 8-bit adder for signal <_n0164> created at line 25.
Found 8-bit subtractor for signal <checksum> created at line 25.
Found 1-bit 40-to-1 multiplexer for signal <bit_number[5]_X_7_o_Mux_7_o> created at line 62.
Found 6-bit comparator greater for signal <n0000> created at line 35
Found 3-bit comparator greater for signal <bus_hold_counter[2]_PWR_7_o_LessThan_17_o> created at line 80
Summary:
inferred 7 Adder/Subtractor(s).
inferred 49 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 8 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <Frame_Transmitter> synthesized.
Synthesizing Unit <Debounce>.
Related source file is "/home/nabav/Workspace/JackController/Debounce.vhd".
depth = 4
Found 4-bit register for signal <debounce_sr>.
Found 1-bit register for signal <filtered>.
Summary:
inferred 5 D-type flip-flop(s).
Unit <Debounce> synthesized.
Synthesizing Unit <Frame_Receiver>.
Related source file is "/home/nabav/Workspace/JackController/Frame_Receiver.vhd".
Found 40-bit register for signal <Rx_Buffer>.
Found 1-bit register for signal <fresh_bit_received>.
Found 1-bit register for signal <Rx_Ready>.
Found 2-bit register for signal <Rx_Frame_Type>.
Found 3-bit register for signal <Rx_Jack_Nember>.
Found 8-bit register for signal <Rx_Parameter_Address>.
Found 16-bit register for signal <Rx_Parameter_Value>.
Found 1-bit register for signal <Receive_Shift_Register.RX_RS485_old>.
Found 7-bit register for signal <low_duration_counter>.
Found 7-bit adder for signal <low_duration_counter[6]_GND_9_o_add_1_OUT> created at line 38.
Found 8-bit adder for signal <n0077> created at line 62.
Found 8-bit adder for signal <n0080> created at line 62.
Found 8-bit adder for signal <n0083> created at line 62.
Found 8-bit adder for signal <checksum> created at line 62.
Found 7-bit comparator greater for signal <low_duration_counter[6]_PWR_11_o_LessThan_1_o> created at line 37
Found 7-bit comparator lessequal for signal <low_duration_counter[6]_GND_9_o_LessThan_26_o> created at line 60
Summary:
inferred 5 Adder/Subtractor(s).
inferred 79 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <Frame_Receiver> synthesized.
Synthesizing Unit <Jack_Controller_Main_State_Machine>.
Related source file is "/home/nabav/Workspace/JackController/Jack_Controller_Main_State_Machine.vhd".
Found 1-bit register for signal <Tx_Start>.
Found 1-bit register for signal <Parameter_Bank_Read_Request>.
Found 1-bit register for signal <Parameter_Bank_Write_Request>.
Found 3-bit register for signal <state>.
Found 8-bit register for signal <Parameter_Bank_Write_Address>.
Found 16-bit register for signal <Parameter_Bank_Write_Data>.
Found 8-bit register for signal <Parameter_Bank_Read_Address>.
Found 3-bit register for signal <Tx_Jack_Nember>.
Found 8-bit register for signal <Tx_Parameter_Address>.
Found 16-bit register for signal <Tx_Parameter_Value>.
Found 1-bit register for signal <Main_FSM.Tx_Busy_old>.
Found 1-bit register for signal <Main_FSM.Rx_Ready_old>.
Found 1-bit register for signal <Main_FSM.Parameter_Bank_Read_Response_old>.
Found 1-bit register for signal <Main_FSM.Parameter_Bank_Write_Done_old>.
Found 13-bit register for signal <Main_FSM.timeout_counter>.
Found finite state machine <FSM_1> for signal <state>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 22 |
| Inputs | 11 |
| Outputs | 6 |
| Clock | clk (rising_edge) |
| Power Up State | idle |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 13-bit adder for signal <Main_FSM.timeout_counter[12]_GND_10_o_add_26_OUT> created at line 100.
Found 3-bit comparator equal for signal <Rx_Jack_Nember[2]_Parameter_Bank_Jack_ID[2]_equal_6_o> created at line 65
Summary:
inferred 1 Adder/Subtractor(s).
inferred 79 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 7 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <Jack_Controller_Main_State_Machine> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 13
13-bit adder : 1
3-bit adder : 1
6-bit adder : 1
6-bit subtractor : 1
7-bit adder : 1
8-bit adder : 7
8-bit subtractor : 1
# Registers : 41
1-bit register : 21
13-bit register : 1
16-bit register : 3
2-bit register : 1
3-bit register : 3
4-bit register : 1
40-bit register : 1
6-bit register : 2
7-bit register : 1
8-bit register : 7
# Comparators : 5
3-bit comparator equal : 1
3-bit comparator greater : 1
6-bit comparator greater : 1
7-bit comparator greater : 1
7-bit comparator lessequal : 1
# Multiplexers : 15
1-bit 2-to-1 multiplexer : 3
1-bit 40-to-1 multiplexer : 1
13-bit 2-to-1 multiplexer : 7
3-bit 2-to-1 multiplexer : 2
6-bit 2-to-1 multiplexer : 2
# FSMs : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
INFO:Xst:2261 - The FF/Latch <Tx_Buffer_39> in Unit <RS485_Frame_Transmitter> is equivalent to the following FF/Latch, which will be removed : <Tx_Buffer_37>
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_35 hinder the constant cleaning in the block RS485_Frame_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_36 hinder the constant cleaning in the block RS485_Frame_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_39 hinder the constant cleaning in the block RS485_Frame_Transmitter.
You should achieve better results by setting this init to 1.
Synthesizing (advanced) Unit <Frame_Receiver>.
The following registers are absorbed into counter <low_duration_counter>: 1 register on signal <low_duration_counter>.
The following adders/subtractors are grouped into adder tree <Madd_checksum1> :
<Madd_n0077> in block <Frame_Receiver>, <Madd_n0080> in block <Frame_Receiver>, <Madd_n0083> in block <Frame_Receiver>, <Madd_checksum> in block <Frame_Receiver>.
Unit <Frame_Receiver> synthesized (advanced).
Synthesizing (advanced) Unit <Frame_Transmitter>.
The following registers are absorbed into counter <baudrate_prescaler_counter>: 1 register on signal <baudrate_prescaler_counter>.
The following adders/subtractors are grouped into adder tree <Madd__n01641> :
<Madd__n0162> in block <Frame_Transmitter>, <Madd__n0163> in block <Frame_Transmitter>.
Unit <Frame_Transmitter> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 4
13-bit adder : 1
3-bit adder : 1
6-bit subtractor : 1
8-bit subtractor : 1
# Adder Trees : 2
8-bit / 4-inputs adder tree : 1
8-bit / 5-inputs adder tree : 1
# Counters : 2
6-bit up counter : 1
7-bit up counter : 1
# Registers : 199
Flip-Flops : 199
# Comparators : 5
3-bit comparator equal : 1
3-bit comparator greater : 1
6-bit comparator greater : 1
7-bit comparator greater : 1
7-bit comparator lessequal : 1
# Multiplexers : 15
1-bit 2-to-1 multiplexer : 3
1-bit 40-to-1 multiplexer : 1
13-bit 2-to-1 multiplexer : 7
3-bit 2-to-1 multiplexer : 2
6-bit 2-to-1 multiplexer : 2
# FSMs : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_37 hinder the constant cleaning in the block Frame_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_39 hinder the constant cleaning in the block Frame_Transmitter.
You should achieve better results by setting this init to 1.
INFO:Xst:2261 - The FF/Latch <Tx_Buffer_39> in Unit <Frame_Transmitter> is equivalent to the following FF/Latch, which will be removed : <Tx_Buffer_37>
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <Main_FSM/FSM_1> on signal <state[1:3]> with user encoding.
--------------------------------------------------
State | Encoding
--------------------------------------------------
idle | 000
decode | 001
write_parameter | 010
wait_for_write_done | 011
read_parameter | 100
wait_for_read_response | 101
transmit_read_response | 110
wait_for_transmit_read_response_done | 111
--------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <RS485_Frame_Transmitter/FSM_0> on signal <state[1:3]> with user encoding.
------------------------------
State | Encoding
------------------------------
idle | 000
capture | 001
send_low | 010
send_bit | 011
send_high | 100
prepare_next_bit | 101
hold_bus_idle | unreached
------------------------------
WARNING:Xst:2677 - Node <bus_hold_counter_0> of sequential type is unconnected in block <Frame_Transmitter>.
WARNING:Xst:2677 - Node <bus_hold_counter_1> of sequential type is unconnected in block <Frame_Transmitter>.
WARNING:Xst:2677 - Node <bus_hold_counter_2> of sequential type is unconnected in block <Frame_Transmitter>.
Optimizing unit <JackController> ...
Optimizing unit <Jack_Controller_Main_State_Machine> ...
Optimizing unit <Frame_Transmitter> ...
Optimizing unit <Frame_Receiver> ...
WARNING:Xst:1426 - The value init of the FF/Latch RS485_Frame_Transmitter/Tx_Buffer_35 hinder the constant cleaning in the block JackController.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch RS485_Frame_Transmitter/Tx_Buffer_36 hinder the constant cleaning in the block JackController.
You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <RS485_Frame_Transmitter/baudrate_prescaler_counter_5> has a constant value of 0 in block <JackController>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <RS485_Frame_Transmitter/Tx_Buffer_35> in Unit <JackController> is equivalent to the following 2 FFs/Latches, which will be removed : <RS485_Frame_Transmitter/Tx_Buffer_36> <RS485_Frame_Transmitter/Tx_Buffer_39>
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block JackController, actual ratio is 1.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 211
Flip-Flops : 211
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : JackController.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 335
# GND : 1
# INV : 3
# LUT1 : 11
# LUT2 : 25
# LUT3 : 45
# LUT4 : 65
# LUT5 : 18
# LUT6 : 77
# MUXCY : 40
# MUXF7 : 4
# VCC : 1
# XORCY : 45
# FlipFlops/Latches : 211
# FD : 63
# FDE : 136
# FDR : 5
# FDRE : 7
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 58
# IBUF : 22
# OBUF : 36
Device utilization summary:
---------------------------
Selected Device : 6slx45fgg484-3
Slice Logic Utilization:
Number of Slice Registers: 211 out of 54576 0%
Number of Slice LUTs: 244 out of 27288 0%
Number used as Logic: 244 out of 27288 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 323
Number with an unused Flip Flop: 112 out of 323 34%
Number with an unused LUT: 79 out of 323 24%
Number of fully used LUT-FF pairs: 132 out of 323 40%
Number of unique control sets: 11
IO Utilization:
Number of IOs: 59
Number of bonded IOBs: 59 out of 316 18%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 211 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 7.440ns (Maximum Frequency: 134.414MHz)
Minimum input arrival time before clock: 5.045ns
Maximum output required time after clock: 3.732ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 7.440ns (frequency: 134.414MHz)
Total number of paths / destination ports: 134313 / 346
-------------------------------------------------------------------------
Delay: 7.440ns (Levels of Logic = 11)
Source: RS485_Frame_Transmitter/Tx_Buffer_16 (FF)
Destination: RS485_Frame_Transmitter/TX_RS485 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: RS485_Frame_Transmitter/Tx_Buffer_16 to RS485_Frame_Transmitter/TX_RS485
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 2 0.447 0.721 RS485_Frame_Transmitter/Tx_Buffer_16 (RS485_Frame_Transmitter/Tx_Buffer_16)
LUT2:I0->O 1 0.203 0.000 RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd1_lut<0> (RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd1_lut<0>)
MUXCY:S->O 1 0.172 0.000 RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd1_cy<0> (RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd1_cy<0>)
XORCY:CI->O 2 0.180 0.617 RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd1_xor<1> (RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd_11)
LUT3:I2->O 1 0.205 0.580 RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd21 (RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd21)
LUT4:I3->O 1 0.205 0.000 RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd2_lut<0>2 (RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd2_lut<0>2)
MUXCY:S->O 1 0.172 0.000 RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd2_cy<0>_1 (RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd2_cy<0>2)
XORCY:CI->O 5 0.180 0.715 RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd2_xor<0>_2 (RS485_Frame_Transmitter/ADDERTREE_INTERNAL_Madd_32)
LUT6:I5->O 2 0.205 0.616 RS485_Frame_Transmitter/Mmux_bit_number[5]_X_7_o_Mux_7_o_102 (RS485_Frame_Transmitter/Mmux_bit_number[5]_X_7_o_Mux_7_o_102)
MUXF7:S->O 3 0.148 0.755 RS485_Frame_Transmitter/Mmux_bit_number[5]_X_7_o_Mux_7_o_6_SW1 (N18)
LUT6:I4->O 1 0.203 0.808 RS485_Frame_Transmitter/Mmux_bit_number[5]_X_7_o_Mux_7_o_111_SW2 (N22)
LUT6:I3->O 1 0.205 0.000 RS485_Frame_Transmitter/Mmux_state[2]_X_7_o_Mux_22_o11 (RS485_Frame_Transmitter/state[2]_X_7_o_Mux_22_o)
FDE:D 0.102 RS485_Frame_Transmitter/TX_RS485
----------------------------------------
Total 7.440ns (2.627ns logic, 4.813ns route)
(35.3% logic, 64.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 179 / 94
-------------------------------------------------------------------------
Offset: 5.045ns (Levels of Logic = 3)
Source: Parameter_Bank_Jack_ID<0> (PAD)
Destination: Main_FSM/Parameter_Bank_Write_Data_15 (FF)
Destination Clock: clk rising
Data Path: Parameter_Bank_Jack_ID<0> to Main_FSM/Parameter_Bank_Write_Data_15
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.222 0.961 Parameter_Bank_Jack_ID_0_IBUF (Parameter_Bank_Jack_ID_0_IBUF)
LUT6:I1->O 2 0.203 0.961 Main_FSM/_n0184_inv11 (Main_FSM/_n0184_inv11)
LUT6:I1->O 24 0.203 1.172 Main_FSM/_n0184_inv2 (Main_FSM/_n0184_inv)
FDE:CE 0.322 Main_FSM/Parameter_Bank_Write_Address_0
----------------------------------------
Total 5.045ns (1.950ns logic, 3.095ns route)
(38.7% logic, 61.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 36 / 36
-------------------------------------------------------------------------
Offset: 3.732ns (Levels of Logic = 1)
Source: RS485_Frame_Transmitter/Tx_Busy (FF)
Destination: DIR_RS485 (PAD)
Source Clock: clk rising
Data Path: RS485_Frame_Transmitter/Tx_Busy to DIR_RS485
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 5 0.447 0.714 RS485_Frame_Transmitter/Tx_Busy (RS485_Frame_Transmitter/Tx_Busy)
OBUF:I->O 2.571 DIR_RS485_OBUF (DIR_RS485)
----------------------------------------
Total 3.732ns (3.018ns logic, 0.714ns route)
(80.9% logic, 19.1% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 7.440| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.91 secs
-->
Total memory usage is 392752 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 11 ( 0 filtered)
Number of infos : 4 ( 0 filtered)