Seamless display patch #1708
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The file You may have to fix the suggested patch up a bit, the chip id TEGRA194 is defined with Let us know if this fixes your problem. I ran into this issue as well, but I have a very specific setup on Xavier AGX with a custom board and displayport with a different configuration than the devkit, as well as a custom display that was very picky about the continuity of its signaling, so I chalked my experience and the additional changes I required up to personal problems. |
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Hello,
I am following Kernel panic error on number of time reboot CPU:0, Error: cbb-noc@2300000, irq=15 L4T 35.4.1 - Jetson & Embedded Systems / Jetson Xavier NX - NVIDIA Developer Forums to debug the exact error outlined in this post, with my NVIDIA NX GPU. I am off Kirkstone.
I believe I can add the "disable-seamless = <1>" where required in the dtb file, but regarding the second patch (Set the display power domains to always-on with the following patch), I am not sure how to add what is required as I don't have a/drivers/soc/tegra/powergate-bpmp.c .
Any general recommendation on how to map nvidia files with meta-tegra ?
Thank you.
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