testrun monday

Author: ThorKn

Chapter_03_Verilog/c03_lecture.md

@@ -104,13 +104,13 @@ Port list and port declaration can be brought together in modern verilog.
 
 // introduces a comment.
 
-### Example: A linear shiftregister
+### Example: A linear feedback shiftregister
 ::: columns
 
 :::: column
 
 ```Verilog
-module LSFR (
+module LFSR (
 
 input  wire   load,
 input  wire   loadIt,

Chapter_03_Verilog/c03_training_advanced.md

@@ -15,23 +15,23 @@ toc: true
 
 # Chapter 3 - Verilog - TRAINING - Advanced
 
-## LSFR - Linear Feedback Shift Register
+## LFSR - Linear Feedback Shift Register
 
-This Trainnig makes use of the Verilog code of the Linear Feedback Shift Register (LSFR) from the lecture slides.
+This Trainnig makes use of the Verilog code of the Linear Feedback Shift Register (LFSR) from the lecture slides.
 
-### LSFR as example
+### LFSR as example
 
 ##### Task: Create directory and Verilog file
 
-- Create a new directory for the LSFR example (in your Documents dir?)
-- Create a new file ```lsfr.v``` inside that directory
-- Copy the Verilog code from the lecture slides into the file ```lsfr.v```
+- Create a new directory for the LFSR example (in your Documents dir?)
+- Create a new file ```lfsr.v``` inside that directory
+- Copy the Verilog code from the lecture slides into the file ```lfsr.v```
 
 ### Analyse parts of the Verilog source
 
 ##### Task: Identify parts in the code
 
-Find combinational and synchronous parts of the LSFR in
+Find combinational and synchronous parts of the LFSR in
 
 - the Verilog code 
 - the Schematic drawing (from the lecture slides)
@@ -54,14 +54,14 @@ Generate
 - Schematic graphic file
 - JSON Netlist
 
-from the LSFR Verilog code
+from the LFSR Verilog code
 
 ### yosys file
 
 ##### Task: Create a yosys config file .ys
 
-- Create a new and empty lsfr.ys file inside your lsfr directory, next to the Verilog file
-- Modify and use the lsfr.ys with yosys to generate the schenatic and the JSON netlist of the LSFR in one go.
+- Create a new and empty lfsr.ys file inside your lfsr directory, next to the Verilog file
+- Modify and use the lfsr.ys with yosys to generate the schenatic and the JSON netlist of the LFSR in one go.
 
 
 

Chapter_04_OpenROAD_first_run/c04_training_advanced.md

@@ -17,24 +17,26 @@ toc: true
 
 ## Build an external example
 
-### EDA tools
-* One of the options of chapter 0 (preparations) is needed.
-* Navigate to the ```/flow``` folder
+### "masked AES" from the HEP Alliance
 
-### Clone the design "masked AES" from the HEP Alliance
+##### Task: Clone the design
 
-Clone the masked AES design from Github.
-Use the tutorial from the HEP Alliance Repository:
+- Clone the masked AES design from Github.
+- Use the tutorial from the HEP Alliance Repository:
 
 https://github.com/HEP-Alliance/masked-aes-tapeout
 
-In a nutshell (clone via https):
+- In a nutshell (clone via https):
 ```
 git clone https://github.com/HEP-Alliance/masked-aes-tapeout.git <ORFS-Root>/flow/designs/ihp-sg13g2/masked_aes
 ```
 
-### Enable the design in the Makefile
-* Edit the Makefile:
+### Makefile
+
+##### Task: Enable the design
+
+- Navigate to the ```/flow``` folder
+- Edit the Makefile:
     * Uncomment the line with your choosen DESIGN_CONFIG from ihp-sg13g2.
     In this case the cloned masked_aes:
 
@@ -51,16 +53,35 @@ git clone https://github.com/HEP-Alliance/masked-aes-tapeout.git <ORFS-Root>/flo
 
     * The line with the default design does not need to be commented. This only applies when no previous line with DESIGN_CONFIG is set.
 
+### Run
+
+##### Task: Run ORFS with the design
 
-### Run the flowscript
-* Run ```make``` from inside the ```/flow``` folder.
+- Run ```make``` from inside the ```/flow``` folder.
 
 ### Success
-* The choosen design should finish after a while and a lot of console output with a table (time/memory) like this:
+
+- The choosen design should finish after a while and a lot of console output with a table (time/memory) like this:
 ```
 Log                            Elapsed seconds Peak Memory/MB
 
 ```
 
 CONGRATS! Your design got build to a GDS!
 
+## Examine the results
+
+### The flow steps
+
+##### Task: Match the shell output
+
+- Scroll the shell output from the command to the (successfull) end,
+- Identify the flow steps in the shell output
+- Try to match your findings to the flow steps and flow components from chapter 2
+- Can you identify single open-source tools in the output of the flow? Name the ones you identified.
+
+### The GDS
+
+##### Task: Examine the GDS
+
+- See the GDS with the command ```make gui_final```

Chapter_04_OpenROAD_first_run/c04_training_bonus.md

@@ -15,33 +15,75 @@ toc: true
 
 # Chapter 04 - OpenROAD first run - TRAINING - Bonus
 
-## 1. Build the IBEX RISC-V design
+## IBEX RISC-V design
 
-Build another example from the flow script designs:
+### Another example from ORFS
+
+##### Task: Build another example from the flow script designs:
 - The IBEX RISC-V example.
 - Modify and follow the steps from the common training for this task.
 
 ## 2. Integrate a new design into OpenROAD flowscripts
 
 In this training session you will integrate a new design for using it with OpenROAD flowscripts.
+
 You can either:
-* Have your own design ready.
-* Take an opensource design from someone else.
+
+- Have your own design ready.
+- Take an opensource design from someone else.
 
 ### Pick a design to integrate
 
-* LSFR from earlier?
-* Pre-selected TinyTapeOut designs?
+##### Task: Choose a design
+
+- LFSR from earlier?
+- TinyTapeOut design? (See earlier Bonus Training)
+- Write a new Verilog file with your own design idea.
+
+### Create a new design in ORFS
+
+##### Task: Insert a new design
+
+- In the ```flow/designs/src``` directory: create new design
+- Create or copy Verilog to there
+- In the ```flow/designs/ihp-sg13g2``` directory: create a new design(same name as in src)
+- Create or copy the ```config.mk``` and ```constraints.sdc``` from the gdc example to there
+- Modify both files to match the Verilog src file and top module.
 
-### Run the flowscript
-Todo.
+### Makefile
+
+##### Task: Enable the design
+
+- Navigate to the ```/flow``` folder
+- Edit the Makefile:
+    * Uncomment the line with your choosen DESIGN_CONFIG from ihp-sg13g2.
+    In this case you must create a new line
+
+        ```
+        DESIGN_CONFIG=./designs/ihp-sg13g2/<your design>/config.mk
+        ```
+    
+    * Re-comment the previous uncommented line with DESIGN_CONFIG.
+    For example the gcd on SKY130 design:
+    
+        ```
+        # DESIGN_CONFIG=./designs/asap7/gcd/config.mk
+        ```
+    
+    * The line with the default design does not need to be commented. This only applies when no previous line with DESIGN_CONFIG is set.
+
+### Run
+
+##### Task: Run ORFS with the design
+
+- Run ```make``` from inside the ```/flow``` folder.
 
 ### Success
-Todo.
-* The choosen design should finish after a while and a lot of console output with a table (time/memory) like this:
+
+- The choosen design should finish after a while and a lot of console output with a table (time/memory) like this:
 ```
 Log                            Elapsed seconds Peak Memory/MB
 
 ``` 
 
-CONGRATS! Your first(?) design got build to a GDS!
+CONGRATS! Your design got build to a GDS!

Chapter_04_OpenROAD_first_run/c04_training_common.md

@@ -17,11 +17,11 @@ toc: true
 
 ## Start the first run
 
-### EDA tools
-* One of the options of chapter 0 (preparations) is needed.
-* Navigate to the ```/flow``` folder
+### Makefile
+
+##### Task: Enable the design in the Makefile
 
-### Enable the design in the Makefile
+* Navigate to the ```/flow``` folder
 * Edit the Makefile:
     * Uncomment the line with your choosen DESIGN_CONFIG from ihp-sg13g2.
     For example the gcd design:
@@ -40,7 +40,10 @@ toc: true
     * The line with the default design does not need to be commented. This only applies when no previous line with DESIGN_CONFIG is set.
 
 
-### Run the flowscript
+### Run
+
+##### Task: Run ORFS with the design
+
 * Run ```make``` from inside the ```/flow``` folder.
 
 ### Success
@@ -71,4 +74,22 @@ Log                            Elapsed seconds Peak Memory/MB
 Total                                       96            899
 ```
 
-CONGRATS! Your first(?) design got build to a GDS!
+CONGRATS! Your first(?) design got build to a GDS!
+
+## Examine the results
+
+### The flow steps
+
+##### Task: Match the shell output
+
+- Scroll the shell output from the command to the (successfull) end,
+- Identify the flow steps in the shell output
+- Try to match your findings to the flow steps and flow components from chapter 2
+- Can you identify single open-source tools in the output of the flow? Name the ones you identified.
+
+### The GDS
+
+##### Task: Examine the GDS
+
+- See the GDS with the command ```make gui_final```
+