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Bump DiffTest for refactor SimTop (#238)
1 parent c5081f6 commit 57078f4

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3 files changed

+19
-12
lines changed

3 files changed

+19
-12
lines changed

src/main/scala/sim/NutShellSim.scala

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ import difftest._
2323
import nutcore.NutCoreConfig
2424
import system._
2525

26-
class SimTop extends Module {
26+
class NutShellSim extends Module with HasDiffTestInterfaces {
2727
lazy val config = NutCoreConfig(FPGAPlatform = false)
2828
val soc = Module(new NutShell()(config))
2929
val mem = Module(new AXI4RAM(memByte = 2L * 1024 * 1024 * 1024, useBlackBox = true))
@@ -41,6 +41,11 @@ class SimTop extends Module {
4141

4242
soc.io.meip := mmio.io.meip
4343

44-
val difftest = DifftestModule.finish("nutshell")
45-
difftest.uart <> mmio.io.uart
44+
override def cpuName: Option[String] = Some("NutShell")
45+
46+
val uart = IO(new UARTIO)
47+
uart <> mmio.io.uart
48+
override def connectTopIOs(difftest: DifftestTopIO): Unit = {
49+
difftest.uart <> uart
50+
}
4651
}

src/test/scala/TopMain.scala

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -20,9 +20,9 @@ import chisel3._
2020
import chisel3.stage.ChiselGeneratorAnnotation
2121
import circt.stage._
2222
import device.AXI4VGA
23-
import difftest.DifftestModule
23+
import difftest.{DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
2424
import nutcore.NutCoreConfig
25-
import sim.SimTop
25+
import sim.NutShellSim
2626
import system.NutShell
2727

2828
class Top extends Module {
@@ -36,15 +36,17 @@ class Top extends Module {
3636
dontTouch(vga.io)
3737
}
3838

39-
class FpgaDiffTop extends Module {
40-
override lazy val desiredName: String = "SimTop"
39+
class FpgaDiffTop extends Module with HasDiffTestInterfaces {
4140
lazy val config = NutCoreConfig(FPGADifftest = true)
4241
val soc = Module(new NutShell()(config))
4342
val io = IO(soc.io.cloneType)
4443
soc.io <> io
4544

46-
val difftest = DifftestModule.finish("nutshell")
47-
dontTouch(soc.io)
45+
override def cpuName: Option[String] = Some("NutShell")
46+
override def connectTopIOs(difftest: DifftestTopIO): Unit = {
47+
val io = IO(chiselTypeOf(this.io))
48+
io <> this.io
49+
}
4850
}
4951

5052
object TopMain extends App {
@@ -79,9 +81,9 @@ object TopMain extends App {
7981
}
8082

8183
val generator = if (board == "sim") {
82-
ChiselGeneratorAnnotation(() => new SimTop)
84+
ChiselGeneratorAnnotation(() => DifftestModule.top(new NutShellSim))
8385
} else if (board == "fpgadiff") {
84-
ChiselGeneratorAnnotation(() => new FpgaDiffTop)
86+
ChiselGeneratorAnnotation(() => DifftestModule.top(new FpgaDiffTop))
8587
}
8688
else {
8789
ChiselGeneratorAnnotation(() => new Top)

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