@@ -20,9 +20,9 @@ import chisel3._
2020import chisel3 .stage .ChiselGeneratorAnnotation
2121import circt .stage ._
2222import device .AXI4VGA
23- import difftest .DifftestModule
23+ import difftest .{ DifftestModule , DifftestTopIO , HasDiffTestInterfaces }
2424import nutcore .NutCoreConfig
25- import sim .SimTop
25+ import sim .NutShellSim
2626import system .NutShell
2727
2828class Top extends Module {
@@ -36,15 +36,17 @@ class Top extends Module {
3636 dontTouch(vga.io)
3737}
3838
39- class FpgaDiffTop extends Module {
40- override lazy val desiredName : String = " SimTop"
39+ class FpgaDiffTop extends Module with HasDiffTestInterfaces {
4140 lazy val config = NutCoreConfig (FPGADifftest = true )
4241 val soc = Module (new NutShell ()(config))
4342 val io = IO (soc.io.cloneType)
4443 soc.io <> io
4544
46- val difftest = DifftestModule .finish(" nutshell" )
47- dontTouch(soc.io)
45+ override def cpuName : Option [String ] = Some (" NutShell" )
46+ override def connectTopIOs (difftest : DifftestTopIO ): Unit = {
47+ val io = IO (chiselTypeOf(this .io))
48+ io <> this .io
49+ }
4850}
4951
5052object TopMain extends App {
@@ -79,9 +81,9 @@ object TopMain extends App {
7981 }
8082
8183 val generator = if (board == " sim" ) {
82- ChiselGeneratorAnnotation (() => new SimTop )
84+ ChiselGeneratorAnnotation (() => DifftestModule .top( new NutShellSim ) )
8385 } else if (board == " fpgadiff" ) {
84- ChiselGeneratorAnnotation (() => new FpgaDiffTop )
86+ ChiselGeneratorAnnotation (() => DifftestModule .top( new FpgaDiffTop ) )
8587 }
8688 else {
8789 ChiselGeneratorAnnotation (() => new Top )
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