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lizhizhoulizhizhou
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Add motor speed test
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‎motor_speed_measurement_hw.tcl

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# TCL File Generated by Component Editor 12.1sp1
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# Mon Feb 19 11:54:36 CST 2018
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# DO NOT MODIFY
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#
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# motor_speed_measurement "motor_speed_measurement" v1.0
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# Zhizhou Li 2018.02.19.11:54:36
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#
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#
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#
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# request TCL package from ACDS 12.1
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#
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package require -exact qsys 12.1
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#
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# module motor_speed_measurement
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#
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set_module_property NAME motor_speed_measurement
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP Lophilo
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set_module_property AUTHOR "Zhizhou Li"
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set_module_property DISPLAY_NAME motor_speed_measurement
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL motor_speed_measurement
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file motor_speed_measurement.v VERILOG PATH qsys_root/motor_speed_measurement.v
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add_fileset SIM_VERILOG SIM_VERILOG "" ""
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set_fileset_property SIM_VERILOG TOP_LEVEL motor_speed_measurement
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file motor_speed_measurement.v VERILOG PATH qsys_root/motor_speed_measurement.v
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point mrst
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#
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add_interface mrst reset end
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set_interface_property mrst associatedClock mclk
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set_interface_property mrst synchronousEdges DEASSERT
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set_interface_property mrst ENABLED true
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add_interface_port mrst rsi_MRST_reset reset Input 1
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#
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# connection point mclk
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#
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add_interface mclk clock end
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set_interface_property mclk clockRate 0
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set_interface_property mclk ENABLED true
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add_interface_port mclk csi_MCLK_clk clk Input 1
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#
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# connection point ctrl
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#
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add_interface ctrl avalon end
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set_interface_property ctrl addressUnits WORDS
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set_interface_property ctrl associatedClock mclk
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set_interface_property ctrl associatedReset mrst
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set_interface_property ctrl bitsPerSymbol 8
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set_interface_property ctrl burstOnBurstBoundariesOnly false
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set_interface_property ctrl burstcountUnits WORDS
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set_interface_property ctrl explicitAddressSpan 0
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set_interface_property ctrl holdTime 0
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set_interface_property ctrl linewrapBursts false
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set_interface_property ctrl maximumPendingReadTransactions 0
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set_interface_property ctrl readLatency 0
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set_interface_property ctrl readWaitTime 1
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set_interface_property ctrl setupTime 0
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set_interface_property ctrl timingUnits Cycles
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set_interface_property ctrl writeWaitTime 0
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set_interface_property ctrl ENABLED true
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add_interface_port ctrl avs_ctrl_writedata writedata Input 32
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add_interface_port ctrl avs_ctrl_readdata readdata Output 32
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add_interface_port ctrl avs_ctrl_byteenable byteenable Input 4
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add_interface_port ctrl avs_ctrl_address address Input 3
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add_interface_port ctrl avs_ctrl_write write Input 1
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add_interface_port ctrl avs_ctrl_read read Input 1
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add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
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set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
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set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point pwmrst
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#
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add_interface pwmrst reset end
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set_interface_property pwmrst associatedClock pwmclk
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set_interface_property pwmrst synchronousEdges DEASSERT
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set_interface_property pwmrst ENABLED true
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add_interface_port pwmrst rsi_PWMRST_reset reset Input 1
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#
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# connection point pwmclk
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#
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add_interface pwmclk clock end
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set_interface_property pwmclk clockRate 0
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set_interface_property pwmclk ENABLED true
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add_interface_port pwmclk csi_PWMCLK_clk clk Input 1
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#
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# connection point conduit_end
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#
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add_interface conduit_end conduit end
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set_interface_property conduit_end associatedClock mclk
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set_interface_property conduit_end associatedReset mrst
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set_interface_property conduit_end ENABLED true
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add_interface_port conduit_end frequent export Input 1
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‎qsys_root/frequent_measure.v

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This file was deleted.

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