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PowerTableMonitor.cs
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using System;
using System.Collections.Generic;
using System.ComponentModel;
using System.Data;
using System.Drawing;
using System.Linq;
using System.Text;
using System.Windows.Forms;
using ZenStates.Core;
namespace ZenStatesDebugTool
{
public partial class PowerTableMonitor : Form
{
private readonly Cpu CPU;
private string[] pmt_labels;
readonly Timer PowerCfgTimer = new Timer();
private readonly BindingList<PowerMonitorItem> list = new BindingList<PowerMonitorItem>();
private class PowerMonitorItem
{
// public string Index { get; set; }
public string Offset { get; set; }
public string TLabel { get; set; }
public string Value { get; set; }
}
private void FillInData(float[] table)
{
list.Clear();
for (var i = 0; i < table.Length; i++)
{
list.Add(new PowerMonitorItem {
// Index = $"{i:D4}",
Offset = $"{(i*4):X4} ",
TLabel = i < pmt_labels.Length ? $" {pmt_labels[i]}" : "",
Value = $"{table[i]:F6}"
});;
}
}
private void RefreshData(float[] table)
{
int index = 0;
foreach (var item in list)
{
item.Value = $"{table[index]:F6}";
index++;
}
dataGridView1.Refresh();
}
private void PowerCfgTimer_Tick(object sender, EventArgs e)
{
Console.WriteLine("refreshing");
if (CPU.RefreshPowerTable() == SMU.Status.OK)
RefreshData(CPU.powerTable.Table);
}
public PowerTableMonitor(Cpu cpu)
{
CPU = cpu;
PowerCfgTimer.Interval = 2000;
PowerCfgTimer.Tick += new EventHandler(PowerCfgTimer_Tick);
switch (cpu.info.codeName) {
case Cpu.CodeName.Vermeer:
case Cpu.CodeName.Matisse:
pmt_labels = pmt_380905;
break;
case Cpu.CodeName.Cezanne:
pmt_labels = pmt_400005;
break;
}
InitializeComponent();
dataGridView1.DataSource = list;
cpu.RefreshPowerTable();
FillInData(cpu.powerTable.Table);
}
private void PowerTableMonitor_FormClosing(object sender, FormClosingEventArgs e)
{
PowerCfgTimer.Stop();
}
private void PowerTableMonitor_Shown(object sender, EventArgs e)
{
PowerCfgTimer.Start();
}
private void ButtonApply_Click(object sender, EventArgs e)
{
PowerCfgTimer.Interval = Convert.ToInt32(numericUpDownInterval.Value);
}
string[] pmt_380905 = {
"PPT_LIMIT",
"PPT_VALUE",
"TDC_LIMIT",
"TDC_VALUE",
"THM_LIMIT",
"THM_VALUE",
"FIT_LIMIT",
"FIT_VALUE",
"EDC_LIMIT",
"EDC_VALUE",
"VID_LIMIT",
"VID_VALUE",
"PPT_WC",
"PPT_ACTUAL",
"TDC_WC",
"TDC_ACTUAL",
"THM_WC",
"THM_ACTUAL",
"FIT_WC",
"FIT_ACTUAL",
"EDC_WC",
"EDC_ACTUAL",
"VID_WC",
"VID_ACTUAL",
"VDDCR_CPU_POWER",
"VDDCR_SOC_POWER",
"VDDIO_MEM_POWER",
"VDD18_POWER",
"ROC_POWER",
"SOCKET_POWER",
"GLOBAL_FREQUENCY",
"PPT_FREQUENCY",
"TDC_FREQUENCY",
"THM_FREQUENCY",
"VOLTAGE_FREQUENCY",
"HTFMAX_FREQUENCY",
"PROCHOT_FREQUENCY",
"CCA_FREQUENCY",
"FIT_VOLTAGE",
"FIT_PRE_VOLTAGE",
"CPU_SET_VOLTAGE",
"CPU_TELEMETRY_VOLTAGE",
"CPU_TELEMETRY_CURRENT",
"CPU_TELEMETRY_POWER",
"SOC_SET_VOLTAGE",
"SOC_TELEMETRY_VOLTAGE",
"SOC_TELEMETRY_CURRENT",
"SOC_TELEMETRY_POWER",
"FCLK_FREQ",
"FCLK_FREQ_EFF",
"MEMCLK_FREQ",
"UCLK_FREQ",
"FCLK_DRAM_SETPOINT",
"FCLK_DRAM_BUSY",
"FCLK_GMI_SETPOINT",
"FCLK_GMI_BUSY",
"FCLK_IOHC_SETPOINT",
"FCLK_IOHC_BUSY",
"FCLK_MEM_LATENCY_SETPOINT",
"FCLK_MEM_LATENCY",
"FCLK_CCLK_SETPOINT",
"FCLK_CCLK_FREQ",
"FCLK_XGMI_SETPOINT",
"FCLK_XGMI_BUSY",
"CCM_READS",
"CCM_WRITES",
"IOMS",
"XGMI",
"CS_UMC_READS",
"CS_UMC_WRITES",
"FCLK_RESIDENCY[0]",
"FCLK_RESIDENCY[1]",
"FCLK_RESIDENCY[2]",
"FCLK_RESIDENCY[3]",
"FCLK_FREQ_TABLE[0]",
"FCLK_FREQ_TABLE[1]",
"FCLK_FREQ_TABLE[2]",
"FCLK_FREQ_TABLE[3]",
"UCLK_FREQ_TABLE[0]",
"UCLK_FREQ_TABLE[1]",
"UCLK_FREQ_TABLE[2]",
"UCLK_FREQ_TABLE[3]",
"MEMCLK_FREQ_TABLE[0]",
"MEMCLK_FREQ_TABLE[1]",
"MEMCLK_FREQ_TABLE[2]",
"MEMCLK_FREQ_TABLE[3]",
"FCLK_VOLTAGE[0]",
"FCLK_VOLTAGE[1]",
"FCLK_VOLTAGE[2]",
"FCLK_VOLTAGE[3]",
"LCLK_SETPOINT_0",
"LCLK_BUSY_0",
"LCLK_FREQ_0",
"LCLK_FREQ_EFF_0",
"LCLK_MAX_DPM_0",
"LCLK_MIN_DPM_0",
"SOCCLK_FREQ_EFF 0",
"SHUBCLK_FREQ_EFF 0",
"LCLK_SETPOINT_1",
"LCLK_BUSY_1",
"LCLK_FREQ_1",
"LCLK_FREQ_EFF_1",
"LCLK_MAX_DPM_1",
"LCLK_MIN_DPM_1",
"SOCCLK_FREQ_EFF 1",
"SHUBCLK_FREQ_EFF 1",
"LCLK_SETPOINT_2",
"LCLK_BUSY_2",
"LCLK_FREQ_2",
"LCLK_FREQ_EFF_2",
"LCLK_MAX_DPM_2",
"LCLK_MIN_DPM_2",
"SOCCLK_FREQ_EFF 2",
"SHUBCLK_FREQ_EFF 2",
"LCLK_SETPOINT_3",
"LCLK_BUSY_3",
"LCLK_FREQ_3",
"LCLK_FREQ_EFF_3",
"LCLK_MAX_DPM_3",
"LCLK_MIN_DPM_3",
"SOCCLK_FREQ_EFF 3",
"SHUBCLK_FREQ_EFF 3",
"XGMI_SETPOINT",
"XGMI_BUSY",
"XGMI_LANE_WIDTH",
"XGMI_DATA_RATE",
"SOC_POWER",
"SOC_TEMP",
"DDR_PHY_POWER",
"DDR_VDDIO_MEM_POWER",
"GMI2_VDDG_POWER",
"IO_VDDCR_SOC_POWER",
"IO_VDDIO_MEM_POWER",
"IO_VDD18_POWER",
"TDP",
"DETERMINISM",
"V_VDDM",
"V_VDDP",
"V_VDDG_IOD",
"V_VDDG_CCD",
"PEAK_TEMP",
"PEAK_VID",
"PEAK_CCLK_FREQ",
"MAX VOLTAGE", // ~
"APML CURRENT", // agrees w/renesas telemetry
"APML_POWER", // for the vddcpu loop
"AVG_CORE_COUNT",
"CCLK LIMIT",
"MAX CORE VID",
"",
"PACKAGE_POWER",
"CPU_DC_BTC",
"SOC_DC_BTC",
"CSTATE_BOOST",
"PROCHOT",
"PC6",
"SELF_REFRESH",
"PWM",
"SOCCLK",
"SHUBCLK",
"SMNCLK",
"SMNCLK_EFF",
"MP0CLK",
"MP0CLK_EFF",
"MP1CLK",
"MP1CLK_EFF",
"MP5CLK",
"TWIXCLK",
"WAFLCLK",
"DPM_BUSY",
"MP1_BUSY",
"MP1 SKIP COUNTER",
"CORE0_POWER",
"---",
"---",
"CORE1_POWER",
"CORE2_POWER",
"CORE3_POWER",
"CORE4_POWER",
"CORE5_POWER",
"CORE0_VOLTAGE",
"---",
"---",
"CORE1_VOLTAGE",
"CORE2_VOLTAGE",
"CORE3_VOLTAGE",
"CORE4_VOLTAGE",
"CORE5_VOLTAGE",
"CORE0_TEMP",
"---",
"---",
"CORE1_TEMP",
"CORE2_TEMP",
"CORE3_TEMP",
"CORE4_TEMP",
"CORE5_TEMP",
"CORE0_FIT",
"---",
"---",
"CORE1_FIT",
"CORE2_FIT",
"CORE3_FIT",
"CORE4_FIT",
"CORE5_FIT",
"CORE0_IDDMAX",
"---",
"---",
"CORE1_IDDMAX",
"CORE2_IDDMAX",
"CORE3_IDDMAX",
"CORE4_IDDMAX",
"CORE5_IDDMAX",
"CORE0_FREQ",
"---",
"---",
"CORE1_FREQ",
"CORE2_FREQ",
"CORE3_FREQ",
"CORE4_FREQ",
"CORE5_FREQ",
"CORE0_FREQEFF",
"---",
"---",
"CORE1_FREQEFF",
"CORE2_FREQEFF",
"CORE3_FREQEFF",
"CORE4_FREQEFF",
"CORE5_FREQEFF",
"CORE0_C0",
"---",
"---",
"CORE1_C0",
"CORE2_C0",
"CORE3_C0",
"CORE4_C0",
"CORE5_C0",
"CORE0_CC1",
"---",
"---",
"CORE1_CC1",
"CORE2_CC1",
"CORE3_CC1",
"CORE4_CC1",
"CORE5_CC1",
"CORE0_CC6",
"---",
"---",
"CORE1_CC6",
"CORE2_CC6",
"CORE3_CC6",
"CORE4_CC6",
"CORE5_CC6",
"CORE0_CKS_FDD",
"---",
"---",
"CORE1_CKS_FDD",
"CORE2_CKS_FDD",
"CORE3_CKS_FDD",
"CORE4_CKS_FDD",
"CORE5_CKS_FDD",
"CORE0_CI_FDD",
"---",
"---",
"CORE1_CI_FDD",
"CORE2_CI_FDD",
"CORE3_CI_FDD",
"CORE4_CI_FDD",
"CORE5_CI_FDD",
"CORE0_IRM",
"---",
"---",
"CORE1_IRM",
"CORE2_IRM",
"CORE3_IRM",
"CORE4_IRM",
"CORE5_IRM",
"CORE0_PSTATE",
"---",
"---",
"CORE1_PSTATE",
"CORE2_PSTATE",
"CORE3_PSTATE",
"CORE4_PSTATE",
"CORE5_PSTATE",
"CORE0_CPPC_MAX",
"---",
"---",
"CORE1_CPPC_MAX",
"CORE2_CPPC_MAX",
"CORE3_CPPC_MAX",
"CORE4_CPPC_MAX",
"CORE5_CPPC_MAX",
"CORE0_CPPC_MIN",
"---",
"---",
"CORE1_CPPC_MIN",
"CORE2_CPPC_MIN",
"CORE3_CPPC_MIN",
"CORE4_CPPC_MIN",
"CORE5_CPPC_MIN",
"CORE0_CPPC_EPP",
"",
"",
"CORE1_CPPC_EPP",
"CORE2_CPPC_EPP",
"CORE3_CPPC_EPP",
"CORE4_CPPC_EPP",
"CORE5_CPPC_EPP",
"CORE0_SC_LIMIT",
"---",
"---",
"CORE1_SC_LIMIT",
"CORE2_SC_LIMIT",
"CORE3_SC_LIMIT",
"CORE4_SC_LIMIT",
"CORE5_SC_LIMIT",
"CORE0_SC_CAC",
"---",
"---",
"CORE1_SC_CAC",
"CORE2_SC_CAC",
"CORE3_SC_CAC",
"CORE4_SC_CAC",
"CORE5_SC_CAC",
"CORE0_SC_RESIDENCY",
"---",
"---",
"CORE1_SC_RESIDENCY",
"CORE2_SC_RESIDENCY",
"CORE3_SC_RESIDENCY",
"CORE4_SC_RESIDENCY",
"CORE5_SC_RESIDENCY",
"CORE0_UOPS_CLK",
"---",
"---",
"CORE1_UOPS_CLK",
"CORE2_UOPS_CLK",
"CORE3_UOPS_CLK",
"CORE4_UOPS_CLK",
"CORE5_UOPS_CLK",
"CORE0_UOPS",
"---",
"---",
"CORE1_UOPS",
"CORE2_UOPS",
"CORE3_UOPS",
"CORE4_UOPS",
"CORE5_UOPS",
"CORE0_MEM_LATENCY",
"---",
"---",
"CORE1_MEM_LATENCY",
"CORE2_MEM_LATENCY",
"CORE3_MEM_LATENCY",
"CORE4_MEM_LATENCY",
"CORE5_MEM_LATENCY",
"L3_LOGIC_POWER",
"L3_VDDM_POWER",
"L3_TEMP",
"L3_FIT",
"L3_IDDMAX",
"L3_FREQ",
"L3_FREQEFF",
"L3_CKS_FDD",
"L3_CCA_THRESHOLD",
"L3_CCA_CAC",
"L3_CCA_ACTIVATION",
"L3_EDC_LIMIT",
"L3_EDC_CAC",
"L3_EDC_RESIDENCY",
"L3_FLL_BTC",
"L3_TEMP2",
""
};
string[] pmt_400005 = {
"STAPM LIMIT",
"STAPM VALUE",
"PPT LIMIT FAST",
"PPT VALUE FAST",
"PPT LIMIT SLOW",
"PPT VALUE SLOW",
"PPT LIMIT APU",
"PPT VALUE APU",
"TDC LIMIT VDD",
"TDC VALUE VDD",
"TDC LIMIT SOC",
"TDC VALUE SOC",
"EDC LIMIT VDD",
"EDC VALUE VDD",
"EDC LIMIT SOC",
"EDC VALUE SOC",
"THM LIMIT CORE",
"THM VALUE CORE",
"THM LIMIT GFX",
"THM VALUE GFX",
"THM LIMIT SOC",
"THM VALUE SOC",
"STT LIMIT APU",
"STT VALUE APU",
"STT LIMIT DGPU",
"STT VALUE DGPU",
"FIT LIMIT",
"FIT VALUE",
"VID LIMIT",
"VID VALUE",
"PSI0 LIMIT VDD",
"PSI0 RESIDENCY VDD",
"PSI0 LIMIT SOC",
"PSI0 RESIDENCY SOC",
"VDDCR_CPU_POWER",
"VDDCR SOC POWER",
"VDDIO MEM POWER",
"ROC POWER",
"SOCKET_POWER",
"CORE GLOBAL FREQ",
"CORE STAPM FREQ",
"CORE PPT FAST FREQ",
"CORE PPT SLOW FREQ",
"CORE PPT APUONLY FREQ",
"CORE TDC FREQ",
"CORE THM FREQ",
"CORE HTFMAX FREQ",
"CORE PROCHOT FREQ",
"CORE VOLTAGE FREQ",
"CORE CCA FREQ",
"GFX GLOBAL FREQ",
"GFX STAPM FREQ",
"GFX PPT FAST FREQ",
"GFX PPT SLOW FREQ",
"GFX PPT APUONLY FREQ",
"GFX TDC FREQ",
"GFX THM FREQ",
"GFX HTFMAX FREQ",
"GFX PROCHOT FREQ",
"GFX VOLTAGE FREQ",
"GFX ? FREQ",
"GFX CCA FREQ",
"FIT VOLTAGE",
"LATCHUP VOLTAGE",
"CORE SETPOINT",
"CORE BUSY",
"GFX SETPOINT",
"GFX BUSY",
"FCLK CCX SETPOINT",
"FCLK CCX BUSY",
"FCLK GFX SETPOINT",
"FCLK GFX BUSY",
"FCLK IO SETPOINT",
"FCLK IO BUSY",
"FCLK DRAM SETPOINT",
"FCLK DRAM BUSY",
"LCLK SETPOINT",
"LCLK BUSY",
"FCLK RESIDENCY 0",
"FCLK RESIDENCY 1",
"FCLK RESIDENCY 2",
"FCLK RESIDENCY 3",
"FCLK FREQ TABLE 0",
"FCLK FREQ TABLE 1",
"FCLK FREQ TABLE 2",
"FCLK FREQ TABLE 3",
"UCLK FREQ TABLE 0",
"UCLK FREQ TABLE 1",
"UCLK FREQ TABLE 2",
"UCLK FREQ TABLE 3",
"MEMCLK FREQ TABLE 0",
"MEMCLK FREQ TABLE 1",
"MEMCLK FREQ TABLE 2",
"MEMCLK FREQ TABLE 3",
"FCLK VOLTAGE 0",
"FCLK VOLTAGE 1",
"FCLK VOLTAGE 2",
"FCLK VOLTAGE 3",
"CPU SET VOLTAGE",
"CPU TELEMETRY VOLTAGE",
"CPU TELEMETRY CURRENT",
"CPU TELEMETRY POWER",
"SOC SET VOLTAGE",
"SOC TELEMETRY VOLTAGE",
"SOC TELEMETRY CURRENT",
"SOC TELEMETRY POWER",
"RAIL0 VOLTAGE",
"RAIL1 VOLTAGE",
"RAIL2 VOLTAGE",
"RAIL3 VOLTAGE",
"RAIL4 VOLTAGE",
"RAIL5 VOLTAGE",
"RAIL6 VOLTAGE",
"RAIL7 VOLTAGE",
"RAIL8 VOLTAGE",
"RAIL9 VOLTAGE",
"RAIL10 VOLTAGE",
"RAIL11 VOLTAGE",
"RAIL12 VOLTAGE",
"RAIL13 VOLTAGE",
"RAIL14 VOLTAGE",
"RAIL15 VOLTAGE",
"RAIL16 VOLTAGE",
"RAIL17 VOLTAGE",
"RAIL18 VOLTAGE",
"RAIL19 VOLTAGE",
"RAIL0 CURRENT",
"RAIL1 CURRENT",
"RAIL2 CURRENT",
"RAIL3 CURRENT",
"RAIL4 CURRENT",
"RAIL5 CURRENT",
"RAIL6 CURRENT",
"RAIL7 CURRENT",
"RAIL8 CURRENT",
"RAIL9 CURRENT",
"RAIL10 CURRENT",
"RAIL11 CURRENT",
"RAIL12 CURRENT",
"RAIL13 CURRENT",
"RAIL14 CURRENT",
"RAIL15 CURRENT",
"RAIL16 CURRENT",
"RAIL17 CURRENT",
"RAIL18 CURRENT",
"RAIL19 CURRENT",
"RAIL0 POWER",
"RAIL1 POWER",
"RAIL2 POWER",
"RAIL3 POWER",
"RAIL4 POWER",
"RAIL5 POWER",
"RAIL6 POWER",
"RAIL7 POWER",
"RAIL8 POWER",
"RAIL9 POWER",
"RAIL10 POWER",
"RAIL11 POWER",
"RAIL12 POWER",
"RAIL13 POWER",
"RAIL14 POWER",
"RAIL15 POWER",
"RAIL16 POWER",
"RAIL17 POWER",
"RAIL18 POWER",
"RAIL19 POWER",
"DF BUSY",
"VCN BUSY",
"IOHC BUSY",
"MMHUB BUSY",
"ATHUB BUSY",
"OSSSYS BUSY",
"HDP BUSY",
"SDMA BUSY",
"SHUB BUSY",
"BIF BUSY",
"ACP BUSY",
"SST0 BUSY",
"SST1 BUSY",
"USB0 BUSY",
"USB1 BUSY",
"CCM READS",
"CCM WRITES",
"GCM 64B READS",
"GCM 64B WRITES",
"GCM 32B READS/WRITES",
"MMHUB READS",
"MMHUB WRITES",
"DCE READS",
"IO READS/WRITES",
"CS READS",
"CS WRITES",
"MAX DRAM BANDWIDTH",
"VCN BUSY",
"VCN DECODE",
"VCN ENCODE GEN",
"VCN ENCODE LOW",
"VCN ENCODE REAL",
"VCN PG",
"VCN JPEG",
"CORE 0 POWER",
"CORE 1 POWER",
"CORE 2 POWER",
"CORE 3 POWER",
"CORE 4 POWER",
"CORE 5 POWER",
"CORE 6 POWER",
"CORE 7 POWER",
"CORE 0 VOLTAGE",
"CORE 1 VOLTAGE",
"CORE 2 VOLTAGE",
"CORE 3 VOLTAGE",
"CORE 4 VOLTAGE",
"CORE 5 VOLTAGE",
"CORE 6 VOLTAGE",
"CORE 7 VOLTAGE",
"CORE 0 TEMP",
"CORE 1 TEMP",
"CORE 2 TEMP",
"CORE 3 TEMP",
"CORE 4 TEMP",
"CORE 5 TEMP",
"CORE 6 TEMP",
"CORE 7 TEMP",
"CORE 0 FIT",
"CORE 1 FIT",
"CORE 2 FIT",
"CORE 3 FIT",
"CORE 4 FIT",
"CORE 5 FIT",
"CORE 6 FIT",
"CORE 7 FIT",
"CORE 0 IDD MAX",
"CORE 1 IDD MAX",
"CORE 2 IDD MAX",
"CORE 3 IDD MAX",
"CORE 4 IDD MAX",
"CORE 5 IDD MAX",
"CORE 6 IDD MAX",
"CORE 7 IDD MAX",
"CORE 0 FREQ",
"CORE 1 FREQ",
"CORE 2 FREQ",
"CORE 3 FREQ",
"CORE 4 FREQ",
"CORE 5 FREQ",
"CORE 6 FREQ",
"CORE 7 FREQ",
"CORE 0 FREQ EFF",
"CORE 1 FREQ EFF",
"CORE 2 FREQ EFF",
"CORE 3 FREQ EFF",
"CORE 4 FREQ EFF",
"CORE 5 FREQ EFF",
"CORE 6 FREQ EFF",
"CORE 7 FREQ EFF",
"CORE 0 C0",
"CORE 1 C0",
"CORE 2 C0",
"CORE 3 C0",
"CORE 4 C0",
"CORE 5 C0",
"CORE 6 C0",
"CORE 7 C0",
"CORE 0 CC1",
"CORE 1 CC1",
"CORE 2 CC1",
"CORE 3 CC1",
"CORE 4 CC1",
"CORE 5 CC1",
"CORE 6 CC1",
"CORE 7 CC1",
"CORE 0 CC6",
"CORE 1 CC6",
"CORE 2 CC6",
"CORE 3 CC6",
"CORE 4 CC6",
"CORE 5 CC6",
"CORE 6 CC6",
"CORE 7 CC6",
"CORE 0 CKS FDD",
"CORE 1 CKS FDD",
"CORE 2 CKS FDD",
"CORE 3 CKS FDD",
"CORE 4 CKS FDD",
"CORE 5 CKS FDD",
"CORE 6 CKS FDD",
"CORE 7 CKS FDD",
"CORE 0 CI FDD",
"CORE 1 CI FDD",
"CORE 2 CI FDD",
"CORE 3 CI FDD",
"CORE 4 CI FDD",
"CORE 5 CI FDD",
"CORE 6 CI FDD",
"CORE 7 CI FDD",
"CORE 0 IRM",
"CORE 1 IRM",
"CORE 2 IRM",
"CORE 3 IRM",
"CORE 4 IRM",
"CORE 5 IRM",
"CORE 6 IRM",
"CORE 7 IRM",
"CORE 0 PSTATE",
"CORE 1 PSTATE",
"CORE 2 PSTATE",
"CORE 3 PSTATE",
"CORE 4 PSTATE",
"CORE 5 PSTATE",
"CORE 6 PSTATE",
"CORE 7 PSTATE",
"CORE 0 CPPC MAX",
"CORE 1 CPPC MAX",
"CORE 2 CPPC MAX",
"CORE 3 CPPC MAX",
"CORE 4 CPPC MAX",
"CORE 5 CPPC MAX",
"CORE 6 CPPC MAX",
"CORE 7 CPPC MAX",
"CORE 0 CPPC MIN",
"CORE 1 CPPC MIN",
"CORE 2 CPPC MIN",
"CORE 3 CPPC MIN",
"CORE 4 CPPC MIN",
"CORE 5 CPPC MIN",
"CORE 6 CPPC MIN",
"CORE 7 CPPC MIN",
"CORE 0 CPPC EPP",
"CORE 1 CPPC EPP",
"CORE 2 CPPC EPP",
"CORE 3 CPPC EPP",
"CORE 4 CPPC EPP",
"CORE 5 CPPC EPP",
"CORE 6 CPPC EPP",
"CORE 7 CPPC EPP",
"CORE 0 SC LIMIT",
"CORE 1 SC LIMIT",
"CORE 2 SC LIMIT",
"CORE 3 SC LIMIT",
"CORE 4 SC LIMIT",
"CORE 5 SC LIMIT",
"CORE 6 SC LIMIT",
"CORE 7 SC LIMIT",
"CORE 0 SC CAC",
"CORE 1 SC CAC",
"CORE 2 SC CAC",
"CORE 3 SC CAC",
"CORE 4 SC CAC",
"CORE 5 SC CAC",
"CORE 6 SC CAC",
"CORE 7 SC CAC",
"CORE 0 SC RESIDENCY",
"CORE 1 SC RESIDENCY",
"CORE 2 SC RESIDENCY",
"CORE 3 SC RESIDENCY",
"CORE 4 SC RESIDENCY",
"CORE 5 SC RESIDENCY",
"CORE 6 SC RESIDENCY",
"CORE 7 SC RESIDENCY",
"CORE 0 UOPS CLK",
"CORE 1 UOPS CLK",
"CORE 2 UOPS CLK",
"CORE 3 UOPS CLK",
"CORE 4 UOPS CLK",
"CORE 5 UOPS CLK",
"CORE 6 UOPS CLK",
"CORE 7 UOPS CLK",
"CORE 0 UOPS",
"CORE 1 UOPS",
"CORE 2 UOPS",
"CORE 3 UOPS",
"CORE 4 UOPS",
"CORE 5 UOPS",
"CORE 6 UOPS",
"CORE 7 UOPS",
"CORE 0 MEM LATENCY",
"CORE 1 MEM LATENCY",
"CORE 2 MEM LATENCY",
"CORE 3 MEM LATENCY",
"CORE 4 MEM LATENCY",
"CORE 5 MEM LATENCY",
"CORE 6 MEM LATENCY",
"CORE 7 MEM LATENCY",
"L3 LOGIC POWER",
"L3 VDDM POWER",
"L3 TEMP",
"L3 FIT",
"L3 IDD MAX",
"L3 FREQ",
"L3 FREQ EFFECTIVE",
"L3 CKS FDD",
"L3 CCA THRESH",
"L3 CCA CAC",
"L3 CCA ACTIVATION",
"L3 EDC LIMIT",
"L3 EDC CAC",
"L3 EDC RESIDENCY",
"L3 FLL BTC",
"GFX VOLTAGE",
"GFX TEMP",
"GFX IDD MAX",
"GFX FREQ",
"GFX FREQ EFFECTIVE",
"GFX BUSY",
"GFX CGPG",
"GFX EDC LIMIT",
"GFX EDC RESIDENCY",
"GFX DEM RESIDENCY",
"FCLK FREQ",
"UCLK FREQ",
"MCLK FREQ",
"VCLK FREQ",
"DCLK FREQ",
"SOCCLK FREQ",
"LCLK FREQ",
"SHUB FREQ",
"MP0CLK FREQ",
"DCFCLK FREQ",
"FCLK FREQ EFF",
"UCLK FREQ EFF",
"MCLK FREQ EFF",
"VCLK FREQ EFF",
"DCLK FREQ EFF",
"SOCCLK FREQ EFF",
"LCLK FREQ EFF",
"SHUBCLK FREQ EFF",
"MP0CLK FREQ EFF",
"DCFCLK FREQ EFF",
"VCLK STATE Freq 0",
"VCLK STATE Freq 1",
"VCLK STATE Freq 2",
"VCLK STATE Freq 3",
"VCLK STATE Freq 4",
"VCLK STATE Freq 5",
"VCLK STATE Freq 6",
"VCLK STATE Freq 7",
"DCLK STATE Freq 0",
"DCLK STATE Freq 1",
"DCLK STATE Freq 2",
"DCLK STATE Freq 3",
"DCLK STATE Freq 4",
"DCLK STATE Freq 5",
"DCLK STATE Freq 6",
"DCLK STATE Freq 7",
"SOCCLK STATE Freq 0",
"SOCCLK STATE Freq 1",
"SOCCLK STATE Freq 2",
"SOCCLK STATE Freq 3",
"SOCCLK STATE Freq 4",
"SOCCLK STATE Freq 5",
"SOCCLK STATE Freq 6",
"SOCCLK STATE Freq 7",
"LCLK STATE Freq 0",
"LCLK STATE Freq 1",
"LCLK STATE Freq 2",
"LCLK STATE Freq 3",
"LCLK STATE Freq 4",
"LCLK STATE Freq 5",
"LCLK STATE Freq 6",
"LCLK STATE Freq 7",
"SHUB STATE Freq 0",
"SHUB STATE Freq 1",
"SHUB STATE Freq 2",
"SHUB STATE Freq 3",
"SHUB STATE Freq 4",
"SHUB STATE Freq 5",
"SHUB STATE Freq 6",
"SHUB STATE Freq 7",
"MP0 STATE Freq 0",
"MP0 STATE Freq 1",
"MP0 STATE Freq 2",
"MP0 STATE Freq 3",
"MP0 STATE Freq 4",
"MP0 STATE Freq 5",
"MP0 STATE Freq 6",
"MP0 STATE Freq 7",
"DCFCLK STATE Freq 0",
"DCFCLK STATE Freq 1",
"DCFCLK STATE Freq 2",
"DCFCLK STATE Freq 3",
"DCFCLK STATE Freq 4",
"DCFCLK STATE Freq 5",
"DCFCLK STATE Freq 6",
"DCFCLK STATE Freq 7",
"VCN STATE RESIDENCY0",
"VCN STATE RESIDENCY1",
"VCN STATE RESIDENCY2",
"VCN STATE RESIDENCY3",
"VCN STATE RESIDENCY4",
"VCN STATE RESIDENCY5",
"VCN STATE RESIDENCY6",
"VCN STATE RESIDENCY7",
"SOCCLK STATE RESIDENCY0",
"SOCCLK STATE RESIDENCY1",
"SOCCLK STATE RESIDENCY2",
"SOCCLK STATE RESIDENCY3",
"SOCCLK STATE RESIDENCY4",
"SOCCLK STATE RESIDENCY5",
"SOCCLK STATE RESIDENCY6",
"SOCCLK STATE RESIDENCY7",
"LCLK STATE RESIDENCY0",
"LCLK STATE RESIDENCY1",
"LCLK STATE RESIDENCY2",
"LCLK STATE RESIDENCY3",
"LCLK STATE RESIDENCY4",
"LCLK STATE RESIDENCY5",
"LCLK STATE RESIDENCY6",
"LCLK STATE RESIDENCY7",
"SHUB STATE RESIDENCY0",
"SHUB STATE RESIDENCY1",
"SHUB STATE RESIDENCY2",
"SHUB STATE RESIDENCY3",
"SHUB STATE RESIDENCY4",
"SHUB STATE RESIDENCY5",
"SHUB STATE RESIDENCY6",
"SHUB STATE RESIDENCY7",
"MP0CLK STATE RESIDENCY0",
"MP0CLK STATE RESIDENCY1",
"MP0CLK STATE RESIDENCY2",
"MP0CLK STATE RESIDENCY3",
"MP0CLK STATE RESIDENCY4",
"MP0CLK STATE RESIDENCY5",
"MP0CLK STATE RESIDENCY6",
"MP0CLK STATE RESIDENCY7",
"DCFCLK STATE RESIDENCY0",