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Backup_20170904_1047
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Backup_20170904_1047
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DATA_BLOCK "WBI"
TITLE =
NAME : WBI
VERSION : 0.1
STRUCT
IW128 : BOOL ; //Spare Wire Break
C8_WBFPLVL : BOOL ; //Fish Pass Water Level in the top 10m of the Fish Pass Wire Break
C8_WBFPWG_POS : BOOL ; //Fish Pass Weir Gate Position for Angular Transmitter Wire Break
<DeleteStart>
Addition1
Addition2
Addition3
<DeleteEnd>
END_STRUCT ;
BEGIN
IW128 := FALSE;
C8_WBFPLVL := FALSE;
C8_WBFPWG_POS := FALSE;
IW134 := FALSE;
Addition4
IW136 := TRUE;
IW138 := TRUE;
IW140 := TRUE;
Add010101
IW142 := TRUE;
END_DATA_BLOCK
DATA_BLOCK "ORI"
TITLE =
NAME : ORI
VERSION : 0.1
STRUCT
IW128 : BOOL ; //Spare Over Range
C8_ORFPLVL : BOOL ; //Fish Pass Water Level in the top 10m of the Fish Pass Over Range
C8_ORFPWG_POS : BOOL ; //Fish Pass Weir Gate Position for Angular Transmitter Over Range
END_STRUCT ;
BEGIN
IW128 := TRUE;
C8_ORFPLVL := FALSE;
C8_ORFPWG_POS := FALSE;
IW134 := FALSE;
IW136 := FALSE;
IW138 := FALSE;
IW140 := FALSE;
IW142 := FALSE;
END_DATA_BLOCK
DATA_BLOCK "RACK FAULT ALARMS"
TITLE =
NAME : RCKFLT
VERSION : 0.1
STRUCT
MasterDP1 : BOOL ; //Fault DP MASTER 1
CPU_Slot1 : BOOL ; //Fault Rack CPU 1 Slot 1
CPU_Slot2 : BOOL ; //Fault Rack CPU 1 Slot 2
CPU_Slot3 : BOOL ; //Fault Rack CPU 1 Slot 3
CPU_Slot4 : BOOL ; //Fault Rack CPU 1 Slot 4
CPU_Slot5 : BOOL ; //Fault Rack CPU 1 Slot 5
CPU_Slot6 : BOOL ; //Fault Rack CPU 1 Slot 6
CPU_Slot7 : BOOL ; //Fault Rack CPU 1 Slot 7
CPU_Slot8 : BOOL ; //Fault Rack CPU 1 Slot 8
CPU_Slot9 : BOOL ; //Fault Rack CPU 1 Slot 9
CPU_Slot10 : BOOL ; //Fault Rack CPU 1 Slot 10
CPU_Slot11 : BOOL ; //Fault Rack CPU 1 Slot 11
CPU_Slot12 : BOOL ; //Fault Rack CPU 1 Slot 12
CPU_Slot13 : BOOL ; //Fault Rack CPU 1 Slot 13
CPU_Slot14 : BOOL ; //Fault Rack CPU 1 Slot 14
CPU_Slot15 : BOOL ; //Fault Rack CPU 1 Slot 15
Bus1_SlaveDP2 : BOOL ; //Fault Rack Module DP2
Bus1_SlaveDP2_Slot1 : BOOL ; //Fault Rack Module DP2 Slot 1
Bus1_SlaveDP2_Slot2 : BOOL ; //Fault Rack Module DP2 Slot 2
Bus1_SlaveDP2_Slot3 : BOOL ; //Fault Rack Module DP2 Slot 3
Bus1_SlaveDP2_Slot4 : BOOL ; //Fault Rack Module DP2 Slot 4
Bus1_SlaveDP2_Slot5 : BOOL ; //Fault Rack Module DP2 Slot 5
Bus1_SlaveDP2_Slot6 : BOOL ; //Fault Rack Module DP2 Slot 6
Bus1_SlaveDP2_Slot7 : BOOL ; //Fault Rack Module DP2 Slot 7
Bus1_SlaveDP2_Slot8 : BOOL ; //Fault Rack Module DP2 Slot 8
Bus1_SlaveDP2_Slot9 : BOOL ; //Fault Rack Module DP2 Slot 9
Bus1_SlaveDP2_Slot10 : BOOL ; //Fault Rack Module DP2 Slot 10
Bus1_SlaveDP2_Slot11 : BOOL ; //Fault Rack Module DP2 Slot 11
Bus1_SlaveDP2_Slot12 : BOOL ; //Fault Rack Module DP2 Slot 12
Bus1_SlaveDP2_Slot13 : BOOL ; //Fault Rack Module DP2 Slot 13
Bus1_SlaveDP2_Slot14 : BOOL ; //Fault Rack Module DP2 Slot 14
Bus1_SlaveDP2_Slot15 : BOOL ; //Fault Rack Module DP2 Slot 15
Bus1_SlaveDP3 : BOOL ; //Fault Rack Module DP3
Bus1_SlaveDP3_Slot1 : BOOL ; //Fault Rack Module DP3 Slot 1
Bus1_SlaveDP3_Slot2 : BOOL ; //Fault Rack Module DP3 Slot 2
Bus1_SlaveDP3_Slot3 : BOOL ; //Fault Rack Module DP3 Slot 3
Bus1_SlaveDP3_Slot4 : BOOL ; //Fault Rack Module DP3 Slot 4
Bus1_SlaveDP3_Slot5 : BOOL ; //Fault Rack Module DP3 Slot 5
Bus1_SlaveDP3_Slot6 : BOOL ; //Fault Rack Module DP3 Slot 6
Bus1_SlaveDP3_Slot7 : BOOL ; //Fault Rack Module DP3 Slot 7
Bus1_SlaveDP3_Slot8 : BOOL ; //Fault Rack Module DP3 Slot 8
Bus1_SlaveDP3_Slot9 : BOOL ; //Fault Rack Module DP3 Slot 9
Bus1_SlaveDP3_Slot10 : BOOL ; //Fault Rack Module DP3 Slot 10
Bus1_SlaveDP3_Slot11 : BOOL ; //Fault Rack Module DP3 Slot 11
Bus1_SlaveDP3_Slot12 : BOOL ; //Fault Rack Module DP3 Slot 12
Bus1_SlaveDP3_Slot13 : BOOL ; //Fault Rack Module DP3 Slot 13
Bus1_SlaveDP3_Slot14 : BOOL ; //Fault Rack Module DP3 Slot 14
Bus1_SlaveDP3_Slot15 : BOOL ; //Fault Rack Module DP3 Slot 15
Bus1_SlaveDP4 : BOOL ; //Fault Rack Module DP4
Bus1_SlaveDP4_Slot1 : BOOL ; //Fault Rack Module DP4 Slot 1
Bus1_SlaveDP4_Slot2 : BOOL ; //Fault Rack Module DP4 Slot 2
Bus1_SlaveDP4_Slot3 : BOOL ; //Fault Rack Module DP4 Slot 3
Bus1_SlaveDP4_Slot4 : BOOL ; //Fault Rack Module DP4 Slot 4
Bus1_SlaveDP4_Slot5 : BOOL ; //Fault Rack Module DP4 Slot 5
Bus1_SlaveDP4_Slot6 : BOOL ; //Fault Rack Module DP4 Slot 6
Bus1_SlaveDP4_Slot7 : BOOL ; //Fault Rack Module DP4 Slot 7
Bus1_SlaveDP4_Slot8 : BOOL ; //Fault Rack Module DP4 Slot 8
Bus1_SlaveDP4_Slot9 : BOOL ; //Fault Rack Module DP4 Slot 9
Bus1_SlaveDP4_Slot10 : BOOL ; //Fault Rack Module DP4 Slot 10
Bus1_SlaveDP4_Slot11 : BOOL ; //Fault Rack Module DP4 Slot 11
Bus1_SlaveDP4_Slot12 : BOOL ; //Fault Rack Module DP4 Slot 12
Bus1_SlaveDP4_Slot13 : BOOL ; //Fault Rack Module DP4 Slot 13
Bus1_SlaveDP4_Slot14 : BOOL ; //Fault Rack Module DP4 Slot 14
Bus1_SlaveDP4_Slot15 : BOOL ; //Fault Rack Module DP4 Slot 15
Bus1_SlaveDP5 : BOOL ; //Fault Rack Module DP5
Bus1_SlaveDP5_Slot1 : BOOL ; //Fault Rack Module DP5 Slot 1
Bus1_SlaveDP5_Slot2 : BOOL ; //Fault Rack Module DP5 Slot 2
Bus1_SlaveDP5_Slot3 : BOOL ; //Fault Rack Module DP5 Slot 3
Bus1_SlaveDP5_Slot4 : BOOL ; //Fault Rack Module DP5 Slot 4
Bus1_SlaveDP5_Slot5 : BOOL ; //Fault Rack Module DP5 Slot 5
Bus1_SlaveDP5_Slot6 : BOOL ; //Fault Rack Module DP5 Slot 6
Bus1_SlaveDP5_Slot7 : BOOL ; //Fault Rack Module DP5 Slot 7
Bus1_SlaveDP5_Slot8 : BOOL ; //Fault Rack Module DP5 Slot 8
Bus1_SlaveDP5_Slot9 : BOOL ; //Fault Rack Module DP5 Slot 9
Bus1_SlaveDP5_Slot10 : BOOL ; //Fault Rack Module DP5 Slot 10
Bus1_SlaveDP5_Slot11 : BOOL ; //Fault Rack Module DP5 Slot 11
Bus1_SlaveDP5_Slot12 : BOOL ; //Fault Rack Module DP5 Slot 12
Bus1_SlaveDP5_Slot13 : BOOL ; //Fault Rack Module DP5 Slot 13
Bus1_SlaveDP5_Slot14 : BOOL ; //Fault Rack Module DP5 Slot 14
Bus1_SlaveDP5_Slot15 : BOOL ; //Fault Rack Module DP5 Slot 15
Bus1_SlaveDP6 : BOOL ; //Fault Rack Module DP6
Bus1_SlaveDP6_Slot1 : BOOL ; //Fault Rack Module DP6 Slot 1
Bus1_SlaveDP6_Slot2 : BOOL ; //Fault Rack Module DP6 Slot 2
Bus1_SlaveDP6_Slot3 : BOOL ; //Fault Rack Module DP6 Slot 3
Bus1_SlaveDP6_Slot4 : BOOL ; //Fault Rack Module DP6 Slot 4
Bus1_SlaveDP6_Slot5 : BOOL ; //Fault Rack Module DP6 Slot 5
Bus1_SlaveDP6_Slot6 : BOOL ; //Fault Rack Module DP6 Slot 6
Bus1_SlaveDP6_Slot7 : BOOL ; //Fault Rack Module DP6 Slot 7
Bus1_SlaveDP6_Slot8 : BOOL ; //Fault Rack Module DP6 Slot 8
Bus1_SlaveDP6_Slot9 : BOOL ; //Fault Rack Module DP6 Slot 9
Bus1_SlaveDP6_Slot10 : BOOL ; //Fault Rack Module DP6 Slot 10
Bus1_SlaveDP6_Slot11 : BOOL ; //Fault Rack Module DP6 Slot 11
Bus1_SlaveDP6_Slot12 : BOOL ; //Fault Rack Module DP6 Slot 12
Bus1_SlaveDP6_Slot13 : BOOL ; //Fault Rack Module DP6 Slot 13
Bus1_SlaveDP6_Slot14 : BOOL ; //Fault Rack Module DP6 Slot 14
Bus1_SlaveDP6_Slot15 : BOOL ; //Fault Rack Module DP6 Slot 15
Bus1_SlaveDP7 : BOOL ; //Fault Rack Module DP7
Bus1_SlaveDP7_Slot1 : BOOL ; //Fault Rack Module DP7 Slot 1
Bus1_SlaveDP7_Slot2 : BOOL ; //Fault Rack Module DP7 Slot 2
Bus1_SlaveDP7_Slot3 : BOOL ; //Fault Rack Module DP7 Slot 3
Bus1_SlaveDP7_Slot4 : BOOL ; //Fault Rack Module DP7 Slot 4
Bus1_SlaveDP7_Slot5 : BOOL ; //Fault Rack Module DP7 Slot 5
Bus1_SlaveDP7_Slot6 : BOOL ; //Fault Rack Module DP7 Slot 6
Bus1_SlaveDP7_Slot7 : BOOL ; //Fault Rack Module DP7 Slot 7
Bus1_SlaveDP7_Slot8 : BOOL ; //Fault Rack Module DP7 Slot 8
Bus1_SlaveDP7_Slot9 : BOOL ; //Fault Rack Module DP7 Slot 9
Bus1_SlaveDP7_Slot10 : BOOL ; //Fault Rack Module DP7 Slot 10
Bus1_SlaveDP7_Slot11 : BOOL ; //Fault Rack Module DP7 Slot 11
Bus1_SlaveDP7_Slot12 : BOOL ; //Fault Rack Module DP7 Slot 12
Bus1_SlaveDP7_Slot13 : BOOL ; //Fault Rack Module DP7 Slot 13
Bus1_SlaveDP7_Slot14 : BOOL ; //Fault Rack Module DP7 Slot 14
Bus1_SlaveDP7_Slot15 : BOOL ; //Fault Rack Module DP7 Slot 15
Bus1_SlaveDP8 : BOOL ; //Fault Rack Module DP8
Bus1_SlaveDP8_Slot1 : BOOL ; //Fault Rack Module DP8 Slot 1
Bus1_SlaveDP8_Slot2 : BOOL ; //Fault Rack Module DP8 Slot 2
Bus1_SlaveDP8_Slot3 : BOOL ; //Fault Rack Module DP8 Slot 3
Bus1_SlaveDP8_Slot4 : BOOL ; //Fault Rack Module DP8 Slot 4
Bus1_SlaveDP8_Slot5 : BOOL ; //Fault Rack Module DP8 Slot 5
Bus1_SlaveDP8_Slot6 : BOOL ; //Fault Rack Module DP8 Slot 6
Bus1_SlaveDP8_Slot7 : BOOL ; //Fault Rack Module DP8 Slot 7
Bus1_SlaveDP8_Slot8 : BOOL ; //Fault Rack Module DP8 Slot 8
Bus1_SlaveDP8_Slot9 : BOOL ; //Fault Rack Module DP8 Slot 9
Bus1_SlaveDP8_Slot10 : BOOL ; //Fault Rack Module DP8 Slot 10
Bus1_SlaveDP8_Slot11 : BOOL ; //Fault Rack Module DP8 Slot 11
Bus1_SlaveDP8_Slot12 : BOOL ; //Fault Rack Module DP8 Slot 12
Bus1_SlaveDP8_Slot13 : BOOL ; //Fault Rack Module DP8 Slot 13
Bus1_SlaveDP8_Slot14 : BOOL ; //Fault Rack Module DP8 Slot 14
Bus1_SlaveDP8_Slot15 : BOOL ; //Fault Rack Module DP8 Slot 15
END_STRUCT ;
BEGIN
MasterDP1 := FALSE;
CPU_Slot1 := FALSE;
CPU_Slot2 := FALSE;
CPU_Slot3 := FALSE;
CPU_Slot4 := FALSE;
CPU_Slot5 := FALSE;
CPU_Slot6 := FALSE;
CPU_Slot7 := FALSE;
CPU_Slot8 := FALSE;
CPU_Slot9 := FALSE;
CPU_Slot10 := FALSE;
CPU_Slot11 := FALSE;
CPU_Slot12 := FALSE;
CPU_Slot13 := FALSE;
CPU_Slot14 := FALSE;
CPU_Slot15 := FALSE;
Bus1_SlaveDP2 := FALSE;
Bus1_SlaveDP2_Slot1 := FALSE;
Bus1_SlaveDP2_Slot2 := FALSE;
Bus1_SlaveDP2_Slot3 := FALSE;
Bus1_SlaveDP2_Slot4 := FALSE;
Bus1_SlaveDP2_Slot5 := FALSE;
Bus1_SlaveDP2_Slot6 := FALSE;
Bus1_SlaveDP2_Slot7 := FALSE;
Bus1_SlaveDP2_Slot8 := FALSE;
Bus1_SlaveDP2_Slot9 := FALSE;
Bus1_SlaveDP2_Slot10 := FALSE;
Bus1_SlaveDP2_Slot11 := FALSE;
Bus1_SlaveDP2_Slot12 := FALSE;
Bus1_SlaveDP2_Slot13 := FALSE;
Bus1_SlaveDP2_Slot14 := FALSE;
Bus1_SlaveDP2_Slot15 := FALSE;
Bus1_SlaveDP3 := FALSE;
Bus1_SlaveDP3_Slot1 := FALSE;
Bus1_SlaveDP3_Slot2 := FALSE;
Bus1_SlaveDP3_Slot3 := FALSE;
Bus1_SlaveDP3_Slot4 := FALSE;
Bus1_SlaveDP3_Slot5 := FALSE;
Bus1_SlaveDP3_Slot6 := FALSE;
Bus1_SlaveDP3_Slot7 := FALSE;
Bus1_SlaveDP3_Slot8 := FALSE;
Bus1_SlaveDP3_Slot9 := FALSE;
Bus1_SlaveDP3_Slot10 := FALSE;
Bus1_SlaveDP3_Slot11 := FALSE;
Bus1_SlaveDP3_Slot12 := FALSE;
Bus1_SlaveDP3_Slot13 := FALSE;
Bus1_SlaveDP3_Slot14 := FALSE;
Bus1_SlaveDP3_Slot15 := FALSE;
Bus1_SlaveDP4 := FALSE;
Bus1_SlaveDP4_Slot1 := FALSE;
Bus1_SlaveDP4_Slot2 := FALSE;
Bus1_SlaveDP4_Slot3 := FALSE;
Bus1_SlaveDP4_Slot4 := FALSE;
Bus1_SlaveDP4_Slot5 := FALSE;
Bus1_SlaveDP4_Slot6 := FALSE;
Bus1_SlaveDP4_Slot7 := FALSE;
Bus1_SlaveDP4_Slot8 := FALSE;
Bus1_SlaveDP4_Slot9 := FALSE;
Bus1_SlaveDP4_Slot10 := FALSE;
Bus1_SlaveDP4_Slot11 := FALSE;
Bus1_SlaveDP4_Slot12 := FALSE;
Bus1_SlaveDP4_Slot13 := FALSE;
Bus1_SlaveDP4_Slot14 := FALSE;
Bus1_SlaveDP4_Slot15 := FALSE;
Bus1_SlaveDP5 := FALSE;
Bus1_SlaveDP5_Slot1 := FALSE;
Bus1_SlaveDP5_Slot2 := FALSE;
Bus1_SlaveDP5_Slot3 := FALSE;
Bus1_SlaveDP5_Slot4 := FALSE;
Bus1_SlaveDP5_Slot5 := FALSE;
Bus1_SlaveDP5_Slot6 := FALSE;
Bus1_SlaveDP5_Slot7 := FALSE;
Bus1_SlaveDP5_Slot8 := FALSE;
Bus1_SlaveDP5_Slot9 := FALSE;
Bus1_SlaveDP5_Slot10 := FALSE;
Bus1_SlaveDP5_Slot11 := FALSE;
Bus1_SlaveDP5_Slot12 := FALSE;
Bus1_SlaveDP5_Slot13 := FALSE;
Bus1_SlaveDP5_Slot14 := FALSE;
Bus1_SlaveDP5_Slot15 := FALSE;
Bus1_SlaveDP6 := FALSE;
Bus1_SlaveDP6_Slot1 := FALSE;
Bus1_SlaveDP6_Slot2 := FALSE;
Bus1_SlaveDP6_Slot3 := FALSE;
Bus1_SlaveDP6_Slot4 := FALSE;
Bus1_SlaveDP6_Slot5 := FALSE;
Bus1_SlaveDP6_Slot6 := FALSE;
Bus1_SlaveDP6_Slot7 := FALSE;
Bus1_SlaveDP6_Slot8 := FALSE;
Bus1_SlaveDP6_Slot9 := FALSE;
Bus1_SlaveDP6_Slot10 := FALSE;
Bus1_SlaveDP6_Slot11 := FALSE;
Bus1_SlaveDP6_Slot12 := FALSE;
Bus1_SlaveDP6_Slot13 := FALSE;
Bus1_SlaveDP6_Slot14 := FALSE;
Bus1_SlaveDP6_Slot15 := FALSE;
Bus1_SlaveDP7 := FALSE;
Bus1_SlaveDP7_Slot1 := FALSE;
Bus1_SlaveDP7_Slot2 := FALSE;
Bus1_SlaveDP7_Slot3 := FALSE;
Bus1_SlaveDP7_Slot4 := FALSE;
Bus1_SlaveDP7_Slot5 := FALSE;
Bus1_SlaveDP7_Slot6 := FALSE;
Bus1_SlaveDP7_Slot7 := FALSE;
Bus1_SlaveDP7_Slot8 := FALSE;
Bus1_SlaveDP7_Slot9 := FALSE;
Bus1_SlaveDP7_Slot10 := FALSE;
Bus1_SlaveDP7_Slot11 := FALSE;
Bus1_SlaveDP7_Slot12 := FALSE;
Bus1_SlaveDP7_Slot13 := FALSE;
Bus1_SlaveDP7_Slot14 := FALSE;
Bus1_SlaveDP7_Slot15 := FALSE;
Bus1_SlaveDP8 := FALSE;
Bus1_SlaveDP8_Slot1 := FALSE;
Bus1_SlaveDP8_Slot2 := FALSE;
Bus1_SlaveDP8_Slot3 := FALSE;
Bus1_SlaveDP8_Slot4 := FALSE;
Bus1_SlaveDP8_Slot5 := FALSE;
Bus1_SlaveDP8_Slot6 := FALSE;
Bus1_SlaveDP8_Slot7 := FALSE;
Bus1_SlaveDP8_Slot8 := FALSE;
Bus1_SlaveDP8_Slot9 := FALSE;
Bus1_SlaveDP8_Slot10 := FALSE;
Bus1_SlaveDP8_Slot11 := FALSE;
Bus1_SlaveDP8_Slot12 := FALSE;
Bus1_SlaveDP8_Slot13 := FALSE;
Bus1_SlaveDP8_Slot14 := FALSE;
Bus1_SlaveDP8_Slot15 := FALSE;
END_DATA_BLOCK
DATA_BLOCK "AI"
TITLE =
NAME : AI
VERSION : 0.0
STRUCT
IW128 : REAL ; //Spare
C8_FPLVL : REAL ; //Fish Pass Water Level in the top 10m of the Fish Pass
C8_FPWG_POS : REAL ; //Fish Pass Weir Gate Position for Angular Transmitter
IW134 : REAL ; //Spare
IW136 : REAL ; //Spare
IW138 : REAL ; //Spare
IW140 : REAL ; //Spare
IW142 : REAL ; //Spare
END_STRUCT ;
BEGIN
IW128 := -8.888000e+003;
C8_FPLVL := 3.335023e+001;
C8_FPWG_POS := 3.498320e+001;
IW134 := 9.872685e+001;
IW136 := -8.888000e+003;
IW138 := -8.888000e+003;
IW140 := -8.888000e+003;
IW142 := -8.888000e+003;
END_DATA_BLOCK
DATA_BLOCK "I"
TITLE =
NAME : I
VERSION : 0.1
STRUCT
Placeholder : ARRAY [1 .. 8 ] OF //Not Actual DI
BYTE ;
C8_FPWG_OPENLS : BOOL ; //Fish Pass Weir Gate Limit Switch Is Open
C8_FPWG_CLOSELS : BOOL ; //Fish Pass Weir Gate Limit Switch Is Closed
C8_FPWG_MOT_OVL : BOOL ; //Fish Pass Weir Gate Motor OverLoad - NC
C8_FPWG_ESTOP : BOOL ; //Fish Pass Weir Gate Local Panel Estop - NO
C8_FPWG_MANMODE : BOOL ; //Fish Pass Weir Gate Local Panel Key Switch in Manual
C8_FPWG_AUTOMODE : BOOL ; //Fish Pass Weir Gate Local Panel Key Switch in Auto
C8_FPWG_OPENPS : BOOL ; //Fish Pass Weir Gate Open Pushbutton
C8_FPWG_STOPPS : BOOL ; //Fish Pass Weir Gate Stop Pushbutton
C8_FPWG_CLOSEPS : BOOL ; //Fish Pass Weir Gate Close Pushbutton
C8_FPLOG1_OPENLS : BOOL ; //Fish Pass Lower Gate 1 Limit Switch Is Open NO
C8_FPLOG1_CLOSELS : BOOL ; //Fish Pass Lower Gate 1 Limit Switch Is Closed - NO
C8_FPLOG1_MOT_OVL : BOOL ; //Fish Pass Lower Gate 1 Motor OverLoad - NC
C8_FPLOG1_ESTOP : BOOL ; //Fish Pass Lower Gate 1 Local Panel Estop
C8_FPLOG1_MANMODE : BOOL ; //Fish Pass Lower Gate 1 Local Panel Key Switch in Manual
C8_FPLOG1_AUTOMODE : BOOL ; //Fish Pass Lower Gate 1 Local Panel Key Switch in Auto
I9_7 : BOOL ; //Spare DI
C8_FPLOG2_OPENLS : BOOL ; //Fish Pass Lower Gate 2 Limit Switch Is Open NO
C8_FPLOG2_CLOSELS : BOOL ; //Fish Pass Lower Gate 2 Limit Switch Is Closed - NO
C8_FPLOG2_MOT_OVL : BOOL ; //Fish Pass Lower Gate 2 Motor OverLoad
C8_FPLOG2_ESTOP : BOOL ; //Fish Pass Lower Gate 2 Local Panel Estop
C8_FPLOG2_MANMODE : BOOL ; //Fish Pass Lower Gate 2 Local Panel Key Switch in Manual
C8_FPLOG2_AUTOMODE : BOOL ; //Fish Pass Lower Gate 2 Local Panel Key Switch in Auto
C8_FPINTAKE_MANMODE : BOOL ; //Fish Pass Intake Panel Key Switch in Manual
C8_FPINTAKE_AUTOMODE : BOOL ; //Fish Pass Intake Panel Key Switch in Auto
C8_FPINTAKE_ESTOP : BOOL ; //Fish Pass Intake Panel Estop
C8_FP_DIRECTION : BOOL ; //Fish Pass Intake Panel Ascending or Descending
C8_FISH_COUNTER : BOOL ; //Fish Pass Fish Counter
I11_3 : BOOL ; //Spare DI
I11_4 : BOOL ; //Spare DI
I11_5 : BOOL ; //Spare DI
I11_6 : BOOL ; //Spare DI
I11_7 : BOOL ; //Spare DI
END_STRUCT ;
BEGIN
Placeholder[1] := B#16#0;
Placeholder[2] := B#16#0;
Placeholder[3] := B#16#0;
Placeholder[4] := B#16#0;
Placeholder[5] := B#16#0;
Placeholder[6] := B#16#0;
Placeholder[7] := B#16#0;
Placeholder[8] := B#16#0;
C8_FPWG_OPENLS := TRUE;
C8_FPWG_CLOSELS := FALSE;
C8_FPWG_MOT_OVL := FALSE;
C8_FPWG_ESTOP := FALSE;
C8_FPWG_MANMODE := FALSE;
C8_FPWG_AUTOMODE := TRUE;
C8_FPWG_OPENPS := FALSE;
C8_FPWG_STOPPS := FALSE;
C8_FPWG_CLOSEPS := FALSE;
C8_FPLOG1_OPENLS := FALSE;
C8_FPLOG1_CLOSELS := TRUE;
C8_FPLOG1_MOT_OVL := FALSE;
C8_FPLOG1_ESTOP := FALSE;
C8_FPLOG1_MANMODE := FALSE;
C8_FPLOG1_AUTOMODE := TRUE;
I9_7 := FALSE;
C8_FPLOG2_OPENLS := FALSE;
C8_FPLOG2_CLOSELS := TRUE;
C8_FPLOG2_MOT_OVL := FALSE;
C8_FPLOG2_ESTOP := FALSE;
C8_FPLOG2_MANMODE := FALSE;
C8_FPLOG2_AUTOMODE := TRUE;
C8_FPINTAKE_MANMODE := FALSE;
C8_FPINTAKE_AUTOMODE := TRUE;
C8_FPINTAKE_ESTOP := FALSE;
C8_FP_DIRECTION := FALSE;
C8_FISH_COUNTER := FALSE;
I11_3 := FALSE;
I11_4 := FALSE;
I11_5 := FALSE;
I11_6 := FALSE;
I11_7 := FALSE;
END_DATA_BLOCK
DATA_BLOCK "HR"
TITLE =
NAME : HR
VERSION : 0.1
STRUCT
PLC_SecOfDay : REAL ; //PLC Time Seconds Past Midnight
TempReal : REAL ; //Temporary Real
AI_Default_Low : REAL ; //AI Wire Break - Default Low Value
AI_Default_High : REAL ; //AI Wire Break - Default High Value
C8_FPLVL_SP : REAL ; //Fish Pass Water Level Inside The Fish Pass SP
C8_FPWG_SP : REAL ; //Fish Pass Weir Gate Open SP
C8_FPTR_SP : REAL ; //Fish Pass Tail Race SP
Spare_28 : REAL ; //Spare
C8_FPWG_SP_LOW : REAL ; //Fish Pass Weir Gate Lower SP Level
C8_FPWG_SP_High : REAL ; //Fish Pass Weir Gate Higher SP Level
C8_FPWG_POS_2 : REAL ; //Fish Pass Weir Gate Level Based On Time
Spare_44 : REAL ; //Spare
Spare_48 : REAL ; //Spare
Spare_52 : REAL ; //Spare
Spare_56 : REAL ; //Spare
Spare_60 : REAL ; //Spare
C8_FPWG_UP_LIMIT : REAL ; //Fish Pass Wier Gate Up Limit
C8_FPWG_DOWN_LIMIT : REAL ; //Fish Pass Wier Gate Down Limit
C8_FPWG_SP_OPEN : REAL ; //Fish Pass Wier Gate Opening SP
C6_HeadRaceLevel : REAL ; //Head Race Level from Drawdown PLC
C6_TailRaceLevel : REAL ; //Tail Race Level from Drawdown PLC
END_STRUCT ;
BEGIN
PLC_SecOfDay := 4.577800e+004;
TempReal := 0.000000e+000;
AI_Default_Low := -8.888000e+003;
AI_Default_High := 8.888000e+003;
C8_FPLVL_SP := 2.740000e+001;
C8_FPWG_SP := 3.050000e-001;
C8_FPTR_SP := 4.530000e+000;
Spare_28 := 0.000000e+000;
C8_FPWG_SP_LOW := 5.000000e-002;
C8_FPWG_SP_High := 5.000000e-002;
C8_FPWG_POS_2 := 0.000000e+000;
Spare_44 := 0.000000e+000;
Spare_48 := 0.000000e+000;
Spare_52 := 3.019000e+001;
Spare_56 := 0.000000e+000;
Spare_60 := 0.000000e+000;
C8_FPWG_UP_LIMIT := 3.313601e+001;
C8_FPWG_DOWN_LIMIT := 3.303601e+001;
C8_FPWG_SP_OPEN := 3.308601e+001;
C6_HeadRaceLevel := 3.339101e+001;
C6_TailRaceLevel := 3.046839e+000;
END_DATA_BLOCK
DATA_BLOCK "HB"
TITLE =
NAME : HB
VERSION : 0.0
STRUCT
C8_Off : BOOL ; //Fish Pass Not Operating
C8_Step01 : BOOL ; //Fish Pass Step 1 Starting Up
C8_Step02 : BOOL ; //Fish Pass Step 2 Starting Up
C8_Step03 : BOOL ; //Fish Pass Step 3 Starting Up
C8_Step04 : BOOL ; //Fish Pass Step 4 Starting Up
C8_Step05 : BOOL ; //Fish Pass Step 5 Starting Up
C8_Step06 : BOOL ; //Fish Pass Step 6 Starting Up
C8_Step07 : BOOL ; //Fish Pass Step 7 Starting Up
C8_Step08 : BOOL ; //Fish Pass Step 8 Starting Up
C8_Step09 : BOOL ; //Fish Pass Step 9 Starting Up
C8_Step10 : BOOL ; //Fish Pass Step 10 Starting Up
C8_Step11 : BOOL ; //Fish Pass Step 11 Starting Up
C8_Step12 : BOOL ; //Fish Pass Step 12 Starting Up
C8_Step13 : BOOL ; //Fish Pass Step 13 Starting Up
C8_Step14 : BOOL ; //Fish Pass Step 14 Starting Up
C8_Step15 : BOOL ; //Fish Pass Step 15 Starting Up
C8_Trans0Ok : BOOL ; //Requirements for transition 0, step 0-step1 OK
C8_Trans1Ok : BOOL ; //Requirements for transition 1, step 1-step 2 OK
C8_Trans2Ok : BOOL ; //Requirements for transition 2, step 2-step 3 OK
C8_Trans3Ok : BOOL ; //Requirements for transition 3, step 3-step 4 OK
C8_Trans4Ok : BOOL ; //Requirements for transition 4, step 4-step 5 OK
C8_Trans5Ok : BOOL ; //Requirements for transition 5, step 5-step 6 OK
C8_Trans6Ok : BOOL ; //Requirements for transition 6, step 6-step 7 OK
C8_Trans7Ok : BOOL ; //Requirements for transition 7, step 7-step 8 OK
C8_Trans8Ok : BOOL ; //Requirements for transition 8, step 8-step9 OK
C8_Trans9Ok : BOOL ; //Requirements for transition 8, step 9-step0 OK
C8_Trans10Ok : BOOL ; //Requirements for transition 8, step 10-step11 OK
C8_Trans11Ok : BOOL ; //Requirements for transition 8, step 11-step12 OK
C8_Trans12Ok : BOOL ; //Requirements for transition 8, step 12-step13 OK
C8_Trans13Ok : BOOL ; //Requirements for transition 8, step 13-step14 OK
C8_Trans14Ok : BOOL ; //Requirements for transition 8, step 14-step15 OK
C8_Trans15Ok : BOOL ; //Requirements for transition 8, step 15-step16 OK
StepTransOk : BOOL ; //Step Transition Conditions OK
C8_StepTimeComp : BOOL ; //Step Time Completed
C8_StartupMon : BOOL ; //Enable Startup time monitoring
C8_LG1CmdIssued : BOOL ; //Lower Gate 1 Open/Close Command Issued
C8_FPLOG1_OPENLS_1 : BOOL ; //Open limit switch after pulsed timer from limit switch DI
C8_FPLOG1_CLOSELS_1 : BOOL ; //Close limit switch after pulsed timer from limit switch DI
C8_LG2CmdIssued : BOOL ; //Lower Gate 2 Open/Close Command Issued
C8_WGCmdIssued : BOOL ; //Weir Gate Open/Close Command Issued
TOD_0000 : BOOL ; //Time Of Day 00:00 Pulse, On 1 Scan
TOD_0000Last : BOOL ; //Time Of Day 00:00 Value Last Scan
TOD_0600 : BOOL ; //Time Of Day Pulse 06:00, On 1 Scan
TOD_0600Last : BOOL ; //Time Of Day Pulse Value Last Scan
TOD_0900 : BOOL ; //Time Of Day Pulse 09:00, On 1 Scan
TOD_0900Last : BOOL ; //Time Of Day Pulse Value Last Scan
C8_OB121_ERROR : BOOL ; //OB121 ERROR PROGRAM
C8_OB85_ERROR : BOOL ; //OB85 OB FAULTING
C8_OB122_ERROR : BOOL ; //OB122 ACCES MODULE ERROR
C8_FPLOG_SEL : BOOL ; //Fish Pass Lower Gate Selection
C8_FP_MOT_OVL : BOOL ; //Fish Pass Motor OverLoad Latch Alarm
C8_FP_ESTOP : BOOL ; //Fish Pass EStop Latch Alarm
C8_FP_RESET : BOOL ; //Fish Pass Reset
C8_FP_MOT_OVL_RS : BOOL ; //Fish Pass Motor OverLoad Reset
C8_FP_ESTOP_RS : BOOL ; //Fish Pass ESTOP Resets
C8_FISH_COUNTER_RS : BOOL ; //Fish Pass Fish Counter Reset
C8_FPWG_HMIOPENCMD : BOOL ; //Fish Pass HMI Weir Gate Open Command
C8_FPWG_HMICLOSECMD : BOOL ; //Fish Pass HMI Weir Gate Closed Command
Rsvd6_2 : BOOL ;
Rsvd6_3 : BOOL ;
Rsvd6_4 : BOOL ;
Rsvd6_5 : BOOL ;
Rsvd6_6 : BOOL ;
Rsvd6_7 : BOOL ;
C8_FPLOG2_OPENLS_1 : BOOL ; //Open limit switch after pulsed timer from limit switch DI
C8_FPLOG_AutoOpenCond : BOOL ; //Fish Pass HMI Lower Gates Auto Open Conditions
C8_FPLOG_AutoCloseCond : BOOL ; //Fish Pass HMI Lower Gates Auto Close Conditions
C8_FPLOG1_Closed : BOOL ; //Fish Pass Lower Gate 1 Closed
C8_FPLOG2_Closed : BOOL ; //Fish Pass Lower Gate 2 Closed
C8_FPLOG1_STOPCMD_Latch : BOOL ; //Fish Pass Lower Gate 1 Stop Command Latch
C8_FPLOG2_STOPCMD_Latch : BOOL ; //Fish Pass Lower Gate 2 Stop Command Latch
C8_WG_STOPCMD_Latch : BOOL ; //Fish Pass Weir Gate Stop Command Latch
C8_FP_MODE_Man : BOOL ; //Fish Pass Operating Mode Manual
C8_FP_MODE_Auto : BOOL ; //Fish Pass Operating Mode Auto
Rsvd8_2 : BOOL ;
Rsvd8_3 : BOOL ;
Rsvd8_4 : BOOL ;
Rsvd8_5 : BOOL ;
Rsvd8_6 : BOOL ;
Rsvd8_7 : BOOL ;
C8_FPLOG1_HMIOPENCMD : BOOL ; //Fish Pass HMI Lower Gate 1 Open Command
C8_FPLOG1_HMICLOSECMD : BOOL ; //Fish Pass HMI Lower Gate 1 Closed Command
Rsvd9_2 : BOOL ;
Rsvd9_3 : BOOL ;
Rsvd9_4 : BOOL ;
Rsvd9_5 : BOOL ;
Rsvd9_6 : BOOL ;
C8_FPLOG2_CLOSELS_1 : BOOL ; //Close limit switch after pulsed timer from limit switch DI
C8_FPLOG2_HMIOPENCMD : BOOL ; //Fish Pass HMI Lower Gate 2 Open Command
C8_FPLOG2_HMICLOSECMD : BOOL ; //Fish Pass HMI Lower Gate 2 Closed Command
Rsvd10_2 : BOOL ;
Rsvd10_3 : BOOL ;
Rsvd10_4 : BOOL ;
Rsvd10_5 : BOOL ;
Rsvd10_6 : BOOL ;
Rsvd10_7 : BOOL ;
C8_FPWG_HMISTOPCMD : BOOL ; //Fish Pass HMI Weir Gate Stop Command
C8_FPLOG1_HMISTOPCMD : BOOL ; //Fish Pass HMI Lower Gate 1 Stop Command
C8_FPLOG2_HMISTOPCMD : BOOL ; //Fish Pass HMI Lower Gate 2 Stop Command
C8_FPWG_AutoOpenCond : BOOL ; //Fish Pass HMI Weir Gate Auto Open Conditions
C8_FPWG_AutoCloseCond : BOOL ; //Fish Pass HMI Weir Gate Auto Close Conditions
C8_FPWL_WGOPNLVL : BOOL ; //Fish Pass Water level OK for 10 s to Open Weir Gate
DrawdownCommFail : BOOL ;
C8_FPWG_OPENCMD_Ons : BOOL ;
C8_FPWG_CLOSECMD_Ons : BOOL ;
C8_FPLOG1_OPENCMD_Ons : BOOL ;
C8_FPLOG1_CLOSECMD_Ons : BOOL ;
C8_FPLOG2_OPENCMD_Ons : BOOL ;
C8_FPLOG2_CLOSECMD_Ons : BOOL ;
C8_FPTIME_MAN_DEFAULT : BOOL ; //Load default set points to fish pass or have manual entry
END_STRUCT ;
BEGIN
C8_Off := TRUE;
C8_Step01 := FALSE;
C8_Step02 := FALSE;
C8_Step03 := FALSE;
C8_Step04 := FALSE;
C8_Step05 := FALSE;
C8_Step06 := FALSE;
C8_Step07 := FALSE;
C8_Step08 := FALSE;
C8_Step09 := FALSE;
C8_Step10 := FALSE;
C8_Step11 := FALSE;
C8_Step12 := FALSE;
C8_Step13 := FALSE;
C8_Step14 := FALSE;
C8_Step15 := FALSE;
C8_Trans0Ok := FALSE;
C8_Trans1Ok := FALSE;
C8_Trans2Ok := FALSE;
C8_Trans3Ok := FALSE;
C8_Trans4Ok := FALSE;
C8_Trans5Ok := FALSE;
C8_Trans6Ok := FALSE;
C8_Trans7Ok := FALSE;
C8_Trans8Ok := FALSE;
C8_Trans9Ok := FALSE;
C8_Trans10Ok := FALSE;
C8_Trans11Ok := FALSE;
C8_Trans12Ok := FALSE;
C8_Trans13Ok := FALSE;
C8_Trans14Ok := FALSE;
C8_Trans15Ok := FALSE;
StepTransOk := FALSE;
C8_StepTimeComp := TRUE;
C8_StartupMon := FALSE;
C8_LG1CmdIssued := FALSE;
C8_FPLOG1_OPENLS_1 := FALSE;
C8_FPLOG1_CLOSELS_1 := TRUE;
C8_LG2CmdIssued := FALSE;
C8_WGCmdIssued := FALSE;
TOD_0000 := FALSE;
TOD_0000Last := FALSE;
TOD_0600 := FALSE;
TOD_0600Last := FALSE;
TOD_0900 := FALSE;
TOD_0900Last := FALSE;
C8_OB121_ERROR := FALSE;
C8_OB85_ERROR := FALSE;
C8_OB122_ERROR := FALSE;
C8_FPLOG_SEL := FALSE;
C8_FP_MOT_OVL := FALSE;
C8_FP_ESTOP := FALSE;
C8_FP_RESET := FALSE;
C8_FP_MOT_OVL_RS := FALSE;
C8_FP_ESTOP_RS := FALSE;
C8_FISH_COUNTER_RS := FALSE;
C8_FPWG_HMIOPENCMD := FALSE;
C8_FPWG_HMICLOSECMD := FALSE;
Rsvd6_2 := FALSE;
Rsvd6_3 := FALSE;
Rsvd6_4 := FALSE;
Rsvd6_5 := FALSE;
Rsvd6_6 := FALSE;
Rsvd6_7 := FALSE;
C8_FPLOG2_OPENLS_1 := FALSE;
C8_FPLOG_AutoOpenCond := FALSE;
C8_FPLOG_AutoCloseCond := FALSE;
C8_FPLOG1_Closed := FALSE;
C8_FPLOG2_Closed := FALSE;
C8_FPLOG1_STOPCMD_Latch := FALSE;
C8_FPLOG2_STOPCMD_Latch := FALSE;
C8_WG_STOPCMD_Latch := FALSE;
C8_FP_MODE_Man := TRUE;
C8_FP_MODE_Auto := FALSE;
Rsvd8_2 := FALSE;
Rsvd8_3 := FALSE;
Rsvd8_4 := FALSE;
Rsvd8_5 := FALSE;
Rsvd8_6 := FALSE;
Rsvd8_7 := FALSE;
C8_FPLOG1_HMIOPENCMD := FALSE;
C8_FPLOG1_HMICLOSECMD := FALSE;
Rsvd9_2 := FALSE;
Rsvd9_3 := FALSE;
Rsvd9_4 := FALSE;
Rsvd9_5 := FALSE;
Rsvd9_6 := FALSE;
C8_FPLOG2_CLOSELS_1 := TRUE;
C8_FPLOG2_HMIOPENCMD := FALSE;
C8_FPLOG2_HMICLOSECMD := FALSE;
Rsvd10_2 := FALSE;
Rsvd10_3 := FALSE;
Rsvd10_4 := FALSE;
Rsvd10_5 := FALSE;
Rsvd10_6 := FALSE;
Rsvd10_7 := FALSE;
C8_FPWG_HMISTOPCMD := FALSE;
C8_FPLOG1_HMISTOPCMD := FALSE;
C8_FPLOG2_HMISTOPCMD := FALSE;
C8_FPWG_AutoOpenCond := FALSE;
C8_FPWG_AutoCloseCond := FALSE;
C8_FPWL_WGOPNLVL := FALSE;
DrawdownCommFail := FALSE;
C8_FPWG_OPENCMD_Ons := TRUE;
C8_FPWG_CLOSECMD_Ons := TRUE;
C8_FPLOG1_OPENCMD_Ons := TRUE;
C8_FPLOG1_CLOSECMD_Ons := TRUE;
C8_FPLOG2_OPENCMD_Ons := TRUE;
C8_FPLOG2_CLOSECMD_Ons := TRUE;
C8_FPTIME_MAN_DEFAULT := TRUE;
END_DATA_BLOCK
DATA_BLOCK "Q"
TITLE =
NAME : Q
VERSION : 0.1
STRUCT
Placeholder : ARRAY [0 .. 3 ] OF //Spare - Place holder not an actual DO
BYTE ;
C8_FPWG_OPENCMD : BOOL ; //Fish Pass Weir Gate Open Command
C8_FPWG_CLOSECMD : BOOL ; //Fish Pass Weir Gate Closed Command
C8_FPWG_STOPCMD : BOOL ; //Fish Pass Weir Gate Stop Command
C8_FPLOG1_OPENCMD : BOOL ; //Fish Pass Lower Gate 1 Open Command
C8_FPLOG1_CLOSECMD : BOOL ; //Fish Pass Lower Gate 1 Closed Command
C8_FPLOG1_STOPCMD : BOOL ; //Fish Pass Lower Gate 1 Stop Command
C8_FPLOG2_OPENCMD : BOOL ; //Fish Pass Lower Gate 2 Open Command
C8_FPLOG2_CLOSECMD : BOOL ; //Fish Pass Lower Gate 2 Closed Command
C8_FPLOG2_STOPCMD : BOOL ; //Fish Pass Lower Gate 2 Stop Command
Q5_1 : BOOL ; //Spare DO
Q5_2 : BOOL ; //Spare DO
Q5_3 : BOOL ; //Spare DO
Q5_4 : BOOL ; //Spare DO
Q5_5 : BOOL ; //Spare DO
Q5_6 : BOOL ; //Spare DO
Q5_7 : BOOL ; //Spare DO
Q6_0 : BOOL ; //Spare DO
Q6_1 : BOOL ; //Spare DO
Q6_2 : BOOL ; //Spare DO
Q6_3 : BOOL ; //Spare DO
Q6_4 : BOOL ; //Spare DO
Q6_5 : BOOL ; //Spare DO
Q6_6 : BOOL ; //Spare DO
Q6_7 : BOOL ; //Spare DO
Q7_0 : BOOL ; //Spare DO
Q7_1 : BOOL ; //Spare DO
Q7_2 : BOOL ; //Spare DO
Q7_3 : BOOL ; //Spare DO
Q7_4 : BOOL ; //Spare DO
Q7_5 : BOOL ; //Spare DO
Q7_6 : BOOL ; //Spare DO
Q7_7 : BOOL ; //Spare DO
END_STRUCT ;
BEGIN
Placeholder[0] := B#16#0;
Placeholder[1] := B#16#0;
Placeholder[2] := B#16#0;
Placeholder[3] := B#16#0;
C8_FPWG_OPENCMD := FALSE;
C8_FPWG_CLOSECMD := FALSE;
C8_FPWG_STOPCMD := TRUE;
C8_FPLOG1_OPENCMD := FALSE;
C8_FPLOG1_CLOSECMD := FALSE;
C8_FPLOG1_STOPCMD := FALSE;
C8_FPLOG2_OPENCMD := FALSE;
C8_FPLOG2_CLOSECMD := FALSE;
C8_FPLOG2_STOPCMD := FALSE;
Q5_1 := FALSE;
Q5_2 := FALSE;
Q5_3 := FALSE;
Q5_4 := FALSE;
Q5_5 := FALSE;
Q5_6 := FALSE;
Q5_7 := FALSE;
Q6_0 := FALSE;
Q6_1 := FALSE;
Q6_2 := FALSE;
Q6_3 := FALSE;
Q6_4 := FALSE;
Q6_5 := FALSE;
Q6_6 := FALSE;
Q6_7 := FALSE;
Q7_0 := FALSE;
Q7_1 := FALSE;
Q7_2 := FALSE;
Q7_3 := FALSE;
Q7_4 := FALSE;
Q7_5 := FALSE;
Q7_6 := FALSE;
Q7_7 := FALSE;
END_DATA_BLOCK
DATA_BLOCK "HW"
TITLE =
NAME : HW
VERSION : 0.0
STRUCT
INCR_EACH_SCAN : DINT ; //0 -> 100 Increment each scan
INCR_EVERY_SEC : DINT ; //0 -> 100 Increment every 1.0 seconds
PLC_Year : DINT ; //PLC Year
PLC_Month : DINT ; //PLC Month
PLC_Day : DINT ; //PLC Day of Month
PLC_Hour : DINT ; //PLC Hour (00-23)
PLC_Minute : DINT ; //PLC Minute (00-59)
PLC_Second : DINT ; //PLC Minute (00-59)
PLC_Date : DINT ; //PLC Date YYYYMMDD
PLC_Time : DINT ; //PLC Time HHMMSS
PLC_DateTime : DATE_AND_TIME ; //DateTime
PLC_Year_BCD : DWORD ; //PLC Year
PLC_Month_BCD : DWORD ; //PLC Month
PLC_Day_BCD : DWORD ; //PLC Day of Month
PLC_Hour_BCD : DWORD ; //PLC Hour (00-23)
PLC_Minute_BCD : DWORD ; //PLC Minute (00-59)
PLC_Second_BCD : DWORD ; //PLC Minute (00-59)
PLC_DT_RetVar : INT ;
TempDINT1 : DINT ; //Temporary DINT 1
TempDINT2 : DINT ; //Temporary DINT 2
C8_FP_COUNTER : DINT ; //Fish Pass Counter
C8_FPG_STEP : DINT ; //Fish Pass Step Number
C8_FP_STEPTIME : DINT ; //Fish Pass Step Time
C8_FP_STEPTIME_REM : DINT ; //Fish Pass Step Time Remaining
C8_FISH_COUNTER : DINT ; //Fish Pass Fish Counter
C8_FP_MODE : DINT ; //Fish Pass Mode 0=Off, 1=Man, 2=Auto
STEP_NUM_MESS : DINT ; //Step Message Number
C8_FPG_STEP_LAST : DINT ; //Step Number Last Scan
C8_FPLOG_CRA_SP : DINT ; //Fish Pass Lower Gate Crack Open SP
C8_FPLOG_OPEN_SP : DINT ; //Fish Pass Lower Gate Open SP
C8_LOG1_POS : DINT ; //Lower Gate 1 Position
C8_LOG2_POS : DINT ; //Lower Gate 2 Position
C8_FPFISH_ASC_SP : DINT ; //Fish Pass Ascending Timer
C8_FPFISH_DES_SP : DINT ; //Fish Pass Descending Timer
C8_FPFISH_ASC_COUNT : DINT ; //Fish Pass Descending Timer Count
C8_FPFISH_DES_COUNT : DINT ; //Fish Pass Ascending Timer Count
Spare_146 : DINT ; //Spare
Step0TimePre : DINT ; //Step 0 Timer Preset
Step1TimePre : DINT ; //Step 1 Timer Preset
Step2TimePre : DINT ; //Step 2 Timer Preset
Step3TimePre : DINT ; //Step 3 Timer Preset
Step4TimePre : DINT ; //Step 4 Timer Preset
Step5TimePre : DINT ; //Step 5 Timer Preset
Step6TimePre : DINT ; //Step 6 Timer Preset
Step7TimePre : DINT ; //Step 7 Timer Preset
Step8TimePre : DINT ; //Step 8 Timer Preset
Step9TimePre : DINT ; //Step 9 Timer Preset
Step2TimePre_ASC : DINT ; //Step 2 Timer Preset Ascending
Step2TimePre_DES : DINT ; //Step 2 Timer Preset Descending
Step8TimePre_ASC : DINT ; //Step 8 Timer Preset Ascending
Step8TimePre_DES : DINT ; //Step 8 Timer Preset Descending
C8_FPESC_ASC_SP : DINT ; //Fish Pass Escaping Ascending Timer
C8_FPESC_DES_SP : DINT ; //Fish Pass Escaping Descending Timer
Spare_214 : DINT ; //Spare
Blank_msg : DINT ; //Fish Pass Blank Transition Message
Tran_Msg : DINT ; //Fish Pass Transition Message in PLC
DrawdownRollRegLast : DINT ;
C8_FPWG_POS_1 : WORD ; //Wier Gate Position based on time
C8_FPWG_POS_2 : DINT ; //Wier Gate Position based on time
END_STRUCT ;
BEGIN
INCR_EACH_SCAN := L#69;
INCR_EVERY_SEC := L#41;
PLC_Year := L#11;
PLC_Month := L#6;
PLC_Day := L#1;
PLC_Hour := L#12;
PLC_Minute := L#42;
PLC_Second := L#59;
PLC_Date := L#20110601;
PLC_Time := L#124259;
PLC_DateTime := DT#11-6-1-12:42:59.317;
PLC_Year_BCD := DW#16#11;
PLC_Month_BCD := DW#16#6;
PLC_Day_BCD := DW#16#1;
PLC_Hour_BCD := DW#16#12;
PLC_Minute_BCD := DW#16#42;
PLC_Second_BCD := DW#16#59;
PLC_DT_RetVar := 0;
TempDINT1 := L#45720;
TempDINT2 := L#45779;
C8_FP_COUNTER := L#265;
C8_FPG_STEP := L#0;
C8_FP_STEPTIME := L#0;
C8_FP_STEPTIME_REM := L#0;
C8_FISH_COUNTER := L#0;
C8_FP_MODE := L#1;
STEP_NUM_MESS := L#5100;
C8_FPG_STEP_LAST := L#0;
C8_FPLOG_CRA_SP := L#10;
C8_FPLOG_OPEN_SP := L#0;
C8_LOG1_POS := L#0;
C8_LOG2_POS := L#0;
C8_FPFISH_ASC_SP := L#8550;
C8_FPFISH_DES_SP := L#4020;
C8_FPFISH_ASC_COUNT := L#0;
C8_FPFISH_DES_COUNT := L#0;
Spare_146 := L#0;
Step0TimePre := L#0;
Step1TimePre := L#0;
Step2TimePre := L#0;
Step3TimePre := L#0;
Step4TimePre := L#10;
Step5TimePre := L#4020;
Step6TimePre := L#30;
Step7TimePre := L#0;
Step8TimePre := L#300;
Step9TimePre := L#8550;
Step2TimePre_ASC := L#0;
Step2TimePre_DES := L#0;
Step8TimePre_ASC := L#300;
Step8TimePre_DES := L#300;
C8_FPESC_ASC_SP := L#4020;
C8_FPESC_DES_SP := L#8550;
Spare_214 := L#0;
Blank_msg := L#5999;
Tran_Msg := L#4000;
DrawdownRollRegLast := L#6685;
C8_FPWG_POS_1 := W#16#0;
C8_FPWG_POS_2 := L#0;
END_DATA_BLOCK
DATA_BLOCK "DDtoFishPass"
TITLE =
VERSION : 0.1
STRUCT
RollReg : DINT ; //Rolling Reg From Other PLC
HeadraceAve : REAL ; //HeadRace Average (From DrawDown PLC)
TailRaveAve : REAL ; //TailRace Average (From DrawDown PLC)
END_STRUCT ;
BEGIN
RollReg := L#6685;
HeadraceAve := 3.339119e+001;
TailRaveAve := 3.046779e+000;
END_DATA_BLOCK
FUNCTION "ANALOG INPUT TO REAL" : VOID
TITLE =Convert Analog Input To REAL And Scale
NAME : ANATORL
VERSION : 0.2
VAR_INPUT
RawIn : WORD ; //12bit analogue value
EuMin : REAL ; //Min Value of the device
EuMax : REAL ; //Max Value of the device
FailValue : REAL ; //Fail Safe Value
END_VAR
VAR_OUTPUT
Wire_Break : BOOL ; //Alarm for wirebreak
Out_Range : BOOL ; //Alarm for Out of range
END_VAR
VAR_IN_OUT
In : REAL ; //Value scaled and in REAL
END_VAR
VAR_TEMP
RawReal : REAL ; //Input Value in REAL
Span : REAL ; //Full range
END_VAR
BEGIN
NETWORK
TITLE =
L #RawIn; //Wirebreak Alarm
L W#16#8000; //Value in case of WireBreak
>=I ;
A( ;
L #RawIn;
L W#16#FD4D;
<=I ;
) ;
= #Wire_Break;
NETWORK
TITLE =
L #RawIn; //Out Of Range Alarm
L W#16#6C01; //Out Of Range when Higher than 20mA
>=I ;
A( ;
L #RawIn;
L W#16#7FFF;
<=I ;
) ;
= #Out_Range;
NETWORK
TITLE =
L #RawIn; //Function For SCALING in REAL
ITD ;
DTR ;
T #RawReal;
L #EuMax;
L #EuMin;
-R ;