T4 over-driving SCLK

[djpohly]

Since commit d10dd99, the Teensy 4.0 in my uBITX/TSW radio has been getting bad data back from the 2.8" SPI touchscreen it controls (identical to the ones available from PJRC).

As best I can tell, configuring the SCLK pin for maximum drive is causing signal integrity issues in my device. I couldn't record it directly, since probing SCLK would make the issue disappear, but MISO showed that the touch controller was sometimes shifting data on half-cycles (where the falling edge would be). I'm not an EE, but most of what I could find about similar clocking issues recommended reducing drive strength. As it turns out, changing the DSE field to anything between 4 and 6 (with any value for SPEED) fixed the SCLK issue for me.

The changes to the clock and divider were discussed at length in the forum and PR #55, but I couldn't find where the changes to DSE and SPEED were explained. Is there a particular need to fix DSE at 7, or could it be bumped down?