forked from stefan9x/lprs2-TowerDefence
-
Notifications
You must be signed in to change notification settings - Fork 1
/
system.log
10337 lines (3857 loc) · 225 KB
/
system.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
Xilinx Platform Studio (XPS)
Xilinx EDK 14.6 Build EDK_P.68d
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
********************************************************************************
At Local date and time: Thu Jun 06 11:58:04 2019
make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"
psf2Edward -inp system.xmp -exit_on_error -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml
Release 14.6 - psf2Edward EDK_P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Checking platform configuration ...
IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 2 slave(s)
IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 2 slave(s)
IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s)
Checking port drivers...
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
INTC INFO:: Processor_clk not connected.. IRQ to Microblaze is generated on AXI
clock.
Conversion to XML complete.
xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html -make_docs_local
Release 14.6 - xdsgen EDK_P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Generated Block Diagram.
Rasterizing vga_periph_mem_0.jpg.....
Rasterizing proc_sys_reset_0.jpg.....
Rasterizing my_peripheral_0.jpg.....
Rasterizing microblaze_0_ilmb.jpg.....
Rasterizing microblaze_0_dlmb.jpg.....
Rasterizing microblaze_0_d_bram_ctrl_0.jpg.....
Rasterizing microblaze_0_i_bram_ctrl_0.jpg.....
Rasterizing microblaze_0_bram_block_0.jpg.....
Rasterizing microblaze_0.jpg.....
Rasterizing debug_module.jpg.....
Rasterizing clock_generator_0.jpg.....
Rasterizing axi4lite_0.jpg.....
Rasterizing RS232.jpg.....
Rasterizing axi_intc_0.jpg.....
Rasterizing microblaze_0_d_bram_ctrl_1.jpg.....
Rasterizing microblaze_0_bram_block_1.jpg.....
Rasterizing microblaze_0_i_bram_ctrl_1.jpg.....
Rasterizing system_blkd.jpg.....
Report generated.
Report generation completed.
"****************************************************"
"Creating system netlist for hardware specification.."
"****************************************************"
platgen -p xc6slx45fgg676-2 -lang vhdl -intstyle default -msg __xps/ise/xmsgprops.lst system.mhs
Release 14.6 - platgen Xilinx EDK 14.6 Build EDK_P.68d
(nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc6slx45fgg676-2 -lang vhdl -intstyle default -msg
__xps/ise/xmsgprops.lst system.mhs
WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable
is set to '2100@licserver'.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@licserver'.
INFO:Security:71 - If a license for part 'xc6slx45' is available, it will be
possible to use 'XPS_TDP' instead of 'XPS'.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your
current version of Xilinx tools will continue to function, but you no longer
qualify for Xilinx software updates or new releases.
Parse C:/Users/student/Desktop/136/CatchTheFlowers/system.mhs ...
Read MPD definitions ...
Overriding IP level properties ...
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ENDIANNESS value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 198
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ICACHE_USE_FSL value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 339
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_USE_FSL value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 369
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is
overriding PARAMETER C_BASEFAMILY value to spartan6 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 81
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:axi_intc_0 - tcl is overriding
PARAMETER C_NUM_INTR_INPUTS value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 85
Computing clock values...
INFO:EDK:1432 - Frequency for Top-Level Input Clock 'vga_periph_0_clk_i_pin' is
not specified. Clock DRCs will not be performed for IPs connected to that
clock port, unless they are connected through the clock generator IP.
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_i_bram_ctrl_0:BRAM_Clk_A. Clock DRCs will not be performed on
this core and cores connected to it.
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_d_bram_ctrl_0:BRAM_Clk_A. Clock DRCs will not be performed on
this core and cores connected to it.
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_d_bram_ctrl_1:BRAM_Clk_A. Clock DRCs will not be performed on
this core and cores connected to it.
INFO:EDK:740 - Cannot determine the input clock associated with port :
microblaze_0_i_bram_ctrl_1:BRAM_Clk_A. Clock DRCs will not be performed on
this core and cores connected to it.
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0000000000-0x0000ffff) microblaze_0_d_bram_ctrl_0 microblaze_0_dlmb
(0000000000-0x0000ffff) microblaze_0_i_bram_ctrl_0 microblaze_0_ilmb
(0x00010000-0x0001ffff) microblaze_0_d_bram_ctrl_1 microblaze_0_dlmb
(0x00010000-0x0001ffff) microblaze_0_i_bram_ctrl_1 microblaze_0_ilmb
(0x40600000-0x4060ffff) RS232 axi4lite_0
(0x41200000-0x4120ffff) axi_intc_0 axi4lite_0
(0x41400000-0x4140ffff) debug_module axi4lite_0
(0x74000000-0x77ffffff) vga_periph_mem_0 axi4lite_0
(0x7de00000-0x7de0ffff) my_peripheral_0 axi4lite_0
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding
PARAMETER C_LMB_NUM_SLAVES value to 2 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data
\lmb_v10_v2_1_0.mpd line 82
INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding
PARAMETER C_LMB_NUM_SLAVES value to 2 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data
\lmb_v10_v2_1_0.mpd line 82
INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block_0 - tool is
overriding PARAMETER C_MEMSIZE value to 0x10000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d
ata\bram_block_v2_1_0.mpd line 78
INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block_1 - tool is
overriding PARAMETER C_MEMSIZE value to 0x10000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d
ata\bram_block_v2_1_0.mpd line 78
Checking platform address map ...
Checking platform configuration ...
IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 2 slave(s)
IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 2 slave(s)
IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s)
WARNING:EDK:3977 - AXI4 protocol type BUSIF: S_AXI of IPINSTANCE:
vga_periph_mem_0 connected with AXI4LITE type BUSIF: M_AXI_DP of IPINSTANCE:
microblaze_0.
Checking port drivers...
WARNING:EDK:4180 - PORT: Interrupt_address_in, CONNECTOR: Interrupt_address_in -
No driver found. Port will be driven to GND -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 131
WARNING:EDK:4181 - PORT: Processor_ack_out, CONNECTOR: Processor_ack_out -
floating connection -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 132
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl_0 -
tcl is overriding PARAMETER C_MASK value to 0x40010000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl_0 -
tcl is overriding PARAMETER C_MASK value to 0x40010000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_D_AXI value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 232
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_ADDR_TAG_BITS value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 337
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_DCACHE_ADDR_TAG value to 0 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 367
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_INTERRUPT value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 401
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_BRK value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 402
INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding
PARAMETER C_USE_EXT_NM_BRK value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_50_b\d
ata\microblaze_v2_1_0.mpd line 403
INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.
INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is
overriding PARAMETER C_RANGE_CHECK value to 1 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_
06_a\data\axi_interconnect_v2_1_0.mpd line 149
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:axi_intc_0 - tcl is overriding
PARAMETER C_KIND_OF_INTR value to 0b11111111111111111111111111111111 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 87
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:axi_intc_0 - tcl is overriding
PARAMETER C_KIND_OF_EDGE value to 0b11111111111111111111111111111111 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 88
INFO:EDK:4130 - IPNAME: axi_intc, INSTANCE:axi_intc_0 - tcl is overriding
PARAMETER C_KIND_OF_LVL value to 0b11111111111111111111111111111111 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat
a\axi_intc_v2_1_0.mpd line 89
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl_1 -
tcl is overriding PARAMETER C_MASK value to 0x04010000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl_1 -
tcl is overriding PARAMETER C_MASK value to 0x04010000 -
C:\Xilinx\14.6\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3
_10_c\data\lmb_bram_if_cntlr_v2_1_0.mpd line 92
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
INTC INFO:: Processor_clk not connected.. IRQ to Microblaze is generated on AXI
clock.
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: Setting timing constaints for microblaze_0_ilmb.
INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS
in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: Setting timing constaints for microblaze_0_dlmb.
INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS
in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: Setting timing constaints for microblaze_0.
INFO: The microblaze_0 core has constraints automatically generated by XPS in
implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.
INTC_INFO_CONSTRAINTS:: Adding Edge interrupt constraints
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
IPNAME:vga_periph_mem INSTANCE:vga_periph_mem_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 33 - Copying
(BBD-specified) netlist files.
Managing cache ...
Elaborating instances ...
IPNAME:bram_block INSTANCE:microblaze_0_bram_block_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 113 - elaborating
IP
IPNAME:bram_block INSTANCE:microblaze_0_bram_block_1 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 213 - elaborating
IP
IPNAME:clock_generator INSTANCE:clock_generator_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 157 - elaborating
IP
ClkGen elaborate status: PASSED
----------------------------------------
----------------------------------------
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 0.00 seconds
Constructing platform-level connectivity ...
Completion time: 0.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:vga_periph_mem_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 33 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:proc_sys_reset_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 57 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:my_peripheral_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 70 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_ilmb -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 81 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_dlmb -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 88 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_d_bram_ctrl_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 95 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_i_bram_ctrl_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 104 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_bram_block_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 113 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0 - C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs
line 120 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:debug_module - C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs
line 144 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:clock_generator_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 157 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:axi4lite_0 - C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs
line 170 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:rs232 - C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line
178 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:axi_intc_0 - C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs
line 193 - Running XST synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_d_bram_ctrl_1 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 204 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_bram_block_1 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 213 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
INSTANCE:microblaze_0_i_bram_ctrl_1 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 220 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Running NGCBUILD ...
IPNAME:system_vga_periph_mem_0_wrapper INSTANCE:vga_periph_mem_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 33 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx45fgg676-2 -intstyle silent -i -sd .. system_vga_periph_mem_0_wrapper.ngc
../system_vga_periph_mem_0_wrapper
Reading NGO file
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/vga_periph_mem_0_wr
apper/system_vga_periph_mem_0_wrapper.ngc" ...
Loading design module
"C:\Users\student\Desktop\136\CatchTheFlowers\implementation\vga_periph_mem_0_wr
apper/char_rom_def.ngc"...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_vga_periph_mem_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_vga_periph_mem_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_microblaze_0_ilmb_wrapper INSTANCE:microblaze_0_ilmb -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 81 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx45fgg676-2 -intstyle silent -i -sd .. system_microblaze_0_ilmb_wrapper.ngc
../system_microblaze_0_ilmb_wrapper
Reading NGO file
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/microblaze_0_ilmb_w
rapper/system_microblaze_0_ilmb_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_microblaze_0_ilmb_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 1 sec
Writing NGCBUILD log file "../system_microblaze_0_ilmb_wrapper.blc"...
NGCBUILD done.
IPNAME:system_microblaze_0_dlmb_wrapper INSTANCE:microblaze_0_dlmb -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 88 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx45fgg676-2 -intstyle silent -i -sd .. system_microblaze_0_dlmb_wrapper.ngc
../system_microblaze_0_dlmb_wrapper
Reading NGO file
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/microblaze_0_dlmb_w
rapper/system_microblaze_0_dlmb_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_microblaze_0_dlmb_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_microblaze_0_dlmb_wrapper.blc"...
NGCBUILD done.
IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 120 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx45fgg676-2 -intstyle silent -i -sd .. system_microblaze_0_wrapper.ngc
../system_microblaze_0_wrapper
Reading NGO file
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/microblaze_0_wrappe
r/system_microblaze_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_microblaze_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../system_microblaze_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 157 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx45fgg676-2 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc
../system_clock_generator_0_wrapper
Reading NGO file
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/clock_generator_0_w
rapper/system_clock_generator_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 1 sec
Total CPU time to NGCBUILD completion: 1 sec
Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...
NGCBUILD done.
IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -
C:\Users\student\Desktop\136\CatchTheFlowers\system.mhs line 170 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p
xc6slx45fgg676-2 -intstyle silent -i -sd .. system_axi4lite_0_wrapper.ngc
../system_axi4lite_0_wrapper
Reading NGO file
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/axi4lite_0_wrapper/
system_axi4lite_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../system_axi4lite_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 1 sec
Writing NGCBUILD log file "../system_axi4lite_0_wrapper.blc"...
NGCBUILD done.
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
Total run time: 154.00 seconds
"Running synthesis..."
cd synthesis & synthesis.cmd
"xst -ifn "system_xst.scr" -intstyle silent"
"Running XST synthesis ..."
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
"XST completed"
"*********************************************"
"Running Xilinx Implementation tools.."
"*********************************************"
xflow -wd implementation -p xc6slx45fgg676-2 -implement xflow.opt system.ngc
Release 14.6 - Xflow P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
xflow.exe -wd implementation -p xc6slx45fgg676-2 -implement xflow.opt system.ngc
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
.... Copying flowfile C:/Xilinx/14.6/ISE_DS/ISE/xilinx/data/fpga.flw into
working directory C:/Users/student/Desktop/136/CatchTheFlowers/implementation
Using Flow File:
C:/Users/student/Desktop/136/CatchTheFlowers/implementation/fpga.flw
Using Option File(s):
C:/Users/student/Desktop/136/CatchTheFlowers/implementation/xflow.opt
Creating Script File ...
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc6slx45fgg676-2 -nt timestamp -bm system.bmm
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system.ngc" -uc
system.ucf system.ngd
#----------------------------------------------#
Release 14.6 - ngdbuild P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6.acd>
Command Line: C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p
xc6slx45fgg676-2 -nt timestamp -bm system.bmm
C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system.ngc -uc
system.ucf system.ngd
Reading NGO file
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system.ngc" ...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_my_periphera
l_0_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_rs232_wrappe
r.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_vga_periph_m
em_0_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_proc_sys_res
et_0_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_clock_genera
tor_0_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_axi_intc_0_w
rapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_ilmb_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_dlmb_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_axi4lite_0_w
rapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_i_bram_ctrl_0_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_i_bram_ctrl_1_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_d_bram_ctrl_0_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_d_bram_ctrl_1_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_debug_module
_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_bram_block_0_wrapper.ngc"...
Loading design module
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_bram_block_1_wrapper.ngc"...
Applying constraints in
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_axi_intc_0_w
rapper.ncf" to module "axi_intc_0"...
Checking Constraint Associations...
Applying constraints in
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_ilmb_wrapper.ncf" to module "microblaze_0_ilmb"...
Checking Constraint Associations...
Applying constraints in
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_dlmb_wrapper.ncf" to module "microblaze_0_dlmb"...
Checking Constraint Associations...
Applying constraints in
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_axi4lite_0_w
rapper.ncf" to module "axi4lite_0"...
Checking Constraint Associations...
Applying constraints in
"C:/Users/student/Desktop/136/CatchTheFlowers/implementation/system_microblaze_0
_wrapper.ncf" to module "microblaze_0"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "system.ucf" ...
WARNING:NgdBuild - The value of SIM_DEVICE on instance
'vga_periph_mem_0/vga_periph_mem_0/USER_LOGIC_I/vga_top_i/char_rom_i/BRAM_MEM
_I/B6/RAMB16BWER' of type RAMB16BWER has been changed from 'SPARTAN3ADSP' to
'SPARTAN6' to correct post-ngdbuild and timing simulation for this primitive.
In order for functional simulation to be correct, the value of SIM_DEVICE
should be changed in this same manner in the source netlist or constraint
file.
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:135 - Constraint <INST
/system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl
ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =
FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block
"axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).
WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS
PADS CPUS;>: CPUS "*" does not match any design objects.
WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_CLK = PERIOD CLK 37.037 ns
HIGH 50 ;> [system.ucf(41)]: Unable to find an active 'TNM' or 'TimeGrp'
constraint named 'CLK'.
WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not
directly or indirectly drive any flip-flops, latches and/or RAMs and is not
actively used by any referencing constraint.
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into PLL_ADV instance
clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM
groups and period specifications were generated at the PLL_ADV output(s):
CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =
PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin
* 2 HIGH 50>
Done...
Processing BMM file "system.bmm" ...
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.
Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 6
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 35 sec
Total CPU time to NGDBUILD completion: 35 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf
#----------------------------------------------#
Release 14.6 - Map P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
<C:/Xilinx/14.6/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file
<C:/Xilinx/14.6/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "6slx45fgg676-2".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to
'2100@licserver'.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1717@licserver'.
INFO:Security:54 - 'xc6slx45' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3402 - The Clock Modifying COMP, vga_periph_mem_0/vga_periph_mem_0/USER_LOGIC_I/vga_top_i/vga_i/res_1.dcm25_i/dcm_sp_inst,
has the attribute CLK_FEEDBACK set to NONE. No phase relationship exists between the input and output clocks of this Clock Modifying
COMP. Data paths between these clock domains must be constrained using FROM/TO constraints.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 14 secs
Total CPU time at the beginning of Placer: 10 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:c67b4ed3) REAL time: 15 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:c67b4ed3) REAL time: 15 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:5eccda03) REAL time: 15 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:ea050a15) REAL time: 28 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:ea050a15) REAL time: 28 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:ea050a15) REAL time: 28 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:ea050a15) REAL time: 28 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:ea050a15) REAL time: 28 secs
Phase 9.8 Global Placement
...........................
.......................................................................................................................................................
...............................
.............
Phase 9.8 Global Placement (Checksum:c722b36f) REAL time: 48 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:c722b36f) REAL time: 48 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:5ea3c59a) REAL time: 55 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:5ea3c59a) REAL time: 55 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:e48f041d) REAL time: 55 secs
Total REAL time to Placer completion: 58 secs
Total CPU time to Placer completion: 54 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 20
Slice Logic Utilization:
Number of Slice Registers: 1,641 out of 54,576 3
Number used as Flip Flops: 1,634
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 2,203 out of 27,288 8
Number used as logic: 2,035 out of 27,288 7
Number using O6 output only: 1,598
Number using O5 output only: 58
Number using O5 and O6: 379
Number used as ROM: 0
Number used as Memory: 141 out of 6,408 2
Number used as Dual Port RAM: 64
Number using O6 output only: 0
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 77
Number using O6 output only: 22
Number using O5 output only: 1
Number using O5 and O6: 54
Number used exclusively as route-thrus: 27
Number with same-slice register load: 19
Number with same-slice carry load: 6
Number with other load: 2
Slice Logic Distribution:
Number of occupied Slices: 1,001 out of 6,822 14
Number of MUXCYs used: 296 out of 13,644 2
Number of LUT Flip Flop pairs used: 2,700
Number with an unused Flip Flop: 1,141 out of 2,700 42
Number with an unused LUT: 497 out of 2,700 18
Number of fully used LUT-FF pairs: 1,062 out of 2,700 39
Number of unique control sets: 142
Number of slice register sites lost
to control set restrictions: 563 out of 54,576 1
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 52 out of 358 14
Number of LOCed IOBs: 52 out of 52 100
IOB Flip Flops: 32
Specific Feature Utilization:
Number of RAMB16BWERs: 109 out of 116 93
Number of RAMB8BWERs: 0 out of 232 0
Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6
Number used as BUFIO2s: 2
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0
Number of BUFG/BUFGMUXs: 3 out of 16 18
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 8 12
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 1 out of 376 1
Number used as ILOGIC2s: 1
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0
Number of OLOGIC2/OSERDES2s: 31 out of 376 8
Number used as OLOGIC2s: 31
Number used as OSERDES2s: 0
Number of BSCANs: 1 out of 4 25
Number of BUFHs: 0 out of 256 0
Number of BUFPLLs: 0 out of 8 0
Number of BUFPLL_MCBs: 0 out of 4 0
Number of DSP48A1s: 4 out of 58 6
Number of ICAPs: 0 out of 1 0
Number of MCBs: 0 out of 2 0
Number of PCILOGICSEs: 0 out of 2 0
Number of PLL_ADVs: 1 out of 4 25
Number of PMVs: 0 out of 1 0
Number of STARTUPs: 0 out of 1 0
Number of SUSPEND_SYNCs: 0 out of 1 0