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system.mhs
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system.mhs
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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.6 Build EDK_P.68d
# Tue Mar 04 13:57:52 2014
# Target Board: Custom
# Family: spartan6
# Device: xc6slx45
# Package: fgg676
# Speed Grade: -2
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 50000000
PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 50000000
PORT my_peripheral_0_DIP_Data_pin = my_peripheral_0_DIP_Data, DIR = I, VEC = [7:0]
PORT my_peripheral_0_LED_Data_pin = my_peripheral_0_LED_Data, DIR = O, VEC = [7:0]
PORT vga_periph_0_clk_i_pin = vga_periph_0_clk_i, DIR = I, SIGIS = CLK
PORT vga_periph_0_vga_vsync_o_pin = vga_periph_0_vga_vsync_o, DIR = O
PORT vga_periph_0_blank_o_pin = vga_periph_0_blank_o, DIR = O
PORT vga_periph_0_vga_hsync_o_pin = vga_periph_0_vga_hsync_o, DIR = O
PORT vga_periph_0_pix_clock_o_pin = vga_periph_0_pix_clock_o, DIR = O
PORT vga_periph_0_psave_o_pin = vga_periph_0_psave_o, DIR = O
PORT vga_periph_0_sync_o_pin = vga_periph_0_sync_o, DIR = O
PORT vga_periph_0_red_o_pin = vga_periph_0_red_o, DIR = O, VEC = [7:0]
PORT vga_periph_0_green_o_pin = vga_periph_0_green_o, DIR = O, VEC = [7:0]
PORT vga_periph_0_blue_o_pin = vga_periph_0_blue_o, DIR = O, VEC = [7:0]
BEGIN vga_periph_mem
PARAMETER INSTANCE = vga_periph_mem_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_S_AXI_MEM0_BASEADDR = 0x74000000
PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x77ffffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT clk_i = vga_periph_0_clk_i
PORT reset_n_i = RESET
PORT vga_vsync_o = vga_periph_0_vga_vsync_o
PORT blank_o = vga_periph_0_blank_o
PORT vga_hsync_o = vga_periph_0_vga_hsync_o
PORT pix_clock_o = vga_periph_0_pix_clock_o
PORT psave_o = vga_periph_0_psave_o
PORT sync_o = vga_periph_0_sync_o
PORT red_o = vga_periph_0_red_o
PORT green_o = vga_periph_0_green_o
PORT blue_o = vga_periph_0_blue_o
PORT direct_mode_i = my_peripheral_0_DIP_Data[0]
PORT display_mode_i = my_peripheral_0_DIP_Data[2:1]
PORT intr_s = vga_periph_mem_0_o_system_start_irq
END
# PORT vga_periph_0_display_mode_i_pin = vga_periph_0_display_mode_i, DIR = I, VEC = [1:0]
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
PORT MB_Reset = proc_sys_reset_0_MB_Reset
PORT Slowest_sync_clk = clk_100_0000MHz
PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
PORT Ext_Reset_In = RESET
PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END
BEGIN my_peripheral
PARAMETER INSTANCE = my_peripheral_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7de00000
PARAMETER C_HIGHADDR = 0x7de0ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT DIP_Data = my_peripheral_0_DIP_Data
PORT LED_Data = my_peripheral_0_LED_Data
END
BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_ilmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_100_0000MHz
END
BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_dlmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_100_0000MHz
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_d_bram_ctrl_0
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000FFFF
BUS_INTERFACE SLMB = microblaze_0_dlmb
BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_i_bram_ctrl_0
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000FFFF
BUS_INTERFACE SLMB = microblaze_0_ilmb
BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END
BEGIN bram_block
PARAMETER INSTANCE = microblaze_0_bram_block_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 8.50.b
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0X00000000
PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF
PARAMETER C_USE_ICACHE = 0
PARAMETER C_ICACHE_ALWAYS_USED = 0
PARAMETER C_DCACHE_BASEADDR = 0X00000000
PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF
PARAMETER C_USE_DCACHE = 0
PARAMETER C_DCACHE_ALWAYS_USED = 0
BUS_INTERFACE ILMB = microblaze_0_ilmb
BUS_INTERFACE DLMB = microblaze_0_dlmb
BUS_INTERFACE M_AXI_DP = axi4lite_0
BUS_INTERFACE DEBUG = microblaze_0_debug
BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
PORT MB_RESET = proc_sys_reset_0_MB_Reset
PORT CLK = clk_100_0000MHz
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.10.a
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_UART = 1
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT S_AXI_ACLK = clk_100_0000MHz
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_GROUP = NONE
PORT LOCKED = proc_sys_reset_0_Dcm_locked
PORT CLKOUT0 = clk_100_0000MHz
PORT RST = RESET
PORT CLKIN = CLK
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi4lite_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT interconnect_aclk = clk_100_0000MHz
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END
BEGIN axi_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.02.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 1
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT TX = RS232_Uart_1_sout
PORT RX = RS232_Uart_1_sin
END
BEGIN axi_intc
PARAMETER INSTANCE = axi_intc_0
PARAMETER HW_VER = 1.04.a
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
PORT S_AXI_ACLK = clk_100_0000MHz
PORT Intr = vga_periph_mem_0_o_system_start_irq
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_d_bram_ctrl_1
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00010000
PARAMETER C_HIGHADDR = 0x0001FFFF
BUS_INTERFACE SLMB = microblaze_0_dlmb
BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_1_BRAM_PORT
END
BEGIN bram_block
PARAMETER INSTANCE = microblaze_0_bram_block_1
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = microblaze_0_d_bram_ctrl_1_BRAM_PORT
BUS_INTERFACE PORTB = microblaze_0_i_bram_ctrl_1_BRAM_PORT
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_i_bram_ctrl_1
PARAMETER HW_VER = 3.10.c
PARAMETER C_BASEADDR = 0x00010000
PARAMETER C_HIGHADDR = 0x0001FFFF
BUS_INTERFACE SLMB = microblaze_0_ilmb
BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_1_BRAM_PORT
END