The verification target can be generated by create a VerilogVerificationTargetGenerator
object. Some prerequisites are:
- ILAng should be configured to have the switch
ILANG_INSTALL_DEV
turned on. - Include the header
ilang/vtarget-out/vtarget_gen.h
The arguments of the constructors are:
- A list of paths to search for Verilog include files
- A list of Verilog design files
- The Verilog top module
- The variable mapping file (first part of refinement map)
- The instruction start/ready conditions (second part of refinement map)
- The output path of the verification targets
- The ILA model
- The choice backend (CoSA/JapserGold, the latter is not open-source and not included in the demo)
- (Optional) Target generator configuration
- (Optional) Verilog generator configuration