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Instruction-level abstraction (ILA) provides an interface between different components in heterogeneous systems. It is an abstraction that formally models firmware-visible behaviors of a hardware module, such as a programmable processor or application specific accelerator. Similar to the instruction-set architecture (ISA) that defines the operation of a processor, an ILA models the operation of a hardware module as a set of instructions, where each instruction represents a certain operation over the states.
ILA is an abstraction of the hardware and serves as the interface between the hardware and other components. Therefore, only states that are visible and persistent across instructions need to be modeled. We let S be the vector of those state variables, where each element can be either a Boolean variable, a bitvector variable, or a memory variable. In the ILA of a processor, S would contain the architectural registers, flag bits, data memory, and the instruction memory. As for accelerators, S could contain memory-mapped registers, internal buffers, output ports to on-chip interconnect, and so on. In addition to state variables, an ILA also contains a vector of input variables W that models the input ports of the hardware module, such as the interrupt signals for processors and command inputs for accelerators.
In an ILA, hardware operations are abstracted into a set of instructions following the fetch/decode/execute model as processors. An ILA fetches the opcode from its states S and inputs W. The opcode is a bitvector that will later be decoded to determine which instruction should be issued. The fetch function indicating how is the opcode fetched is represented by F : (S × W)↦bve**cw where w is the width of the opcode. Take programmable cores without interrupts for example, the opcode is fetched from the instruction memory pointed by the program counter, i.e. 