From 87bd6bdb5494d28e4f415a7be4a843e62767eb60 Mon Sep 17 00:00:00 2001 From: Jonathan Balkind Date: Sat, 20 Jul 2024 11:48:11 -0700 Subject: [PATCH] Simulation now runs on VCS and verilator for ariane and ost1 --- .../design/chip/tile/common/rtl/ucb_bus_in.v | 4 +-- .../design/chip/tile/common/rtl/ucb_bus_out.v | 4 +-- piton/design/chip/tile/rtl/tile.v.pyv | 14 ++++---- piton/tools/src/sims/manycore.config | 1 + piton/tools/src/sims/sims,2.0 | 12 +++++++ piton/tools/verilator/my_top.cpp | 2 ++ piton/verif/diag/riscv/rv64/diaglist_riscv64 | 36 +++++++++---------- .../diag/riscv/rv64/rv64-simple.diaglist | 7 ++++ piton/verif/env/common/fake_mem_ctrl.v | 1 - piton/verif/env/manycore/async_fifo_mon.v.pyv | 1 - piton/verif/env/manycore/ciop_iob.v.pyv | 4 +-- .../env/manycore/cmp_l15_messages_mon.v.pyv | 1 - piton/verif/env/manycore/iob_mon.v | 1 - piton/verif/env/manycore/jtag_mon.v.pyv | 1 - piton/verif/env/manycore/l2_mon.v.pyv | 1 - piton/verif/env/manycore/manycore.flist | 23 ------------ .../env/manycore/manycore_network_mon.v.pyv | 1 - piton/verif/env/manycore/manycore_ost1.flist | 24 +++++++++++++ piton/verif/env/manycore/manycore_top.v.pyv | 4 +-- piton/verif/env/manycore/monitor.v.pyv | 2 ++ piton/verif/env/manycore/pc_cmp.v.pyv | 8 +++++ piton/verif/env/manycore/sas_intf.v | 2 -- 22 files changed, 88 insertions(+), 66 deletions(-) create mode 100644 piton/verif/diag/riscv/rv64/rv64-simple.diaglist create mode 100644 piton/verif/env/manycore/manycore_ost1.flist diff --git a/piton/design/chip/tile/common/rtl/ucb_bus_in.v b/piton/design/chip/tile/common/rtl/ucb_bus_in.v index 51a37312b..fea5ede6e 100644 --- a/piton/design/chip/tile/common/rtl/ucb_bus_in.v +++ b/piton/design/chip/tile/common/rtl/ucb_bus_in.v @@ -29,8 +29,8 @@ //////////////////////////////////////////////////////////////////////// // Global header file includes //////////////////////////////////////////////////////////////////////// -`include "sys.h" // system level definition file which contains the - // time scale definition +//`include "sys.h" // system level definition file which contains the +// // time scale definition //////////////////////////////////////////////////////////////////////// // Local header file includes / local defines diff --git a/piton/design/chip/tile/common/rtl/ucb_bus_out.v b/piton/design/chip/tile/common/rtl/ucb_bus_out.v index 342034308..ad9af84aa 100644 --- a/piton/design/chip/tile/common/rtl/ucb_bus_out.v +++ b/piton/design/chip/tile/common/rtl/ucb_bus_out.v @@ -29,8 +29,8 @@ //////////////////////////////////////////////////////////////////////// // Global header file includes //////////////////////////////////////////////////////////////////////// -`include "sys.h" // system level definition file which - // contains the time scale definition +//`include "sys.h" // system level definition file which +// // contains the time scale definition //////////////////////////////////////////////////////////////////////// // Local header file includes / local defines diff --git a/piton/design/chip/tile/rtl/tile.v.pyv b/piton/design/chip/tile/rtl/tile.v.pyv index 09bd6c5c0..f6f0dd040 100644 --- a/piton/design/chip/tile/rtl/tile.v.pyv +++ b/piton/design/chip/tile/rtl/tile.v.pyv @@ -871,13 +871,13 @@ if (TILE_TYPE == `ARIANE_RV64_TILE) begin : g_ariane_core // Could remove this converter after Ariane is changed to send the // PMesh standard data size - assign transducer_l15_size = (transducer_l15_size_pcx_standard == `PCX_SZ_1B) ? `MSG_DATA_SIZE_1B : - (transducer_l15_size_pcx_standard == `PCX_SZ_2B) ? `MSG_DATA_SIZE_2B : - (transducer_l15_size_pcx_standard == `PCX_SZ_4B) ? `MSG_DATA_SIZE_4B : - (transducer_l15_size_pcx_standard == `PCX_SZ_8B) ? `MSG_DATA_SIZE_8B : - (transducer_l15_size_pcx_standard == `PCX_SZ_16B && - transducer_l15_rqtype == `PCX_REQTYPE_IFILL && - ~transducer_l15_invalidate_cacheline) ? `MSG_DATA_SIZE_32B : `MSG_DATA_SIZE_16B; + assign transducer_l15_size = (transducer_l15_size_pcx_standard == 3'b000) ? `MSG_DATA_SIZE_1B : + (transducer_l15_size_pcx_standard == 3'b001) ? `MSG_DATA_SIZE_2B : + (transducer_l15_size_pcx_standard == 3'b010) ? `MSG_DATA_SIZE_4B : + (transducer_l15_size_pcx_standard == 3'b011) ? `MSG_DATA_SIZE_8B : + (transducer_l15_size_pcx_standard == 3'b111 && + transducer_l15_rqtype == `PCX_REQTYPE_IFILL && + ~transducer_l15_invalidate_cacheline) ? `MSG_DATA_SIZE_32B : `MSG_DATA_SIZE_16B; wire [63:0] ariane_bootaddr; diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index a2d153ddf..24abdd071 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -59,6 +59,7 @@ -flist=$OST1_ROOT/common/rtl/Flist.clib_common -flist=$OST1_ROOT/common/rtl/Flist.dft_common -flist=$OST1_ROOT/common/rtl/Flist.dlib_common + -flist=$DV_ROOT/verif/env/manycore/manycore_ost1.flist -sparcv9 -config_rtl=PITON_OST1 #endif diff --git a/piton/tools/src/sims/sims,2.0 b/piton/tools/src/sims/sims,2.0 index e9c7900b3..0b6076fec 100755 --- a/piton/tools/src/sims/sims,2.0 +++ b/piton/tools/src/sims/sims,2.0 @@ -912,6 +912,10 @@ sub regress } else { $cmd .= "-other_sim_build " ; } + $cmd .= "-ost1 " if $opt{ost1} ; + $cmd .= "-ariane " if $opt{ariane} ; + $cmd .= "-pico " if $opt{pico} ; + $cmd .= "-pico_het " if $opt{pico_het} ; $cmd .= "$buildargs " ; $cmd .= "-build_id=$build_id " ; @@ -987,6 +991,10 @@ sub regress push (@cmd, "-other_sim_run") ; } push (@cmd, "-sys=${sys}") ; + push (@cmd, "-ost1") if $opt{ost1} ; + push (@cmd, "-ariane") if $opt{ariane} ; + push (@cmd, "-pico") if $opt{pico} ; + push (@cmd, "-pico_het") if $opt{pico_het} ; push (@cmd, "-build_id=${build_id}") ; push (@cmd, "-regress_id=${regress_id}") ; push (@cmd, "-alias=${dirname}") ; @@ -2610,6 +2618,10 @@ sub parse_args 'dmbr!', 'dmbr_checker!', 'oram!', + 'ost1!', + 'ariane!', + 'pico!', + 'pico_het!', ); # print out all command line arguments + config arguments diff --git a/piton/tools/verilator/my_top.cpp b/piton/tools/verilator/my_top.cpp index 171b5648f..028dddf5a 100644 --- a/piton/tools/verilator/my_top.cpp +++ b/piton/tools/verilator/my_top.cpp @@ -31,6 +31,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "verilated_vcd_c.h" #endif +extern "C" void init_jbus_model_call(char *str, int oram); + uint64_t main_time = 0; // Current simulation time uint64_t clk = 0; Vcmp_top* top; diff --git a/piton/verif/diag/riscv/rv64/diaglist_riscv64 b/piton/verif/diag/riscv/rv64/diaglist_riscv64 index fe6d02e81..a2e1c440e 100644 --- a/piton/verif/diag/riscv/rv64/diaglist_riscv64 +++ b/piton/verif/diag/riscv/rv64/diaglist_riscv64 @@ -1,13 +1,13 @@ - + // note: these asm tests assume that the RISCV tests have been precompiled with the // correct environment - #include "riscv/rv64/rv64ui-p.diaglist" - #include "riscv/rv64/rv64mi-p.diaglist" - #include "riscv/rv64/rv64si-p.diaglist" - #include "riscv/rv64/rv64um-p.diaglist" +#include "riscv/rv64/rv64ui-p.diaglist" +#include "riscv/rv64/rv64mi-p.diaglist" +#include "riscv/rv64/rv64si-p.diaglist" +#include "riscv/rv64/rv64um-p.diaglist" @@ -15,8 +15,8 @@ // correct environment - #include "riscv/rv64/rv64ui-v.diaglist" - #include "riscv/rv64/rv64um-v.diaglist" +#include "riscv/rv64/rv64ui-v.diaglist" +#include "riscv/rv64/rv64um-v.diaglist" @@ -24,7 +24,7 @@ // correct environment - #include "riscv/rv64/rv64ua-p.diaglist" +#include "riscv/rv64/rv64ua-p.diaglist" @@ -32,7 +32,7 @@ // correct environment - #include "riscv/rv64/rv64ua-v.diaglist" +#include "riscv/rv64/rv64ua-v.diaglist" @@ -40,8 +40,8 @@ // correct environment - #include "riscv/rv64/rv64uf-p.diaglist" - #include "riscv/rv64/rv64ud-p.diaglist" +#include "riscv/rv64/rv64uf-p.diaglist" +#include "riscv/rv64/rv64ud-p.diaglist" @@ -49,8 +49,8 @@ // correct environment - #include "riscv/rv64/rv64uf-v.diaglist" - #include "riscv/rv64/rv64ud-v.diaglist" +#include "riscv/rv64/rv64uf-v.diaglist" +#include "riscv/rv64/rv64ud-v.diaglist" @@ -58,15 +58,13 @@ // correct environment - #include "riscv/rv64/rv64-benchmarks.diaglist" +#include "riscv/rv64/rv64-benchmarks.diaglist" - - ariane-hello-world hello_world.c - ariane-accu accu_test.c - ariane-amo-align amo_align.c + +#include "riscv/rv64/rv64-simple.diaglist" @@ -77,7 +75,7 @@ - ariane-hello-world-many hello_world_many.c +ariane-hello-world-many hello_world_many.c diff --git a/piton/verif/diag/riscv/rv64/rv64-simple.diaglist b/piton/verif/diag/riscv/rv64/rv64-simple.diaglist new file mode 100644 index 000000000..5af717701 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64-simple.diaglist @@ -0,0 +1,7 @@ + + + ariane-hello-world hello_world.c + ariane-accu accu_test.c + ariane-amo-align amo_align.c + + diff --git a/piton/verif/env/common/fake_mem_ctrl.v b/piton/verif/env/common/fake_mem_ctrl.v index 652850a80..54771b3f1 100644 --- a/piton/verif/env/common/fake_mem_ctrl.v +++ b/piton/verif/env/common/fake_mem_ctrl.v @@ -39,7 +39,6 @@ `include "l2.tmp.h" `include "define.tmp.h" -`include "iop.h" `define MEM_ADDR_WIDTH 64 diff --git a/piton/verif/env/manycore/async_fifo_mon.v.pyv b/piton/verif/env/manycore/async_fifo_mon.v.pyv index e7f1391e9..135583dd4 100644 --- a/piton/verif/env/manycore/async_fifo_mon.v.pyv +++ b/piton/verif/env/manycore/async_fifo_mon.v.pyv @@ -40,7 +40,6 @@ -`include "iop.h" `include "define.tmp.h" `include "cross_module.tmp.h" diff --git a/piton/verif/env/manycore/ciop_iob.v.pyv b/piton/verif/env/manycore/ciop_iob.v.pyv index fc68679d4..648cdeb49 100644 --- a/piton/verif/env/manycore/ciop_iob.v.pyv +++ b/piton/verif/env/manycore/ciop_iob.v.pyv @@ -46,9 +46,9 @@ print(tt) %> ); //temp. memory. -reg [`CPX_WIDTH-1:0] fake_iob_out_data; +reg [159:0] fake_iob_out_data; -wire [`CPX_WIDTH-1:0] cpx_data = fake_iob_out_data; +wire [159:0] cpx_data = fake_iob_out_data; // Output buffer // The output buffer need to be asynchronous and cannot ever be overflowed. diff --git a/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv b/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv index 982fcd34e..70e0937fb 100644 --- a/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv +++ b/piton/verif/env/manycore/cmp_l15_messages_mon.v.pyv @@ -21,7 +21,6 @@ // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////// -`include "iop.h" `include "define.tmp.h" `include "cross_module.tmp.h" `include "l15.tmp.h" diff --git a/piton/verif/env/manycore/iob_mon.v b/piton/verif/env/manycore/iob_mon.v index 2ebc9d0d6..19ca0067f 100644 --- a/piton/verif/env/manycore/iob_mon.v +++ b/piton/verif/env/manycore/iob_mon.v @@ -40,7 +40,6 @@ -`include "iop.h" `include "cross_module.tmp.h" module iob_mon ( diff --git a/piton/verif/env/manycore/jtag_mon.v.pyv b/piton/verif/env/manycore/jtag_mon.v.pyv index e533b4391..030861f11 100644 --- a/piton/verif/env/manycore/jtag_mon.v.pyv +++ b/piton/verif/env/manycore/jtag_mon.v.pyv @@ -21,7 +21,6 @@ // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////// -`include "iop.h" `include "cross_module.tmp.h" `include "jtag.vh" diff --git a/piton/verif/env/manycore/l2_mon.v.pyv b/piton/verif/env/manycore/l2_mon.v.pyv index 65f086963..215419c9b 100644 --- a/piton/verif/env/manycore/l2_mon.v.pyv +++ b/piton/verif/env/manycore/l2_mon.v.pyv @@ -47,7 +47,6 @@ `include "define.tmp.h" `include "l2.tmp.h" -`include "iop.h" `include "cross_module.tmp.h" module l2_mon ( diff --git a/piton/verif/env/manycore/manycore.flist b/piton/verif/env/manycore/manycore.flist index 5c1096718..5ca4a162b 100644 --- a/piton/verif/env/manycore/manycore.flist +++ b/piton/verif/env/manycore/manycore.flist @@ -26,32 +26,9 @@ cross_module.h manycore_network_mon.v // -v one_hot_mux_mon.v --v sas_intf.v -// //-v tlb_mon.v -v monitor.v --v sas_tasks.v -v pc_cmp.v --v sas_task.v --v l_cache_mon.v --v thrfsm_mon.v // monitors for X's in the processor states --v sparc_pipe_flow.v --v multicycle_mon.v -v dmbr_mon.v --v cmp_pcxandcpx.v --v tso_mon.v --v lsu_mon.v --v lsu_mon2.v --v exu_mon.v -// -v err_inject.v --v mask_mon.v --v pc_muxsel_mon.v --v nukeint_mon.v --v stb_ovfl_mon.v --v icache_mutex_mon.v --v nc_inv_chk.v --v tlu_mon.v --v softint_mon.v - -v slam_init.v -v ciop_iob.v -v cmp_l15_messages_mon.v -v jtag_mon.v diff --git a/piton/verif/env/manycore/manycore_network_mon.v.pyv b/piton/verif/env/manycore/manycore_network_mon.v.pyv index 0db8074bd..45fc67504 100644 --- a/piton/verif/env/manycore/manycore_network_mon.v.pyv +++ b/piton/verif/env/manycore/manycore_network_mon.v.pyv @@ -21,7 +21,6 @@ // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////// -`include "iop.h" `include "cross_module.tmp.h" diff --git a/piton/verif/env/manycore/manycore_ost1.flist b/piton/verif/env/manycore/manycore_ost1.flist new file mode 100644 index 000000000..0317e0d80 --- /dev/null +++ b/piton/verif/env/manycore/manycore_ost1.flist @@ -0,0 +1,24 @@ + +-v sas_intf.v +// //-v tlb_mon.v +-v sas_tasks.v +-v sas_task.v +-v l_cache_mon.v +-v thrfsm_mon.v // monitors for X's in the processor states +-v sparc_pipe_flow.v +-v multicycle_mon.v +-v cmp_pcxandcpx.v +-v tso_mon.v +-v lsu_mon.v +-v lsu_mon2.v +-v exu_mon.v +// -v err_inject.v +-v mask_mon.v +-v pc_muxsel_mon.v +-v nukeint_mon.v +-v stb_ovfl_mon.v +-v icache_mutex_mon.v +-v nc_inv_chk.v +-v tlu_mon.v +-v softint_mon.v + -v slam_init.v diff --git a/piton/verif/env/manycore/manycore_top.v.pyv b/piton/verif/env/manycore/manycore_top.v.pyv index 5fb70ba67..a14c36543 100644 --- a/piton/verif/env/manycore/manycore_top.v.pyv +++ b/piton/verif/env/manycore/manycore_top.v.pyv @@ -21,9 +21,7 @@ // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////// -`include "iop.h" `include "cross_module.tmp.h" -`include "ifu.tmp.h" `include "define.tmp.h" `include "piton_system.vh" @@ -482,9 +480,11 @@ system system( print(tt) %> +`ifdef PITON_OST1 `ifndef VERILATOR // T1's TSO monitor, stripped of all L2 references tso_mon tso_mon(`CHIP_INT_CLK, `CHIP.rst_n_inter_sync); +`endif `endif // L15 MONITORS diff --git a/piton/verif/env/manycore/monitor.v.pyv b/piton/verif/env/manycore/monitor.v.pyv index 72fb15637..bdc2d6e61 100644 --- a/piton/verif/env/manycore/monitor.v.pyv +++ b/piton/verif/env/manycore/monitor.v.pyv @@ -20,8 +20,10 @@ // // ========== Copyright Header End ============================================ `include "cross_module.tmp.h" +`ifdef PITON_OST1 `include "iop.h" `include "ifu.tmp.h" +`endif //define and will move all the define to cross.h later `define PLI_QUIT 1 /* None */ diff --git a/piton/verif/env/manycore/pc_cmp.v.pyv b/piton/verif/env/manycore/pc_cmp.v.pyv index 4ef433a51..3c5dbc656 100644 --- a/piton/verif/env/manycore/pc_cmp.v.pyv +++ b/piton/verif/env/manycore/pc_cmp.v.pyv @@ -21,7 +21,9 @@ // ========== Copyright Header End ============================================ `include "define.tmp.h" +`ifdef INCLUDE_SAS_TASKS `include "ifu.tmp.h" +`endif <% from pyhplib import * @@ -51,7 +53,9 @@ input rst_l; reg [31:0] active_thread; reg [31:0] back_thread, good_delay; reg [31:0] good, good_for; + `ifdef INCLUDE_SAS_TASKS reg [4:0] thread_status[31:0]; + `endif ''' tt2 = r'''reg [7:0] done;''' tt1 = tt1.replace("31", repr(PITON_NUM_TILES*4-1)); @@ -345,14 +349,18 @@ task check_time; begin for(ind = head; ind < tail; ind = ind + 1)begin if(timeout[ind] > max && (good[ind] == 0))begin + `ifdef INCLUDE_SAS_TASKS if((max_cycle == 0 || finish_mask[ind] == 0) && (thread_status[ind] == `THRFSM_HALT) )begin timeout[ind] = 0; end else begin + `endif $display("Info: spc(%0d) thread(%0d) -> timeout happen", ind / 4, ind % 4); `MONITOR_PATH.fail("TIMEOUT"); + `ifdef INCLUDE_SAS_TASKS end + `endif end else if(active_thread[ind] != good[ind])begin timeout[ind] = timeout[ind] + 1; diff --git a/piton/verif/env/manycore/sas_intf.v b/piton/verif/env/manycore/sas_intf.v index d536ce36d..9246f4c67 100644 --- a/piton/verif/env/manycore/sas_intf.v +++ b/piton/verif/env/manycore/sas_intf.v @@ -21,9 +21,7 @@ // ========== Copyright Header End ============================================ //////////////////////////////////////////////////////// -`include "iop.h" `include "lsu.tmp.h" -`include "ifu.tmp.h" `include "cross_module.tmp.h" `define INTF0_WIDTH 61 `define INTF1_WIDTH 125