Fix verilator complaint on diag_done

diag_done shouldn't have been an input to manycore_top.v.pyv - it's not used in my_top.cpp

Author: Jbalkind

piton/verif/env/manycore/manycore_top.v.pyv

@@ -59,7 +59,6 @@ input reg [4:0]                       pll_rangea,
 output wire                            pll_lock,
 input reg [1:0]                       clk_mux_sel,
 input reg                             async_mux,
-input                                 diag_done,
 input                                 ok_iob
 `endif
 );
@@ -80,9 +79,10 @@ reg [1:0]                       clk_mux_sel;
 reg                             async_mux;
 // For simulation only, monitor stuff.  Only cross-module referenced
 // do not delete.
-reg                             diag_done;
 `endif // ifndef VERILATOR
 
+reg                             diag_done;
+
 reg                             io_clk;
 reg                             jtag_clk;
 reg                             chipset_clk_osc_p;