From f00ed67440a69e0191dadc175682c396eeb9c87e Mon Sep 17 00:00:00 2001 From: Jonathan Balkind Date: Sat, 23 Sep 2023 13:28:55 -0700 Subject: [PATCH] Refactoring riscv64 ISA tests to make use by multiple cores easier --- piton/verif/diag/master_diaglist | 4 +- .../{master_diaglist_rv32 => diaglist_rv32} | 0 piton/verif/diag/riscv/rv64/diaglist_riscv64 | 84 +++++ .../diag/riscv/rv64/master_diaglist_riscv64 | 295 ------------------ .../diag/riscv/rv64/rv64-benchmarks.diaglist | 14 + piton/verif/diag/riscv/rv64/rv64mi-p.diaglist | 15 + piton/verif/diag/riscv/rv64/rv64si-p.diaglist | 13 + piton/verif/diag/riscv/rv64/rv64ua-p.diaglist | 25 ++ piton/verif/diag/riscv/rv64/rv64ua-v.diaglist | 25 ++ piton/verif/diag/riscv/rv64/rv64uc-p.diaglist | 7 + piton/verif/diag/riscv/rv64/rv64uc-v.diaglist | 7 + piton/verif/diag/riscv/rv64/rv64ud-f.diaglist | 18 ++ piton/verif/diag/riscv/rv64/rv64ud-p.diaglist | 18 ++ piton/verif/diag/riscv/rv64/rv64ud-v.diaglist | 19 ++ piton/verif/diag/riscv/rv64/rv64uf-p.diaglist | 17 + piton/verif/diag/riscv/rv64/rv64uf-v.diaglist | 18 ++ piton/verif/diag/riscv/rv64/rv64ui-p.diaglist | 57 ++++ piton/verif/diag/riscv/rv64/rv64ui-v.diaglist | 57 ++++ piton/verif/diag/riscv/rv64/rv64um-p.diaglist | 19 ++ piton/verif/diag/riscv/rv64/rv64um-v.diaglist | 19 ++ 20 files changed, 434 insertions(+), 297 deletions(-) rename piton/verif/diag/riscv/rv32/{master_diaglist_rv32 => diaglist_rv32} (100%) create mode 100644 piton/verif/diag/riscv/rv64/diaglist_riscv64 delete mode 100644 piton/verif/diag/riscv/rv64/master_diaglist_riscv64 create mode 100644 piton/verif/diag/riscv/rv64/rv64-benchmarks.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64mi-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64si-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64ua-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64ua-v.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64uc-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64uc-v.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64ud-f.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64ud-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64ud-v.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64uf-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64uf-v.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64ui-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64ui-v.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64um-p.diaglist create mode 100644 piton/verif/diag/riscv/rv64/rv64um-v.diaglist diff --git a/piton/verif/diag/master_diaglist b/piton/verif/diag/master_diaglist index 6cb108750..65553ac2b 100644 --- a/piton/verif/diag/master_diaglist +++ b/piton/verif/diag/master_diaglist @@ -31,11 +31,11 @@ // ifdef SPARCV9 #endif #ifdef RISCV64 -#include "riscv/rv64/master_diaglist_riscv64" +#include "riscv/rv64/diaglist_riscv64" // ifdef RISCV64 #endif #ifdef RISCV32 -#include "riscv/rv32/master_diaglist_riscv32" +#include "riscv/rv32/diaglist_riscv32" // ifdef RISCV32 #endif diff --git a/piton/verif/diag/riscv/rv32/master_diaglist_rv32 b/piton/verif/diag/riscv/rv32/diaglist_rv32 similarity index 100% rename from piton/verif/diag/riscv/rv32/master_diaglist_rv32 rename to piton/verif/diag/riscv/rv32/diaglist_rv32 diff --git a/piton/verif/diag/riscv/rv64/diaglist_riscv64 b/piton/verif/diag/riscv/rv64/diaglist_riscv64 new file mode 100644 index 000000000..fe6d02e81 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/diaglist_riscv64 @@ -0,0 +1,84 @@ + + + // note: these asm tests assume that the RISCV tests have been precompiled with the + // correct environment + + + #include "riscv/rv64/rv64ui-p.diaglist" + #include "riscv/rv64/rv64mi-p.diaglist" + #include "riscv/rv64/rv64si-p.diaglist" + #include "riscv/rv64/rv64um-p.diaglist" + + + + // note: these asm tests assume that the RISCV tests have been precompiled with the + // correct environment + + + #include "riscv/rv64/rv64ui-v.diaglist" + #include "riscv/rv64/rv64um-v.diaglist" + + + + // note: these asm tests assume that the RISCV tests have been precompiled with the + // correct environment + + + #include "riscv/rv64/rv64ua-p.diaglist" + + + + // note: these asm tests assume that the RISCV tests have been precompiled with the + // correct environment + + + #include "riscv/rv64/rv64ua-v.diaglist" + + + + // note: these asm tests assume that the RISCV tests have been precompiled with the + // correct environment + + + #include "riscv/rv64/rv64uf-p.diaglist" + #include "riscv/rv64/rv64ud-p.diaglist" + + + + // note: these asm tests assume that the RISCV tests have been precompiled with the + // correct environment + + + #include "riscv/rv64/rv64uf-v.diaglist" + #include "riscv/rv64/rv64ud-v.diaglist" + + + + // note: these asm tests assume that the RISCV tests have been precompiled with the + // correct environment + + + #include "riscv/rv64/rv64-benchmarks.diaglist" + + + + + + ariane-hello-world hello_world.c + ariane-accu accu_test.c + ariane-amo-align amo_align.c + + + + + + + + + + + ariane-hello-world-many hello_world_many.c + + + + diff --git a/piton/verif/diag/riscv/rv64/master_diaglist_riscv64 b/piton/verif/diag/riscv/rv64/master_diaglist_riscv64 deleted file mode 100644 index 7c9e819c3..000000000 --- a/piton/verif/diag/riscv/rv64/master_diaglist_riscv64 +++ /dev/null @@ -1,295 +0,0 @@ - - - // note: these asm tests assume that the RISCV tests have been precompiled with the - // correct environment - - - ariane-rv64ui-p-add rv64ui-p-add.S - ariane-rv64ui-p-addi rv64ui-p-addi.S - ariane-rv64ui-p-slli rv64ui-p-slli.S - ariane-rv64ui-p-addiw rv64ui-p-addiw.S - ariane-rv64ui-p-addw rv64ui-p-addw.S - ariane-rv64ui-p-and rv64ui-p-and.S - ariane-rv64ui-p-auipc rv64ui-p-auipc.S - ariane-rv64ui-p-beq rv64ui-p-beq.S - ariane-rv64ui-p-bge rv64ui-p-bge.S - ariane-rv64ui-p-bgeu rv64ui-p-bgeu.S - ariane-rv64ui-p-andi rv64ui-p-andi.S - ariane-rv64ui-p-blt rv64ui-p-blt.S - ariane-rv64ui-p-bltu rv64ui-p-bltu.S - ariane-rv64ui-p-bne rv64ui-p-bne.S - // ariane-rv64ui-p-simple rv64ui-p-simple.S - ariane-rv64ui-p-jal rv64ui-p-jal.S - ariane-rv64ui-p-jalr rv64ui-p-jalr.S - ariane-rv64ui-p-or rv64ui-p-or.S - ariane-rv64ui-p-ori rv64ui-p-ori.S - ariane-rv64ui-p-sub rv64ui-p-sub.S - ariane-rv64ui-p-subw rv64ui-p-subw.S - ariane-rv64ui-p-xor rv64ui-p-xor.S - ariane-rv64ui-p-xori rv64ui-p-xori.S - ariane-rv64ui-p-slliw rv64ui-p-slliw.S - ariane-rv64ui-p-sll rv64ui-p-sll.S - ariane-rv64ui-p-sllw rv64ui-p-sllw.S - ariane-rv64ui-p-slt rv64ui-p-slt.S - ariane-rv64ui-p-slti rv64ui-p-slti.S - ariane-rv64ui-p-sltiu rv64ui-p-sltiu.S - ariane-rv64ui-p-sltu rv64ui-p-sltu.S - ariane-rv64ui-p-sra rv64ui-p-sra.S - ariane-rv64ui-p-srai rv64ui-p-srai.S - ariane-rv64ui-p-sraiw rv64ui-p-sraiw.S - ariane-rv64ui-p-sraw rv64ui-p-sraw.S - ariane-rv64ui-p-srl rv64ui-p-srl.S - ariane-rv64ui-p-srli rv64ui-p-srli.S - ariane-rv64ui-p-srliw rv64ui-p-srliw.S - ariane-rv64ui-p-srlw rv64ui-p-srlw.S - ariane-rv64ui-p-lb rv64ui-p-lb.S - ariane-rv64ui-p-lbu rv64ui-p-lbu.S - ariane-rv64ui-p-ld rv64ui-p-ld.S - ariane-rv64ui-p-lh rv64ui-p-lh.S - ariane-rv64ui-p-lhu rv64ui-p-lhu.S - ariane-rv64ui-p-lui rv64ui-p-lui.S - ariane-rv64ui-p-lw rv64ui-p-lw.S - ariane-rv64ui-p-lwu rv64ui-p-lwu.S - // ariane-rv64mi-p-csr rv64mi-p-csr.S - ariane-rv64mi-p-mcsr rv64mi-p-mcsr.S - ariane-rv64mi-p-illegal rv64mi-p-illegal.S - ariane-rv64mi-p-ma_addr rv64mi-p-ma_addr.S - ariane-rv64mi-p-ma_fetch rv64mi-p-ma_fetch.S - ariane-rv64mi-p-sbreak rv64mi-p-sbreak.S - // ariane-rv64mi-p-scall rv64mi-p-scall.S - // ariane-rv64si-p-csr rv64si-p-csr.S - ariane-rv64si-p-ma_fetch rv64si-p-ma_fetch.S - ariane-rv64si-p-scall rv64si-p-scall.S - // ariane-rv64si-p-wfi rv64si-p-wfi.S - ariane-rv64si-p-sbreak rv64si-p-sbreak.S - ariane-rv64si-p-dirty rv64si-p-dirty.S - ariane-rv64uc-p-rvc rv64uc-p-rvc.S - ariane-rv64um-p-mul rv64um-p-mul.S - ariane-rv64um-p-mulh rv64um-p-mulh.S - ariane-rv64um-p-mulhsu rv64um-p-mulhsu.S - ariane-rv64um-p-mulhu rv64um-p-mulhu.S - ariane-rv64um-p-div rv64um-p-div.S - ariane-rv64um-p-divu rv64um-p-divu.S - ariane-rv64um-p-rem rv64um-p-rem.S - ariane-rv64um-p-remu rv64um-p-remu.S - ariane-rv64um-p-mulw rv64um-p-mulw.S - ariane-rv64um-p-divw rv64um-p-divw.S - ariane-rv64um-p-divuw rv64um-p-divuw.S - ariane-rv64um-p-remw rv64um-p-remw.S - ariane-rv64um-p-remuw rv64um-p-remuw.S - - - - // note: these asm tests assume that the RISCV tests have been precompiled with the - // correct environment - - // note: we have to offset the trap here since the core operates in VM - - ariane-rv64ui-v-add rv64ui-v-add.S - ariane-rv64ui-v-addi rv64ui-v-addi.S - ariane-rv64ui-v-addiw rv64ui-v-addiw.S - ariane-rv64ui-v-addw rv64ui-v-addw.S - ariane-rv64ui-v-and rv64ui-v-and.S - ariane-rv64ui-v-auipc rv64ui-v-auipc.S - ariane-rv64ui-v-beq rv64ui-v-beq.S - ariane-rv64ui-v-bge rv64ui-v-bge.S - ariane-rv64ui-v-bgeu rv64ui-v-bgeu.S - ariane-rv64ui-v-andi rv64ui-v-andi.S - ariane-rv64ui-v-blt rv64ui-v-blt.S - ariane-rv64ui-v-bltu rv64ui-v-bltu.S - ariane-rv64ui-v-bne rv64ui-v-bne.S - // ariane-rv64ui-v-simple rv64ui-v-simple.S - ariane-rv64ui-v-jal rv64ui-v-jal.S - ariane-rv64ui-v-jalr rv64ui-v-jalr.S - ariane-rv64ui-v-or rv64ui-v-or.S - ariane-rv64ui-v-ori rv64ui-v-ori.S - ariane-rv64ui-v-sub rv64ui-v-sub.S - ariane-rv64ui-v-subw rv64ui-v-subw.S - ariane-rv64ui-v-xor rv64ui-v-xor.S - ariane-rv64ui-v-xori rv64ui-v-xori.S - ariane-rv64ui-v-sll rv64ui-v-sll.S - ariane-rv64ui-v-slli rv64ui-v-slli.S - ariane-rv64ui-v-slliw rv64ui-v-slliw.S - ariane-rv64ui-v-slt rv64ui-v-slt.S - ariane-rv64ui-v-slti rv64ui-v-slti.S - ariane-rv64ui-v-sltiu rv64ui-v-sltiu.S - ariane-rv64ui-v-sltu rv64ui-v-sltu.S - ariane-rv64ui-v-sra rv64ui-v-sra.S - ariane-rv64ui-v-srai rv64ui-v-srai.S - ariane-rv64ui-v-sraiw rv64ui-v-sraiw.S - ariane-rv64ui-v-sraw rv64ui-v-sraw.S - ariane-rv64ui-v-srl rv64ui-v-srl.S - ariane-rv64ui-v-srli rv64ui-v-srli.S - ariane-rv64ui-v-srliw rv64ui-v-srliw.S - ariane-rv64ui-v-srlw rv64ui-v-srlw.S - ariane-rv64ui-v-lb rv64ui-v-lb.S - ariane-rv64ui-v-lbu rv64ui-v-lbu.S - ariane-rv64ui-v-ld rv64ui-v-ld.S - ariane-rv64ui-v-lh rv64ui-v-lh.S - ariane-rv64ui-v-lhu rv64ui-v-lhu.S - ariane-rv64ui-v-lui rv64ui-v-lui.S - ariane-rv64um-v-mul rv64um-v-mul.S - ariane-rv64um-v-mulh rv64um-v-mulh.S - ariane-rv64um-v-mulhsu rv64um-v-mulhsu.S - ariane-rv64um-v-mulhu rv64um-v-mulhu.S - ariane-rv64um-v-div rv64um-v-div.S - ariane-rv64um-v-divu rv64um-v-divu.S - ariane-rv64um-v-rem rv64um-v-rem.S - ariane-rv64um-v-remu rv64um-v-remu.S - ariane-rv64um-v-mulw rv64um-v-mulw.S - ariane-rv64um-v-divw rv64um-v-divw.S - ariane-rv64um-v-divuw rv64um-v-divuw.S - ariane-rv64um-v-remw rv64um-v-remw.S - ariane-rv64um-v-remuw rv64um-v-remuw.S - - - - // note: these asm tests assume that the RISCV tests have been precompiled with the - // correct environment - - - ariane-rv64ua-p-amoadd_d rv64ua-p-amoadd_d.S - ariane-rv64ua-p-amoadd_w rv64ua-p-amoadd_w.S - ariane-rv64ua-p-amoor_d rv64ua-p-amoor_d.S - ariane-rv64ua-p-amoor_w rv64ua-p-amoor_w.S - ariane-rv64ua-p-amoand_d rv64ua-p-amoand_d.S - ariane-rv64ua-p-amoand_w rv64ua-p-amoand_w.S - ariane-rv64ua-p-amoswap_d rv64ua-p-amoswap_d.S - ariane-rv64ua-p-amoswap_w rv64ua-p-amoswap_w.S - ariane-rv64ua-p-amoxor_d rv64ua-p-amoxor_d.S - ariane-rv64ua-p-amoxor_w rv64ua-p-amoxor_w.S - ariane-rv64ua-p-amomax_d rv64ua-p-amomax_d.S - ariane-rv64ua-p-amomaxu_d rv64ua-p-amomaxu_d.S - ariane-rv64ua-p-amomaxu_w rv64ua-p-amomaxu_w.S - ariane-rv64ua-p-amomax_w rv64ua-p-amomax_w.S - ariane-rv64ua-p-amomin_d rv64ua-p-amomin_d.S - ariane-rv64ua-p-amomin_w rv64ua-p-amomin_w.S - ariane-rv64ua-p-amominu_d rv64ua-p-amominu_d.S - ariane-rv64ua-p-amominu_w rv64ua-p-amominu_w.S - ariane-rv64ua-p-lrsc rv64ua-p-lrsc.S - - - - // note: these asm tests assume that the RISCV tests have been precompiled with the - // correct environment - - // note: we have to offset the trap here since the core operates in VM - - ariane-rv64ua-v-amoadd_d rv64ua-v-amoadd_d.S - ariane-rv64ua-v-amoadd_w rv64ua-v-amoadd_w.S - ariane-rv64ua-v-amoor_d rv64ua-v-amoor_d.S - ariane-rv64ua-v-amoor_w rv64ua-v-amoor_w.S - ariane-rv64ua-v-amoand_d rv64ua-v-amoand_d.S - ariane-rv64ua-v-amoand_w rv64ua-v-amoand_w.S - ariane-rv64ua-v-amoswap_d rv64ua-v-amoswap_d.S - ariane-rv64ua-v-amoswap_w rv64ua-v-amoswap_w.S - ariane-rv64ua-v-amoxor_d rv64ua-v-amoxor_d.S - ariane-rv64ua-v-amoxor_w rv64ua-v-amoxor_w.S - ariane-rv64ua-v-amomax_d rv64ua-v-amomax_d.S - ariane-rv64ua-v-amomaxu_d rv64ua-v-amomaxu_d.S - ariane-rv64ua-v-amomaxu_w rv64ua-v-amomaxu_w.S - ariane-rv64ua-v-amomax_w rv64ua-v-amomax_w.S - ariane-rv64ua-v-amomin_d rv64ua-v-amomin_d.S - ariane-rv64ua-v-amomin_w rv64ua-v-amomin_w.S - ariane-rv64ua-v-amominu_d rv64ua-v-amominu_d.S - ariane-rv64ua-v-amominu_w rv64ua-v-amominu_w.S - ariane-rv64ua-v-lrsc rv64ua-v-lrsc.S - - - - // note: these asm tests assume that the RISCV tests have been precompiled with the - // correct environment - - - ariane-rv64uf-p-fadd rv64uf-p-fadd.S - ariane-rv64uf-p-fclass rv64uf-p-fclass.S - ariane-rv64uf-p-fcmp rv64uf-p-fcmp.S - ariane-rv64uf-p-fcvt rv64uf-p-fcvt.S - ariane-rv64uf-p-fcvt_w rv64uf-p-fcvt_w.S - ariane-rv64uf-p-fdiv rv64uf-p-fdiv.S - ariane-rv64uf-p-fmadd rv64uf-p-fmadd.S - ariane-rv64uf-p-fmin rv64uf-p-fmin.S - ariane-rv64uf-p-ldst rv64uf-p-ldst.S - ariane-rv64uf-p-move rv64uf-p-move.S - ariane-rv64uf-p-recoding rv64uf-p-recoding.S - ariane-rv64ud-p-fadd rv64ud-p-fadd.S - ariane-rv64ud-p-fclass rv64ud-p-fclass.S - ariane-rv64ud-p-fcmp rv64ud-p-fcmp.S - ariane-rv64ud-p-fcvt rv64ud-p-fcvt.S - ariane-rv64ud-p-fcvt_w rv64ud-p-fcvt_w.S - ariane-rv64ud-p-fdiv rv64ud-p-fdiv.S - ariane-rv64ud-p-fmadd rv64ud-p-fmadd.S - ariane-rv64ud-p-fmin rv64ud-p-fmin.S - ariane-rv64ud-p-ldst rv64ud-p-ldst.S - ariane-rv64ud-p-move rv64ud-p-move.S - ariane-rv64ud-p-recoding rv64ud-p-recoding.S - // ariane-rv64ud-p-structural rv64ud-p-structural.S - - - - // note: these asm tests assume that the RISCV tests have been precompiled with the - // correct environment - - // note: we have to offset the trap here since the core operates in VM - - ariane-rv64uf-v-fadd rv64uf-v-fadd.S - ariane-rv64uf-v-fclass rv64uf-v-fclass.S - ariane-rv64uf-v-fcmp rv64uf-v-fcmp.S - ariane-rv64uf-v-fcvt rv64uf-v-fcvt.S - ariane-rv64uf-v-fcvt_w rv64uf-v-fcvt_w.S - ariane-rv64uf-v-fdiv rv64uf-v-fdiv.S - ariane-rv64uf-v-fmadd rv64uf-v-fmadd.S - ariane-rv64uf-v-fmin rv64uf-v-fmin.S - ariane-rv64uf-v-ldst rv64uf-v-ldst.S - ariane-rv64uf-v-move rv64uf-v-move.S - ariane-rv64uf-v-recoding rv64uf-v-recoding.S - ariane-rv64ud-v-fadd rv64ud-v-fadd.S - ariane-rv64ud-v-fclass rv64ud-v-fclass.S - ariane-rv64ud-v-fcmp rv64ud-v-fcmp.S - ariane-rv64ud-v-fcvt rv64ud-v-fcvt.S - ariane-rv64ud-v-fcvt_w rv64ud-v-fcvt_w.S - ariane-rv64ud-v-fdiv rv64ud-v-fdiv.S - ariane-rv64ud-v-fmadd rv64ud-v-fmadd.S - ariane-rv64ud-v-fmin rv64ud-v-fmin.S - ariane-rv64ud-v-ldst rv64ud-v-ldst.S - ariane-rv64ud-v-move rv64ud-v-move.S - ariane-rv64ud-v-recoding rv64ud-v-recoding.S - // ariane-rv64ud-v-structural rv64ud-v-structural.S - - - - // note: these asm tests assume that the RISCV tests have been precompiled with the - // correct environment - - - ariane-dhrystone dhrystone.riscv - ariane-median median.riscv - ariane-multiply multiply.riscv - ariane-pmp pmp.riscv - ariane-qsort qsort.riscv - ariane-rsort rsort.riscv - ariane-towers towers.riscv - ariane-vvadd vvadd.riscv - - - - - - ariane-hello-world hello_world.c - ariane-accu accu_test.c - ariane-amo-align amo_align.c - - - - - - - - - - - ariane-hello-world-many hello_world_many.c - - - - diff --git a/piton/verif/diag/riscv/rv64/rv64-benchmarks.diaglist b/piton/verif/diag/riscv/rv64/rv64-benchmarks.diaglist new file mode 100644 index 000000000..b4c49b241 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64-benchmarks.diaglist @@ -0,0 +1,14 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + dhrystone dhrystone.riscv + median median.riscv + multiply multiply.riscv + pmp pmp.riscv + qsort qsort.riscv + rsort rsort.riscv + towers towers.riscv + vvadd vvadd.riscv + + diff --git a/piton/verif/diag/riscv/rv64/rv64mi-p.diaglist b/piton/verif/diag/riscv/rv64/rv64mi-p.diaglist new file mode 100644 index 000000000..0e1ab7a3d --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64mi-p.diaglist @@ -0,0 +1,15 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64mi-p-access rv64mi-p-access.S + rv64mi-p-breakpoint rv64mi-p-breakpoint.S + rv64mi-p-csr rv64mi-p-csr.S + rv64mi-p-illegal rv64mi-p-illegal.S + rv64mi-p-ma_addr rv64mi-p-ma_addr.S + rv64mi-p-ma_fetch rv64mi-p-ma_fetch.S + rv64mi-p-mcsr rv64mi-p-mcsr.S + rv64mi-p-sbreak rv64mi-p-sbreak.S + rv64mi-p-scall rv64mi-p-scall.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64si-p.diaglist b/piton/verif/diag/riscv/rv64/rv64si-p.diaglist new file mode 100644 index 000000000..30dca7459 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64si-p.diaglist @@ -0,0 +1,13 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64si-p-csr rv64si-p-csr.S + rv64si-p-dirty rv64si-p-dirty.S + rv64si-p-icache-alias rv64si-p-icache-alias.S + rv64si-p-ma_fetch rv64si-p-ma_fetch.S + rv64si-p-sbreak rv64si-p-sbreak.S + rv64si-p-scall rv64si-p-scall.S + rv64si-p-wfi rv64si-p-wfi.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64ua-p.diaglist b/piton/verif/diag/riscv/rv64/rv64ua-p.diaglist new file mode 100644 index 000000000..5ee2bd034 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64ua-p.diaglist @@ -0,0 +1,25 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64ua-p-amoadd_d rv64ua-p-amoadd_d.S + rv64ua-p-amoadd_w rv64ua-p-amoadd_w.S + rv64ua-p-amoor_d rv64ua-p-amoor_d.S + rv64ua-p-amoor_w rv64ua-p-amoor_w.S + rv64ua-p-amoand_d rv64ua-p-amoand_d.S + rv64ua-p-amoand_w rv64ua-p-amoand_w.S + rv64ua-p-amoswap_d rv64ua-p-amoswap_d.S + rv64ua-p-amoswap_w rv64ua-p-amoswap_w.S + rv64ua-p-amoxor_d rv64ua-p-amoxor_d.S + rv64ua-p-amoxor_w rv64ua-p-amoxor_w.S + rv64ua-p-amomax_d rv64ua-p-amomax_d.S + rv64ua-p-amomaxu_d rv64ua-p-amomaxu_d.S + rv64ua-p-amomaxu_w rv64ua-p-amomaxu_w.S + rv64ua-p-amomax_w rv64ua-p-amomax_w.S + rv64ua-p-amomin_d rv64ua-p-amomin_d.S + rv64ua-p-amomin_w rv64ua-p-amomin_w.S + rv64ua-p-amominu_d rv64ua-p-amominu_d.S + rv64ua-p-amominu_w rv64ua-p-amominu_w.S + rv64ua-p-lrsc rv64ua-p-lrsc.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64ua-v.diaglist b/piton/verif/diag/riscv/rv64/rv64ua-v.diaglist new file mode 100644 index 000000000..de3764b33 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64ua-v.diaglist @@ -0,0 +1,25 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64ua-v-amoadd_d rv64ua-v-amoadd_d.S + rv64ua-v-amoadd_w rv64ua-v-amoadd_w.S + rv64ua-v-amoor_d rv64ua-v-amoor_d.S + rv64ua-v-amoor_w rv64ua-v-amoor_w.S + rv64ua-v-amoand_d rv64ua-v-amoand_d.S + rv64ua-v-amoand_w rv64ua-v-amoand_w.S + rv64ua-v-amoswap_d rv64ua-v-amoswap_d.S + rv64ua-v-amoswap_w rv64ua-v-amoswap_w.S + rv64ua-v-amoxor_d rv64ua-v-amoxor_d.S + rv64ua-v-amoxor_w rv64ua-v-amoxor_w.S + rv64ua-v-amomax_d rv64ua-v-amomax_d.S + rv64ua-v-amomaxu_d rv64ua-v-amomaxu_d.S + rv64ua-v-amomaxu_w rv64ua-v-amomaxu_w.S + rv64ua-v-amomax_w rv64ua-v-amomax_w.S + rv64ua-v-amomin_d rv64ua-v-amomin_d.S + rv64ua-v-amomin_w rv64ua-v-amomin_w.S + rv64ua-v-amominu_d rv64ua-v-amominu_d.S + rv64ua-v-amominu_w rv64ua-v-amominu_w.S + rv64ua-v-lrsc rv64ua-v-lrsc.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64uc-p.diaglist b/piton/verif/diag/riscv/rv64/rv64uc-p.diaglist new file mode 100644 index 000000000..f06fb1129 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64uc-p.diaglist @@ -0,0 +1,7 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64uc-p-rvc rv64uc-p-rvc.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64uc-v.diaglist b/piton/verif/diag/riscv/rv64/rv64uc-v.diaglist new file mode 100644 index 000000000..0d8d1b1c9 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64uc-v.diaglist @@ -0,0 +1,7 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64uc-v-rvc rv64uc-v-rvc.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64ud-f.diaglist b/piton/verif/diag/riscv/rv64/rv64ud-f.diaglist new file mode 100644 index 000000000..134ee040c --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64ud-f.diaglist @@ -0,0 +1,18 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + // note: we have to offset the trap here since the core operates in VM + + rv64uf-v-fadd rv64uf-v-fadd.S + rv64uf-v-fclass rv64uf-v-fclass.S + rv64uf-v-fcmp rv64uf-v-fcmp.S + rv64uf-v-fcvt rv64uf-v-fcvt.S + rv64uf-v-fcvt_w rv64uf-v-fcvt_w.S + rv64uf-v-fdiv rv64uf-v-fdiv.S + rv64uf-v-fmadd rv64uf-v-fmadd.S + rv64uf-v-fmin rv64uf-v-fmin.S + rv64uf-v-ldst rv64uf-v-ldst.S + rv64uf-v-move rv64uf-v-move.S + rv64uf-v-recoding rv64uf-v-recoding.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64ud-p.diaglist b/piton/verif/diag/riscv/rv64/rv64ud-p.diaglist new file mode 100644 index 000000000..d8ba08514 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64ud-p.diaglist @@ -0,0 +1,18 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64ud-p-fadd rv64ud-p-fadd.S + rv64ud-p-fclass rv64ud-p-fclass.S + rv64ud-p-fcmp rv64ud-p-fcmp.S + rv64ud-p-fcvt rv64ud-p-fcvt.S + rv64ud-p-fcvt_w rv64ud-p-fcvt_w.S + rv64ud-p-fdiv rv64ud-p-fdiv.S + rv64ud-p-fmadd rv64ud-p-fmadd.S + rv64ud-p-fmin rv64ud-p-fmin.S + rv64ud-p-ldst rv64ud-p-ldst.S + rv64ud-p-move rv64ud-p-move.S + rv64ud-p-recoding rv64ud-p-recoding.S + // rv64ud-p-structural rv64ud-p-structural.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64ud-v.diaglist b/piton/verif/diag/riscv/rv64/rv64ud-v.diaglist new file mode 100644 index 000000000..68c0c741f --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64ud-v.diaglist @@ -0,0 +1,19 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + // note: we have to offset the trap here since the core operates in VM + + rv64ud-v-fadd rv64ud-v-fadd.S + rv64ud-v-fclass rv64ud-v-fclass.S + rv64ud-v-fcmp rv64ud-v-fcmp.S + rv64ud-v-fcvt rv64ud-v-fcvt.S + rv64ud-v-fcvt_w rv64ud-v-fcvt_w.S + rv64ud-v-fdiv rv64ud-v-fdiv.S + rv64ud-v-fmadd rv64ud-v-fmadd.S + rv64ud-v-fmin rv64ud-v-fmin.S + rv64ud-v-ldst rv64ud-v-ldst.S + rv64ud-v-move rv64ud-v-move.S + rv64ud-v-recoding rv64ud-v-recoding.S + // rv64ud-v-structural rv64ud-v-structural.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64uf-p.diaglist b/piton/verif/diag/riscv/rv64/rv64uf-p.diaglist new file mode 100644 index 000000000..f9a3292fa --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64uf-p.diaglist @@ -0,0 +1,17 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64uf-p-fadd rv64uf-p-fadd.S + rv64uf-p-fclass rv64uf-p-fclass.S + rv64uf-p-fcmp rv64uf-p-fcmp.S + rv64uf-p-fcvt rv64uf-p-fcvt.S + rv64uf-p-fcvt_w rv64uf-p-fcvt_w.S + rv64uf-p-fdiv rv64uf-p-fdiv.S + rv64uf-p-fmadd rv64uf-p-fmadd.S + rv64uf-p-fmin rv64uf-p-fmin.S + rv64uf-p-ldst rv64uf-p-ldst.S + rv64uf-p-move rv64uf-p-move.S + rv64uf-p-recoding rv64uf-p-recoding.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64uf-v.diaglist b/piton/verif/diag/riscv/rv64/rv64uf-v.diaglist new file mode 100644 index 000000000..134ee040c --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64uf-v.diaglist @@ -0,0 +1,18 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + // note: we have to offset the trap here since the core operates in VM + + rv64uf-v-fadd rv64uf-v-fadd.S + rv64uf-v-fclass rv64uf-v-fclass.S + rv64uf-v-fcmp rv64uf-v-fcmp.S + rv64uf-v-fcvt rv64uf-v-fcvt.S + rv64uf-v-fcvt_w rv64uf-v-fcvt_w.S + rv64uf-v-fdiv rv64uf-v-fdiv.S + rv64uf-v-fmadd rv64uf-v-fmadd.S + rv64uf-v-fmin rv64uf-v-fmin.S + rv64uf-v-ldst rv64uf-v-ldst.S + rv64uf-v-move rv64uf-v-move.S + rv64uf-v-recoding rv64uf-v-recoding.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64ui-p.diaglist b/piton/verif/diag/riscv/rv64/rv64ui-p.diaglist new file mode 100644 index 000000000..00a6ab994 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64ui-p.diaglist @@ -0,0 +1,57 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64ui-p-add rv64ui-p-add.S + rv64ui-p-addi rv64ui-p-addi.S + rv64ui-p-addiw rv64ui-p-addiw.S + rv64ui-p-addw rv64ui-p-addw.S + rv64ui-p-and rv64ui-p-and.S + rv64ui-p-andi rv64ui-p-andi.S + rv64ui-p-auipc rv64ui-p-auipc.S + rv64ui-p-beq rv64ui-p-beq.S + rv64ui-p-bge rv64ui-p-bge.S + rv64ui-p-bgeu rv64ui-p-bgeu.S + rv64ui-p-blt rv64ui-p-blt.S + rv64ui-p-bltu rv64ui-p-bltu.S + rv64ui-p-bne rv64ui-p-bne.S + rv64ui-p-fence_i rv64ui-p-fence_i.S + rv64ui-p-jal rv64ui-p-jal.S + rv64ui-p-jalr rv64ui-p-jalr.S + rv64ui-p-lb rv64ui-p-lb.S + rv64ui-p-lbu rv64ui-p-lbu.S + rv64ui-p-ld rv64ui-p-ld.S + rv64ui-p-lh rv64ui-p-lh.S + rv64ui-p-lhu rv64ui-p-lhu.S + rv64ui-p-lui rv64ui-p-lui.S + rv64ui-p-lw rv64ui-p-lw.S + rv64ui-p-lwu rv64ui-p-lwu.S + rv64ui-p-or rv64ui-p-or.S + rv64ui-p-ori rv64ui-p-ori.S + rv64ui-p-sb rv64ui-p-sb.S + rv64ui-p-sd rv64ui-p-sd.S + rv64ui-p-sh rv64ui-p-sh.S + // rv64ui-p-simple rv64ui-p-simple.S + rv64ui-p-sll rv64ui-p-sll.S + rv64ui-p-slli rv64ui-p-slli.S + rv64ui-p-slliw rv64ui-p-slliw.S + rv64ui-p-sllw rv64ui-p-sllw.S + rv64ui-p-slt rv64ui-p-slt.S + rv64ui-p-slti rv64ui-p-slti.S + rv64ui-p-sltiu rv64ui-p-sltiu.S + rv64ui-p-sltu rv64ui-p-sltu.S + rv64ui-p-sra rv64ui-p-sra.S + rv64ui-p-srai rv64ui-p-srai.S + rv64ui-p-sraiw rv64ui-p-sraiw.S + rv64ui-p-sraw rv64ui-p-sraw.S + rv64ui-p-srl rv64ui-p-srl.S + rv64ui-p-srli rv64ui-p-srli.S + rv64ui-p-srliw rv64ui-p-srliw.S + rv64ui-p-srlw rv64ui-p-srlw.S + rv64ui-p-sub rv64ui-p-sub.S + rv64ui-p-subw rv64ui-p-subw.S + rv64ui-p-sw rv64ui-p-sw.S + rv64ui-p-xor rv64ui-p-xor.S + rv64ui-p-xori rv64ui-p-xori.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64ui-v.diaglist b/piton/verif/diag/riscv/rv64/rv64ui-v.diaglist new file mode 100644 index 000000000..ac0181e4a --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64ui-v.diaglist @@ -0,0 +1,57 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64ui-v-add rv64ui-v-add.S + rv64ui-v-addi rv64ui-v-addi.S + rv64ui-v-addiw rv64ui-v-addiw.S + rv64ui-v-addw rv64ui-v-addw.S + rv64ui-v-and rv64ui-v-and.S + rv64ui-v-andi rv64ui-v-andi.S + rv64ui-v-auipc rv64ui-v-auipc.S + rv64ui-v-beq rv64ui-v-beq.S + rv64ui-v-bge rv64ui-v-bge.S + rv64ui-v-bgeu rv64ui-v-bgeu.S + rv64ui-v-blt rv64ui-v-blt.S + rv64ui-v-bltu rv64ui-v-bltu.S + rv64ui-v-bne rv64ui-v-bne.S + rv64ui-v-fence_i rv64ui-v-fence_i.S + rv64ui-v-jal rv64ui-v-jal.S + rv64ui-v-jalr rv64ui-v-jalr.S + rv64ui-v-lb rv64ui-v-lb.S + rv64ui-v-lbu rv64ui-v-lbu.S + rv64ui-v-ld rv64ui-v-ld.S + rv64ui-v-lh rv64ui-v-lh.S + rv64ui-v-lhu rv64ui-v-lhu.S + rv64ui-v-lui rv64ui-v-lui.S + rv64ui-v-lw rv64ui-v-lw.S + rv64ui-v-lwu rv64ui-v-lwu.S + rv64ui-v-or rv64ui-v-or.S + rv64ui-v-ori rv64ui-v-ori.S + rv64ui-v-sb rv64ui-v-sb.S + rv64ui-v-sd rv64ui-v-sd.S + rv64ui-v-sh rv64ui-v-sh.S + // rv64ui-v-simple rv64ui-v-simple.S + rv64ui-v-sll rv64ui-v-sll.S + rv64ui-v-slli rv64ui-v-slli.S + rv64ui-v-slliw rv64ui-v-slliw.S + rv64ui-v-sllw rv64ui-v-sllw.S + rv64ui-v-slt rv64ui-v-slt.S + rv64ui-v-slti rv64ui-v-slti.S + rv64ui-v-sltiu rv64ui-v-sltiu.S + rv64ui-v-sltu rv64ui-v-sltu.S + rv64ui-v-sra rv64ui-v-sra.S + rv64ui-v-srai rv64ui-v-srai.S + rv64ui-v-sraiw rv64ui-v-sraiw.S + rv64ui-v-sraw rv64ui-v-sraw.S + rv64ui-v-srl rv64ui-v-srl.S + rv64ui-v-srli rv64ui-v-srli.S + rv64ui-v-srliw rv64ui-v-srliw.S + rv64ui-v-srlw rv64ui-v-srlw.S + rv64ui-v-sub rv64ui-v-sub.S + rv64ui-v-subw rv64ui-v-subw.S + rv64ui-v-sw rv64ui-v-sw.S + rv64ui-v-xor rv64ui-v-xor.S + rv64ui-v-xori rv64ui-v-xori.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64um-p.diaglist b/piton/verif/diag/riscv/rv64/rv64um-p.diaglist new file mode 100644 index 000000000..002bee74b --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64um-p.diaglist @@ -0,0 +1,19 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64um-p-div rv64um-p-div.S + rv64um-p-divu rv64um-p-divu.S + rv64um-p-divuw rv64um-p-divuw.S + rv64um-p-divw rv64um-p-divw.S + rv64um-p-mul rv64um-p-mul.S + rv64um-p-mulh rv64um-p-mulh.S + rv64um-p-mulhsu rv64um-p-mulhsu.S + rv64um-p-mulhu rv64um-p-mulhu.S + rv64um-p-mulw rv64um-p-mulw.S + rv64um-p-rem rv64um-p-rem.S + rv64um-p-remu rv64um-p-remu.S + rv64um-p-remuw rv64um-p-remuw.S + rv64um-p-remw rv64um-p-remw.S + + diff --git a/piton/verif/diag/riscv/rv64/rv64um-v.diaglist b/piton/verif/diag/riscv/rv64/rv64um-v.diaglist new file mode 100644 index 000000000..11725ecf8 --- /dev/null +++ b/piton/verif/diag/riscv/rv64/rv64um-v.diaglist @@ -0,0 +1,19 @@ + +// note: these asm tests assume that the RISCV tests have been precompiled with the +// correct environment + + rv64um-v-div rv64um-v-div.S + rv64um-v-divu rv64um-v-divu.S + rv64um-v-divuw rv64um-v-divuw.S + rv64um-v-divw rv64um-v-divw.S + rv64um-v-mul rv64um-v-mul.S + rv64um-v-mulh rv64um-v-mulh.S + rv64um-v-mulhsu rv64um-v-mulhsu.S + rv64um-v-mulhu rv64um-v-mulhu.S + rv64um-v-mulw rv64um-v-mulw.S + rv64um-v-rem rv64um-v-rem.S + rv64um-v-remu rv64um-v-remu.S + rv64um-v-remuw rv64um-v-remuw.S + rv64um-v-remw rv64um-v-remw.S + +