diff --git a/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv b/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv index 41e36c51e..46a3a7dcf 100644 --- a/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_mshr.v.pyv @@ -163,24 +163,24 @@ integer i=0; always @ * begin - for(i = 0; i < `L15_NUM_THREADS; i = i+1) - begin + for(i = 0; i < `L15_NUM_THREADS; i = i+1) + begin tmp_vals[i] = 0; tmp_vals[i][`L15_MSHR_ID_IFILL] = ifill_val[i]; - tmp_vals[i][`L15_MSHR_ID_LD] = ld_val[i]; - tmp_vals[i][`L15_MSHR_ID_ST] = st_val[i]; + tmp_vals[i][`L15_MSHR_ID_LD] = ld_val[i]; + tmp_vals[i][`L15_MSHR_ID_ST] = st_val[i]; tmp_st_address[i] = st_address[i]; tmp_ld_address[i] = ld_address[i]; - tmp_st_way[i] = st_way[i]; - tmp_st_state[i] = st_state[i]; + tmp_st_way[i] = st_way[i]; + tmp_st_state[i] = st_state[i]; - mshr_pipe_vals_s1[(`L15_NUM_MSHRID_PER_THREAD*(i+1))-1 -: `L15_NUM_MSHRID_PER_THREAD] = tmp_vals[i]; - mshr_pipe_ld_address[(`L15_PADDR_WIDTH*(i+1))-1 -: `L15_PADDR_WIDTH] = tmp_ld_address[i]; - mshr_pipe_st_address[(`L15_PADDR_WIDTH*(i+1))-1 -: `L15_PADDR_WIDTH] = tmp_st_address[i]; - mshr_pipe_st_way_s1[(2*(i+1))-1 -: 2] = tmp_st_way[i]; - mshr_pipe_st_state_s1[(`L15_MESI_TRANS_STATE_WIDTH*(i+1))-1 -: `L15_MESI_TRANS_STATE_WIDTH] = tmp_st_state[i]; - end + mshr_pipe_vals_s1[(`L15_NUM_MSHRID_PER_THREAD*(i+1))-1 -: `L15_NUM_MSHRID_PER_THREAD] = tmp_vals[i]; + mshr_pipe_ld_address[(`L15_PADDR_WIDTH*(i+1))-1 -: `L15_PADDR_WIDTH] = tmp_ld_address[i]; + mshr_pipe_st_address[(`L15_PADDR_WIDTH*(i+1))-1 -: `L15_PADDR_WIDTH] = tmp_st_address[i]; + mshr_pipe_st_way_s1[(2*(i+1))-1 -: 2] = tmp_st_way[i]; + mshr_pipe_st_state_s1[(`L15_MESI_TRANS_STATE_WIDTH*(i+1))-1 -: `L15_MESI_TRANS_STATE_WIDTH] = tmp_st_state[i]; + end // S1 read @@ -361,11 +361,11 @@ always @ (posedge clk) begin if (!rst_n) begin - for(i = 0; i < `L15_NUM_THREADS; i = i+1) - begin - st_homeid[i] <= '0; - ld_homeid[i] <= '0; - end + for(i = 0; i < `L15_NUM_THREADS; i = i+1) + begin + st_homeid[i] <= {PACKET_HOME_ID_WIDTH{1'b0}}; + ld_homeid[i] <= {PACKET_HOME_ID_WIDTH{1'b0}}; + end end else begin diff --git a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv index efe7fca35..8f5449f07 100644 --- a/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv +++ b/piton/design/chip/tile/l15/rtl/l15_pipeline.v.pyv @@ -404,27 +404,15 @@ begin // predecode_mshr_read_address_s1 = mshr_pipe_address_s1; predecode_mshr_read_homeid_s1 = mshr_pipe_readres_homeid_s1; - // mshr_val_array - //mshr_val_array[0] = mshr_pipe_vals_s1[`L15_NUM_MSHRID_PER_THREAD*1 - 1 -: `L15_NUM_MSHRID_PER_THREAD]; - //mshr_st_state_array[0] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*1 - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; - //mshr_st_address_array[0] = mshr_pipe_st_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; - //mshr_ld_address_array[0] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*1 - 1 -: `L15_PADDR_WIDTH]; - //mshr_st_way_array[0] = mshr_pipe_st_way_s1[2*1 - 1 -: 2]; - // - //mshr_val_array[1] = mshr_pipe_vals_s1[`L15_NUM_MSHRID_PER_THREAD*2 - 1 -: `L15_NUM_MSHRID_PER_THREAD]; - //mshr_st_state_array[1] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*2 - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; - //mshr_st_address_array[1] = mshr_pipe_st_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; - //mshr_ld_address_array[1] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*2 - 1 -: `L15_PADDR_WIDTH]; - //mshr_st_way_array[1] = mshr_pipe_st_way_s1[2*2 - 1 -: 2]; - - for(i = 0; i < `L15_NUM_THREADS; i = i+1) - begin - mshr_val_array[i] = mshr_pipe_vals_s1[`L15_NUM_MSHRID_PER_THREAD*(i+1) - 1 -: `L15_NUM_MSHRID_PER_THREAD]; - mshr_st_state_array[i] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*(i+1) - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; - mshr_st_address_array[i] = mshr_pipe_st_address[`L15_PADDR_WIDTH*(i+1) - 1 -: `L15_PADDR_WIDTH]; - mshr_ld_address_array[i] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*(i+1) - 1 -: `L15_PADDR_WIDTH]; - mshr_st_way_array[i] = mshr_pipe_st_way_s1[`L15_WAY_WIDTH*(i+1) - 1 -: `L15_WAY_WIDTH]; - end + // mshr_val_array + for(i = 0; i < `L15_NUM_THREADS; i = i+1) + begin + mshr_val_array[i] = mshr_pipe_vals_s1[`L15_NUM_MSHRID_PER_THREAD*(i+1) - 1 -: `L15_NUM_MSHRID_PER_THREAD]; + mshr_st_state_array[i] = mshr_pipe_st_state_s1[`L15_MESI_TRANS_STATE_WIDTH*(i+1) - 1 -: `L15_MESI_TRANS_STATE_WIDTH]; + mshr_st_address_array[i] = mshr_pipe_st_address[`L15_PADDR_WIDTH*(i+1) - 1 -: `L15_PADDR_WIDTH]; + mshr_ld_address_array[i] = mshr_pipe_ld_address[`L15_PADDR_WIDTH*(i+1) - 1 -: `L15_PADDR_WIDTH]; + mshr_st_way_array[i] = mshr_pipe_st_way_s1[`L15_WAY_WIDTH*(i+1) - 1 -: `L15_WAY_WIDTH]; + end end @@ -450,10 +438,6 @@ reg predecode_tagcheck_matched_trd_ld_s1 [`L15_THREAD_ARRAY_MASK]; // each eleme reg predecode_tagcheck_matched_trd_st_s1 [`L15_THREAD_ARRAY_MASK]; reg predecode_tagcheck_matched_lds_s1; reg predecode_tagcheck_matched_sts_s1; -//reg predecode_tagcheck_matched_t0ld_s1; -//reg predecode_tagcheck_matched_t0st_s1; -//reg predecode_tagcheck_matched_t1ld_s1; -//reg predecode_tagcheck_matched_t1st_s1; reg predecode_int_vec_dis_s1; reg predecode_tagcheck_matched_s1; @@ -850,28 +834,27 @@ begin // TAG CHECKING predecode_partial_tag_s1[19:4] = pcxdecoder_l15_address[19:4]; // compare partial tag to save energy & timing - predecode_tagcheck_matched_lds_s1 = 0; - predecode_tagcheck_matched_sts_s1 = 0; + predecode_tagcheck_matched_lds_s1 = 0; + predecode_tagcheck_matched_sts_s1 = 0; - for(i = 0; i < `L15_NUM_THREADS; i = i+1) - begin - predecode_tagcheck_matched_trd_ld_s1[i] = mshr_val_array[i][`L15_MSHR_ID_LD] + for(i = 0; i < `L15_NUM_THREADS; i = i+1) + begin + predecode_tagcheck_matched_trd_ld_s1[i] = mshr_val_array[i][`L15_MSHR_ID_LD] && (predecode_partial_tag_s1[19:4] == mshr_ld_address_array[i][19:4]); - predecode_tagcheck_matched_trd_st_s1[i] = mshr_val_array[i][`L15_MSHR_ID_ST] - && (pcxdecoder_l15_address[39:4] == mshr_st_address_array[i][39:4]); + predecode_tagcheck_matched_trd_st_s1[i] = mshr_val_array[i][`L15_MSHR_ID_ST] + && (pcxdecoder_l15_address[39:4] == mshr_st_address_array[i][39:4]); - predecode_tagcheck_matched_lds_s1 = predecode_tagcheck_matched_trd_ld_s1[i] | predecode_tagcheck_matched_lds_s1; - predecode_tagcheck_matched_sts_s1 = predecode_tagcheck_matched_trd_st_s1[i] | predecode_tagcheck_matched_sts_s1; + predecode_tagcheck_matched_lds_s1 = predecode_tagcheck_matched_trd_ld_s1[i] | predecode_tagcheck_matched_lds_s1; + predecode_tagcheck_matched_sts_s1 = predecode_tagcheck_matched_trd_st_s1[i] | predecode_tagcheck_matched_sts_s1; - if(predecode_tagcheck_matched_trd_st_s1[i] == 1) - predecode_hit_stbuf_threadid_s1 = i; + if(predecode_tagcheck_matched_trd_st_s1[i] == 1) + predecode_hit_stbuf_threadid_s1 = i; - end + end - predecode_tagcheck_matched_s1 = predecode_tagcheck_matched_lds_s1 | predecode_tagcheck_matched_sts_s1; + predecode_tagcheck_matched_s1 = predecode_tagcheck_matched_lds_s1 | predecode_tagcheck_matched_sts_s1; // misc predecode_hit_stbuf_s1 = predecode_tagcheck_matched_sts_s1; - //predecode_hit_stbuf_threadid_s1 = predecode_tagcheck_matched_t1st_s1 ? 1'b1 : 1'b0; // note: only work with 2 threads for now; need to change the algo of mshr if need to increase the num of threads end @@ -3326,31 +3309,35 @@ reg [`L15_UNPARAM_1_0] stbuf_way_s3; // wmt todo: move calculation to s2 always @ * begin - stbuf_compare_match_val_s3 = 0; - stbuf_compare_lru_match_val_s3 = 0; - for(i = 0; i < `L15_NUM_THREADS; i = i+1) - begin - `ifdef PITON_ASIC_RTL - stbuf_compare_address_match_s3[i] = mshr_st_address_array[i][10:4] == cache_index_s3; - `else - stbuf_compare_address_match_s3[i] = mshr_st_address_array[i][39:4] == address_s3[39:4]; - `endif + stbuf_compare_match_val_s3 = 0; + stbuf_compare_lru_match_val_s3 = 0; + for(i = 0; i < `L15_NUM_THREADS; i = i+1) + begin + `ifdef PITON_ASIC_RTL + stbuf_compare_address_match_s3[i] = mshr_st_address_array[i][10:4] == cache_index_s3; + `else + stbuf_compare_address_match_s3[i] = mshr_st_address_array[i][39:4] == address_s3[39:4]; + `endif - stbuf_compare_match_s3[i] = mshr_val_array[i][`L15_MSHR_ID_ST] - && (mshr_st_state_array[i] == `L15_MESI_TRANSITION_STATE_SM) - && (stbuf_compare_address_match_s3[i] == 1'b1); + stbuf_compare_match_s3[i] = mshr_val_array[i][`L15_MSHR_ID_ST] + && (mshr_st_state_array[i] == `L15_MESI_TRANSITION_STATE_SM) + && (stbuf_compare_address_match_s3[i] == 1'b1); - stbuf_compare_lru_match_s3[i] = stbuf_compare_match_s3[i] && (mshr_st_way_array[i] == lru_way_s3); + stbuf_compare_lru_match_s3[i] = stbuf_compare_match_s3[i] && (mshr_st_way_array[i] == lru_way_s3); - if (stbuf_compare_match_s3[i] == 1) + if (stbuf_compare_match_s3[i] == 1) + begin stbuf_compare_threadid_s3 = i; + end - if (stbuf_compare_lru_match_s3[i] == 1) + if (stbuf_compare_lru_match_s3[i] == 1) + begin stbuf_compare_lru_threadid_s3 = i; + end - stbuf_compare_match_val_s3 = stbuf_compare_match_s3[i] | stbuf_compare_match_val_s3; - stbuf_compare_lru_match_val_s3 = stbuf_compare_lru_match_s3[i] | stbuf_compare_lru_match_val_s3; - end + stbuf_compare_match_val_s3 = stbuf_compare_match_s3[i] | stbuf_compare_match_val_s3; + stbuf_compare_lru_match_val_s3 = stbuf_compare_lru_match_s3[i] | stbuf_compare_lru_match_val_s3; + end stbuf_way_s3 = mshr_st_way_array[stbuf_compare_threadid_s3]; // stbuf_way_wmt_data_s3 = wmt_data_s3[stbuf_way_s3]; diff --git a/piton/design/include/l15.h.pyv b/piton/design/include/l15.h.pyv index 2b6b6f054..c99153606 100644 --- a/piton/design/include/l15.h.pyv +++ b/piton/design/include/l15.h.pyv @@ -86,8 +86,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. print("`define L15_CACHELINE_WIDTH %d" % (L15_LINE_SIZE*8)) - print("`define L15_NUM_THREADS %d" % L15_NUM_THREADS) - print("`define L15_THREADID_WIDTH %d" % int(math.log(L15_NUM_THREADS, 2))) + print("`define L15_NUM_THREADS %d" % CONFIG_L15_NUM_THREADS) + print("`define L15_THREADID_WIDTH %d" % int(math.log(CONFIG_L15_NUM_THREADS, 2))) %> `define L15_MESI_STATE_WIDTH 2 diff --git a/piton/tools/bin/pyhplib.py b/piton/tools/bin/pyhplib.py index 86db0d2d8..aa4172f0a 100644 --- a/piton/tools/bin/pyhplib.py +++ b/piton/tools/bin/pyhplib.py @@ -72,6 +72,7 @@ # cache configurations CONFIG_L15_SIZE = int(os.environ.get('CONFIG_L15_SIZE', '8192')) CONFIG_L15_ASSOCIATIVITY = int(os.environ.get('CONFIG_L15_ASSOCIATIVITY', '4')) +CONFIG_L15_NUM_THREADS = int(os.environ.get('CONFIG_L15_NUM_THREADS', '2')) CONFIG_L1D_SIZE = int(os.environ.get('CONFIG_L1D_SIZE', '8192')) CONFIG_L1D_ASSOCIATIVITY = int(os.environ.get('CONFIG_L1D_ASSOCIATIVITY', '4')) CONFIG_L1I_SIZE = int(os.environ.get('CONFIG_L1I_SIZE', '16384')) @@ -87,8 +88,6 @@ L15_LINE_SIZE = 16 L2_LINE_SIZE = 64 -L15_NUM_THREADS = int(os.environ.get('CONFIG_L15_NUM_THREADS', '2')) - ######################################################### # BRAM configurations ######################################################### diff --git a/piton/tools/src/sims/manycore.config b/piton/tools/src/sims/manycore.config index 6aab7e48c..2f6fc0c81 100644 --- a/piton/tools/src/sims/manycore.config +++ b/piton/tools/src/sims/manycore.config @@ -112,7 +112,7 @@ // No scan chains -config_rtl=NO_SCAN - + -config_l1i_size=16384 // default -config_l1i_associativity=4 // default diff --git a/piton/tools/verilator/my_top.cpp b/piton/tools/verilator/my_top.cpp index e505f1a20..48b71d085 100644 --- a/piton/tools/verilator/my_top.cpp +++ b/piton/tools/verilator/my_top.cpp @@ -38,7 +38,7 @@ Vcmp_top* top; VerilatedVcdC* tfp; #endif -extern "C" void init_jbus_model_call(const char *str, int oram); +extern "C" void init_jbus_model_call(char *str, int oram); // This is a 64-bit integer to reduce wrap over issues and // // allow modulus. You can also use a double, if you wish.