Revert "drm/amd/display: Only use ODM2:1 policy for high pixel rate displays"

hongkzha-amd · hongkzha-amd · commit 76c0ce831a04 · 2022-11-29T10:37:42.000+08:00
This reverts commit 8df9afa. Reviwed-by: Feifei Xu <feifxu@amd.com> Signed-off-by: Hongkun Zhang <hongkun.zhang@amd.com>
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1915,7 +1915,6 @@ int dcn32_populate_dml_pipes_from_context(
 				context->stream_status[0].plane_count <= 1 &&
 				!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&
 				is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
-				pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&
 				dc->debug.enable_single_display_2to1_odm_policy) {
 			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -37,7 +37,6 @@
 #define DCN3_2_MBLK_WIDTH 128
 #define DCN3_2_MBLK_HEIGHT_4BPE 128
 #define DCN3_2_MBLK_HEIGHT_8BPE 64
-#define DCN3_2_VMIN_DISPCLK_HZ 717000000
 
 #define TO_DCN32_RES_POOL(pool)\
 	container_of(pool, struct dcn32_resource_pool, base)

Original file line number	Diff line number	Diff line change
`@@ -1915,7 +1915,6 @@ int dcn32_populate_dml_pipes_from_context(`
`1915`	`1915`	`context->stream_status[0].plane_count <= 1 &&`
`1916`	`1916`	`!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&`
`1917`	`1917`	`is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&`
`1918`		`- pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&`
`1919`	`1918`	`dc->debug.enable_single_display_2to1_odm_policy) {`
`1920`	`1919`	`pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;`
`1921`	`1920`	`}`