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  1. simple_spi simple_spi Public

    Forked from euvm/simple_spi

    Verilog

  2. RISCV-MYTH-WORKSHOP/RISC-V-CPU-Core-using-TL-Verilog RISCV-MYTH-WORKSHOP/RISC-V-CPU-Core-using-TL-Verilog Public

    risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom

    Verilog 12 8