(Under Verification) [TDM] adjust tdm format and fix some driver issues #6968
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Switch to using Left Justified WS/FS/LRCLK
Because 8CH is used there will be 2 DMA buffers combined to produce final requested bytes So half the size of each buffer should be requested. Also, FIFO is reset upon each transfer completion to avoid stale bytes in the FIFO that may be copied into DMA buffer
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See #6969 for testing the waveform Example output |
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TODO:
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@lhenry-realtek The entire schedule is up to the end of October. Therefore, BSP development must be completed by October 10th. |
WCLK is kept active for entire TDM operation, it will be stopped only when I2S_PAUSE is called
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@lhenry-realtek How about validation tdm data ? Is DMA operation still abnormal? |
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if .data_format = SP_DF_LEFT , ais25ba should be configed as like this.
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allen-kim-sec
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Sep 26, 2025
allen-kim-sec
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allen-kim-sec
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it's okay only for BSP.
if .data_format = SP_DF_LEFT , ais25ba should be configed as like this.
TDM_CTRL_REG (0x2e) as 0x02
. delayed : 0
. data_valid : 0 ( Sampling timing is at the rise edge of BCLK because generate signal start at the falling edge )
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These commits aim to fix some fifo and waveform issues in the TDM driver when streaming data.
A separate PR for testing will be created, there are some important issues to address