Carry Select Adder

Verilog code:
module full_adder(
    input a,
    input b,
    input cin,
    output sum,
    output cout
);
assign sum=a^b^cin;
assign cout=(a&b)|(a&cin)|(b&cin);
endmodule
module csla(
    input [3:0] A,
    input [3:0] B,
    output [3:0] S,
    output cout);
wire [3:0] carry1, carry2;
full_adder FA0(A[0], B[0], 0, S[0], carry1[0]);
full_adder FA1(A[1], B[1], 0, S[1], carry1[1]);
full_adder FA2(A[2], B[2], 0, S[2], carry1[2]);
full_adder FA3(A[3], B[3], 0, S[3], carry1[3]);
full_adder FA4(S[0], B[0], carry1[0], S[0], carry2[0]);
full_adder FA5(S[1], B[1], carry1[1], S[1], carry2[1]);
full_adder FA6(S[2], B[2], carry1[2], S[2], carry2[2]);
full_adder FA7(S[3], B[3], carry1[3], S[3], carry2[3]);
assign cout = carry2[3];
endmodule
Testbench code:
module carry_select_tb();
    // Signals
    reg [3:0] A, B;
    wire [3:0] S;
    wire cout;
    // Instantiate the unit under test (UUT
    csla DUT (
        .A(A),
        .B(B),
        .S(S),
        .cout(cout)
    );
    // Stimulus
    initial begin
        // Initialize input
        A = 4'b0000;
        B = 4'b0000;      
        // Apply stimulus
        #10 A = 4'b1010; // 10
        #10 B = 4'b0101; // 5
        #10 A = 4'b1111; // 15
        #10 B = 4'b0001; // 1
        
        #10 A = 4'b0110; // 6
        #10 B = 4'b1101; // 13
         #10 $finish;
         end
    // Display results
    always @(posedge cout) begin
        $display("Result: %b, Carry out: %b", S, cout);
    end
endmodule