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mir-gen-aarch64.c
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mir-gen-aarch64.c
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/* This file is a part of MIR project.
Copyright (C) 2020-2024 Vladimir Makarov <[email protected]>.
*/
static void fancy_abort (int code) {
if (!code) abort ();
}
#undef gen_assert
#define gen_assert(c) fancy_abort (c)
#include <limits.h>
#include "mir-aarch64.h"
static const MIR_reg_t FP_HARD_REG = R29_HARD_REG;
static const MIR_reg_t LINK_HARD_REG = R30_HARD_REG;
static inline MIR_reg_t target_nth_loc (MIR_reg_t loc, MIR_type_t type MIR_UNUSED, int n) {
return loc + n;
}
static inline int target_call_used_hard_reg_p (MIR_reg_t hard_reg, MIR_type_t type) {
assert (hard_reg <= MAX_HARD_REG);
if (hard_reg <= SP_HARD_REG) return !(hard_reg >= R19_HARD_REG && hard_reg <= R28_HARD_REG);
return type == MIR_T_LD || !(hard_reg >= V8_HARD_REG && hard_reg <= V15_HARD_REG);
}
/* Stack layout (sp refers to the last reserved stack slot address)
from higher address to lower address memory:
| ... | prev func stack (start aligned to 16 bytes)
|---------------|
| gr save area | 64 bytes optional area for vararg func integer reg save area (absent for
APPLE)
|---------------|
| vr save area | 128 bytes optional area for vararg func fp reg save area (absent for APPLE)
|---------------|
| saved regs | callee saved regs used in the func (known only after RA), rounded 16 bytes
|---------------|
| slots assigned| can be absent for small functions (known only after RA), rounded 16 bytes
| to pseudos |
|---------------|
| previous | 16-bytes setup in prolog, used only for varag func or args passed on stack
| stack start | to move args and to setup va_start on machinize pass
|---------------|
| LR | sp before prologue and after saving LR = start sp
|---------------|
| old FP | frame pointer for previous func stack frame; new FP refers for here
| | it has lowest address as 12-bit offsets are only positive
|---------------|
| small aggr |
| save area | optional
|---------------|
| alloca areas | optional
|---------------|
| slots for | dynamically allocated/deallocated by caller
| passing args |
size of slots and saved regs is multiple of 16 bytes
*/
#if !defined(__APPLE__)
static const int int_reg_save_area_size = 8 * 8;
static const int reg_save_area_size = 8 * 8 + 8 * 16;
#endif
static const MIR_insn_code_t target_io_dup_op_insn_codes[] = {MIR_INSN_BOUND};
static MIR_insn_code_t get_ext_code (MIR_type_t type) {
switch (type) {
case MIR_T_I8: return MIR_EXT8;
case MIR_T_U8: return MIR_UEXT8;
case MIR_T_I16: return MIR_EXT16;
case MIR_T_U16: return MIR_UEXT16;
case MIR_T_I32: return MIR_EXT32;
case MIR_T_U32: return MIR_UEXT32;
default: return MIR_INVALID_INSN;
}
}
static MIR_reg_t get_arg_reg (MIR_type_t arg_type, size_t *int_arg_num, size_t *fp_arg_num,
MIR_insn_code_t *mov_code) {
MIR_reg_t arg_reg;
if (arg_type == MIR_T_F || arg_type == MIR_T_D || arg_type == MIR_T_LD) {
switch (*fp_arg_num) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7: arg_reg = V0_HARD_REG + *fp_arg_num; break;
default: arg_reg = MIR_NON_VAR; break;
}
(*fp_arg_num)++;
*mov_code = arg_type == MIR_T_F ? MIR_FMOV : arg_type == MIR_T_D ? MIR_DMOV : MIR_LDMOV;
} else { /* including BLK, RBLK: */
switch (*int_arg_num) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7: arg_reg = R0_HARD_REG + *int_arg_num; break;
default: arg_reg = MIR_NON_VAR; break;
}
(*int_arg_num)++;
*mov_code = MIR_MOV;
}
return arg_reg;
}
static void mir_blk_mov (uint64_t *to, uint64_t *from, uint64_t nwords) {
for (; nwords > 0; nwords--) *to++ = *from++;
}
static MIR_insn_t gen_mov (gen_ctx_t gen_ctx, MIR_insn_t anchor, MIR_insn_code_t code,
MIR_op_t dst_op, MIR_op_t src_op) {
MIR_insn_t insn = MIR_new_insn (gen_ctx->ctx, code, dst_op, src_op);
gen_add_insn_before (gen_ctx, anchor, insn);
return insn;
}
static MIR_reg_t target_get_stack_slot_base_reg (gen_ctx_t gen_ctx MIR_UNUSED) {
return FP_HARD_REG;
}
static int target_valid_mem_offset_p (gen_ctx_t gen_ctx, MIR_type_t type, MIR_disp_t offset);
static MIR_op_t new_mem_op (gen_ctx_t gen_ctx, MIR_insn_t anchor, MIR_type_t type, MIR_disp_t disp,
MIR_reg_t base) {
MIR_context_t ctx = gen_ctx->ctx;
if (target_valid_mem_offset_p (gen_ctx, type, disp))
return _MIR_new_var_mem_op (ctx, type, disp, base, MIR_NON_VAR, 1);
MIR_reg_t temp_reg = gen_new_temp_reg (gen_ctx, MIR_T_I64, curr_func_item->u.func);
MIR_op_t temp_reg_op = _MIR_new_var_op (ctx, temp_reg);
gen_mov (gen_ctx, anchor, MIR_MOV, temp_reg_op, MIR_new_int_op (ctx, disp));
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (ctx, MIR_ADD, temp_reg_op, temp_reg_op,
_MIR_new_var_op (ctx, base)));
return _MIR_new_var_mem_op (ctx, type, 0, temp_reg, MIR_NON_VAR, 1);
}
static MIR_op_t get_new_hard_reg_mem_op (gen_ctx_t gen_ctx, MIR_type_t type, MIR_disp_t disp,
MIR_reg_t base, MIR_insn_t *insn1, MIR_insn_t *insn2) {
MIR_context_t ctx = gen_ctx->ctx;
*insn1 = *insn2 = NULL;
if (target_valid_mem_offset_p (gen_ctx, type, disp))
return _MIR_new_var_mem_op (ctx, type, disp, base, MIR_NON_VAR, 1);
MIR_op_t temp_reg_op = _MIR_new_var_op (ctx, TEMP_INT_HARD_REG2);
*insn1 = MIR_new_insn (ctx, MIR_MOV, temp_reg_op, MIR_new_int_op (ctx, disp));
*insn2 = MIR_new_insn (ctx, MIR_ADD, temp_reg_op, temp_reg_op, _MIR_new_var_op (ctx, base));
return _MIR_new_var_mem_op (ctx, type, 0, TEMP_INT_HARD_REG2, MIR_NON_VAR, 1);
}
static MIR_op_t new_hard_reg_mem_op (gen_ctx_t gen_ctx, MIR_insn_t anchor, MIR_type_t type,
MIR_disp_t disp, MIR_reg_t base) {
MIR_insn_t insn1, insn2;
MIR_op_t op = get_new_hard_reg_mem_op (gen_ctx, type, disp, base, &insn1, &insn2);
if (insn1 != NULL) gen_add_insn_before (gen_ctx, anchor, insn1);
if (insn2 != NULL) gen_add_insn_before (gen_ctx, anchor, insn2);
return op;
}
static const char *BLK_MOV = "mir.blk_mov";
static const char *BLK_MOV_P = "mir.blk_mov.p";
static void gen_blk_mov (gen_ctx_t gen_ctx, MIR_insn_t anchor, size_t to_disp,
MIR_reg_t to_base_hard_reg, size_t from_disp, MIR_reg_t from_base_reg,
size_t qwords, int save_regs) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func = curr_func_item->u.func;
MIR_item_t proto_item, func_import_item;
MIR_insn_t new_insn;
MIR_op_t ops[5], freg_op, treg_op, treg_op2, treg_op3;
treg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
if (qwords <= 16) {
for (; qwords > 0; qwords--, to_disp += 8, from_disp += 8) {
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op,
new_mem_op (gen_ctx, anchor, MIR_T_I64, from_disp, from_base_reg));
gen_mov (gen_ctx, anchor, MIR_MOV,
new_hard_reg_mem_op (gen_ctx, anchor, MIR_T_I64, to_disp, to_base_hard_reg),
treg_op);
}
return;
}
treg_op2 = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
treg_op3 = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
/* Save arg regs: */
if (save_regs > 0)
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op, _MIR_new_var_op (ctx, R0_HARD_REG));
if (save_regs > 1)
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op2, _MIR_new_var_op (ctx, R1_HARD_REG));
if (save_regs > 2)
gen_mov (gen_ctx, anchor, MIR_MOV, treg_op3, _MIR_new_var_op (ctx, R2_HARD_REG));
/* call blk move: */
proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, BLK_MOV_P, 0, NULL, 3, MIR_T_I64,
"to", MIR_T_I64, "from", MIR_T_I64, "nwords");
func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, BLK_MOV, mir_blk_mov);
freg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, anchor, new_insn);
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (gen_ctx->ctx, MIR_ADD, _MIR_new_var_op (ctx, R0_HARD_REG),
_MIR_new_var_op (ctx, to_base_hard_reg),
MIR_new_int_op (ctx, to_disp)));
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (gen_ctx->ctx, MIR_ADD, _MIR_new_var_op (ctx, R1_HARD_REG),
_MIR_new_var_op (ctx, from_base_reg),
MIR_new_int_op (ctx, from_disp)));
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, R2_HARD_REG),
MIR_new_int_op (ctx, qwords));
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = _MIR_new_var_op (ctx, R0_HARD_REG);
ops[3] = _MIR_new_var_op (ctx, R1_HARD_REG);
ops[4] = _MIR_new_var_op (ctx, R2_HARD_REG);
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 5, ops);
gen_add_insn_before (gen_ctx, anchor, new_insn);
/* Restore arg regs: */
if (save_regs > 0)
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, R0_HARD_REG), treg_op);
if (save_regs > 1)
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, R1_HARD_REG), treg_op2);
if (save_regs > 2)
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, R2_HARD_REG), treg_op3);
}
static void machinize_call (gen_ctx_t gen_ctx, MIR_insn_t call_insn) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func = curr_func_item->u.func;
MIR_proto_t proto = call_insn->ops[0].u.ref->u.proto;
size_t nargs, nops = MIR_insn_nops (ctx, call_insn), start = proto->nres + 2;
size_t int_arg_num = 0, fp_arg_num = 0, mem_size = 0, blk_offset = 0, qwords;
MIR_type_t type, mem_type;
MIR_op_mode_t mode;
MIR_var_t *arg_vars = NULL;
MIR_reg_t arg_reg;
MIR_op_t arg_op, temp_op, arg_reg_op, ret_reg_op, mem_op;
MIR_insn_code_t new_insn_code, ext_code;
MIR_insn_t new_insn, prev_insn, next_insn, ext_insn, insn1, insn2;
MIR_insn_t prev_call_insn = DLIST_PREV (MIR_insn_t, call_insn);
MIR_insn_t curr_prev_call_insn = prev_call_insn;
uint32_t n_iregs, n_vregs;
if (call_insn->code == MIR_INLINE) call_insn->code = MIR_CALL;
if (proto->args == NULL) {
nargs = 0;
} else {
gen_assert (nops >= VARR_LENGTH (MIR_var_t, proto->args)
&& (proto->vararg_p || nops - start == VARR_LENGTH (MIR_var_t, proto->args)));
nargs = VARR_LENGTH (MIR_var_t, proto->args);
arg_vars = VARR_ADDR (MIR_var_t, proto->args);
}
if (call_insn->ops[1].mode != MIR_OP_VAR) {
// ??? to optimize (can be immediate operand for func call)
temp_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, call_insn->ops[1]);
call_insn->ops[1] = temp_op;
gen_add_insn_before (gen_ctx, call_insn, new_insn);
}
for (size_t i = start; i < nops; i++) { /* calculate offset for blk params */
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else if (call_insn->ops[i].mode == MIR_OP_VAR_MEM) {
type = call_insn->ops[i].u.var_mem.type;
gen_assert (MIR_all_blk_type_p (type));
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
gen_assert (mode == MIR_OP_INT || mode == MIR_OP_UINT || mode == MIR_OP_FLOAT
|| mode == MIR_OP_DOUBLE || mode == MIR_OP_LDOUBLE);
if (mode == MIR_OP_FLOAT)
(*MIR_get_error_func (ctx)) (MIR_call_op_error,
"passing float variadic arg (should be passed as double)");
if (mode == MIR_OP_LDOUBLE && __SIZEOF_LONG_DOUBLE__ == 8) mode = MIR_OP_DOUBLE;
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
gen_assert (!MIR_all_blk_type_p (type) || call_insn->ops[i].mode == MIR_OP_VAR_MEM);
if (type == MIR_T_RBLK && i == start) continue; /* hidden arg */
#if defined(__APPLE__) /* all varargs are passed on stack */
if (i - start == nargs) int_arg_num = fp_arg_num = 8;
#endif
if (MIR_blk_type_p (type) && (qwords = (call_insn->ops[i].u.var_mem.disp + 7) / 8) <= 2) {
if (int_arg_num + qwords > 8) blk_offset += qwords * 8;
int_arg_num += qwords;
} else if (get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code) == MIR_NON_VAR) {
if (type == MIR_T_LD && __SIZEOF_LONG_DOUBLE__ == 16 && blk_offset % 16 != 0)
blk_offset = (blk_offset + 15) / 16 * 16;
blk_offset += type == MIR_T_LD && __SIZEOF_LONG_DOUBLE__ == 16 ? 16 : 8;
}
}
blk_offset = (blk_offset + 15) / 16 * 16;
int_arg_num = fp_arg_num = 0;
for (size_t i = start; i < nops; i++) {
#if defined(__APPLE__) /* all varargs are passed on stack */
if (i - start == nargs) int_arg_num = fp_arg_num = 8;
#endif
arg_op = call_insn->ops[i];
gen_assert (arg_op.mode == MIR_OP_VAR
|| (arg_op.mode == MIR_OP_VAR_MEM && MIR_all_blk_type_p (arg_op.u.var_mem.type)));
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else if (call_insn->ops[i].mode == MIR_OP_VAR_MEM) {
type = call_insn->ops[i].u.var_mem.type;
gen_assert (MIR_all_blk_type_p (type));
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
if (mode == MIR_OP_LDOUBLE && __SIZEOF_LONG_DOUBLE__ == 8) mode = MIR_OP_DOUBLE;
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
ext_insn = NULL;
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) { /* extend arg if necessary */
temp_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
ext_insn = MIR_new_insn (ctx, ext_code, temp_op, arg_op);
call_insn->ops[i] = arg_op = temp_op;
}
gen_assert (!MIR_all_blk_type_p (type)
|| (arg_op.mode == MIR_OP_VAR_MEM && arg_op.u.var_mem.disp >= 0
&& arg_op.u.var_mem.index == MIR_NON_VAR));
if (type == MIR_T_RBLK && i == start) { /* hidden arg */
arg_reg_op = _MIR_new_var_op (ctx, R8_HARD_REG);
gen_mov (gen_ctx, call_insn, MIR_MOV, arg_reg_op,
_MIR_new_var_op (ctx, arg_op.u.var_mem.base));
call_insn->ops[i] = arg_reg_op;
continue;
} else if (MIR_blk_type_p (type)) {
qwords = (arg_op.u.var_mem.disp + 7) / 8;
if (qwords <= 2) {
arg_reg = R0_HARD_REG + int_arg_num;
if (int_arg_num + qwords <= 8) {
/* A trick to keep arg regs live: */
call_insn->ops[i] = _MIR_new_var_mem_op (ctx, MIR_T_UNDEF, 0, int_arg_num,
qwords < 2 ? MIR_NON_VAR : int_arg_num + 1, 1);
if (qwords == 0) continue;
new_insn = MIR_new_insn (ctx, MIR_MOV, _MIR_new_var_op (ctx, R0_HARD_REG + int_arg_num++),
_MIR_new_var_mem_op (ctx, MIR_T_I64, 0, arg_op.u.var_mem.base,
MIR_NON_VAR, 1));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
if (qwords == 2) {
new_insn
= MIR_new_insn (ctx, MIR_MOV, _MIR_new_var_op (ctx, R0_HARD_REG + int_arg_num++),
_MIR_new_var_mem_op (ctx, MIR_T_I64, 8, arg_op.u.var_mem.base,
MIR_NON_VAR, 1));
gen_add_insn_before (gen_ctx, call_insn, new_insn);
}
} else { /* pass on stack w/o address: */
gen_blk_mov (gen_ctx, call_insn, mem_size, SP_HARD_REG, 0, arg_op.u.var_mem.base, qwords,
int_arg_num);
call_insn->ops[i]
= _MIR_new_var_mem_op (ctx, MIR_T_UNDEF,
mem_size, /* we don't care about valid mem disp here */
SP_HARD_REG, MIR_NON_VAR, 1);
mem_size += qwords * 8;
blk_offset += qwords * 8;
int_arg_num += qwords;
}
continue;
}
gen_blk_mov (gen_ctx, call_insn, blk_offset, SP_HARD_REG, 0, arg_op.u.var_mem.base, qwords,
int_arg_num);
arg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
gen_assert (curr_prev_call_insn
!= NULL); /* call_insn should not be 1st after simplification */
new_insn = MIR_new_insn (gen_ctx->ctx, MIR_ADD, arg_op, _MIR_new_var_op (ctx, SP_HARD_REG),
MIR_new_int_op (ctx, blk_offset));
gen_add_insn_after (gen_ctx, curr_prev_call_insn, new_insn);
curr_prev_call_insn = DLIST_NEXT (MIR_insn_t, new_insn);
blk_offset += qwords * 8;
}
if ((arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code)) != MIR_NON_VAR) {
/* put arguments to argument hard regs */
if (ext_insn != NULL) gen_add_insn_before (gen_ctx, call_insn, ext_insn);
arg_reg_op = _MIR_new_var_op (ctx, arg_reg);
if (type != MIR_T_RBLK) {
new_insn = MIR_new_insn (ctx, new_insn_code, arg_reg_op, arg_op);
} else {
assert (arg_op.mode == MIR_OP_VAR_MEM);
new_insn
= MIR_new_insn (ctx, MIR_MOV, arg_reg_op, _MIR_new_var_op (ctx, arg_op.u.var_mem.base));
arg_reg_op
= _MIR_new_var_mem_op (ctx, MIR_T_RBLK,
arg_op.u.var_mem.disp, /* we don't care about valid disp here */
arg_reg, MIR_NON_VAR, 1);
}
gen_add_insn_before (gen_ctx, call_insn, new_insn);
call_insn->ops[i] = arg_reg_op;
} else { /* put arguments on the stack */
if (type == MIR_T_LD && __SIZEOF_LONG_DOUBLE__ == 16 && mem_size % 16 != 0)
mem_size = (mem_size + 15) / 16 * 16;
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code = (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: type == MIR_T_LD ? MIR_LDMOV
: MIR_MOV);
mem_op = get_new_hard_reg_mem_op (gen_ctx, mem_type, mem_size, SP_HARD_REG, &insn1, &insn2);
if (type != MIR_T_RBLK) {
new_insn = MIR_new_insn (ctx, new_insn_code, mem_op, arg_op);
} else {
assert (arg_op.mode == MIR_OP_VAR_MEM);
new_insn
= MIR_new_insn (ctx, new_insn_code, mem_op, _MIR_new_var_op (ctx, arg_op.u.var_mem.base));
}
gen_assert (curr_prev_call_insn
!= NULL); /* call_insn should not be 1st after simplification */
MIR_insert_insn_after (ctx, curr_func_item, curr_prev_call_insn, new_insn);
if (insn2 != NULL) MIR_insert_insn_after (ctx, curr_func_item, curr_prev_call_insn, insn2);
if (insn1 != NULL) MIR_insert_insn_after (ctx, curr_func_item, curr_prev_call_insn, insn1);
prev_insn = curr_prev_call_insn;
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (gen_ctx, prev_insn, next_insn, call_insn);
call_insn->ops[i] = mem_op;
mem_size += type == MIR_T_LD && __SIZEOF_LONG_DOUBLE__ == 16 ? 16 : 8;
if (ext_insn != NULL) gen_add_insn_after (gen_ctx, curr_prev_call_insn, ext_insn);
curr_prev_call_insn = new_insn;
}
}
blk_offset = (blk_offset + 15) / 16 * 16;
if (blk_offset != 0) mem_size = blk_offset;
n_iregs = n_vregs = 0;
for (size_t i = 0; i < proto->nres; i++) {
int float_p;
ret_reg_op = call_insn->ops[i + 2];
gen_assert (ret_reg_op.mode == MIR_OP_VAR);
type = proto->res_types[i];
float_p = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD;
if (float_p && n_vregs < 8) {
new_insn = MIR_new_insn (ctx,
type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: MIR_LDMOV,
ret_reg_op, _MIR_new_var_op (ctx, V0_HARD_REG + n_vregs));
n_vregs++;
} else if (!float_p && n_iregs < 8) {
new_insn
= MIR_new_insn (ctx, MIR_MOV, ret_reg_op, _MIR_new_var_op (ctx, R0_HARD_REG + n_iregs));
n_iregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"aarch64 can not handle this combination of return values");
}
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
call_insn->ops[i + 2] = new_insn->ops[1];
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) {
MIR_insert_insn_after (ctx, curr_func_item, new_insn,
MIR_new_insn (ctx, ext_code, ret_reg_op, ret_reg_op));
new_insn = DLIST_NEXT (MIR_insn_t, new_insn);
}
create_new_bb_insns (gen_ctx, call_insn, DLIST_NEXT (MIR_insn_t, new_insn), call_insn);
}
if (mem_size != 0) { /* allocate/deallocate stack for args passed on stack */
mem_size = (mem_size + 15) / 16 * 16; /* make it of several 16 bytes */
new_insn = MIR_new_insn (ctx, MIR_SUB, _MIR_new_var_op (ctx, SP_HARD_REG),
_MIR_new_var_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (gen_ctx, prev_call_insn, next_insn, call_insn);
new_insn = MIR_new_insn (ctx, MIR_ADD, _MIR_new_var_op (ctx, SP_HARD_REG),
_MIR_new_var_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (gen_ctx, call_insn, next_insn, call_insn);
}
}
static long double mir_i2ld (int64_t i) { return i; }
static const char *I2LD = "mir.i2ld";
static const char *I2LD_P = "mir.i2ld.p";
static long double mir_ui2ld (uint64_t i) { return i; }
static const char *UI2LD = "mir.ui2ld";
static const char *UI2LD_P = "mir.ui2ld.p";
static long double mir_f2ld (float f) { return f; }
static const char *F2LD = "mir.f2ld";
static const char *F2LD_P = "mir.f2ld.p";
static long double mir_d2ld (double d) { return d; }
static const char *D2LD = "mir.d2ld";
static const char *D2LD_P = "mir.d2ld.p";
static int64_t mir_ld2i (long double ld) { return ld; }
static const char *LD2I = "mir.ld2i";
static const char *LD2I_P = "mir.ld2i.p";
static float mir_ld2f (long double ld) { return ld; }
static const char *LD2F = "mir.ld2f";
static const char *LD2F_P = "mir.ld2f.p";
static double mir_ld2d (long double ld) { return ld; }
static const char *LD2D = "mir.ld2d";
static const char *LD2D_P = "mir.ld2d.p";
static long double mir_ldadd (long double d1, long double d2) { return d1 + d2; }
static const char *LDADD = "mir.ldadd";
static const char *LDADD_P = "mir.ldadd.p";
static long double mir_ldsub (long double d1, long double d2) { return d1 - d2; }
static const char *LDSUB = "mir.ldsub";
static const char *LDSUB_P = "mir.ldsub.p";
static long double mir_ldmul (long double d1, long double d2) { return d1 * d2; }
static const char *LDMUL = "mir.ldmul";
static const char *LDMUL_P = "mir.ldmul.p";
static long double mir_lddiv (long double d1, long double d2) { return d1 / d2; }
static const char *LDDIV = "mir.lddiv";
static const char *LDDIV_P = "mir.lddiv.p";
static long double mir_ldneg (long double d) { return -d; }
static const char *LDNEG = "mir.ldneg";
static const char *LDNEG_P = "mir.ldneg.p";
static const char *VA_ARG_P = "mir.va_arg.p";
static const char *VA_ARG = "mir.va_arg";
static const char *VA_BLOCK_ARG_P = "mir.va_block_arg.p";
static const char *VA_BLOCK_ARG = "mir.va_block_arg";
static int64_t mir_ldeq (long double d1, long double d2) { return d1 == d2; }
static const char *LDEQ = "mir.ldeq";
static const char *LDEQ_P = "mir.ldeq.p";
static int64_t mir_ldne (long double d1, long double d2) { return d1 != d2; }
static const char *LDNE = "mir.ldne";
static const char *LDNE_P = "mir.ldne.p";
static int64_t mir_ldlt (long double d1, long double d2) { return d1 < d2; }
static const char *LDLT = "mir.ldlt";
static const char *LDLT_P = "mir.ldlt.p";
static int64_t mir_ldge (long double d1, long double d2) { return d1 >= d2; }
static const char *LDGE = "mir.ldge";
static const char *LDGE_P = "mir.ldge.p";
static int64_t mir_ldgt (long double d1, long double d2) { return d1 > d2; }
static const char *LDGT = "mir.ldgt";
static const char *LDGT_P = "mir.ldgt.p";
static int64_t mir_ldle (long double d1, long double d2) { return d1 <= d2; }
static const char *LDLE = "mir.ldle";
static const char *LDLE_P = "mir.ldle.p";
static int get_builtin (gen_ctx_t gen_ctx, MIR_insn_code_t code, MIR_item_t *proto_item,
MIR_item_t *func_import_item) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_type_t res_type;
*func_import_item = *proto_item = NULL; /* to remove uninitialized warning */
switch (code) {
case MIR_I2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, I2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, I2LD, mir_i2ld);
return 1;
case MIR_UI2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2LD, mir_ui2ld);
return 1;
case MIR_F2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, F2LD_P, 1, &res_type, 1, MIR_T_F, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, F2LD, mir_f2ld);
return 1;
case MIR_D2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, D2LD_P, 1, &res_type, 1, MIR_T_D, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, D2LD, mir_d2ld);
return 1;
case MIR_LD2I:
res_type = MIR_T_I64;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2I_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2I, mir_ld2i);
return 1;
case MIR_LD2F:
res_type = MIR_T_F;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2F_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2F, mir_ld2f);
return 1;
case MIR_LD2D:
res_type = MIR_T_D;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2D_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2D, mir_ld2d);
return 1;
case MIR_LDADD:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDADD_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDADD, mir_ldadd);
return 2;
case MIR_LDSUB:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDSUB_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDSUB, mir_ldsub);
return 2;
case MIR_LDMUL:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDMUL_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDMUL, mir_ldmul);
return 2;
case MIR_LDDIV:
res_type = MIR_T_LD;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDDIV_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDDIV, mir_lddiv);
return 2;
case MIR_LDNEG:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LDNEG_P, 1, &res_type, 1, MIR_T_LD, "d");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNEG, mir_ldneg);
return 1;
case MIR_LDEQ:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDEQ_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDEQ, mir_ldeq);
return 2;
case MIR_LDNE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDNE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDNE, mir_ldne);
return 2;
case MIR_LDLT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLT, mir_ldlt);
return 2;
case MIR_LDGE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGE, mir_ldge);
return 2;
case MIR_LDGT:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDGT_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDGT, mir_ldgt);
return 2;
case MIR_LDLE:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, LDLE_P, 1, &res_type, 2,
MIR_T_LD, "d1", MIR_T_LD, "d2");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LDLE, mir_ldle);
return 2;
case MIR_VA_ARG:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, VA_ARG_P, 1, &res_type, 2,
MIR_T_I64, "va", MIR_T_I64, "type");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, VA_ARG, va_arg_builtin);
return 2;
case MIR_VA_BLOCK_ARG:
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, VA_BLOCK_ARG_P, 0, NULL, 4, MIR_T_I64,
"res", MIR_T_I64, "va", MIR_T_I64, "size", MIR_T_I64, "ncase");
*func_import_item
= _MIR_builtin_func (ctx, curr_func_item->module, VA_BLOCK_ARG, va_block_arg_builtin);
return 4;
default: return 0;
}
}
struct insn_pattern_info {
int start, num;
};
typedef struct insn_pattern_info insn_pattern_info_t;
DEF_VARR (insn_pattern_info_t);
struct label_ref {
int abs_addr_p, short_p;
size_t label_val_disp;
union {
MIR_label_t label;
void *jump_addr; /* absolute addr for BBV */
} u;
};
typedef struct label_ref label_ref_t;
DEF_VARR (label_ref_t);
struct target_ctx {
unsigned char alloca_p, block_arg_func_p, leaf_p, short_bb_branch_p;
size_t small_aggregate_save_area;
MIR_insn_t temp_jump;
const char *temp_jump_replacement;
VARR (int) * pattern_indexes;
VARR (insn_pattern_info_t) * insn_pattern_info;
VARR (uint8_t) * result_code;
VARR (label_ref_t) * label_refs;
VARR (uint64_t) * abs_address_locs;
VARR (MIR_code_reloc_t) * relocs;
};
#define alloca_p gen_ctx->target_ctx->alloca_p
#define block_arg_func_p gen_ctx->target_ctx->block_arg_func_p
#define leaf_p gen_ctx->target_ctx->leaf_p
#define short_bb_branch_p gen_ctx->target_ctx->short_bb_branch_p
#define small_aggregate_save_area gen_ctx->target_ctx->small_aggregate_save_area
#define temp_jump gen_ctx->target_ctx->temp_jump
#define temp_jump_replacement gen_ctx->target_ctx->temp_jump_replacement
#define pattern_indexes gen_ctx->target_ctx->pattern_indexes
#define insn_pattern_info gen_ctx->target_ctx->insn_pattern_info
#define result_code gen_ctx->target_ctx->result_code
#define label_refs gen_ctx->target_ctx->label_refs
#define abs_address_locs gen_ctx->target_ctx->abs_address_locs
#define relocs gen_ctx->target_ctx->relocs
static MIR_disp_t target_get_stack_slot_offset (gen_ctx_t gen_ctx, MIR_type_t type MIR_UNUSED,
MIR_reg_t slot) {
/* slot is 0, 1, ... */
size_t offset = curr_func_item->u.func->vararg_p || block_arg_func_p ? 32 : 16;
return ((MIR_disp_t) slot * 8 + offset);
}
static int target_valid_mem_offset_p (gen_ctx_t gen_ctx MIR_UNUSED, MIR_type_t type,
MIR_disp_t offset) {
int scale;
switch (type) {
case MIR_T_I8:
case MIR_T_U8: scale = 1; break;
case MIR_T_I16:
case MIR_T_U16: scale = 2; break;
case MIR_T_I32:
case MIR_T_U32:
#if MIR_PTR32
case MIR_T_P:
#endif
case MIR_T_F: scale = 4; break;
case MIR_T_LD: scale = 16; break;
default: scale = 8; break;
}
return offset >= 0 && offset % scale == 0 && offset / scale < (1 << 12);
}
static void target_machinize (gen_ctx_t gen_ctx) {
MIR_context_t ctx = gen_ctx->ctx;
MIR_func_t func;
MIR_type_t type, mem_type, res_type;
MIR_insn_code_t code, new_insn_code;
MIR_insn_t insn, next_insn, new_insn, anchor;
MIR_var_t var;
MIR_reg_t ret_reg, arg_reg;
MIR_op_t ret_reg_op, arg_reg_op, mem_op, temp_op;
size_t i, int_arg_num, fp_arg_num, mem_size, qwords;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
block_arg_func_p = FALSE;
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
small_aggregate_save_area = 0;
for (i = int_arg_num = fp_arg_num = mem_size = 0; i < func->nargs; i++) {
/* Argument extensions is already done in simplify */
/* Prologue: generate arg_var = hard_reg|stack mem|stack addr ... */
var = VARR_GET (MIR_var_t, func->vars, i);
type = var.type;
if (type == MIR_T_RBLK && i == 0) { /* hidden arg */
arg_reg_op = _MIR_new_var_op (ctx, R8_HARD_REG);
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, i + MAX_HARD_REG + 1), arg_reg_op);
continue;
} else if (MIR_blk_type_p (type) && (qwords = (var.size + 7) / 8) <= 2) {
if (int_arg_num + qwords <= 8) {
small_aggregate_save_area += qwords * 8;
new_insn = MIR_new_insn (ctx, MIR_SUB, _MIR_new_var_op (ctx, i + MAX_HARD_REG + 1),
_MIR_new_var_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, small_aggregate_save_area));
gen_add_insn_before (gen_ctx, anchor, new_insn);
if (qwords == 0) continue;
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 0, i + MAX_HARD_REG + 1, MIR_NON_VAR, 1),
_MIR_new_var_op (ctx, int_arg_num));
if (qwords == 2)
gen_mov (gen_ctx, anchor, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 8, i + MAX_HARD_REG + 1, MIR_NON_VAR, 1),
_MIR_new_var_op (ctx, int_arg_num + 1));
} else { /* pass on stack w/o address: */
if (!block_arg_func_p) {
block_arg_func_p = TRUE;
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, R8_HARD_REG),
_MIR_new_var_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_VAR, 1));
}
gen_add_insn_before (gen_ctx, anchor,
MIR_new_insn (ctx, MIR_ADD,
_MIR_new_var_op (ctx, i + MAX_HARD_REG + 1),
_MIR_new_var_op (ctx, R8_HARD_REG),
MIR_new_int_op (ctx, mem_size)));
mem_size += qwords * 8;
}
int_arg_num += qwords;
continue;
}
arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code);
if (arg_reg != MIR_NON_VAR) {
arg_reg_op = _MIR_new_var_op (ctx, arg_reg);
gen_mov (gen_ctx, anchor, new_insn_code, _MIR_new_var_op (ctx, i + MAX_HARD_REG + 1),
arg_reg_op);
} else {
/* arg is on the stack */
if (!block_arg_func_p) {
block_arg_func_p = TRUE;
gen_mov (gen_ctx, anchor, MIR_MOV, _MIR_new_var_op (ctx, R8_HARD_REG),
_MIR_new_var_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_VAR, 1));
}
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
if (type == MIR_T_LD) mem_size = (mem_size + 15) / 16 * 16;
new_insn_code = (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV
: type == MIR_T_LD ? MIR_LDMOV
: MIR_MOV);
mem_op = new_hard_reg_mem_op (gen_ctx, anchor, mem_type, mem_size, R8_HARD_REG);
gen_mov (gen_ctx, anchor, new_insn_code, _MIR_new_var_op (ctx, i + MAX_HARD_REG + 1), mem_op);
mem_size += type == MIR_T_LD ? 16 : 8;
}
}
alloca_p = FALSE;
leaf_p = TRUE;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
MIR_item_t proto_item, func_import_item;
int nargs;
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
if (code == MIR_LDBEQ || code == MIR_LDBNE || code == MIR_LDBLT || code == MIR_LDBGE
|| code == MIR_LDBGT || code == MIR_LDBLE) {
temp_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
code = (code == MIR_LDBEQ ? MIR_LDEQ
: code == MIR_LDBNE ? MIR_LDNE
: code == MIR_LDBLT ? MIR_LDLT
: code == MIR_LDBGE ? MIR_LDGE
: code == MIR_LDBGT ? MIR_LDGT
: MIR_LDLE);
new_insn = MIR_new_insn (ctx, code, temp_op, insn->ops[1], insn->ops[2]);
gen_add_insn_before (gen_ctx, insn, new_insn);
next_insn = MIR_new_insn (ctx, MIR_BT, insn->ops[0], temp_op);
gen_add_insn_after (gen_ctx, new_insn, next_insn);
gen_delete_insn (gen_ctx, insn);
insn = new_insn;
}
if ((nargs = get_builtin (gen_ctx, code, &proto_item, &func_import_item)) > 0) {
if (code == MIR_VA_ARG || code == MIR_VA_BLOCK_ARG) {
/* Use a builtin func call:
mov func_reg, func ref; [mov reg3, type;] call proto, func_reg, res_reg, va_reg,
reg3 */
MIR_op_t ops[6], func_reg_op, reg_op3;
MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], op3 = insn->ops[2];
assert (res_reg_op.mode == MIR_OP_VAR && va_reg_op.mode == MIR_OP_VAR
&& op3.mode == (code == MIR_VA_ARG ? MIR_OP_VAR_MEM : MIR_OP_VAR));
func_reg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
reg_op3 = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, func_reg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, insn, new_insn);
if (code == MIR_VA_ARG) {
new_insn = MIR_new_insn (ctx, MIR_MOV, reg_op3,
MIR_new_int_op (ctx, (int64_t) op3.u.var_mem.type));
op3 = reg_op3;
gen_add_insn_before (gen_ctx, insn, new_insn);
}
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = func_reg_op;
ops[2] = res_reg_op;
ops[3] = va_reg_op;
ops[4] = op3;
if (code == MIR_VA_BLOCK_ARG) ops[5] = insn->ops[3];
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, code == MIR_VA_ARG ? 5 : 6, ops);
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_delete_insn (gen_ctx, insn);
} else { /* Use builtin: mov freg, func ref; call proto, freg, res_reg, op_reg[, op_reg2] */
MIR_op_t freg_op, res_reg_op = insn->ops[0], op_reg_op = insn->ops[1], ops[5];
assert (res_reg_op.mode == MIR_OP_VAR && op_reg_op.mode == MIR_OP_VAR);
freg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (gen_ctx, insn, new_insn);
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = res_reg_op;
ops[3] = op_reg_op;
if (nargs == 2) ops[4] = insn->ops[2];
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, nargs + 3, ops);
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_delete_insn (gen_ctx, insn);
}
} else if (code == MIR_VA_START) {
#if !defined(__APPLE__)
MIR_op_t treg_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
#endif
MIR_op_t prev_sp_op = _MIR_new_var_op (ctx, gen_new_temp_reg (gen_ctx, MIR_T_I64, func));
MIR_op_t va_op = insn->ops[0];
MIR_reg_t va_reg;
int gp_offset, fp_offset;
assert (func->vararg_p && va_op.mode == MIR_OP_VAR);
gp_offset = (int_arg_num >= 8 ? 0 : 8 * int_arg_num - 64);
fp_offset = (fp_arg_num >= 8 ? 0 : 16 * fp_arg_num - 128);
va_reg = va_op.u.var;
/* Insns can be not simplified as soon as they match a machine insn. */
#if !defined(__APPLE__)
/* mem32[va_reg].__gr_offset = gp_offset; mem32[va_reg].__vr_offset = fp_offset */
gen_mov (gen_ctx, insn, MIR_MOV, treg_op, MIR_new_int_op (ctx, gp_offset));
gen_mov (gen_ctx, insn, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_U32, 24, va_reg, MIR_NON_VAR, 1), treg_op);
gen_mov (gen_ctx, insn, MIR_MOV, treg_op, MIR_new_int_op (ctx, fp_offset));
gen_mov (gen_ctx, insn, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_U32, 28, va_reg, MIR_NON_VAR, 1), treg_op);
#endif
/* __stack: prev_sp = mem64[fp + 16] */
gen_mov (gen_ctx, insn, MIR_MOV, prev_sp_op,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 16, FP_HARD_REG, MIR_NON_VAR, 1));
#if defined(__APPLE__)
gen_mov (gen_ctx, insn, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 0, va_reg, MIR_NON_VAR, 1), prev_sp_op);
#else
/* mem64[va_reg].__stack = prev_sp + mem_size */
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, prev_sp_op, MIR_new_int_op (ctx, mem_size));
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_mov (gen_ctx, insn, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 0, va_reg, MIR_NON_VAR, 1), treg_op);
/* __gr_top: mem64[va_reg].__gr_top = prev_sp */
gen_mov (gen_ctx, insn, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 8, va_reg, MIR_NON_VAR, 1), prev_sp_op);
/* __vr_top: treg = prev_sp - int_reg_save_area; mem64[va_reg].__vr_top = treg */
new_insn = MIR_new_insn (ctx, MIR_SUB, treg_op, prev_sp_op,
MIR_new_int_op (ctx, int_reg_save_area_size));
gen_add_insn_before (gen_ctx, insn, new_insn);
gen_mov (gen_ctx, insn, MIR_MOV,
_MIR_new_var_mem_op (ctx, MIR_T_I64, 16, va_reg, MIR_NON_VAR, 1), treg_op);
#endif
gen_delete_insn (gen_ctx, insn);
} else if (code == MIR_VA_END) { /* do nothing */
gen_delete_insn (gen_ctx, insn);
} else if (MIR_call_code_p (code)) {
machinize_call (gen_ctx, insn);
leaf_p = FALSE;
} else if (code == MIR_ALLOCA) {
alloca_p = TRUE;
} else if (code == MIR_FBLT) { /* don't use blt/ble for correct nan processing: */
SWAP (insn->ops[1], insn->ops[2], temp_op);
insn->code = MIR_FBGT;
} else if (code == MIR_FBLE) {
SWAP (insn->ops[1], insn->ops[2], temp_op);
insn->code = MIR_FBGE;
} else if (code == MIR_DBLT) {
SWAP (insn->ops[1], insn->ops[2], temp_op);
insn->code = MIR_DBGT;
} else if (code == MIR_DBLE) {
SWAP (insn->ops[1], insn->ops[2], temp_op);
insn->code = MIR_DBGE;
} else if (code == MIR_RET) {
/* In simplify we already transformed code for one return insn
and added extension insn (if any). */
uint32_t n_iregs = 0, n_vregs = 0;
assert (func->nres == MIR_insn_nops (ctx, insn));
for (i = 0; i < func->nres; i++) {
assert (insn->ops[i].mode == MIR_OP_VAR);
res_type = func->res_types[i];
if ((res_type == MIR_T_F || res_type == MIR_T_D || res_type == MIR_T_LD) && n_vregs < 8) {
new_insn_code = res_type == MIR_T_F ? MIR_FMOV
: res_type == MIR_T_D ? MIR_DMOV
: MIR_LDMOV;
ret_reg = V0_HARD_REG + n_vregs++;
} else if (n_iregs < 8) {
new_insn_code = MIR_MOV;
ret_reg = R0_HARD_REG + n_iregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"aarch64 can not handle this combination of return values");
}
ret_reg_op = _MIR_new_var_op (ctx, ret_reg);
gen_mov (gen_ctx, insn, new_insn_code, ret_reg_op, insn->ops[i]);
insn->ops[i] = ret_reg_op;
}
}
}
}
#if !defined(__APPLE__)
static void isave (gen_ctx_t gen_ctx, MIR_insn_t anchor, int disp, MIR_reg_t base,