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mir-interp.c
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mir-interp.c
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/* This file is a part of MIR project.
Copyright (C) 2018-2024 Vladimir Makarov <[email protected]>.
File contains MIR interpreter which is an obligatory part of MIR API.
*/
#ifdef MIR_NO_INTERP
static void interp_init (MIR_context_t ctx) {}
static void finish_func_interpretation (MIR_item_t func_item) {}
static void interp_finish (MIR_context_t ctx) {}
void MIR_interp (MIR_context_t ctx, MIR_item_t func_item, MIR_val_t *results, size_t nargs, ...) {}
void MIR_interp_arr_varg (MIR_context_t ctx, MIR_item_t func_item, MIR_val_t *results, size_t nargs,
MIR_val_t *vals, va_list va) {}
void MIR_interp_arr (MIR_context_t ctx, MIR_item_t func_item, MIR_val_t *results, size_t nargs,
MIR_val_t *vals) {}
void MIR_set_interp_interface (MIR_context_t ctx, MIR_item_t func_item) {}
#else
#ifndef MIR_INTERP_TRACE
#define MIR_INTERP_TRACE 0
#endif
#if !defined(MIR_DIRECT_DISPATCH) && defined(__GNUC__)
#define DIRECT_THREADED_DISPATCH 1
#else
#define DIRECT_THREADED_DISPATCH 0
#endif
#if defined(__GNUC__)
#define ALWAYS_INLINE inline __attribute ((always_inline))
#else
#define ALWAYS_INLINE inline
#endif
#if defined(_MSC_VER)
#define alloca _alloca
#endif
typedef MIR_val_t *code_t;
typedef struct func_desc {
MIR_reg_t nregs;
MIR_item_t func_item;
MIR_val_t code[1];
} *func_desc_t;
static void update_max_nreg (MIR_reg_t reg, MIR_reg_t *max_nreg) {
if (*max_nreg < reg) *max_nreg = reg;
}
static MIR_reg_t get_reg (MIR_op_t op, MIR_reg_t *max_nreg) {
/* We do not interpret code with hard regs */
mir_assert (op.mode == MIR_OP_REG);
update_max_nreg (op.u.reg, max_nreg);
return op.u.reg;
}
#define IC_EL(i) IC_##i
#define REP_SEP ,
typedef enum {
IC_LDI8 = MIR_INSN_BOUND,
REP6 (IC_EL, LDU8, LDI16, LDU16, LDI32, LDU32, LDI64),
REP3 (IC_EL, LDF, LDD, LDLD),
REP7 (IC_EL, STI8, STU8, STI16, STU16, STI32, STU32, STI64),
REP8 (IC_EL, STF, STD, STLD, MOVI, MOVP, MOVF, MOVD, MOVLD),
REP6 (IC_EL, IMM_CALL, IMM_JCALL, MOVFG, FMOVFG, DMOVFG, LDMOVFG),
REP5 (IC_EL, MOVTG, FMOVTG, DMOVTG, LDMOVTG, INSN_BOUND),
} MIR_full_insn_code_t;
#undef REP_SEP
DEF_VARR (MIR_val_t);
struct ff_interface {
size_t arg_vars_num, nres, nargs;
MIR_type_t *res_types;
_MIR_arg_desc_t *arg_descs;
void *interface_addr;
};
typedef struct ff_interface *ff_interface_t;
DEF_HTAB (ff_interface_t);
DEF_VARR (_MIR_arg_desc_t);
struct interp_ctx {
#if DIRECT_THREADED_DISPATCH
void *dispatch_label_tab[IC_INSN_BOUND];
#endif
MIR_val_t global_regs[MAX_HARD_REG + 1];
VARR (MIR_val_t) * code_varr;
VARR (MIR_insn_t) * branches;
VARR (MIR_val_t) * arg_vals_varr;
MIR_val_t *arg_vals;
#if MIR_INTERP_TRACE
int trace_insn_ident;
#endif
void *(*bstart_builtin) (void);
void (*bend_builtin) (void *);
void *jret_addr;
VARR (MIR_val_t) * call_res_args_varr;
MIR_val_t *call_res_args;
VARR (_MIR_arg_desc_t) * call_arg_descs_varr;
_MIR_arg_desc_t *call_arg_descs;
HTAB (ff_interface_t) * ff_interface_tab;
};
#define dispatch_label_tab interp_ctx->dispatch_label_tab
#define global_regs interp_ctx->global_regs
#define code_varr interp_ctx->code_varr
#define branches interp_ctx->branches
#define jret_addr interp_ctx->jret_addr
#define arg_vals_varr interp_ctx->arg_vals_varr
#define arg_vals interp_ctx->arg_vals
#define trace_insn_ident interp_ctx->trace_insn_ident
#define trace_ident interp_ctx->trace_ident
#define bstart_builtin interp_ctx->bstart_builtin
#define bend_builtin interp_ctx->bend_builtin
#define call_res_args_varr interp_ctx->call_res_args_varr
#define call_res_args interp_ctx->call_res_args
#define call_arg_descs_varr interp_ctx->call_arg_descs_varr
#define call_arg_descs interp_ctx->call_arg_descs
#define ff_interface_tab interp_ctx->ff_interface_tab
static void get_icode (struct interp_ctx *interp_ctx, MIR_val_t *v, int code) {
#if DIRECT_THREADED_DISPATCH
v->a = dispatch_label_tab[code];
#else
v->ic = code;
#endif
}
static void push_insn_start (struct interp_ctx *interp_ctx, int code,
MIR_insn_t original_insn MIR_UNUSED) {
MIR_val_t v;
get_icode (interp_ctx, &v, code);
VARR_PUSH (MIR_val_t, code_varr, v);
#if MIR_INTERP_TRACE
v.a = original_insn;
VARR_PUSH (MIR_val_t, code_varr, v);
#endif
}
static MIR_full_insn_code_t get_int_mem_insn_code (int load_p, MIR_type_t t) {
switch (t) {
case MIR_T_I8: return load_p ? IC_LDI8 : IC_STI8;
case MIR_T_U8: return load_p ? IC_LDU8 : IC_STU8;
case MIR_T_I16: return load_p ? IC_LDI16 : IC_STI16;
case MIR_T_U16: return load_p ? IC_LDU16 : IC_STU16;
case MIR_T_I32: return load_p ? IC_LDI32 : IC_STI32;
#if MIR_PTR32
case MIR_T_P:
#endif
case MIR_T_U32: return load_p ? IC_LDU32 : IC_STU32;
#if MIR_PTR64
case MIR_T_P:
#endif
case MIR_T_I64:
case MIR_T_U64: return load_p ? IC_LDI64 : IC_STI64;
default: mir_assert (FALSE); return load_p ? IC_LDI64 : IC_STI64; /* to remove a warning */
}
}
static void push_mem (struct interp_ctx *interp_ctx, MIR_op_t op) {
MIR_val_t v;
mir_assert (op.mode == MIR_OP_MEM && op.u.mem.disp == 0 && op.u.mem.index == 0);
v.i = op.u.mem.base;
VARR_PUSH (MIR_val_t, code_varr, v);
}
static void redirect_interface_to_interp (MIR_context_t ctx, MIR_item_t func_item);
static void generate_icode (MIR_context_t ctx, MIR_item_t func_item) {
struct interp_ctx *interp_ctx = ctx->interp_ctx;
int imm_call_p;
MIR_func_t func = func_item->u.func;
MIR_insn_t insn, label;
MIR_type_t type;
MIR_val_t v;
size_t i;
MIR_reg_t max_nreg = 0;
func_desc_t func_desc;
VARR_TRUNC (MIR_insn_t, branches, 0);
VARR_TRUNC (MIR_val_t, code_varr, 0);
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL;
insn = DLIST_NEXT (MIR_insn_t, insn)) {
MIR_insn_code_t code = insn->code;
size_t nops = MIR_insn_nops (ctx, insn);
MIR_op_t *ops = insn->ops;
insn->data = (void *) VARR_LENGTH (MIR_val_t, code_varr);
switch (code) {
case MIR_MOV: /* loads, imm moves */
if (ops[0].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, get_int_mem_insn_code (FALSE, ops[0].u.mem.type), insn);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[0]);
} else if (ops[1].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, get_int_mem_insn_code (TRUE, ops[1].u.mem.type), insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[1]);
} else if (ops[1].mode == MIR_OP_INT || ops[1].mode == MIR_OP_UINT) {
push_insn_start (interp_ctx, IC_MOVI, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
if (ops[1].mode == MIR_OP_INT)
v.i = ops[1].u.i;
else
v.u = ops[1].u.u;
VARR_PUSH (MIR_val_t, code_varr, v);
} else if (ops[1].mode == MIR_OP_REF) {
MIR_item_t item = ops[1].u.ref;
if (item->item_type == MIR_import_item && item->ref_def != NULL)
item->addr = item->ref_def->addr;
push_insn_start (interp_ctx, IC_MOVP, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.a = item->addr;
VARR_PUSH (MIR_val_t, code_varr, v);
} else {
const char *hard_reg_name;
regreg:
mir_assert (ops[0].mode == MIR_OP_REG && ops[1].mode == MIR_OP_REG);
type = MIR_reg_type (ctx, ops[0].u.reg, func);
mir_assert (type == MIR_reg_type (ctx, ops[1].u.reg, func));
if ((hard_reg_name = MIR_reg_hard_reg_name (ctx, ops[0].u.reg, func)) != NULL) {
mir_assert (MIR_reg_hard_reg_name (ctx, ops[1].u.reg, func) == NULL);
push_insn_start (interp_ctx,
type == MIR_T_F ? IC_FMOVTG
: type == MIR_T_D ? IC_DMOVTG
: type == MIR_T_LD ? IC_LDMOVTG
: IC_MOVTG,
insn);
v.i = _MIR_get_hard_reg (ctx, hard_reg_name);
mir_assert (v.i <= MAX_HARD_REG);
VARR_PUSH (MIR_val_t, code_varr, v);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
} else if ((hard_reg_name = MIR_reg_hard_reg_name (ctx, ops[1].u.reg, func)) != NULL) {
mir_assert (MIR_reg_hard_reg_name (ctx, ops[0].u.reg, func) == NULL);
push_insn_start (interp_ctx,
type == MIR_T_F ? IC_FMOVFG
: type == MIR_T_D ? IC_DMOVFG
: type == MIR_T_LD ? IC_LDMOVFG
: IC_MOVFG,
insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.i = _MIR_get_hard_reg (ctx, hard_reg_name);
mir_assert (v.i <= MAX_HARD_REG);
VARR_PUSH (MIR_val_t, code_varr, v);
} else {
push_insn_start (interp_ctx, code, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
}
}
break;
case MIR_FMOV:
if (ops[0].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, IC_STF, insn);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[0]);
} else if (ops[1].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, IC_LDF, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[1]);
} else if (ops[1].mode == MIR_OP_FLOAT) {
push_insn_start (interp_ctx, IC_MOVF, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.f = ops[1].u.f;
VARR_PUSH (MIR_val_t, code_varr, v);
} else {
goto regreg;
}
break;
case MIR_DMOV:
if (ops[0].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, IC_STD, insn);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[0]);
} else if (ops[1].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, IC_LDD, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[1]);
} else if (ops[1].mode == MIR_OP_DOUBLE) {
push_insn_start (interp_ctx, IC_MOVD, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.d = ops[1].u.d;
VARR_PUSH (MIR_val_t, code_varr, v);
} else {
goto regreg;
}
break;
case MIR_LDMOV:
if (ops[0].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, IC_STLD, insn);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[0]);
} else if (ops[1].mode == MIR_OP_MEM) {
push_insn_start (interp_ctx, IC_LDLD, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
push_mem (interp_ctx, ops[1]);
} else if (ops[1].mode == MIR_OP_LDOUBLE) {
push_insn_start (interp_ctx, IC_MOVLD, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.ld = ops[1].u.ld;
VARR_PUSH (MIR_val_t, code_varr, v);
} else {
goto regreg;
}
break;
case MIR_LABEL: break;
case MIR_INVALID_INSN:
(*MIR_get_error_func (ctx)) (MIR_invalid_insn_error, "invalid insn for interpreter");
break;
case MIR_JMP:
VARR_PUSH (MIR_insn_t, branches, insn);
push_insn_start (interp_ctx, code, insn);
v.i = 0;
VARR_PUSH (MIR_val_t, code_varr, v);
break;
case MIR_LADDR:
VARR_PUSH (MIR_insn_t, branches, insn);
push_insn_start (interp_ctx, code, insn);
v.i = get_reg (ops[0], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.i = 0;
VARR_PUSH (MIR_val_t, code_varr, v);
break;
case MIR_BT:
case MIR_BTS:
case MIR_BF:
case MIR_BFS:
VARR_PUSH (MIR_insn_t, branches, insn);
push_insn_start (interp_ctx, code, insn);
v.i = 0;
VARR_PUSH (MIR_val_t, code_varr, v);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
break;
case MIR_BEQ:
case MIR_BEQS:
case MIR_FBEQ:
case MIR_DBEQ:
case MIR_BNE:
case MIR_BNES:
case MIR_FBNE:
case MIR_DBNE:
case MIR_BLT:
case MIR_BLTS:
case MIR_UBLT:
case MIR_UBLTS:
case MIR_FBLT:
case MIR_DBLT:
case MIR_BLE:
case MIR_BLES:
case MIR_UBLE:
case MIR_UBLES:
case MIR_FBLE:
case MIR_DBLE:
case MIR_BGT:
case MIR_BGTS:
case MIR_UBGT:
case MIR_UBGTS:
case MIR_FBGT:
case MIR_DBGT:
case MIR_BGE:
case MIR_BGES:
case MIR_UBGE:
case MIR_UBGES:
case MIR_FBGE:
case MIR_DBGE:
case MIR_LDBEQ:
case MIR_LDBNE:
case MIR_LDBLT:
case MIR_LDBLE:
case MIR_LDBGT:
case MIR_LDBGE:
VARR_PUSH (MIR_insn_t, branches, insn);
push_insn_start (interp_ctx, code, insn);
v.i = 0;
VARR_PUSH (MIR_val_t, code_varr, v);
v.i = get_reg (ops[1], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
v.i = get_reg (ops[2], &max_nreg);
VARR_PUSH (MIR_val_t, code_varr, v);
break;
case MIR_BO:
case MIR_UBO:
case MIR_BNO:
case MIR_UBNO:
VARR_PUSH (MIR_insn_t, branches, insn);
push_insn_start (interp_ctx, code, insn);
v.i = 0;
VARR_PUSH (MIR_val_t, code_varr, v);
break;
case MIR_PRSET: break; /* just ignore */
case MIR_PRBEQ: /* make jump if property is zero or ignore otherwise */
if (ops[2].mode == MIR_OP_INT && ops[2].u.i == 0) goto jump;
break;
case MIR_PRBNE: /* make jump if property is nonzero or ignore otherwise */
if (ops[2].mode != MIR_OP_INT || ops[2].u.i == 0) break;
jump:
VARR_PUSH (MIR_insn_t, branches, insn);
push_insn_start (interp_ctx, MIR_JMP, insn);
v.i = 0;
VARR_PUSH (MIR_val_t, code_varr, v); /* place for label */
break;
default:
imm_call_p = FALSE;
if (MIR_call_code_p (code))
imm_call_p = (ops[1].mode == MIR_OP_REF
&& (ops[1].u.ref->item_type == MIR_import_item
|| ops[1].u.ref->item_type == MIR_export_item
|| ops[1].u.ref->item_type == MIR_forward_item
|| ops[1].u.ref->item_type == MIR_func_item));
push_insn_start (interp_ctx,
imm_call_p ? (code == MIR_JCALL ? IC_IMM_JCALL : IC_IMM_CALL)
: code == MIR_INLINE ? MIR_CALL
: code,
insn);
if (code == MIR_SWITCH) {
VARR_PUSH (MIR_insn_t, branches, insn);
v.i = nops;
VARR_PUSH (MIR_val_t, code_varr, v);
} else if (code == MIR_RET) {
v.i = nops;
VARR_PUSH (MIR_val_t, code_varr, v);
} else if (MIR_call_code_p (code)) {
v.i = nops;
VARR_PUSH (MIR_val_t, code_varr, v);
v.a = insn;
VARR_PUSH (MIR_val_t, code_varr, v);
v.a = NULL;
VARR_PUSH (MIR_val_t, code_varr, v); /* for ffi interface */
}
for (i = 0; i < nops; i++) {
if (i == 0 && MIR_call_code_p (code)) { /* prototype ??? */
mir_assert (ops[i].mode == MIR_OP_REF && ops[i].u.ref->item_type == MIR_proto_item);
v.a = ops[i].u.ref;
} else if (i == 1 && imm_call_p) {
MIR_item_t item = ops[i].u.ref;
mir_assert (item->item_type == MIR_import_item || item->item_type == MIR_export_item
|| item->item_type == MIR_forward_item || item->item_type == MIR_func_item);
v.a = item->addr;
} else if (code == MIR_VA_ARG && i == 2) { /* type */
mir_assert (ops[i].mode == MIR_OP_MEM);
v.i = ops[i].u.mem.type;
} else if (code == MIR_SWITCH && i > 0) {
mir_assert (ops[i].mode == MIR_OP_LABEL);
v.i = 0;
} else if (MIR_call_code_p (code) && ops[i].mode == MIR_OP_MEM) {
mir_assert (MIR_all_blk_type_p (ops[i].u.mem.type));
v.i = ops[i].u.mem.base;
update_max_nreg ((MIR_reg_t) v.i, &max_nreg);
} else {
mir_assert (ops[i].mode == MIR_OP_REG);
v.i = get_reg (ops[i], &max_nreg);
}
VARR_PUSH (MIR_val_t, code_varr, v);
}
}
}
for (i = 0; i < VARR_LENGTH (MIR_insn_t, branches); i++) {
size_t start_label_nop = 0, bound_label_nop = 1, start_label_loc = 1, n;
insn = VARR_GET (MIR_insn_t, branches, i);
if (insn->code == MIR_LADDR) {
start_label_nop = 1;
bound_label_nop = 2;
} else if (insn->code == MIR_SWITCH) {
start_label_nop = 1;
bound_label_nop = start_label_nop + insn->nops - 1;
start_label_loc++; /* we put nops for MIR_SWITCH */
}
for (n = start_label_nop; n < bound_label_nop; n++) {
label = insn->ops[n].u.label;
v.i = (size_t) label->data;
#if MIR_INTERP_TRACE
VARR_SET (MIR_val_t, code_varr, (size_t) insn->data + n + start_label_loc + 1, v);
#else
VARR_SET (MIR_val_t, code_varr, (size_t) insn->data + n + start_label_loc, v);
#endif
}
}
func_item->data = func_desc
= malloc (sizeof (struct func_desc) + VARR_LENGTH (MIR_val_t, code_varr) * sizeof (MIR_val_t));
if (func_desc == NULL)
(*MIR_get_error_func (ctx)) (MIR_alloc_error, "no memory for interpreter code");
memmove (func_desc->code, VARR_ADDR (MIR_val_t, code_varr),
VARR_LENGTH (MIR_val_t, code_varr) * sizeof (MIR_val_t));
for (MIR_lref_data_t lref = func->first_lref; lref != NULL; lref = lref->next) {
if (lref->label2 == NULL)
*(void **) lref->load_addr
= (char *) (func_desc->code + (int64_t) lref->label->data) + lref->disp;
else
*(int64_t *) lref->load_addr
= (int64_t) lref->label->data - (int64_t) lref->label2->data + lref->disp;
}
mir_assert (max_nreg < MIR_MAX_REG_NUM);
func_desc->nregs = max_nreg + 1;
func_desc->func_item = func_item;
}
static void finish_func_interpretation (MIR_item_t func_item) {
mir_assert (func_item->item_type == MIR_func_item);
if (func_item->data == NULL) return;
for (MIR_insn_t insn = DLIST_HEAD (MIR_insn_t, func_item->u.func->insns); insn != NULL;
insn = DLIST_NEXT (MIR_insn_t, insn))
insn->data = NULL; /* it was used for interpretation preparation */
free (func_item->data);
func_item->data = NULL;
}
static ALWAYS_INLINE void *get_a (MIR_val_t *v) { return v->a; }
static ALWAYS_INLINE int64_t get_i (MIR_val_t *v) { return v->i; }
static ALWAYS_INLINE float get_f (MIR_val_t *v) { return v->f; }
static ALWAYS_INLINE double get_d (MIR_val_t *v) { return v->d; }
static ALWAYS_INLINE long double get_ld (MIR_val_t *v) { return v->ld; }
static ALWAYS_INLINE void **get_aop (MIR_val_t *bp, code_t c) { return &bp[get_i (c)].a; }
static ALWAYS_INLINE int64_t *get_iop (MIR_val_t *bp, code_t c) { return &bp[get_i (c)].i; }
static ALWAYS_INLINE uint64_t *get_uop (MIR_val_t *bp, code_t c) { return &bp[get_i (c)].u; }
static ALWAYS_INLINE float *get_fop (MIR_val_t *bp, code_t c) { return &bp[get_i (c)].f; }
static ALWAYS_INLINE double *get_dop (MIR_val_t *bp, code_t c) { return &bp[get_i (c)].d; }
static ALWAYS_INLINE long double *get_ldop (MIR_val_t *bp, code_t c) { return &bp[get_i (c)].ld; }
static ALWAYS_INLINE int64_t *get_2iops (MIR_val_t *bp, code_t c, int64_t *p) {
*p = *get_iop (bp, c + 1);
return get_iop (bp, c);
}
static ALWAYS_INLINE int64_t *get_2isops (MIR_val_t *bp, code_t c, int32_t *p) {
*p = (int32_t) *get_iop (bp, c + 1);
return get_iop (bp, c);
}
static ALWAYS_INLINE int64_t *get_3iops (MIR_val_t *bp, code_t c, int64_t *p1, int64_t *p2) {
*p1 = *get_iop (bp, c + 1);
*p2 = *get_iop (bp, c + 2);
return get_iop (bp, c);
}
static ALWAYS_INLINE int64_t *get_3isops (MIR_val_t *bp, code_t c, int32_t *p1, int32_t *p2) {
*p1 = (int32_t) *get_iop (bp, c + 1);
*p2 = (int32_t) *get_iop (bp, c + 2);
return get_iop (bp, c);
}
static ALWAYS_INLINE uint64_t *get_3uops (MIR_val_t *bp, code_t c, uint64_t *p1, uint64_t *p2) {
*p1 = *get_uop (bp, c + 1);
*p2 = *get_uop (bp, c + 2);
return get_uop (bp, c);
}
static ALWAYS_INLINE uint64_t *get_3usops (MIR_val_t *bp, code_t c, uint32_t *p1, uint32_t *p2) {
*p1 = (uint32_t) *get_uop (bp, c + 1);
*p2 = (uint32_t) *get_uop (bp, c + 2);
return get_uop (bp, c);
}
static ALWAYS_INLINE float *get_2fops (MIR_val_t *bp, code_t c, float *p) {
*p = *get_fop (bp, c + 1);
return get_fop (bp, c);
}
static ALWAYS_INLINE float *get_3fops (MIR_val_t *bp, code_t c, float *p1, float *p2) {
*p1 = *get_fop (bp, c + 1);
*p2 = *get_fop (bp, c + 2);
return get_fop (bp, c);
}
static ALWAYS_INLINE int64_t *get_fcmp_ops (MIR_val_t *bp, code_t c, float *p1, float *p2) {
*p1 = *get_fop (bp, c + 1);
*p2 = *get_fop (bp, c + 2);
return get_iop (bp, c);
}
static ALWAYS_INLINE double *get_2dops (MIR_val_t *bp, code_t c, double *p) {
*p = *get_dop (bp, c + 1);
return get_dop (bp, c);
}
static ALWAYS_INLINE double *get_3dops (MIR_val_t *bp, code_t c, double *p1, double *p2) {
*p1 = *get_dop (bp, c + 1);
*p2 = *get_dop (bp, c + 2);
return get_dop (bp, c);
}
static ALWAYS_INLINE int64_t *get_dcmp_ops (MIR_val_t *bp, code_t c, double *p1, double *p2) {
*p1 = *get_dop (bp, c + 1);
*p2 = *get_dop (bp, c + 2);
return get_iop (bp, c);
}
static ALWAYS_INLINE long double *get_2ldops (MIR_val_t *bp, code_t c, long double *p) {
*p = *get_ldop (bp, c + 1);
return get_ldop (bp, c);
}
static ALWAYS_INLINE long double *get_3ldops (MIR_val_t *bp, code_t c, long double *p1,
long double *p2) {
*p1 = *get_ldop (bp, c + 1);
*p2 = *get_ldop (bp, c + 2);
return get_ldop (bp, c);
}
static ALWAYS_INLINE int64_t *get_ldcmp_ops (MIR_val_t *bp, code_t c, long double *p1,
long double *p2) {
*p1 = *get_ldop (bp, c + 1);
*p2 = *get_ldop (bp, c + 2);
return get_iop (bp, c);
}
static ALWAYS_INLINE int64_t get_mem_addr (MIR_val_t *bp, code_t c) { return bp[get_i (c)].i; }
#define EXT(tp) \
do { \
int64_t *r = get_iop (bp, ops); \
tp s = (tp) * get_iop (bp, ops + 1); \
*r = (int64_t) s; \
} while (0)
#define IOP2(op) \
do { \
int64_t *r, p; \
r = get_2iops (bp, ops, &p); \
*r = op p; \
} while (0)
#define IOP2S(op) \
do { \
int64_t *r; \
int32_t p; \
r = get_2isops (bp, ops, &p); \
*r = op p; \
} while (0)
#define IOP3(op) \
do { \
int64_t *r, p1, p2; \
r = get_3iops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define IOP3S(op) \
do { \
int64_t *r; \
int32_t p1, p2; \
r = get_3isops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define ICMP(op) \
do { \
int64_t *r, p1, p2; \
r = get_3iops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define ICMPS(op) \
do { \
int64_t *r; \
int32_t p1, p2; \
r = get_3isops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define BICMP(op) \
do { \
int64_t op1 = *get_iop (bp, ops + 1), op2 = *get_iop (bp, ops + 2); \
if (op1 op op2) pc = code + get_i (ops); \
} while (0)
#define BICMPS(op) \
do { \
int32_t op1 = (int32_t) * get_iop (bp, ops + 1), op2 = (int32_t) * get_iop (bp, ops + 2); \
if (op1 op op2) pc = code + get_i (ops); \
} while (0)
#define UOP3(op) \
do { \
uint64_t *r, p1, p2; \
r = get_3uops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define UOP3S(op) \
do { \
uint64_t *r; \
uint32_t p1, p2; \
r = get_3usops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define UIOP3(op) \
do { \
uint64_t *r, p1, p2; \
r = get_3uops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define UIOP3S(op) \
do { \
uint64_t *r; \
uint32_t p1, p2; \
r = get_3usops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define UCMP(op) \
do { \
uint64_t *r, p1, p2; \
r = get_3uops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define UCMPS(op) \
do { \
uint64_t *r; \
uint32_t p1, p2; \
r = get_3usops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define BUCMP(op) \
do { \
uint64_t op1 = *get_uop (bp, ops + 1), op2 = *get_uop (bp, ops + 2); \
if (op1 op op2) pc = code + get_i (ops); \
} while (0)
#define BUCMPS(op) \
do { \
uint32_t op1 = (uint32_t) * get_uop (bp, ops + 1), op2 = (uint32_t) * get_uop (bp, ops + 2); \
if (op1 op op2) pc = code + get_i (ops); \
} while (0)
#define FOP2(op) \
do { \
float *r, p; \
r = get_2fops (bp, ops, &p); \
*r = op p; \
} while (0)
#define FOP3(op) \
do { \
float *r, p1, p2; \
r = get_3fops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define FCMP(op) \
do { \
int64_t *r; \
float p1, p2; \
r = get_fcmp_ops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define BFCMP(op) \
do { \
float op1 = *get_fop (bp, ops + 1), op2 = *get_fop (bp, ops + 2); \
if (op1 op op2) pc = code + get_i (ops); \
} while (0)
#define DOP2(op) \
do { \
double *r, p; \
r = get_2dops (bp, ops, &p); \
*r = op p; \
} while (0)
#define DOP3(op) \
do { \
double *r, p1, p2; \
r = get_3dops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define DCMP(op) \
do { \
int64_t *r; \
double p1, p2; \
r = get_dcmp_ops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define BDCMP(op) \
do { \
double op1 = *get_dop (bp, ops + 1), op2 = *get_dop (bp, ops + 2); \
if (op1 op op2) pc = code + get_i (ops); \
} while (0)
#define LDOP2(op) \
do { \
long double *r, p; \
r = get_2ldops (bp, ops, &p); \
*r = op p; \
} while (0)
#define LDOP3(op) \
do { \
long double *r, p1, p2; \
r = get_3ldops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define LDCMP(op) \
do { \
int64_t *r; \
long double p1, p2; \
r = get_ldcmp_ops (bp, ops, &p1, &p2); \
*r = p1 op p2; \
} while (0)
#define BLDCMP(op) \
do { \
long double op1 = *get_ldop (bp, ops + 1), op2 = *get_ldop (bp, ops + 2); \
if (op1 op op2) pc = code + get_i (ops); \
} while (0)
#define LD(op, val_type, mem_type) \
do { \
val_type *r = get_##op (bp, ops); \
int64_t a = get_mem_addr (bp, ops + 1); \
*r = *((mem_type *) a); \
} while (0)
#define ST(op, val_type, mem_type) \
do { \
val_type v = (val_type) * get_##op (bp, ops); \
int64_t a = get_mem_addr (bp, ops + 1); \
*((mem_type *) a) = (mem_type) v; \
} while (0)
#if !MIR_INTERP_TRACE && defined(__GNUC__) && !defined(__clang__)
#define OPTIMIZE \
__attribute__ ((__optimize__ ("O2"))) __attribute__ ((__optimize__ ("-fno-ipa-cp-clone")))
#else
#define OPTIMIZE
#endif
static void call (MIR_context_t ctx, MIR_val_t *bp, MIR_op_t *insn_arg_ops, code_t ffi_address_ptr,
MIR_item_t proto_item, void *addr, code_t res_ops, size_t nargs);
#if MIR_INTERP_TRACE
static void start_insn_trace (MIR_context_t ctx, const char *name, func_desc_t func_desc, code_t pc,
size_t nops) {
struct interp_ctx *interp_ctx = ctx->interp_ctx;
MIR_insn_t insn = pc[1].a;
code_t ops = pc + 2;
for (int i = 0; i < trace_insn_ident; i++) fprintf (stderr, " ");
fprintf (stderr, "%s", name);
for (size_t i = 0; i < nops; i++) {
fprintf (stderr, i == 0 ? "\t" : ", ");
fprintf (stderr, "%" PRId64, ops[i].i);
}
fprintf (stderr, "\t#");
MIR_output_insn (ctx, stderr, insn, func_desc->func_item->u.func, FALSE);
}
static void finish_insn_trace (MIR_context_t ctx, MIR_full_insn_code_t code, code_t ops,
MIR_val_t *bp) {
struct interp_ctx *interp_ctx = ctx->interp_ctx;
int out_p;
MIR_op_mode_t op_mode = MIR_OP_UNDEF;
MIR_val_t *res = bp;
switch (code) {
case IC_LDI8:
case IC_LDU8:
case IC_LDI16:
case IC_LDU16:
case IC_LDI32:
case IC_LDU32:
case IC_LDI64:
case IC_MOVI:
case IC_MOVTG:
res = global_regs;
/* falls through */
case IC_MOVFG:
case IC_MOVP: op_mode = MIR_OP_INT; break;
case IC_LDF:
case IC_FMOVTG:
res = global_regs;
/* falls through */
case IC_FMOVFG:
case IC_MOVF: op_mode = MIR_OP_FLOAT; break;
case IC_LDD:
case IC_DMOVTG:
res = global_regs;
/* falls through */
case IC_DMOVFG:
case IC_MOVD: op_mode = MIR_OP_DOUBLE; break;
case IC_LDLD:
case IC_LDMOVTG:
res = global_regs;
/* falls through */
case IC_LDMOVFG:
case IC_MOVLD: op_mode = MIR_OP_LDOUBLE; break;
case IC_STI8:
case IC_STU8:
case IC_STI16:
case IC_STU16:
case IC_STI32:
case IC_STU32:
case IC_STI64:
case IC_STF:
case IC_STD:;
case IC_STLD: break;
case IC_IMM_CALL: break;
case IC_IMM_JCALL: break;
default:
op_mode = _MIR_insn_code_op_mode (ctx, (MIR_insn_code_t) code, 0, &out_p);
if (op_mode == MIR_OP_BOUND || !out_p) op_mode = MIR_OP_UNDEF;
break;
}
switch (op_mode) {
case MIR_OP_INT:
case MIR_OP_UINT:
fprintf (stderr, "\t# res = %" PRId64 " (%" PRIu64 "u, 0x%" PRIx64 ")", res[ops[0].i].i,
res[ops[0].i].u, res[ops[0].i].u);
break;
case MIR_OP_FLOAT: fprintf (stderr, "\t# res = %.*ef", FLT_DECIMAL_DIG, res[ops[0].i].f); break;
case MIR_OP_LDOUBLE:
#ifndef _WIN32
fprintf (stderr, "\t# res = %.*Le", LDBL_DECIMAL_DIG, res[ops[0].i].ld);
break;
#endif
case MIR_OP_DOUBLE: fprintf (stderr, "\t# res = %.*e", DBL_DECIMAL_DIG, res[ops[0].i].d); break;
default: assert (op_mode == MIR_OP_UNDEF);
}
fprintf (stderr, "\n");
}
#endif
static code_t call_insn_execute (MIR_context_t ctx, code_t pc, MIR_val_t *bp, code_t ops,
int imm_p) {
struct interp_ctx *interp_ctx = ctx->interp_ctx;
int64_t nops = get_i (ops); /* #args w/o nop, insn, and ff interface address */
MIR_insn_t insn = get_a (ops + 1);
MIR_item_t proto_item = get_a (ops + 3);
void *func_addr = imm_p ? get_a (ops + 4) : *get_aop (bp, ops + 4);
size_t start = proto_item->u.proto->nres + 5;
if (VARR_EXPAND (MIR_val_t, arg_vals_varr, nops)) arg_vals = VARR_ADDR (MIR_val_t, arg_vals_varr);
for (size_t i = start; i < (size_t) nops + 3; i++) arg_vals[i - start] = bp[get_i (ops + i)];
#if MIR_INTERP_TRACE
trace_insn_ident += 2;
#endif
call (ctx, bp, &insn->ops[proto_item->u.proto->nres + 2] /* arg ops */,
ops + 2 /* ffi address holder */, proto_item, func_addr, ops + 5 /* results start */,
nops - start + 3 /* arg # */);
#if MIR_INTERP_TRACE
trace_insn_ident -= 2;
#endif
pc += nops + 3; /* nops itself, the call insn, add ff interface address */
return pc;
}
static int64_t addr_offset8, addr_offset16, addr_offset32;
static void OPTIMIZE eval (MIR_context_t ctx, func_desc_t func_desc, MIR_val_t *bp,
MIR_val_t *results) {
struct interp_ctx *interp_ctx = ctx->interp_ctx;
MIR_val_t *globals = global_regs;
code_t pc, ops, code;
void *jmpi_val; /* where label thunk execution result will be: */
int64_t offset;
int signed_overflow_p = FALSE, unsigned_overflow_p = FALSE; /* to avoid uninitialized warnings */
#if MIR_INTERP_TRACE
MIR_full_insn_code_t trace_insn_code;
#define START_INSN(v, nops) \
do { \
trace_insn_code = (MIR_full_insn_code_t) v; \
start_insn_trace (ctx, #v, func_desc, pc, nops); \
ops = pc + 2; /* skip original insn too */ \
pc += nops + 2; \
} while (0)
#else
#define START_INSN(v, nops) \
do { \
ops = pc + 1; \
pc += nops + 1; \
} while (0)
#endif
#if DIRECT_THREADED_DISPATCH
void **ltab = dispatch_label_tab;
#define LAB_EL(i) ltab[i] = &&L_##i
#define REP_SEP ;
if (bp == NULL) {
REP4 (LAB_EL, MIR_MOV, MIR_FMOV, MIR_DMOV, MIR_LDMOV);
REP6 (LAB_EL, MIR_EXT8, MIR_EXT16, MIR_EXT32, MIR_UEXT8, MIR_UEXT16, MIR_UEXT32);
REP6 (LAB_EL, MIR_I2F, MIR_I2D, MIR_I2LD, MIR_UI2F, MIR_UI2D, MIR_UI2LD);
REP8 (LAB_EL, MIR_F2I, MIR_D2I, MIR_LD2I, MIR_F2D, MIR_F2LD, MIR_D2F, MIR_D2LD, MIR_LD2F);
REP6 (LAB_EL, MIR_LD2D, MIR_NEG, MIR_NEGS, MIR_FNEG, MIR_DNEG, MIR_LDNEG);
REP6 (LAB_EL, MIR_ADDR, MIR_ADDR8, MIR_ADDR16, MIR_ADDR32, MIR_ADD, MIR_ADDS);
REP8 (LAB_EL, MIR_FADD, MIR_DADD, MIR_LDADD, MIR_SUB, MIR_SUBS, MIR_FSUB, MIR_DSUB, MIR_LDSUB);
REP8 (LAB_EL, MIR_MUL, MIR_MULS, MIR_FMUL, MIR_DMUL, MIR_LDMUL, MIR_DIV, MIR_DIVS, MIR_UDIV);
REP8 (LAB_EL, MIR_UDIVS, MIR_FDIV, MIR_DDIV, MIR_LDDIV, MIR_MOD, MIR_MODS, MIR_UMOD, MIR_UMODS);
REP8 (LAB_EL, MIR_AND, MIR_ANDS, MIR_OR, MIR_ORS, MIR_XOR, MIR_XORS, MIR_LSH, MIR_LSHS);
REP8 (LAB_EL, MIR_RSH, MIR_RSHS, MIR_URSH, MIR_URSHS, MIR_EQ, MIR_EQS, MIR_FEQ, MIR_DEQ);