diff --git a/modules/axhal/src/percpu.rs b/modules/axhal/src/percpu.rs
index d6f1c88771..09f738dcd5 100644
--- a/modules/axhal/src/percpu.rs
+++ b/modules/axhal/src/percpu.rs
@@ -80,6 +80,10 @@ pub(crate) fn init_primary(cpu_id: usize) {
         CPU_ID.write_current_raw(cpu_id);
         IS_BSP.write_current_raw(true);
     }
+    #[cfg(all(feature = "irq", target_arch = "riscv64"))]
+    {
+        axplat_riscv64_qemu_virt::register_this_cpu_id(this_cpu_id);
+    }
 }
 
 #[allow(dead_code)]
@@ -89,4 +93,8 @@ pub(crate) fn init_secondary(cpu_id: usize) {
         CPU_ID.write_current_raw(cpu_id);
         IS_BSP.write_current_raw(false);
     }
+    #[cfg(all(feature = "irq", target_arch = "riscv64"))]
+    {
+        axplat_riscv64_qemu_virt::register_this_cpu_id(this_cpu_id);
+    }
 }
diff --git a/modules/axruntime/Cargo.toml b/modules/axruntime/Cargo.toml
index 25216be460..c74d8e65c6 100644
--- a/modules/axruntime/Cargo.toml
+++ b/modules/axruntime/Cargo.toml
@@ -48,3 +48,6 @@ chrono = { workspace = true, optional = true }
 crate_interface = { workspace = true }
 indoc = "2"
 percpu = { workspace = true, optional = true }
+
+[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
+riscv = "0.14"
\ No newline at end of file
diff --git a/modules/axruntime/src/lib.rs b/modules/axruntime/src/lib.rs
index 8609d09e2b..2dfdc5d932 100644
--- a/modules/axruntime/src/lib.rs
+++ b/modules/axruntime/src/lib.rs
@@ -246,6 +246,11 @@ pub fn rust_main(cpu_id: usize, arg: usize) -> ! {
         core::hint::spin_loop();
     }
 
+    #[cfg(target_arch = "riscv64")]
+    unsafe {
+        use riscv::register::sstatus;
+        sstatus::set_sum();
+    }
     unsafe { main() };
 
     #[cfg(feature = "multitask")]
diff --git a/modules/axruntime/src/mp.rs b/modules/axruntime/src/mp.rs
index 464cfd7326..50a6fd4091 100644
--- a/modules/axruntime/src/mp.rs
+++ b/modules/axruntime/src/mp.rs
@@ -51,6 +51,14 @@ pub fn rust_main_secondary(cpu_id: usize) -> ! {
     #[cfg(feature = "ipi")]
     axipi::init();
 
+    #[cfg(target_arch = "riscv64")]
+    {
+        use riscv::register::sstatus;
+        unsafe {
+            sstatus::set_sum();
+        }
+    }
+
     info!("Secondary CPU {:x} init OK.", cpu_id);
     super::INITED_CPUS.fetch_add(1, Ordering::Release);