fix(riscv64): enable SUM for all cores (#10)

Co-authored-by: 朝倉水希 <asakuramizu111@gmail.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

Author: 3 people

src/riscv/init.rs

@@ -10,6 +10,8 @@ pub fn init_trap() {
         fn trap_vector_base();
     }
     unsafe {
+        #[cfg(feature = "uspace")]
+        riscv::register::sstatus::set_sum();
         crate::asm::write_trap_vector_base(trap_vector_base as usize);
     }
 }