diff --git a/page_table_entry/src/arch/loongarch64.rs b/page_table_entry/src/arch/loongarch64.rs
index 354119fe..bab6a9b9 100644
--- a/page_table_entry/src/arch/loongarch64.rs
+++ b/page_table_entry/src/arch/loongarch64.rs
@@ -97,7 +97,7 @@ impl From<MappingFlags> for PTEFlags {
             ret |= Self::NR;
         }
         if f.contains(MappingFlags::WRITE) {
-            ret |= Self::W;
+            ret |= Self::W | Self::D;
         }
         if !f.contains(MappingFlags::EXECUTE) {
             ret |= Self::NX;
@@ -134,7 +134,7 @@ impl LA64PTE {
 
 impl GenericPTE for LA64PTE {
     fn new_page(paddr: PhysAddr, flags: MappingFlags, is_huge: bool) -> Self {
-        let mut flags = PTEFlags::from(flags) | PTEFlags::D;
+        let mut flags = PTEFlags::from(flags);
         if is_huge {
             flags |= PTEFlags::GH;
         }
@@ -153,7 +153,7 @@ impl GenericPTE for LA64PTE {
         self.0 = (self.0 & !Self::PHYS_ADDR_MASK) | (paddr.as_usize() as u64 & Self::PHYS_ADDR_MASK)
     }
     fn set_flags(&mut self, flags: MappingFlags, is_huge: bool) {
-        let mut flags = PTEFlags::from(flags) | PTEFlags::D;
+        let mut flags = PTEFlags::from(flags);
         if is_huge {
             flags |= PTEFlags::GH;
         }
diff --git a/page_table_multiarch/src/arch/aarch64.rs b/page_table_multiarch/src/arch/aarch64.rs
index d79e2e5e..28cd71a7 100644
--- a/page_table_multiarch/src/arch/aarch64.rs
+++ b/page_table_multiarch/src/arch/aarch64.rs
@@ -24,7 +24,8 @@ impl PagingMetaData for A64PagingMetaData {
         unsafe {
             if let Some(vaddr) = vaddr {
                 // TLB Invalidate by VA, All ASID, EL1, Inner Shareable
-                asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) vaddr.as_usize())
+                // va[55:12] => reg[43:0]
+                asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) ((vaddr.as_usize() >> 12) & 0xFFF_FFFF_FFFF))
             } else {
                 // TLB Invalidate by VMID, All at stage 1, EL1
                 asm!("tlbi vmalle1; dsb sy; isb")