diff --git a/src/aarch64/vdso_data.rs b/src/aarch64/vdso_data.rs
index 006ed17..566a51a 100644
--- a/src/aarch64/vdso_data.rs
+++ b/src/aarch64/vdso_data.rs
@@ -3,10 +3,7 @@ use axplat::time::{
 };
 
 use super::config::ClockMode;
-use crate::{
-    update::{clocks_calc_mult_shift, update_vdso_clock},
-    vdso::VdsoClock,
-};
+use crate::update::{VdsoClock, clocks_calc_mult_shift, update_vdso_clock};
 
 #[repr(C)]
 #[repr(align(4096))]
diff --git a/src/loongarch64/vdso_data.rs b/src/loongarch64/vdso_data.rs
index 5aa825b..167a1b5 100644
--- a/src/loongarch64/vdso_data.rs
+++ b/src/loongarch64/vdso_data.rs
@@ -2,10 +2,7 @@ use axplat::time::{
     NANOS_PER_SEC, current_ticks, monotonic_time_nanos, nanos_to_ticks, wall_time_nanos,
 };
 
-use crate::{
-    update::{clocks_calc_mult_shift, update_vdso_clock},
-    vdso::VdsoClock,
-};
+use crate::update::{VdsoClock, clocks_calc_mult_shift, update_vdso_clock};
 
 #[repr(C)]
 #[repr(align(4096))]
diff --git a/src/riscv64/vdso_data.rs b/src/riscv64/vdso_data.rs
index b569df2..5dce2db 100644
--- a/src/riscv64/vdso_data.rs
+++ b/src/riscv64/vdso_data.rs
@@ -2,10 +2,7 @@ use axplat::time::{
     NANOS_PER_SEC, current_ticks, monotonic_time_nanos, nanos_to_ticks, wall_time_nanos,
 };
 
-use crate::{
-    update::{clocks_calc_mult_shift, update_vdso_clock},
-    vdso::VdsoClock,
-};
+use crate::update::{VdsoClock, clocks_calc_mult_shift, update_vdso_clock};
 
 #[repr(C)]
 #[repr(align(4096))]
diff --git a/src/update.rs b/src/update.rs
index 3d506da..062ad89 100644
--- a/src/update.rs
+++ b/src/update.rs
@@ -1,8 +1,69 @@
-use core::sync::atomic::Ordering;
+use core::sync::atomic::{AtomicU32, AtomicU64, Ordering};
 
 use axplat::time::NANOS_PER_SEC;
 
-use crate::{config::ClockMode, vdso::VdsoClock};
+use crate::config::ClockMode;
+
+/// Number of clock bases
+const VDSO_BASES: usize = 16;
+
+/// vDSO timestamp structure
+#[repr(C)]
+#[derive(Clone, Copy, Default)]
+pub struct VdsoTimestamp {
+    /// Seconds
+    pub sec: u64,
+    /// Nanoseconds
+    pub nsec: u64,
+}
+
+impl VdsoTimestamp {
+    /// Create a new zero timestamp
+    pub const fn new() -> Self {
+        Self { sec: 0, nsec: 0 }
+    }
+}
+
+#[repr(C)]
+#[derive(Default)]
+pub struct VdsoClock {
+    pub seq: AtomicU32,
+    pub clock_mode: i32,
+    pub cycle_last: AtomicU64,
+    pub mask: u64,
+    pub mult: u32,
+    pub shift: u32,
+    pub basetime: [VdsoTimestamp; VDSO_BASES],
+    pub _unused: u32,
+}
+
+impl VdsoClock {
+    /// Create a new VdsoClock with default values.
+    pub const fn new() -> Self {
+        Self {
+            seq: AtomicU32::new(0),
+            clock_mode: 1,
+            cycle_last: AtomicU64::new(0),
+            mask: u64::MAX,
+            mult: 0,
+            shift: 32,
+            basetime: [VdsoTimestamp::new(); VDSO_BASES],
+            _unused: 0,
+        }
+    }
+
+    pub fn write_seqcount_begin(&self) {
+        let seq = self.seq.load(Ordering::Relaxed);
+        self.seq.store(seq.wrapping_add(1), Ordering::Release);
+        core::sync::atomic::fence(Ordering::SeqCst);
+    }
+
+    pub fn write_seqcount_end(&self) {
+        core::sync::atomic::fence(Ordering::SeqCst);
+        let seq = self.seq.load(Ordering::Relaxed);
+        self.seq.store(seq.wrapping_add(1), Ordering::Release);
+    }
+}
 
 /// Update vDSO clock.
 pub fn update_vdso_clock(
diff --git a/src/vdso.rs b/src/vdso.rs
index ed0a05c..3b1081c 100644
--- a/src/vdso.rs
+++ b/src/vdso.rs
@@ -2,77 +2,13 @@
 extern crate alloc;
 extern crate log;
 use alloc::alloc::alloc_zeroed;
-use core::{
-    alloc::Layout,
-    sync::atomic::{AtomicU32, AtomicU64, Ordering},
-};
+use core::alloc::Layout;
 
 use axerrno::{AxError, AxResult};
 use axplat::{mem::virt_to_phys, time::monotonic_time_nanos};
 
 const PAGE_SIZE_4K: usize = 4096;
 
-/// Number of clock bases
-const VDSO_BASES: usize = 16;
-
-/// vDSO timestamp structure
-#[repr(C)]
-#[derive(Clone, Copy, Default)]
-pub struct VdsoTimestamp {
-    /// Seconds
-    pub sec: u64,
-    /// Nanoseconds
-    pub nsec: u64,
-}
-
-impl VdsoTimestamp {
-    /// Create a new zero timestamp
-    pub const fn new() -> Self {
-        Self { sec: 0, nsec: 0 }
-    }
-}
-
-#[repr(C)]
-#[derive(Default)]
-pub struct VdsoClock {
-    pub seq: AtomicU32,
-    pub clock_mode: i32,
-    pub cycle_last: AtomicU64,
-    pub mask: u64,
-    pub mult: u32,
-    pub shift: u32,
-    pub basetime: [VdsoTimestamp; VDSO_BASES],
-    pub _unused: u32,
-}
-
-impl VdsoClock {
-    /// Create a new VdsoClock with default values.
-    pub const fn new() -> Self {
-        Self {
-            seq: AtomicU32::new(0),
-            clock_mode: 1,
-            cycle_last: AtomicU64::new(0),
-            mask: u64::MAX,
-            mult: 0,
-            shift: 32,
-            basetime: [VdsoTimestamp::new(); VDSO_BASES],
-            _unused: 0,
-        }
-    }
-
-    pub(crate) fn write_seqcount_begin(&self) {
-        let seq = self.seq.load(Ordering::Relaxed);
-        self.seq.store(seq.wrapping_add(1), Ordering::Release);
-        core::sync::atomic::fence(Ordering::SeqCst);
-    }
-
-    pub(crate) fn write_seqcount_end(&self) {
-        core::sync::atomic::fence(Ordering::SeqCst);
-        let seq = self.seq.load(Ordering::Relaxed);
-        self.seq.store(seq.wrapping_add(1), Ordering::Release);
-    }
-}
-
 /// Global vDSO data instance
 #[unsafe(link_section = ".data")]
 pub static mut VDSO_DATA: crate::vdso_data::VdsoData = crate::vdso_data::VdsoData::new();
@@ -151,22 +87,6 @@ pub fn prepare_vdso_pages(vdso_kstart: usize, vdso_kend: usize) -> AxResult<Vdso
     }
 }
 
-#[cfg(target_arch = "aarch64")]
-pub fn enable_cntvct_access() {
-    log::info!("Enabling user-space access to timer counter registers...");
-    unsafe {
-        let mut cntkctl_el1: u64;
-        core::arch::asm!("mrs {}, CNTKCTL_EL1", out(reg) cntkctl_el1);
-
-        cntkctl_el1 |= 0x3;
-
-        core::arch::asm!("msr CNTKCTL_EL1, {}", in(reg) cntkctl_el1);
-        core::arch::asm!("isb");
-
-        log::info!("CNTKCTL_EL1 configured: {:#x}", cntkctl_el1);
-    }
-}
-
 /// Calculate ASLR-randomized vDSO user address
 pub fn calculate_vdso_aslr_addr(
     vdso_kstart: usize,
@@ -193,3 +113,19 @@ pub fn calculate_vdso_aslr_addr(
 
     (base_addr, vdso_addr)
 }
+
+#[cfg(target_arch = "aarch64")]
+pub fn enable_cntvct_access() {
+    log::info!("Enabling user-space access to timer counter registers...");
+    unsafe {
+        let mut cntkctl_el1: u64;
+        core::arch::asm!("mrs {}, CNTKCTL_EL1", out(reg) cntkctl_el1);
+
+        cntkctl_el1 |= 0x3;
+
+        core::arch::asm!("msr CNTKCTL_EL1, {}", in(reg) cntkctl_el1);
+        core::arch::asm!("isb");
+
+        log::info!("CNTKCTL_EL1 configured: {:#x}", cntkctl_el1);
+    }
+}
diff --git a/src/x86_64/vdso_data.rs b/src/x86_64/vdso_data.rs
index fa270ab..db53c77 100644
--- a/src/x86_64/vdso_data.rs
+++ b/src/x86_64/vdso_data.rs
@@ -3,10 +3,7 @@ use axplat::time::{
 };
 
 use super::config::ClockMode;
-use crate::{
-    update::{clocks_calc_mult_shift, update_vdso_clock},
-    vdso::VdsoClock,
-};
+use crate::update::{VdsoClock, clocks_calc_mult_shift, update_vdso_clock};
 
 #[repr(C)]
 #[repr(align(4096))]