diff --git a/designs/ci b/designs/ci
index 666807207..1656c0a7e 160000
--- a/designs/ci
+++ b/designs/ci
@@ -1 +1 @@
-Subproject commit 666807207ec46b9e12c278039d2d03ae098f7d45
+Subproject commit 1656c0a7e873b626148c8c232fbdef364208bb6e
diff --git a/docs/_static/digital_flow/broken_aspect_ratio.png b/docs/_static/digital_flow/broken_aspect_ratio.png
index eae51712e..fe3fbb32a 100644
Binary files a/docs/_static/digital_flow/broken_aspect_ratio.png and b/docs/_static/digital_flow/broken_aspect_ratio.png differ
diff --git a/docs/_static/digital_flow/final_def.png b/docs/_static/digital_flow/final_def.png
index 06c5dae1c..199795d6e 100644
Binary files a/docs/_static/digital_flow/final_def.png and b/docs/_static/digital_flow/final_def.png differ
diff --git a/docs/_static/digital_flow/final_gds.png b/docs/_static/digital_flow/final_gds.png
index 3d9974d35..05deba5d8 100644
Binary files a/docs/_static/digital_flow/final_gds.png and b/docs/_static/digital_flow/final_gds.png differ
diff --git a/docs/_static/digital_flow/floorplan_def_loaded.png b/docs/_static/digital_flow/floorplan_def_loaded.png
index b611498a3..4f9bf3dfe 100644
Binary files a/docs/_static/digital_flow/floorplan_def_loaded.png and b/docs/_static/digital_flow/floorplan_def_loaded.png differ
diff --git a/docs/_static/digital_flow/mem_1r1w_def.png b/docs/_static/digital_flow/mem_1r1w_def.png
index 37398e8fb..653ec397c 100644
Binary files a/docs/_static/digital_flow/mem_1r1w_def.png and b/docs/_static/digital_flow/mem_1r1w_def.png differ
diff --git a/docs/source/tutorials/digital_guide.md b/docs/source/tutorials/digital_guide.md
index ffe24b49e..8792dcaaf 100644
--- a/docs/source/tutorials/digital_guide.md
+++ b/docs/source/tutorials/digital_guide.md
@@ -109,22 +109,18 @@ Create the Verilog blackbox `./designs/regfile_2r1w/bb/mem_1r1w.bb.v`:
 
 Then, add `VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS`, and `EXTRA_GDS_FILES` to the `config.json` file within `regfile_2r1w`:
 
-```{note}
-For the sake of the tutorial, `FP_CORE_UTIL` is set to `60`.
-```
-
 ```json
 {
-"DESIGN_NAME": "regfile_2r1w",
-"VERILOG_FILES": "dir::src/*.v",
-"CLOCK_PORT": "clk",
-"CLOCK_PERIOD": 10.0,
-"FP_PDN_MULTILAYER": true,
-"FP_CORE_UTIL": 60,
-
-"EXTRA_LEFS":      "dir::../mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
-"EXTRA_GDS_FILES": "dir::../mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
-"VERILOG_FILES_BLACKBOX": "dir::bb/*.v"
+    "DESIGN_NAME": "regfile_2r1w",
+    "VERILOG_FILES": "dir::src/*.v",
+    "CLOCK_PORT": "clk",
+    "CLOCK_PERIOD": 10.0,
+    "FP_PDN_MULTILAYER": true,
+    "FP_CORE_UTIL": 60,
+
+    "EXTRA_LEFS":      "dir::../mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
+    "EXTRA_GDS_FILES": "dir::../mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
+    "VERILOG_FILES_BLACKBOX": "dir::bb/*.v"
 }
 ```
 
@@ -154,23 +150,22 @@ lane1 13 14 N
 ```
 
 This tells the flow to place `lane0` at location (15, 200) in microns with North orientation
-and `lane1` at location (13, 14) in microns with North orientation
+and `lane1` at location (13, 14) in microns with North orientation.
 
 Then change the JSON configuration to point to this file:
 
 ```json
 {
-"DESIGN_NAME": "regfile_2r1w",
-"VERILOG_FILES": "dir::src/*.v",
-"CLOCK_PORT": "clk",
-"CLOCK_PERIOD": 10.0,
-"FP_PDN_MULTILAYER": true,
-"FP_CORE_UTIL": 60,
-
-"EXTRA_LEFS":      "dir::../mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
-"EXTRA_GDS_FILES": "dir::../mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
-"VERILOG_FILES_BLACKBOX": "dir::bb/*.v"
-"MACRO_PLACEMENT_CFG": "dir::macro.cfg"
+    "DESIGN_NAME": "regfile_2r1w",
+    "VERILOG_FILES": "dir::src/*.v",
+    "CLOCK_PORT": "clk",
+    "CLOCK_PERIOD": 10.0,
+    "FP_PDN_MULTILAYER": true,
+
+    "EXTRA_LEFS":      "dir::../mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
+    "EXTRA_GDS_FILES": "dir::../mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
+    "VERILOG_FILES_BLACKBOX": "dir::bb/*.v"
+    "MACRO_PLACEMENT_CFG": "dir::macro.cfg"
 }
 ```
 
@@ -208,8 +203,7 @@ To debug this issue, open the OpenROAD GUI:
 $ python3 gui.py ./designs/regfile_2r1w/runs/full_guide_broken_aspect_ratio/
 ```
 
-```{figure}
-../../\_static/digital_flow/broken_aspect_ratio.png
+```{figure} ../../_static/digital_flow/broken_aspect_ratio.png
 ```
 
 As shown in the image. The instances overlap and the Flow was unable to create a PDN properly
@@ -227,7 +221,6 @@ The `config.json` file should look like this:
     "CLOCK_PORT": "clk",
     "CLOCK_PERIOD": 10.0,
     "FP_PDN_MULTILAYER": true,
-    "FP_CORE_UTIL": 60,
     "FP_ASPECT_RATIO": 2,
 
     "EXTRA_LEFS": "dir::../mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
@@ -255,7 +248,7 @@ $ ./flow.tcl -design regfile_2r1w -tag full_guide -overwrite
 Open the OpenROAD GUI to view the results of the flow.
 
 ```console
-$ python3 gui.py --viewer openroad ./designs/mem_1r1w/runs/full_guide/
+$ python3 gui.py --viewer openroad ./designs/regfile_2r1w/runs/full_guide/
 ```
 
 ```{figure} ../../_static/digital_flow/final_def.png