` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.
(Default: NONE)|
| `FP_CONTEXT_DEF` | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations.
(Default: NONE)|
| `FP_CONTEXT_LEF` | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations.
(Default: NONE)|
@@ -161,6 +161,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
| `PDN_CFG` | **Deprecated: Use `FP_PDN_CFG`**: Points to a PDN configuration file that describes how to construct the PDN in detail. |
| `FP_HORIZONTAL_HALO` | **Deprecated: Use `FP_PDN_HORIZONTAL_HALO`**: Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns.|
| `FP_PDN_VERTICAL_HALO` | **Deprecated: Use `FP_PDN_VERTICAL_HALO`**: Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. |
+| `DESIGN_IS_CORE` | **Deprecated as even macros can have a full-stack PDN if core rings are used: New variable is `FP_PDN_FULL_STACK`** Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro
(Default: `1`)|
| `FP_PDN_IRDROP` | **Removed: No point running it this early in the flow**: Enable calculation of power grid IR drop during PDN generation. |
### Deprecated I/O Layer variables
diff --git a/docs/source/tutorials/digital_guide.md b/docs/source/tutorials/digital_guide.md
index 6b2dc2761..36755b8cc 100644
--- a/docs/source/tutorials/digital_guide.md
+++ b/docs/source/tutorials/digital_guide.md
@@ -58,7 +58,7 @@ Modify the `config.json` to include following:
:language: json
```
-`DESIGN_IS_CORE` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
+`FP_PDN_FULL_STACK` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
`FP_PDN_CORE_RING` is set to `false` to disable a power ring around the macroblock.
@@ -136,7 +136,7 @@ Then add `VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS` and `EXTRA_GDS_FILES` to the `co
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
- "DESIGN_IS_CORE": true,
+ "FP_PDN_FULL_STACK": true,
"EXTRA_LEFS": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
"EXTRA_GDS_FILES": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
@@ -156,7 +156,7 @@ This is a [known issue documented here](https://github.com/The-OpenROAD-Project/
The PDN straps will be routed in opposite directions.
In locations where the two routings cross each other,
-VIAs connecting the layers are added. When `DESIGN_IS_CORE` is set to `true` then higher layers (met5 in sky130) are used.
+VIAs connecting the layers are added. When `FP_PDN_FULL_STACK` is set to `true` then higher layers (met5 in sky130) are used.
If it is set to `false` then VIAs will be missing and you will get LVS issues.
### Verilog files
@@ -493,7 +493,7 @@ Fanout Cap Slew Delay Time Description
### Demo: Debugging LVS issues due to PDN issues
-Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `DESIGN_IS_CORE` to `false`.
+Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `FP_PDN_FULL_STACK` to `false`.
```
{
@@ -501,7 +501,7 @@ Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `DESI
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
- "DESIGN_IS_CORE": false,
+ "FP_PDN_FULL_STACK": false,
"FP_ASPECT_RATIO": 2,
"EXTRA_LEFS": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
@@ -589,7 +589,7 @@ The submacros are by default logically connected to `VPWR/VGND` power domain.
As can be seen, the PDN is missing the power straps in layer `met5`.
Therefore the layout, does not have connections to the submacro, while the net is logically connected.
-This is expected as it was disabled by setting `DESIGN_IS_CORE` to `false` above.
+This is expected as it was disabled by setting `FP_PDN_FULL_STACK` to `false` above.
Of course, reverting the change fixes this issue.
:::{note}
diff --git a/docs/source/usage/advanced_power_grid_control.md b/docs/source/usage/advanced_power_grid_control.md
index 000fb3da0..da42aba9f 100644
--- a/docs/source/usage/advanced_power_grid_control.md
+++ b/docs/source/usage/advanced_power_grid_control.md
@@ -31,7 +31,7 @@ The first decision to make at the core level is the core ring. So first, you nee
```json
- "DESIGN_IS_CORE": true,
+ "FP_PDN_FULL_STACK": true,
"FP_PDN_CORE_RING": true,
"VDD_NETS": "vccd1 vccd2 vdda1 cdda2",
"GND_NETS": "vssd1 vssd2 vssa1 vssa2",
@@ -44,7 +44,7 @@ The first decision to make at the core level is the core ring. So first, you nee
|
```tcl
-set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_FULL_STACK) 1
set ::env(FP_PDN_CORE_RING) 1
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
@@ -198,7 +198,7 @@ To begin the configurations for your macro, you want to announce that the design
|
```json
- "DESIGN_IS_CORE": false,
+ "FP_PDN_FULL_STACK": false,
"FP_PDN_CORE_RING": false,
"RT_MAX_LAYER": "met4"
```
@@ -208,7 +208,7 @@ To begin the configurations for your macro, you want to announce that the design
|
```tcl
-set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_FULL_STACK) 0
set ::env(FP_PDN_CORE_RING) 0
set ::env(RT_MAX_LAYER) "met4"
```
diff --git a/docs/source/usage/chip_integration.md b/docs/source/usage/chip_integration.md
index 4963a9dc2..b664876a3 100644
--- a/docs/source/usage/chip_integration.md
+++ b/docs/source/usage/chip_integration.md
@@ -99,7 +99,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
|
```json
- "DESIGN_IS_CORE": true,
+ "FP_PDN_FULL_STACK": true,
"FP_PDN_CORE_RING": true
```
@@ -108,7 +108,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
|
```tcl
- set ::env(DESIGN_IS_CORE) 1
+ set ::env(FP_PDN_FULL_STACK) 1
set ::env(FP_PDN_CORE_RING) 1
```
|
diff --git a/docs/source/usage/hardening_macros.md b/docs/source/usage/hardening_macros.md
index 57574e931..b59b4014e 100644
--- a/docs/source/usage/hardening_macros.md
+++ b/docs/source/usage/hardening_macros.md
@@ -21,7 +21,7 @@ Click on any variable name listed in this document to get its usage information.
* [`VERILOG_FILES`](../reference/configuration.md#VERILOG_FILES)
* [`CLOCK_PORT`](../reference/configuration.md#CLOCK_PORT)
* [`CLOCK_PERIOD`](../reference/configuration.md#CLOCK_PERIOD)
-* [`DESIGN_IS_CORE`](../reference/configuration.md#DESIGN_IS_CORE) (You may leave it empty if true)
+* [`FP_PDN_FULL_STACK`](../reference/configuration.md#FP_PDN_FULL_STACK) (You may leave it empty if true)
So, for example:
@@ -44,7 +44,7 @@ set ::env(DESIGN_NAME) {spm}
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(CLOCK_PORT) {clk}
-set ::env(DESIGN_IS_CORE) {0}
+set ::env(FP_PDN_FULL_STACK) {0}
```
diff --git a/scripts/config/init.py b/scripts/config/init.py
index 3ef9583e6..9d3246d5a 100644
--- a/scripts/config/init.py
+++ b/scripts/config/init.py
@@ -72,7 +72,7 @@ def init_config(
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_PERIOD) "10.0"
- set ::env(DESIGN_IS_CORE) {{1}}
+ set ::env(FP_PDN_FULL_STACK) {{1}}
set tech_specific_config "$::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl"
if {{ [file exists $tech_specific_config] == 1 }} {{
@@ -93,7 +93,7 @@ def init_config(
"VERILOG_FILES": verilog_arg,
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
- "DESIGN_IS_CORE": True,
+ "FP_PDN_FULL_STACK": True,
},
indent=4,
sort_keys=False,
diff --git a/scripts/openroad/common/pdn_cfg.tcl b/scripts/openroad/common/pdn_cfg.tcl
index b93ba9fbb..5b3128b2d 100644
--- a/scripts/openroad/common/pdn_cfg.tcl
+++ b/scripts/openroad/common/pdn_cfg.tcl
@@ -43,25 +43,35 @@ foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
-secondary_power $secondary
-# Assesses whether the design is the core of the chip or not based on the
-# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
-if { $::env(DESIGN_IS_CORE) == 1 } {
- # Used if the design is the core of the chip
- define_pdn_grid \
- -name stdcell_grid \
- -starts_with POWER \
- -voltage_domain CORE \
- -pins "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+set pdn_grid_common_args [list]
+lappend pdn_grid_common_args -starts_with POWER
+if { $::env(FP_PDN_CORE_RING) } {
+ lappend pdn_grid_common_args -extend_to_core_ring
+}
- add_pdn_stripe \
- -grid stdcell_grid \
- -layer $::env(FP_PDN_VERTICAL_LAYER) \
- -width $::env(FP_PDN_VWIDTH) \
- -pitch $::env(FP_PDN_VPITCH) \
- -offset $::env(FP_PDN_VOFFSET) \
- -spacing $::env(FP_PDN_VSPACING) \
- -starts_with POWER -extend_to_core_ring
+set used_layer_list "$::env(FP_PDN_VERTICAL_LAYER)"
+
+if { $::env(FP_PDN_FULL_STACK) == 1 } {
+ set used_layer_list "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+}
+
+define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins "$used_layer_list"
+
+add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_VERTICAL_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -spacing $::env(FP_PDN_VSPACING) \
+ {*}$pdn_grid_common_args
+
+if { $::env(FP_PDN_FULL_STACK) == 1 } {
add_pdn_stripe \
-grid stdcell_grid \
-layer $::env(FP_PDN_HORIZONTAL_LAYER) \
@@ -69,26 +79,13 @@ if { $::env(DESIGN_IS_CORE) == 1 } {
-pitch $::env(FP_PDN_HPITCH) \
-offset $::env(FP_PDN_HOFFSET) \
-spacing $::env(FP_PDN_HSPACING) \
- -starts_with POWER -extend_to_core_ring
+ {*}$pdn_grid_common_args
+}
+if { [llength $used_layer_list] >= 2 } {
add_pdn_connect \
-grid stdcell_grid \
- -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
-} else {
- # Used if the design is a macro in the core
- define_pdn_grid \
- -name stdcell_grid \
- -starts_with POWER \
- -voltage_domain CORE \
- -pins $::env(FP_PDN_VERTICAL_LAYER)
-
- add_pdn_stripe \
- -grid stdcell_grid \
- -layer $::env(FP_PDN_VERTICAL_LAYER) \
- -width $::env(FP_PDN_VWIDTH) \
- -pitch $::env(FP_PDN_VPITCH) \
- -offset $::env(FP_PDN_VOFFSET) \
- -starts_with POWER
+ -layers "$used_layer_list"
}
# Adds the standard cell rails if enabled.
@@ -125,4 +122,4 @@ define_pdn_grid \
add_pdn_connect \
-grid macro \
- -layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
+ -layers "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
diff --git a/scripts/openroad/pdn.tcl b/scripts/openroad/pdn.tcl
index 7fe6e27c1..d4a62a0dc 100644
--- a/scripts/openroad/pdn.tcl
+++ b/scripts/openroad/pdn.tcl
@@ -16,6 +16,10 @@ source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
read
# load the grid definitions
+
+## For backwards compat
+set ::env(DESIGN_IS_CORE) $::env(FP_PDN_FULL_STACK)
+
if {[catch {source $::env(FP_PDN_CFG)} errmsg]} {
puts stderr $errmsg
exit 1
diff --git a/scripts/tcl_commands/all.tcl b/scripts/tcl_commands/all.tcl
index d83d732a2..351e5a6cf 100755
--- a/scripts/tcl_commands/all.tcl
+++ b/scripts/tcl_commands/all.tcl
@@ -400,6 +400,42 @@ proc load_overrides {args} {
}
}
+proc handle_config_var_deprecation {args} {
+ # DEPRECATED CONFIGS
+ ## PDK
+ handle_deprecated_pdk_config SYNTH_MAX_TRAN MAX_TRANSITION_CONSTRAINT
+ handle_deprecated_pdk_config SYNTH_MAX_FANOUT MAX_FANOUT_CONSTRAINT
+ handle_deprecated_pdk_config SYNTH_CAP_LOAD OUTPUT_CAP_LOAD
+ handle_deprecated_pdk_config WIRE_RC_LAYER DATA_WIRE_RC_LAYER
+ handle_deprecated_pdk_config WIRE_RC_LAYER CLOCK_WIRE_RC_LAYER
+
+ ## Flow
+ handle_diode_insertion_strategy
+
+ handle_deprecated_config SYNTH_TOP_LEVEL SYNTH_ELABORATE_ONLY 0
+
+ handle_deprecated_config VERILATOR_RELATIVE_INCLUDES LINTER_RELATIVE_INCLUDES 1
+
+ handle_deprecated_config FP_HORIZONTAL_HALO FP_PDN_HORIZONTAL_HALO 10
+ handle_deprecated_config FP_VERTICAL_HALO FP_PDN_VERTICAL_HALO $::env(FP_PDN_HORIZONTAL_HALO)
+
+ handle_deprecated_config LIB_RESIZER_OPT RSZ_LIB
+ handle_deprecated_config UNBUFFER_NETS RSZ_DONT_TOUCH_RX "$^"
+
+ handle_deprecated_config RCX_SDC_FILE SIGNOFF_SDC_FILE
+ handle_deprecated_config PRIMARY_SIGNOFF_TOOL PRIMARY_GDSII_STREAMOUT_TOOL "magic"
+
+ ### Checkers/Quitting
+ handle_deprecated_config QUIT_ON_VERILATOR_WARNINGS QUIT_ON_LINTER_WARNINGS 0
+ handle_deprecated_config QUIT_ON_VERILATOR_ERRORS QUIT_ON_LINTER_ERRORS 1
+
+ ### Flow Control
+ handle_deprecated_config RUN_VERILATOR RUN_LINTER 1
+
+ ### PDN
+ handle_deprecated_config DESIGN_IS_CORE FP_PDN_FULL_STACK 1
+}
+
proc prep {args} {
set ::env(timer_start) [clock seconds]
TIMER::timer_start
@@ -616,64 +652,6 @@ proc prep {args} {
set ::env(OPENLANE_VERBOSE) $arg_values(-verbose)
- # DEPRECATED CONFIGS
- ## PDK
- handle_deprecated_pdk_config SYNTH_MAX_TRAN MAX_TRANSITION_CONSTRAINT
- handle_deprecated_pdk_config SYNTH_MAX_FANOUT MAX_FANOUT_CONSTRAINT
- handle_deprecated_pdk_config SYNTH_CAP_LOAD OUTPUT_CAP_LOAD
- handle_deprecated_pdk_config WIRE_RC_LAYER DATA_WIRE_RC_LAYER
- handle_deprecated_pdk_config WIRE_RC_LAYER CLOCK_WIRE_RC_LAYER
-
- ## Flow
- handle_diode_insertion_strategy
-
- handle_deprecated_config SYNTH_TOP_LEVEL SYNTH_ELABORATE_ONLY
-
- handle_deprecated_config VERILATOR_RELATIVE_INCLUDES LINTER_RELATIVE_INCLUDES
-
- handle_deprecated_config FP_HORIZONTAL_HALO FP_PDN_HORIZONTAL_HALO
- handle_deprecated_config FP_VERTICAL_HALO FP_PDN_VERTICAL_HALO
-
- handle_deprecated_config LIB_RESIZER_OPT RSZ_LIB
- handle_deprecated_config UNBUFFER_NETS RSZ_DONT_TOUCH_RX
-
- handle_deprecated_config RCX_SDC_FILE SIGNOFF_SDC_FILE
- handle_deprecated_config PRIMARY_SIGNOFF_TOOL PRIMARY_GDSII_STREAMOUT_TOOL
-
- ### Checkers/Quitting
- handle_deprecated_config CHECK_ASSIGN_STATEMENTS QUIT_ON_ASSIGN_STATEMENTS
- handle_deprecated_config CHECK_UNMAPPED_CELLS QUIT_ON_UNMAPPED_CELLS
- handle_deprecated_config QUIT_ON_VERILATOR_WARNINGS QUIT_ON_LINTER_WARNINGS
- handle_deprecated_config QUIT_ON_VERILATOR_ERRORS QUIT_ON_LINTER_ERRORS
-
- ### Flow Control
- handle_deprecated_config CLOCK_TREE_SYNTH RUN_CTS
- handle_deprecated_config TAP_DECAP_INSERTION RUN_TAP_DECAP_INSERTION
- handle_deprecated_config RUN_ROUTING_DETAILED RUN_DRT
- handle_deprecated_config FILL_INSERTION RUN_FILL_INSERTION
- handle_deprecated_config RUN_VERILATOR RUN_LINTER
-
- ### PDN
- handle_deprecated_config FP_PDN_RAILS_LAYER FP_PDN_RAIL_LAYER
- handle_deprecated_config FP_PDN_UPPER_LAYER FP_PDN_HORIZONTAL_LAYER
- handle_deprecated_config FP_PDN_LOWER_LAYER FP_PDN_VERTICAL_LAYER
- handle_deprecated_config PDN_CFG FP_PDN_CFG
-
- ### GLB_RT -> GRT (Document using ‡)
- handle_deprecated_config GLB_RT_ALLOW_CONGESTION GRT_ALLOW_CONGESTION
- handle_deprecated_config GLB_RT_OVERFLOW_ITERS GRT_OVERFLOW_ITERS
- handle_deprecated_config GLB_RT_ANT_ITERS GRT_ANT_ITERS
- handle_deprecated_config GLB_RT_ESTIMATE_PARASITICS GRT_ESTIMATE_PARASITICS
- handle_deprecated_config GLB_RT_MAX_DIODE_INS_ITERS GRT_MAX_DIODE_INS_ITERS
- handle_deprecated_config GLB_RT_OBS GRT_OBS
- handle_deprecated_config GLB_RT_ADJUSTMENT GRT_ADJUSTMENT
- handle_deprecated_config GLB_RT_MACRO_EXTENSION GRT_MACRO_EXTENSION
- handle_deprecated_config GLB_RT_LAYER_ADJUSTMENTS GRT_LAYER_ADJUSTMENTS
-
- ### Spelling (No need to document)
- handle_deprecated_config CELL_PAD_EXECLUDE CELL_PAD_EXCLUDE
- handle_deprecated_config SYNTH_CLOCK_UNCERTAINITY SYNTH_CLOCK_UNCERTAINTY
-
#
############################
# Prep directories and files
@@ -706,6 +684,10 @@ proc prep {args} {
# file mkdir works like shell mkdir -p, i.e., its OK if it already exists
file mkdir $::env(RESULTS_DIR) $::env(TMP_DIR) $::env(LOGS_DIR) $::env(REPORTS_DIR)
+ # must be called after RUN_DIR is created so deprecation warnings are
+ # properly set to file
+ handle_config_var_deprecation
+
set run_subfolder_structure [list \
synthesis\
floorplan\
@@ -1248,7 +1230,7 @@ proc run_antenna_check {args} {
proc run_irdrop_report {args} {
if { ![info exists ::env(VSRC_LOC_FILES)] } {
- puts_info "Skipping IR-drop analysis-- VSRC_LOC_FILES was not given a value."
+ puts_warn "Skipping IR-drop analysis as VSRC_LOC_FILES was not given a value. If you are not integrating a top-level chip for manufacture, you can ignore this warning, otherwise, see the documentation for VSRC_LOC_FILES."
return
}
diff --git a/scripts/tcl_commands/floorplan.tcl b/scripts/tcl_commands/floorplan.tcl
index 71714f85a..519523882 100755
--- a/scripts/tcl_commands/floorplan.tcl
+++ b/scripts/tcl_commands/floorplan.tcl
@@ -88,7 +88,7 @@ proc init_floorplan {args} {
set ::env(FP_PDN_VPITCH) [lindex $adjusted_values 2]
set ::env(FP_PDN_HPITCH) [lindex $adjusted_values 3]
- puts_warn "Current core area is too small for the power grid settings chosen. The power grid will be scaled down."
+ puts_warn "Current core area is too small for the power grid settings chosen. The power grid was scaled down to an offset of 1/8 the core width and height and a pitch of 1/4 the core width and height."
}
}
diff --git a/scripts/utils/utils.tcl b/scripts/utils/utils.tcl
index c101610e6..5fe79e449 100755
--- a/scripts/utils/utils.tcl
+++ b/scripts/utils/utils.tcl
@@ -21,9 +21,9 @@ proc throw_error {} {
}
}
-proc handle_deprecated_config {old new} {
+proc handle_deprecated_config {old new {default ""}} {
if { [info exists ::env($old)] } {
- puts_warn "$old is now deprecated; use $new instead."
+ puts_warn "The variable name $old was renamed to $new\. Update your configuration file."
if { ! [info exists ::env($new)] } {
set ::env($new) $::env($old)
@@ -32,6 +32,10 @@ proc handle_deprecated_config {old new} {
puts_err "Conflicting values of $new and $old; please remove $old from your design configurations"
throw_error
}
+ } elseif { [info exists ::env($new)] } {
+ # That's fine
+ } elseif { $default != "" } {
+ set ::env($new) $default
}
}