From f691c8c0712ca6c6645e3fd548985b3cbcf08c78 Mon Sep 17 00:00:00 2001 From: Darryl Miles Date: Wed, 22 Nov 2023 13:45:53 +0000 Subject: [PATCH] yosys/synth.tcl: migrate to newer supported drw & drf commands (#2051) + Add tt05-i2c-bert (https://github.com/dlmiles/tt05-i2c-bert) to CI ~ Replace instances of ABC command `rewrite` with `drw -l` with `SYNTH_ABC_LEGACY_REWRITE` being set to `1` restoring the older functionality (`0` by default) ~ Replace instances of ABC command `refactor` with `drf -l` with `SYNTH_ABC_LEGACY_REFACTOR` being set to `1` restoring the older functionality (`0` by default) ~ Added `delete t:\$print` to `synth.tcl` to fix designs such as PPU with synthesized prints (as in https://github.com/efabless/openlane2/pull/189) --------- Co-authored-by: Mohamed Gaber --- .github/test_sets/test_sets.yml | 1 + configuration/synthesis.tcl | 3 +- designs/ci | 2 +- docs/source/reference/configuration.md | 3 +- .../sky130A/sky130_fd_sc_hd.csv | 3 +- scripts/yosys/synth.tcl | 34 ++++++++++++------- 6 files changed, 30 insertions(+), 16 deletions(-) diff --git a/.github/test_sets/test_sets.yml b/.github/test_sets/test_sets.yml index 6a4349cd9..e82d97e13 100644 --- a/.github/test_sets/test_sets.yml +++ b/.github/test_sets/test_sets.yml @@ -14,6 +14,7 @@ - ./designs/ci/gcd - ./designs/ci/caravel_upw - ./designs/ci/aes_user_project_wrapper + - ./designs/ci/tt05_i2c_bert - scl: sky130A/sky130_fd_sc_hd name: extended_test_set designs: diff --git a/configuration/synthesis.tcl b/configuration/synthesis.tcl index 32aa0476b..68f80694a 100755 --- a/configuration/synthesis.tcl +++ b/configuration/synthesis.tcl @@ -32,4 +32,5 @@ set ::env(SYNTH_ELABORATE_ONLY) 0 set ::env(SYNTH_FLAT_TOP) 0 set ::env(IO_PCT) 0.2 set ::env(SYNTH_EXTRA_MAPPING_FILE) "" - +set ::env(SYNTH_ABC_LEGACY_REFACTOR) 0 +set ::env(SYNTH_ABC_LEGACY_REWRITE) 0 diff --git a/designs/ci b/designs/ci index 97024ecb0..6fdb36a4a 160000 --- a/designs/ci +++ b/designs/ci @@ -1 +1 @@ -Subproject commit 97024ecb02c85db0259a5925ccd94b2a37bd8925 +Subproject commit 6fdb36a4afec4061b7011cf96944c0e6ce90c564 diff --git a/docs/source/reference/configuration.md b/docs/source/reference/configuration.md index 16919544a..01831df23 100644 --- a/docs/source/reference/configuration.md +++ b/docs/source/reference/configuration.md @@ -88,6 +88,8 @@ files you may be depending on, including headers, in `VERILOG_FILES`. | `SYNTH_READ_BLACKBOX_LIB` | A flag that enable reading the full(untrimmed) liberty file as a blackbox for synthesis. Please note that this is not used in technology mapping. This should only be used when trying to preserve gate instances in the rtl of the design.
Enabled = 1, Disabled = 0
(Default: `0`)| | `SYNTH_NO_FLAT` | A flag that disables flattening the hierarchy during synthesis, only flattening it after synthesis, mapping and optimizations.
Enabled = 1, Disabled = 0
(Default: `0`)| | `SYNTH_SHARE_RESOURCES` | A flag that enables yosys to reduce the number of cells by determining shareable resources and merging them.
Enabled = 1, Disabled = 0
(Default: `1`)| +| `SYNTH_ABC_LEGACY_REFACTOR` | Replaces the ABC command `drf -l` with `refactor` which matches older versions of OpenLane but is more unstable.
Enabled = 1, Disabled = 0
(Default: `0`) | +| `SYNTH_ABC_LEGACY_REWRITE` | Replaces the ABC command `drw -l` with `rewrite` which matches older versions of OpenLane but is more unstable.
Enabled = 1, Disabled = 0
(Default: `0`) | | `SYNTH_ADDER_TYPE` | Adder type to which the $add and $sub operators are mapped to.
Possible values are `YOSYS/FA/RCA/CSA`; where `YOSYS` refers to using Yosys internal adder definition, `FA` refers to full-adder structure, `RCA` refers to ripple carry adder structure, and `CSA` refers to carry select adder.
(Default: `YOSYS`)| | `SYNTH_EXTRA_MAPPING_FILE` | Points to extra techmap file for yosys that runs right after yosys `synth` before generic techmap.
(Default: `""`)| | `SYNTH_PARAMETERS` | Whitespace-delimited key value pairs to be `chparam`ed in Yosys. In the format `key1=value1 key2=value2`
(Default: None) | @@ -100,7 +102,6 @@ files you may be depending on, including headers, in `VERILOG_FILES`. | `SYNTH_TOP_LEVEL` | **Deprecated: Use `SYNTH_ELABORATE_ONLY`**: "Elaborate" the design only without attempting any logic mapping. Useful when dealing with structural Verilog netlists. | | `SYNTH_MAX_FANOUT` | **Deprecated: Use the PDK's `MAX_FANOUT_CONSTRAINT` value**: The max load that the output ports can drive. | | `SYNTH_MAX_TRAN` | **Deprecated: Use the PDK's `MAX_TRANSITION_CONSTRAINT` value**: The max transition time (slew) from high to low or low to high on cell inputs in ns. If unset, the library's default maximum transition time will be used. | - ## Static Timing Analysis (STA) | Variable | Description | diff --git a/regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv b/regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv index 9b3487e06..5233711f0 100644 --- a/regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv +++ b/regression_results/benchmark_results/sky130A/sky130_fd_sc_hd.csv @@ -3,7 +3,7 @@ design,design_name,config,flow_status,total_runtime,routed_runtime,DIEAREA_mm^2, ./designs/ci/PPU,PPU,run_config,flow completed,0h13m54s0ms,0h6m31s0ms,0.733195271625,18162.9649226804,20.49,25.0,2077.11,12649,0,0,0,0,0,0,0,72,65,0,-1,-1,914385,99369,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,640716798.0,0.0,36.57,38.6,7.09,12.5,0.17,5308,8922,576,4178,0,0,0,7674,52,8,53,75,466,113,21,3014,2918,2927,21,43486,10075,708,14399,13317,81985,703299.52,-1,-1,-1,-1,-1,-1,-1,-1,-1,9.05,18.0,1,20,153.18,153.6,0.3,1,0.25,0,sky130_fd_sc_hd,8,AREA 0 ./designs/ci/aes,aes,run_config,flow completed,0h31m18s0ms,0h16m12s0ms,1.5614589344249998,13835.778529747611,15.32,19.0,3995.48,20122,0,0,0,0,0,0,0,75,70,0,-1,-1,1906160,185725,-26.68,-45.4,-1,0.0,0.0,-77174.7,-129120.43,-1,0.0,0.0,1421600626.0,0.0,34.34,35.77,9.34,16.27,0.15,21918,39764,1376,19222,0,0,0,24130,219,143,88,346,8958,2179,691,1414,3037,3024,24,98615,21612,1617,28611,21604,172059,1519006.8479999998,-1,-1,-1,-1,-1,-1,-1,-1,-1,2.91,25.0,1,15,153.18,153.6,0.3,1,0.25,0,sky130_fd_sc_hd,8,AREA 0 ./designs/ci/aes_core,aes_core,run_config,flow completed,0h38m54s0ms,0h17m41s0ms,0.8670581510250001,24200.22229788714,25.56,36.0,3197.34,19301,0,0,0,0,0,0,0,10,10,0,-1,-1,1995431,218062,-20.25,-33.48,-1,0.0,0.0,-47470.02,-78096.02,-1,0.0,0.0,1553775824.0,0.0,54.68,59.5,32.22,50.36,2.92,21779,38579,1339,18139,0,0,0,23475,303,11,176,343,8963,2035,834,1198,2865,2604,25,50614,11830,22472,31654,20983,137553,835761.5616,-1,-1,-1,-1,-1,-1,-1,-1,-1,2.9899999999999998,22.0,1,25,153.18,153.6,0.3,1,0.3,1,sky130_fd_sc_hd,6,AREA 0 -./designs/ci/aes_user_project_wrapper,aes_user_project_wrapper,run_config,flow completed,0h9m22s0ms,0h1m31s0ms,0.19458281444582815,10.2784,0.09729140722291407,-1,-1,601.34,1,0,0,0,0,0,0,0,0,0,0,-1,-1,13333,216,0.0,-1,-1,-1,0.0,0.0,-1,-1,-1,0.0,-1,0.0,0.02,0.01,0.08,0.0,-1,19,637,19,637,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,1,1,10173980.1536,-1,-1,-1,0.0279,0.0325,1.77e-07,-1,-1,-1,5.079999999999998,25.0,40.0,25,1,50,81.6,81.6,0.3,0,0.6,0,sky130_fd_sc_hd,10,AREA 0 +./designs/ci/aes_user_project_wrapper,aes_user_project_wrapper,run_config,flow completed,0h9m31s0ms,0h0m56s0ms,10.2784,0.09729140722291407,-1,6.44782,514.45,1,0,0,0,0,0,0,0,0,0,0,-1,-1,13328,214,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,-1,0.0,0.02,0.01,0.08,0.0,-1,19,637,19,637,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,1,1,10173980.1536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,25,1,50,81.6,81.6,0.3,0,10,0.6,0,sky130_fd_sc_hd,AREA 0 ./designs/ci/blabla,blabla,run_config,flow completed,0h37m16s0ms,0h9m39s0ms,1.44,9359.027777777776,8.74,14.0,2878.57,11696,0,0,0,0,0,0,0,118,111,0,-1,-1,2328661,115651,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,2126108228.0,0.0,46.54,44.08,12.63,29.41,0.0,10117,21673,226,11782,0,0,0,12090,654,5,575,813,507,2076,906,1434,2004,1100,50,92567,20010,5285,28187,13477,159526,1399932.6464000002,-1,-1,-1,-1,-1,-1,-1,-1,-1,8.7,65.0,1,11,153.18,153.6,0.3,1,0.16,0,sky130_fd_sc_hd,10,AREA 0 ./designs/ci/caravel_upw,user_project_wrapper,run_config,flow completed,0h6m23s0ms,0h1m58s0ms,-1.0,-1.0,-1.0,11.0,755.36,2,0,0,0,0,0,0,0,0,0,0,-1,-1,1803198,5162,0.0,-1.0,-1,0.0,0.0,0.0,-1.0,-1,0.0,0.0,-1.0,0.0,3.56,7.04,0.84,2.89,-1.0,19,637,19,637,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,2,2,10173980.1536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1.0,10.0,1,50,180.0,180.0,0.3,1,0.55,0,sky130_fd_sc_hd,10,AREA 0 ./designs/ci/gcd,gcd,run_config,flow completed,0h1m34s0ms,0h1m4s0ms,0.0784251948,4743.373617989407,5.25,7.0,562.96,313,0,0,0,0,0,0,0,0,0,0,-1,-1,19936,2738,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,17027897.0,0.0,7.09,7.52,1.69,3.98,0.0,347,1106,140,899,0,0,0,293,6,3,2,6,41,25,6,32,70,52,11,4823,970,14,1092,372,7271,67039.29599999999,-1,-1,-1,-1,-1,-1,-1,-1,-1,3.48,10.0,1,50,27.2,27.14,0.3,1,0.55,0,sky130_fd_sc_hd,10,DELAY 4 @@ -13,6 +13,7 @@ design,design_name,config,flow_status,total_runtime,routed_runtime,DIEAREA_mm^2, ./designs/ci/s44,lut_s44,run_config,flow completed,0h1m10s0ms,0h0m50s0ms,0.043010922,3510.7361799870278,4.15,7.0,531.9,121,0,0,0,0,0,0,0,0,0,0,-1,-1,8322,1048,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,7096590.0,0.0,5.64,7.12,0.11,0.0,0.0,49,140,20,111,0,0,0,62,0,0,0,0,0,0,0,30,48,33,6,2648,504,8,603,151,3914,36347.35999999999,-1,-1,-1,-1,-1,-1,-1,-1,-1,2.039999999999999,30.0,1,4,153.18,153.6,0.3,1,0.5,0,sky130_fd_sc_hd,10,AREA 0 ./designs/ci/salsa20,salsa20,run_config,flow completed,0h30m6s0ms,0h16m6s0ms,1.2177938729000002,20405.752199116683,20.45,25.0,3386.25,22965,0,0,0,0,0,0,0,171,157,0,-1,-1,2147090,196715,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1822593739.0,0.0,45.76,45.64,21.0,34.13,5.38,12472,21091,252,8871,0,0,0,17446,488,5,592,642,1679,2296,741,1288,3720,3710,51,74068,16842,2694,26166,24850,144620,1179677.6544,-1,-1,-1,-1,-1,-1,-1,-1,-1,4.57,38.0,1,20,153.18,153.6,0.3,1,0.25,0,sky130_fd_sc_hd,6,AREA 0 spm,spm,run_config,flow completed,0h1m10s0ms,0h0m52s0ms,0.0114652544999999,30090.91512098576,47.85,45.0,521.98,301,0,0,0,0,0,0,0,0,0,0,-1,-1,10140,2035,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,8701631.0,0.0,21.21,38.83,1.2,4.41,0.0,354,415,196,257,0,0,0,253,32,64,31,31,1,63,31,0,97,128,4,539,105,0,227,345,1216,8134.051200000001,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.5899999999999999,10.0,1,45,22.44,22.655,0.3,1,0.5,0,sky130_fd_sc_hd,10,AREA 0 +./designs/ci/tt05_i2c_bert,tt_um_dlmiles_tt05_i2c_bert,run_config,flow completed,0h2m1s0ms,0h1m38s0ms,0.0187755072,56563.052528349275,58.15,72.5264,563.35,976,0,0,0,0,0,0,0,0,0,0,-1,-1,27417,7556,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,20810646.0,0.0,52.59,39.65,14.91,5.06,-1,1497,1999,250,727,0,0,0,1445,45,10,49,60,354,57,13,128,156,123,16,802,246,3,449,1062,2562,17274.0672,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,15,1,50,26.520,40.710,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0 ./designs/ci/usb,usb,run_config,flow completed,0h1m54s0ms,0h1m22s0ms,0.0327793473,31239.182117576816,41.81,41.0,574.89,929,0,0,0,0,0,0,0,1,1,0,-1,-1,29931,7401,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,20708179.0,0.0,30.4,30.25,0.89,0.63,0.0,830,1083,140,374,0,0,0,927,27,24,33,34,200,47,8,79,214,193,8,1629,372,3,771,1024,3799,26875.776,-1,-1,-1,-1,-1,-1,-1,-1,-1,2.16,15.0,1,40,40.8,41.165,0.3,1,0.45,0,sky130_fd_sc_hd,6,DELAY 0 ./designs/ci/usb_cdc_core,usb_cdc_core,run_config,flow completed,0h2m33s0ms,0h1m40s0ms,0.0754478433,27250.613272334587,31.22,32.0,644.57,1953,0,0,0,0,0,0,0,2,2,0,-1,-1,67456,14023,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,51889425.0,0.0,29.21,29.69,1.5,1.46,0.0,2046,2771,265,943,0,0,0,2150,100,47,109,89,681,130,41,60,325,605,14,4182,912,15,1617,2056,8782,65980.78080000001,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.91,15.6,1,30,153.18,153.6,0.3,1,0.32,0,sky130_fd_sc_hd,6,AREA 0 ./designs/ci/wbqspiflash,wbqspiflash,run_config,flow completed,0h4m42s0ms,0h3m26s0ms,0.0673063305,41749.4161266153,41.39,53.0,724.34,2671,0,0,0,0,0,0,0,0,0,0,-1,-1,141899,25584,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,105133202.0,0.0,54.18,62.0,18.33,28.05,0.0,2873,3297,70,485,0,0,0,3100,55,1,142,148,796,79,6,744,340,288,18,3605,819,1255,2411,2810,10900,58796.3904,-1,-1,-1,-1,-1,-1,-1,-1,-1,3.63,20.0,1,40,153.18,153.6,0.3,1,0.45,1,sky130_fd_sc_hd,4,DELAY 0 diff --git a/scripts/yosys/synth.tcl b/scripts/yosys/synth.tcl index cca92a6ec..2a1c9ca4c 100755 --- a/scripts/yosys/synth.tcl +++ b/scripts/yosys/synth.tcl @@ -98,11 +98,20 @@ close $outfile set abc_rs_K "resub,-K," set abc_rs "resub" set abc_rsz "resub,-z" -set abc_rw_K "rewrite,-K," -set abc_rw "rewrite" -set abc_rwz "rewrite,-z" -set abc_rf "refactor" -set abc_rfz "refactor,-z" +set abc_rf "drf,-l" +set abc_rfz "drf,-l,-z" +set abc_rw "drw,-l" +set abc_rwz "drw,-l,-z" +set abc_rw_K "drw,-l,-K" +if { $::env(SYNTH_ABC_LEGACY_REFACTOR) == "1" } { + set abc_rf "refactor" + set abc_rfz "refactor,-z" +} +if { $::env(SYNTH_ABC_LEGACY_REWRITE) == "1" } { + set abc_rw "rewrite" + set abc_rwz "rewrite,-z" + set abc_rw_K "rewrite,-K" +} set abc_b "balance" set abc_resyn2 "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}" @@ -143,22 +152,22 @@ if {$buffering==1} { set delay_scripts [list \ - "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ + "+read_constr,${sdc_file};fx;mfs;strash;${abc_rf};${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ \ - "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ + "+read_constr,${sdc_file};fx;mfs;strash;${abc_rf};${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ \ - "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ + "+read_constr,${sdc_file};fx;mfs;strash;${abc_rf};${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ \ - "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ + "+read_constr,${sdc_file};fx;mfs;strash;${abc_rf};${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ "+read_constr,${sdc_file};&get -n;&st;&dch;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;&get -n;&st;&syn2;&if -g -K 6;&synch2;&nf;&put;buffer -c -N ${max_FO};topo;stime -c;upsize -c;dnsize -c;;stime,-p;print_stats -m" \ ] set area_scripts [list \ - "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ + "+read_constr,${sdc_file};fx;mfs;strash;${abc_rf};${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ \ - "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ + "+read_constr,${sdc_file};fx;mfs;strash;${abc_rf};${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ \ - "+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ + "+read_constr,${sdc_file};fx;mfs;strash;${abc_rf};${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};&get,-n;&st;&dch;&nf;&put;${abc_fine_tune};stime,-p;print_stats -m" \ "+read_constr,${sdc_file};strash;dch;map -B 0.9;topo;stime -c;buffer -c -N ${max_FO};upsize -c;dnsize -c;stime,-p;print_stats -m" \ ] @@ -297,6 +306,7 @@ opt -fast hierarchy -check stat check +delete t:\$print if { $::env(SYNTH_EXTRA_MAPPING_FILE) ne "" } { if { [file exists $::env(SYNTH_EXTRA_MAPPING_FILE)] } {