diff --git a/src/dft/src/architect/ScanArchitect.cpp b/src/dft/src/architect/ScanArchitect.cpp
index 9931d013761..b86e1b1f61a 100644
--- a/src/dft/src/architect/ScanArchitect.cpp
+++ b/src/dft/src/architect/ScanArchitect.cpp
@@ -63,7 +63,7 @@ bool CompareScanCells(const std::unique_ptr<ScanCell>& lhs,
 
 void SortScanCells(std::vector<std::unique_ptr<ScanCell>>& scan_cells)
 {
-  std::sort(scan_cells.begin(), scan_cells.end(), CompareScanCells);
+  std::stable_sort(scan_cells.begin(), scan_cells.end(), CompareScanCells);
 }
 
 }  // namespace
@@ -72,6 +72,21 @@ ScanCellsBucket::ScanCellsBucket(utl::Logger* logger) : logger_(logger)
 {
 }
 
+namespace {
+void showBuckets(
+    utl::Logger* logger,
+    const std::unordered_map<size_t, std::vector<std::unique_ptr<ScanCell>>>&
+        buckets)
+{
+  for (auto& bucket : buckets) {
+    debugPrint(logger, utl::DFT, "buckets", 2, "Bucket {}", bucket.first);
+    for (auto& scan_cell : bucket.second) {
+      debugPrint(logger, utl::DFT, "buckets", 2, "\t{}", scan_cell->getName());
+    }
+  }
+}
+};  // namespace
+
 void ScanCellsBucket::init(const ScanArchitectConfig& config,
                            std::vector<std::unique_ptr<ScanCell>>& scan_cells)
 {
@@ -85,6 +100,8 @@ void ScanCellsBucket::init(const ScanArchitectConfig& config,
   for (auto& [hash_domain, scan_cells] : buckets_) {
     SortScanCells(scan_cells);
   }
+
+  showBuckets(logger_, buckets_);
 }
 
 std::unordered_map<size_t, uint64_t>
diff --git a/src/dft/src/clock_domain/ClockDomain.cpp b/src/dft/src/clock_domain/ClockDomain.cpp
index 17ccff4489d..da7e3888758 100644
--- a/src/dft/src/clock_domain/ClockDomain.cpp
+++ b/src/dft/src/clock_domain/ClockDomain.cpp
@@ -32,6 +32,9 @@
 
 #include "ClockDomain.hh"
 
+#include <boost/container_hash/hash.hpp>
+#include <cstdint>
+
 namespace dft {
 
 ClockDomain::ClockDomain(const std::string& clock_name, ClockEdge clock_edge)
@@ -63,10 +66,27 @@ std::string_view ClockDomain::getClockEdgeName() const
   return "Unknown clock edge";
 }
 
+namespace {
+size_t FNV1a(const uint8_t* data, size_t length)
+{
+  size_t hash = 0xcbf29ce484222325;
+  for (size_t i = 0; i < length; i += 1) {
+    hash ^= data[i];
+    hash *= 0x00000100000001b3;
+  }
+  return hash;
+}
+};  // namespace
+
 size_t ClockDomain::getClockDomainId() const
 {
-  return std::hash<std::string_view>{}(clock_name_)
-         ^ std::hash<ClockEdge>{}(clock_edge_);
+  size_t seed = 0;
+  seed = boost::hash_detail::hash_mix(
+      seed + 0x9e3779b9
+      + FNV1a((uint8_t*) clock_name_.data(), clock_name_.length()));
+  seed = boost::hash_detail::hash_mix(
+      seed + 0x9e3779b9 + FNV1a((uint8_t*) &clock_edge_, sizeof(ClockEdge)));
+  return seed;
 }
 
 }  // namespace dft
diff --git a/src/dft/src/clock_domain/ClockDomainHash.cpp b/src/dft/src/clock_domain/ClockDomainHash.cpp
index 159308942bf..2343b0bcc17 100644
--- a/src/dft/src/clock_domain/ClockDomainHash.cpp
+++ b/src/dft/src/clock_domain/ClockDomainHash.cpp
@@ -42,8 +42,7 @@ std::function<size_t(const ClockDomain&)> GetClockDomainHashFn(
     // For NoMix, every clock domain is different
     case ScanArchitectConfig::ClockMixing::NoMix:
       return [](const ClockDomain& clock_domain) {
-        return std::hash<std::string_view>{}(clock_domain.getClockName())
-               ^ std::hash<ClockEdge>{}(clock_domain.getClockEdge());
+        return clock_domain.getClockDomainId();
       };
     case ScanArchitectConfig::ClockMixing::ClockMix:
       return [](const ClockDomain& clock_domain) { return 1; };
diff --git a/src/dft/test/scan_architect_clock_mix_sky130.ok b/src/dft/test/scan_architect_clock_mix_sky130.ok
index d1eabfbb5a1..bdf94e3a8ae 100644
--- a/src/dft/test/scan_architect_clock_mix_sky130.ok
+++ b/src/dft/test/scan_architect_clock_mix_sky130.ok
@@ -9,43 +9,43 @@ Clock domain: Clock Mix
 Scan chain 'chain_0' has 3 cells (3 bits)
 
   ff8_clk2_falling (clock2, falling)
-  ff2_clk2_falling
   ff6_clk2_falling
+  ff4_clk2_falling
 
 Scan chain 'chain_1' has 3 cells (3 bits)
 
-  ff10_clk2_falling (clock2, falling)
-  ff4_clk2_falling
-  ff10_clk2_rising (clock2, rising)
+  ff2_clk2_falling (clock2, falling)
+  ff10_clk2_falling
+  ff8_clk2_rising (clock2, rising)
 
 Scan chain 'chain_2' has 3 cells (3 bits)
 
-  ff8_clk2_rising (clock2, rising)
+  ff6_clk2_rising (clock2, rising)
+  ff4_clk2_rising
   ff2_clk2_rising
-  ff6_clk2_rising
 
 Scan chain 'chain_3' has 3 cells (3 bits)
 
-  ff1_clk1_falling (clock1, falling)
-  ff3_clk1_falling
-  ff4_clk2_rising (clock2, rising)
+  ff9_clk1_falling (clock1, falling)
+  ff7_clk1_falling
+  ff10_clk2_rising (clock2, rising)
 
 Scan chain 'chain_4' has 3 cells (3 bits)
 
-  ff7_clk1_falling (clock1, falling)
-  ff9_clk1_falling
-  ff5_clk1_falling
+  ff5_clk1_falling (clock1, falling)
+  ff3_clk1_falling
+  ff1_clk1_falling
 
 Scan chain 'chain_5' has 3 cells (3 bits)
 
-  ff3_clk1_rising (clock1, rising)
-  ff5_clk1_rising
+  ff9_clk1_rising (clock1, rising)
   ff7_clk1_rising
+  ff5_clk1_rising
 
 Scan chain 'chain_6' has 2 cells (2 bits)
 
-  ff1_clk1_rising (clock1, rising)
-  ff9_clk1_rising
+  ff3_clk1_rising (clock1, rising)
+  ff1_clk1_rising
 
 
 No differences found.
diff --git a/src/dft/test/scan_architect_clock_mix_sky130.vok b/src/dft/test/scan_architect_clock_mix_sky130.vok
index 84827e7deb2..b7168cd0ea5 100644
--- a/src/dft/test/scan_architect_clock_mix_sky130.vok
+++ b/src/dft/test/scan_architect_clock_mix_sky130.vok
@@ -66,91 +66,91 @@ module scan_architect (clock1,
 
  sky130_fd_sc_hd__sdfsbp_1 ff10_clk2_rising (.D(port1),
     .Q(output10),
-    .SCD(output14),
+    .SCD(output17),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock2));
  sky130_fd_sc_hd__sdfbbn_1 ff1_clk1_falling (.D(port1),
     .Q(output11),
-    .SCD(scan_in_3),
+    .SCD(output13),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock1));
  sky130_fd_sc_hd__sdfsbp_1 ff1_clk1_rising (.D(port1),
     .Q(output1),
-    .SCD(scan_in_6),
+    .SCD(output3),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock1));
  sky130_fd_sc_hd__sdfbbn_1 ff2_clk2_falling (.D(port1),
     .Q(output12),
-    .SCD(output18),
+    .SCD(scan_in_1),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock2));
  sky130_fd_sc_hd__sdfsbp_1 ff2_clk2_rising (.D(port1),
     .Q(output2),
-    .SCD(output8),
+    .SCD(output4),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock2));
  sky130_fd_sc_hd__sdfbbn_1 ff3_clk1_falling (.D(port1),
     .Q(output13),
-    .SCD(output11),
+    .SCD(output15),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock1));
  sky130_fd_sc_hd__sdfsbp_1 ff3_clk1_rising (.D(port1),
     .Q(output3),
-    .SCD(scan_in_5),
+    .SCD(scan_in_6),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock1));
  sky130_fd_sc_hd__sdfbbn_1 ff4_clk2_falling (.D(port1),
     .Q(output14),
-    .SCD(output20),
+    .SCD(output16),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock2));
  sky130_fd_sc_hd__sdfsbp_1 ff4_clk2_rising (.D(port1),
     .Q(output4),
-    .SCD(output13),
+    .SCD(output6),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock2));
  sky130_fd_sc_hd__sdfbbn_1 ff5_clk1_falling (.D(port1),
     .Q(output15),
-    .SCD(output19),
+    .SCD(scan_in_4),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock1));
  sky130_fd_sc_hd__sdfsbp_1 ff5_clk1_rising (.D(port1),
     .Q(output5),
-    .SCD(output3),
+    .SCD(output7),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock1));
  sky130_fd_sc_hd__sdfbbn_1 ff6_clk2_falling (.D(port1),
     .Q(output16),
-    .SCD(output12),
+    .SCD(output18),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock2));
  sky130_fd_sc_hd__sdfsbp_1 ff6_clk2_rising (.D(port1),
     .Q(output6),
-    .SCD(output2),
+    .SCD(scan_in_2),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock2));
  sky130_fd_sc_hd__sdfbbn_1 ff7_clk1_falling (.D(port1),
     .Q(output17),
-    .SCD(scan_in_4),
+    .SCD(output19),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock1));
  sky130_fd_sc_hd__sdfsbp_1 ff7_clk1_rising (.D(port1),
     .Q(output7),
-    .SCD(output5),
+    .SCD(output9),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock1));
@@ -162,25 +162,25 @@ module scan_architect (clock1,
     .CLK_N(clock2));
  sky130_fd_sc_hd__sdfsbp_1 ff8_clk2_rising (.D(port1),
     .Q(output8),
-    .SCD(scan_in_2),
+    .SCD(output20),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock2));
  sky130_fd_sc_hd__sdfbbn_1 ff9_clk1_falling (.D(port1),
     .Q(output19),
-    .SCD(output17),
+    .SCD(scan_in_3),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock1));
  sky130_fd_sc_hd__sdfsbp_1 ff9_clk1_rising (.D(port1),
     .Q(output9),
-    .SCD(output1),
+    .SCD(scan_in_5),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock1));
  sky130_fd_sc_hd__sdfbbn_1 ff10_clk2_falling (.D(port1),
     .Q(output20),
-    .SCD(scan_in_1),
+    .SCD(output12),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock2));
diff --git a/src/dft/test/scan_architect_no_mix_sky130.ok b/src/dft/test/scan_architect_no_mix_sky130.ok
index 1a2672cb141..7a3e0e96a93 100644
--- a/src/dft/test/scan_architect_no_mix_sky130.ok
+++ b/src/dft/test/scan_architect_no_mix_sky130.ok
@@ -16,13 +16,21 @@ Scan chain 'chain_0' has 5 cells (5 bits)
 
 Scan chain 'chain_1' has 5 cells (5 bits)
 
+  ff8_clk2_rising (clock2, rising)
+  ff6_clk2_rising
+  ff4_clk2_rising
+  ff2_clk2_rising
+  ff10_clk2_rising
+
+Scan chain 'chain_2' has 5 cells (5 bits)
+
   ff9_clk1_rising (clock1, rising)
   ff7_clk1_rising
   ff5_clk1_rising
   ff3_clk1_rising
   ff1_clk1_rising
 
-Scan chain 'chain_2' has 5 cells (5 bits)
+Scan chain 'chain_3' has 5 cells (5 bits)
 
   ff8_clk2_falling (clock2, falling)
   ff6_clk2_falling
@@ -30,14 +38,6 @@ Scan chain 'chain_2' has 5 cells (5 bits)
   ff2_clk2_falling
   ff10_clk2_falling
 
-Scan chain 'chain_3' has 5 cells (5 bits)
-
-  ff8_clk2_rising (clock2, rising)
-  ff6_clk2_rising
-  ff4_clk2_rising
-  ff2_clk2_rising
-  ff10_clk2_rising
-
 
 No differences found.
 No differences found.
diff --git a/src/dft/test/scan_architect_no_mix_sky130.vok b/src/dft/test/scan_architect_no_mix_sky130.vok
index f8098892812..5b198292bed 100644
--- a/src/dft/test/scan_architect_no_mix_sky130.vok
+++ b/src/dft/test/scan_architect_no_mix_sky130.vok
@@ -150,13 +150,13 @@ module scan_architect (clock1,
     .CLK(clock1));
  sky130_fd_sc_hd__sdfbbn_1 ff8_clk2_falling (.D(port1),
     .Q(output18),
-    .SCD(scan_in_2),
+    .SCD(scan_in_3),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK_N(clock2));
  sky130_fd_sc_hd__sdfsbp_1 ff8_clk2_rising (.D(port1),
     .Q(output8),
-    .SCD(scan_in_3),
+    .SCD(scan_in_1),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock2));
@@ -168,7 +168,7 @@ module scan_architect (clock1,
     .CLK_N(clock1));
  sky130_fd_sc_hd__sdfsbp_1 ff9_clk1_rising (.D(port1),
     .Q(output9),
-    .SCD(scan_in_1),
+    .SCD(scan_in_2),
     .SCE(scan_enable_0),
     .SET_B(set_b),
     .CLK(clock1));
diff --git a/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.ok b/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.ok
index fe8774ca0c9..a43f550c5f7 100644
--- a/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.ok
+++ b/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.ok
@@ -6,41 +6,44 @@ Number of chains: 2
 Clock domain: No Mix
 ***************************
 
-Scan chain 'chain_0' has 64 cells (64 bits)
+Scan chain 'chain_0' has 32 cells (32 bits)
 
-  bank2/_287_ (clk2, rising)
-  bank2/_286_
-  bank2/_285_
-  bank2/_284_
-  bank2/_283_
-  bank2/_282_
-  bank2/_281_
-  bank2/_280_
-  bank2/_279_
-  bank2/_278_
-  bank2/_277_
-  bank2/_276_
-  bank2/_275_
-  bank2/_274_
-  bank2/_273_
-  bank2/_256_
-  bank2/_271_
-  bank2/_270_
-  bank2/_269_
-  bank2/_268_
-  bank2/_267_
-  bank2/_266_
-  bank2/_265_
-  bank2/_264_
-  bank2/_263_
-  bank2/_262_
-  bank2/_261_
-  bank2/_260_
-  bank2/_259_
-  bank2/_258_
-  bank2/_257_
-  bank2/_272_
-  bank2/_319_
+  bank1/_159_ (clk1, rising)
+  bank1/_158_
+  bank1/_157_
+  bank1/_156_
+  bank1/_155_
+  bank1/_154_
+  bank1/_153_
+  bank1/_152_
+  bank1/_151_
+  bank1/_150_
+  bank1/_149_
+  bank1/_148_
+  bank1/_147_
+  bank1/_146_
+  bank1/_145_
+  bank1/_144_
+  bank1/_143_
+  bank1/_142_
+  bank1/_141_
+  bank1/_140_
+  bank1/_139_
+  bank1/_138_
+  bank1/_137_
+  bank1/_136_
+  bank1/_135_
+  bank1/_134_
+  bank1/_133_
+  bank1/_132_
+  bank1/_131_
+  bank1/_130_
+  bank1/_129_
+  bank1/_128_
+
+Scan chain 'chain_1' has 64 cells (64 bits)
+
+  bank2/_319_ (clk2, rising)
   bank2/_318_
   bank2/_317_
   bank2/_316_
@@ -55,7 +58,7 @@ Scan chain 'chain_0' has 64 cells (64 bits)
   bank2/_307_
   bank2/_306_
   bank2/_305_
-  bank2/_288_
+  bank2/_304_
   bank2/_303_
   bank2/_302_
   bank2/_301_
@@ -71,42 +74,39 @@ Scan chain 'chain_0' has 64 cells (64 bits)
   bank2/_291_
   bank2/_290_
   bank2/_289_
-  bank2/_304_
-
-Scan chain 'chain_1' has 32 cells (32 bits)
-
-  bank1/_129_ (clk1, rising)
-  bank1/_130_
-  bank1/_131_
-  bank1/_132_
-  bank1/_133_
-  bank1/_134_
-  bank1/_135_
-  bank1/_136_
-  bank1/_137_
-  bank1/_138_
-  bank1/_139_
-  bank1/_140_
-  bank1/_141_
-  bank1/_142_
-  bank1/_143_
-  bank1/_128_
-  bank1/_145_
-  bank1/_146_
-  bank1/_147_
-  bank1/_148_
-  bank1/_149_
-  bank1/_150_
-  bank1/_151_
-  bank1/_152_
-  bank1/_153_
-  bank1/_154_
-  bank1/_155_
-  bank1/_156_
-  bank1/_157_
-  bank1/_158_
-  bank1/_159_
-  bank1/_144_
+  bank2/_288_
+  bank2/_287_
+  bank2/_286_
+  bank2/_285_
+  bank2/_284_
+  bank2/_283_
+  bank2/_282_
+  bank2/_281_
+  bank2/_280_
+  bank2/_279_
+  bank2/_278_
+  bank2/_277_
+  bank2/_276_
+  bank2/_275_
+  bank2/_274_
+  bank2/_273_
+  bank2/_272_
+  bank2/_271_
+  bank2/_270_
+  bank2/_269_
+  bank2/_268_
+  bank2/_267_
+  bank2/_266_
+  bank2/_265_
+  bank2/_264_
+  bank2/_263_
+  bank2/_262_
+  bank2/_261_
+  bank2/_260_
+  bank2/_259_
+  bank2/_258_
+  bank2/_257_
+  bank2/_256_
 
 
 No differences found.
diff --git a/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.vok b/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.vok
index 6b05bc54579..c23991bf22a 100644
--- a/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.vok
+++ b/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.vok
@@ -409,193 +409,193 @@ module top (clk1,
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_129_  (.D(\bank1/_033_ ),
     .Q(outputs_32[1]),
     .RESET_B(\bank1/_001_ ),
-    .SCD(scan_in_1),
+    .SCD(outputs_32[2]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_130_  (.D(\bank1/_034_ ),
     .Q(outputs_32[2]),
     .RESET_B(\bank1/_002_ ),
-    .SCD(outputs_32[1]),
+    .SCD(outputs_32[3]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_131_  (.D(\bank1/_035_ ),
     .Q(outputs_32[3]),
     .RESET_B(\bank1/_003_ ),
-    .SCD(outputs_32[2]),
+    .SCD(outputs_32[4]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_132_  (.D(\bank1/_036_ ),
     .Q(outputs_32[4]),
     .RESET_B(\bank1/_004_ ),
-    .SCD(outputs_32[3]),
+    .SCD(outputs_32[5]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_133_  (.D(\bank1/_037_ ),
     .Q(outputs_32[5]),
     .RESET_B(\bank1/_005_ ),
-    .SCD(outputs_32[4]),
+    .SCD(outputs_32[6]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_134_  (.D(\bank1/_038_ ),
     .Q(outputs_32[6]),
     .RESET_B(\bank1/_006_ ),
-    .SCD(outputs_32[5]),
+    .SCD(outputs_32[7]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_135_  (.D(\bank1/_039_ ),
     .Q(outputs_32[7]),
     .RESET_B(\bank1/_007_ ),
-    .SCD(outputs_32[6]),
+    .SCD(outputs_32[8]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_136_  (.D(\bank1/_040_ ),
     .Q(outputs_32[8]),
     .RESET_B(\bank1/_008_ ),
-    .SCD(outputs_32[7]),
+    .SCD(outputs_32[9]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_137_  (.D(\bank1/_041_ ),
     .Q(outputs_32[9]),
     .RESET_B(\bank1/_009_ ),
-    .SCD(outputs_32[8]),
+    .SCD(outputs_32[10]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_138_  (.D(\bank1/_042_ ),
     .Q(outputs_32[10]),
     .RESET_B(\bank1/_010_ ),
-    .SCD(outputs_32[9]),
+    .SCD(outputs_32[11]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_139_  (.D(\bank1/_043_ ),
     .Q(outputs_32[11]),
     .RESET_B(\bank1/_011_ ),
-    .SCD(outputs_32[10]),
+    .SCD(outputs_32[12]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_140_  (.D(\bank1/_044_ ),
     .Q(outputs_32[12]),
     .RESET_B(\bank1/_012_ ),
-    .SCD(outputs_32[11]),
+    .SCD(outputs_32[13]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_141_  (.D(\bank1/_045_ ),
     .Q(outputs_32[13]),
     .RESET_B(\bank1/_013_ ),
-    .SCD(outputs_32[12]),
+    .SCD(outputs_32[14]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_142_  (.D(\bank1/_046_ ),
     .Q(outputs_32[14]),
     .RESET_B(\bank1/_014_ ),
-    .SCD(outputs_32[13]),
+    .SCD(outputs_32[15]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_143_  (.D(\bank1/_047_ ),
     .Q(outputs_32[15]),
     .RESET_B(\bank1/_015_ ),
-    .SCD(outputs_32[14]),
+    .SCD(outputs_32[16]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_144_  (.D(\bank1/_048_ ),
     .Q(outputs_32[16]),
     .RESET_B(\bank1/_016_ ),
-    .SCD(outputs_32[31]),
+    .SCD(outputs_32[17]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_145_  (.D(\bank1/_049_ ),
     .Q(outputs_32[17]),
     .RESET_B(\bank1/_017_ ),
-    .SCD(outputs_32[0]),
+    .SCD(outputs_32[18]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_146_  (.D(\bank1/_050_ ),
     .Q(outputs_32[18]),
     .RESET_B(\bank1/_018_ ),
-    .SCD(outputs_32[17]),
+    .SCD(outputs_32[19]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_147_  (.D(\bank1/_051_ ),
     .Q(outputs_32[19]),
     .RESET_B(\bank1/_019_ ),
-    .SCD(outputs_32[18]),
+    .SCD(outputs_32[20]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_148_  (.D(\bank1/_052_ ),
     .Q(outputs_32[20]),
     .RESET_B(\bank1/_020_ ),
-    .SCD(outputs_32[19]),
+    .SCD(outputs_32[21]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_149_  (.D(\bank1/_053_ ),
     .Q(outputs_32[21]),
     .RESET_B(\bank1/_021_ ),
-    .SCD(outputs_32[20]),
+    .SCD(outputs_32[22]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_150_  (.D(\bank1/_054_ ),
     .Q(outputs_32[22]),
     .RESET_B(\bank1/_022_ ),
-    .SCD(outputs_32[21]),
+    .SCD(outputs_32[23]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_151_  (.D(\bank1/_055_ ),
     .Q(outputs_32[23]),
     .RESET_B(\bank1/_023_ ),
-    .SCD(outputs_32[22]),
+    .SCD(outputs_32[24]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_152_  (.D(\bank1/_056_ ),
     .Q(outputs_32[24]),
     .RESET_B(\bank1/_024_ ),
-    .SCD(outputs_32[23]),
+    .SCD(outputs_32[25]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_153_  (.D(\bank1/_057_ ),
     .Q(outputs_32[25]),
     .RESET_B(\bank1/_025_ ),
-    .SCD(outputs_32[24]),
+    .SCD(outputs_32[26]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_154_  (.D(\bank1/_058_ ),
     .Q(outputs_32[26]),
     .RESET_B(\bank1/_026_ ),
-    .SCD(outputs_32[25]),
+    .SCD(outputs_32[27]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_155_  (.D(\bank1/_059_ ),
     .Q(outputs_32[27]),
     .RESET_B(\bank1/_027_ ),
-    .SCD(outputs_32[26]),
+    .SCD(outputs_32[28]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_156_  (.D(\bank1/_060_ ),
     .Q(outputs_32[28]),
     .RESET_B(\bank1/_028_ ),
-    .SCD(outputs_32[27]),
+    .SCD(outputs_32[29]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_157_  (.D(\bank1/_061_ ),
     .Q(outputs_32[29]),
     .RESET_B(\bank1/_029_ ),
-    .SCD(outputs_32[28]),
+    .SCD(outputs_32[30]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_158_  (.D(\bank1/_062_ ),
     .Q(outputs_32[30]),
     .RESET_B(\bank1/_030_ ),
-    .SCD(outputs_32[29]),
+    .SCD(outputs_32[31]),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_159_  (.D(\bank1/_063_ ),
     .Q(outputs_32[31]),
     .RESET_B(\bank1/_031_ ),
-    .SCD(outputs_32[30]),
+    .SCD(scan_in_0),
     .SCE(scan_enable_0),
     .CLK(clk1));
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_256_  (.D(\bank2/_064_ ),
     .Q(outputs_64[11]),
     .RESET_B(\bank2/_000_ ),
-    .SCD(outputs_64[28]),
+    .SCD(outputs_64[12]),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__clkinv_1 \bank2/_128_  (.A(reset),
@@ -1069,13 +1069,13 @@ module top (clk1,
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_271_  (.D(\bank2/_079_ ),
     .Q(outputs_64[26]),
     .RESET_B(\bank2/_015_ ),
-    .SCD(outputs_64[11]),
+    .SCD(outputs_64[27]),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_272_  (.D(\bank2/_080_ ),
     .Q(outputs_64[27]),
     .RESET_B(\bank2/_016_ ),
-    .SCD(outputs_64[12]),
+    .SCD(outputs_64[28]),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_273_  (.D(\bank2/_081_ ),
@@ -1165,13 +1165,13 @@ module top (clk1,
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_287_  (.D(\bank2/_095_ ),
     .Q(outputs_64[42]),
     .RESET_B(\bank2/_031_ ),
-    .SCD(scan_in_0),
+    .SCD(outputs_64[43]),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_288_  (.D(\bank2/_096_ ),
     .Q(outputs_64[43]),
     .RESET_B(\bank2/_032_ ),
-    .SCD(outputs_64[60]),
+    .SCD(outputs_64[44]),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_289_  (.D(\bank2/_097_ ),
@@ -1261,13 +1261,13 @@ module top (clk1,
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_303_  (.D(\bank2/_111_ ),
     .Q(outputs_64[58]),
     .RESET_B(\bank2/_047_ ),
-    .SCD(outputs_64[43]),
+    .SCD(outputs_64[59]),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_304_  (.D(\bank2/_112_ ),
     .Q(outputs_64[59]),
     .RESET_B(\bank2/_048_ ),
-    .SCD(outputs_64[44]),
+    .SCD(outputs_64[60]),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_305_  (.D(\bank2/_113_ ),
@@ -1357,13 +1357,13 @@ module top (clk1,
  sky130_fd_sc_hd__sdfrbp_1 \bank2/_319_  (.D(\bank2/_127_ ),
     .Q(outputs_64[10]),
     .RESET_B(\bank2/_063_ ),
-    .SCD(outputs_64[27]),
+    .SCD(scan_in_1),
     .SCE(scan_enable_0),
     .CLK(clk2));
  sky130_fd_sc_hd__sdfrbp_1 \bank1/_128_  (.D(\bank1/_032_ ),
     .Q(outputs_32[0]),
     .RESET_B(\bank1/_000_ ),
-    .SCD(outputs_32[15]),
+    .SCD(outputs_32[1]),
     .SCE(scan_enable_0),
     .CLK(clk1));
 endmodule