Merge pull request #8433 from titan73/master

odb: Replace CDL <> (normal and escaped) to [] to match master term name when exporting CDL file.

Author: maliberty

src/odb/src/cdl/cdl.cpp

@@ -129,6 +129,9 @@ readMasters(utl::Logger* logger, dbBlock* block, const char* fileName)
           }
           mterms = &mtermMap[master];
         } else {
+          // Replace CDL <> (normal and escaped) to []
+          token = std::regex_replace(token, std::regex(R"(\\?<)"), "[");
+          token = std::regex_replace(token, std::regex(R"(\\?>)"), "]");
           dbMTerm* mterm = master->findMTerm(token.c_str());
           if (!mterm) {
             logger->warn(utl::ODB,

src/odb/test/BUILD

@@ -195,6 +195,7 @@ COMPULSORY_TESTS = [
     "smash_vias",
     "transform",
     "wire_encoder",
+    "write_cdl",
     "write_def58",
     "write_def58_gzip",
     "write_lef_and_def",
@@ -344,6 +345,9 @@ filegroup(
             "replace_hier_mod4": [
                 "gcd_abstract_lef.lefok",
             ],
+            "write_cdl": [
+                "write_cdl_escaped.cdl",
+            ],
         }.get(
             test_name,
             [],

src/odb/test/CMakeLists.txt

@@ -53,6 +53,7 @@ or_integration_tests(
     smash_vias
     transform
     wire_encoder
+    write_cdl
     write_def58
     write_def58_gzip
     write_lef_and_def

src/odb/test/write_cdl.cdl

@@ -0,0 +1,27 @@
+*.BIPOLAR
+*.RESI = 2000
+*.RESVAL
+*.CAPVAL
+*.DIOPERI
+*.DIOAREA
+*.EQUATION
+*.SCALE METER
+*.MEGA
+.PARAM
+*.EXPAND_ON_M_FACTOR
+
+.SUBCKT BUFFER A Z inh_gnd inh_vdd
+*.PININFO A:I Z:O inh_gnd:B inh_vdd:B
+MM0   netx A inh_vdd inh_vdd P250 W=1e-6 L=1e-6 M=1 ngcon=1 nfing=1 srcefirst=1
+MM1   Z netx inh_vdd inh_vdd P250 W=1e-6 L=1e-6 M=1 ngcon=1 nfing=1 srcefirst=1
+MMN1  netx A inh_gnd inh_gnd N250 W=1u   L=1u   M=1 ngcon=1 nfing=1 srcefirst=1
+MMN10 Z netx inh_gnd inh_gnd N250 W=1u   L=1u   M=1 ngcon=1 nfing=1 srcefirst=1
+.ENDS
+
+.SUBCKT MACRO_CELL IN_REG<0> IN_REG<1> OUT_REG<0> OUT_REG<1> VDD GND
+*.PININFO IN_REG<0>:I IN_REG<1>:I
+*.PININFO OUT_REG<0>:O OUT_REG<1>:O
+*.PININFO VDD:B GND:B
+BUFFER IN_REG<0> OUT_REG<0> VDD GND / buffer0
+BUFFER IN_REG<1> OUT_REG<1> VDD GND / buffer1
+.ENDS

src/odb/test/write_cdl.cdlok

@@ -0,0 +1,8 @@
+* CDL Netlist generated by OpenROAD
+
+*.BUSDELIMITER [
+
+.SUBCKT top in_reg[0] in_reg[1] out_reg[0] out_reg[1]
+Xi_macro in_reg[0] in_reg[1] out_reg[0] out_reg[1] _unconnected_0
++ _unconnected_1 MACRO_CELL
+.ENDS top

src/odb/test/write_cdl.lef

@@ -0,0 +1,82 @@
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+UNITS
+	DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+USEMINSPACING OBS OFF ;
+
+PROPERTYDEFINITIONS
+LAYER LEF58_TYPE STRING ;
+LAYER LEF58_SPACING STRING ;
+LAYER LEF58_WIDTH STRING ;
+LAYER LEF58_AREA STRING ;
+LAYER LEF58_MINENCLOSEDAREA STRING ;
+END PROPERTYDEFINITIONS
+
+LAYER metal1
+	TYPE ROUTING ;
+	DIRECTION HORIZONTAL ;
+	PITCH 1 ;
+	WIDTH 1 ;
+END metal1
+
+MACRO MACRO_CELL
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 10 BY 10 ;
+  SYMMETRY X Y R90 ;
+  PIN VDD
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER metal1 ;
+        RECT 0 5 0 5 ;
+    END
+  END VDD
+  PIN GND
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER metal1 ;
+        RECT 0 5 0 5 ;
+    END
+  END GND
+  PIN IN_REG[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER metal1 ;
+        RECT 0 5 0 5 ;
+    END
+  END IN_REG[0]
+  PIN IN_REG[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER metal1 ;
+        RECT 0 5 0 5 ;
+    END
+  END IN_REG[1]
+  PIN OUT_REG[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER metal1 ;
+        RECT 0 5 0 5 ;
+    END
+  END OUT_REG[0]
+  PIN OUT_REG[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER metal1 ;
+        RECT 0 5 0 5 ;
+    END
+  END OUT_REG[1]
+END MACRO_CELL
+
+END LIBRARY

src/odb/test/write_cdl.lib

@@ -0,0 +1,58 @@
+ library(MACRO_CELL){
+
+  input_threshold_pct_fall : 60;
+  input_threshold_pct_rise : 40;
+  output_threshold_pct_fall : 60;
+  output_threshold_pct_rise : 40;
+  slew_lower_threshold_pct_fall : 10;
+  slew_lower_threshold_pct_rise : 10;
+  slew_upper_threshold_pct_fall : 90;
+  slew_upper_threshold_pct_rise : 90;
+
+  type(bus_1_0){
+   base_type : array;
+   bit_from : 1;
+   bit_to : 0;
+   bit_width : 2;
+   data_type : bit;
+   downto : true;
+  }
+
+  cell(MACRO_CELL){
+   is_macro_cell : true;
+   pg_pin(GND){
+    pg_type : primary_ground;
+   }
+   pg_pin(VDD){
+    pg_type : primary_power;
+   }
+   bus(IN_REG){
+    bus_type : bus_1_0;
+    direction : input;
+    pin(IN_REG[0]){
+     direction : input;
+     related_ground_pin : GNDD;
+     related_power_pin : VDDD;
+    }
+    pin(IN_REG[1]){
+     direction : input;
+     related_ground_pin : GNDD;
+     related_power_pin : VDDD;
+    }
+   }
+   bus(OUT_REG){
+    bus_type : bus_1_0;
+    direction : output;
+    pin(OUT_REG[0]){
+     direction : output;
+     related_ground_pin : GNDD;
+     related_power_pin : VDDD;
+    }
+    pin(OUT_REG[1]){
+     direction : output;
+     related_ground_pin : GNDD;
+     related_power_pin : VDDD;
+    }
+   }
+  }
+ }

src/odb/test/write_cdl.ok

@@ -0,0 +1,5 @@
+[INFO ODB-0227] LEF file: write_cdl.lef, created 1 layers, 1 library cells
+[WARNING ODB-0284] Master BUFFER not found.
+[WARNING ODB-0284] Master BUFFER not found.
+No differences found.
+No differences found.

src/odb/test/write_cdl.tcl

@@ -0,0 +1,18 @@
+source "helpers.tcl"
+
+read_lef write_cdl.lef
+read_liberty write_cdl.lib
+
+read_verilog write_cdl.v
+
+link_design top
+
+set cdl_file [make_result_file write_cdl_out.cdl]
+write_cdl -masters {write_cdl.cdl} $cdl_file
+
+set cdl_escaped_file [make_result_file write_cdl_escaped_out.cdl]
+write_cdl -masters {write_cdl_escaped.cdl} $cdl_escaped_file
+
+diff_files write_cdl.cdlok $cdl_file
+
+diff_files write_cdl.cdlok $cdl_escaped_file

src/odb/test/write_cdl.v

@@ -0,0 +1,8 @@
+module top ( in_reg, out_reg );
+    output [1:0] in_reg;
+    output [1:0] out_reg;
+    MACRO_CELL i_macro (
+        .IN_REG(in_reg),
+        .OUT_REG(out_reg)
+  );
+endmodule