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There is a problem in this design that I'll fix. You can also look at mock-array which doesn't have this issue. |
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I'm running the aes-block design (platform=asap7) to get some experience with the hierarchical flow in Openroad. I'm running the design as-is in the latest version of Openroad right out of the box, without any modifications. For some reason the macro power pins are unconnected upon completion of the flow. In the attached screenshot you can see that I've highlighted (in yellow) the VDD network in the u0/u3 macro instance. Notice that the top-level nets aren't highlighted, implying that they're not connected (additionally, the top-level stripes don't even overlap the macro). So the top-level build didn't connect the top-level PDN to the VDD/VSS pins on the macro. How do I address this?
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