Troubles with triton route with new technology #6779

pars97 · 2025-02-26T21:32:58Z

pars97
Feb 26, 2025

Hi,

I'm trying to understand what went wrong while creating a new technology.
The purpose of that technology is to bring up the electronics potential to a Silicon photonics platform, hence I need to design new cells, new vias, new track sizes since the tech has different rules.

To test my comprehension of the flow and everything that comes behind it, I made a simple new design, an 2 inputs nand gate.

I've sucessfully used the gf180mcu technology to compile and have a .gds output of such design which is pretty simple.

Where I don't undersstand what went wrong is when I try to use my own platform.

First thing firsts, I am using a WSL Ubuntu machine, with a locally compiled OpenROAD-flow-scripts and OpenRoad gui.

My platform is called 'amf' and has its own folder with everything in it : I am able to get up to step 5.1 and open-up the DB with OpenROAD gui.

Sadly, it fails at step 5.2 with errors message I do not understand.

==========================================================================
global route report_design_area
--------------------------------------------------------------------------
Design area 5506 u^2 19% utilization.
[INFO FLW-0007] clock core_clock period 10.000000
[INFO FLW-0008] Clock core_clock period 4.433
[INFO FLW-0009] Clock core_clock slack 5.334
[WARNING STA-0450] virtual clock core_clock can not be propagated.
[INFO FLW-0011] Path endpoint path count 1
Elapsed time: 0:00.90[h:]min:sec. CPU time: user 0.84 sys 0.14 (109%). Peak memory: 506496KB.
Running detail_route.tcl, stage 5_2_route
Signal 11 received
Stack trace:
 0# 0x0000563030AF0DF3 in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 1# 0x00007F37FA180330 in /lib/x86_64-linux-gnu/libc.so.6
 2# odb::dbTrackGrid::getTechLayer() in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 3# odb::dbTrackGrid::getAverageTrackSpacing(int&, int&, int&) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 4# grt::GlobalRouter::initGrid(int) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 5# grt::GlobalRouter::initCoreGrid(int) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 6# grt::GlobalRouter::initGridAndNets() in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 7# 0x0000563032F550B8 in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 8# grt::GlobalRouter::haveRoutes() in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 9# 0x0000563031316EF4 in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
10# TclNRRunCallbacks in /lib/x86_64-linux-gnu/libtcl8.6.so
11# 0x00007F37FEA786BC in /lib/x86_64-linux-gnu/libtcl8.6.so
12# Tcl_EvalEx in /lib/x86_64-linux-gnu/libtcl8.6.so
13# Tcl_Eval in /lib/x86_64-linux-gnu/libtcl8.6.so
14# sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
15# 0x0000563030AF053F in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
16# Tcl_MainEx in /lib/x86_64-linux-gnu/libtcl8.6.so
17# main in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
18# 0x00007F37FA1651CA in /lib/x86_64-linux-gnu/libc.so.6
19# __libc_start_main in /lib/x86_64-linux-gnu/libc.so.6
20# _start in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
Command terminated by signal 11
Elapsed time: 0:01.53[h:]min:sec. CPU time: user 0.59 sys 0.07 (43%). Peak memory: 137556KB.
make[1]: *** [Makefile:764: do-5_2_route] Error 139
make: *** [Makefile:762: results/amf/nand2_1/base/5_2_route.odb] Error 2

I checked other discussions that mentionned RAM usage, I do not think it is the issue since my design is only 4 gates with 2 inputs and 1 output.

How could I go to debug the issue mentionned above?

If you need additionnal info, feel free to comment.

Thanks

Answered by pars97

Mar 3, 2025

I was reading this discussion here :#4165

I discovered that leaving a third metal layer that doesnt really exists in the LEF definition (with the via to access it) makes it that the routing is going more smoothly and the error is no more.

It does seem that the router is not able to take only to layer as an input but is able to route on only 2 layers.

View full answer

maliberty · 2025-02-26T23:24:37Z

maliberty
Feb 26, 2025
Maintainer

Do you have routing layers defined with tracks successfully generated? You can open the gui at an earlier step (eg make gui_floorplan) and turn on the tracks to see if you see them for each layer.

2 replies

pars97 Feb 27, 2025
Author

I can see tracks and the cells LEF definitions out of the step 5.1 :

In this tech, I only have 2 layers of metal. On the image, we see the metal 1 definition of cells with the VDD/VSS tracks.

The routing is supposed to be done at MT1 and MT2 levels.

VERSION 5.7 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;

UNITS
    DATABASE MICRONS 1000  ;
    CAPACITANCE PICOFARADS 1 ;
    CURRENT MILLIAMPS 1 ;
    RESISTANCE OHMS 1 ;
END UNITS

SITE AMF_SITE
  SYMMETRY X Y ;
  CLASS core ;
  SIZE 3.3 BY 30.9 ;
END AMF_SITE

PROPERTYDEFINITIONS
  LAYER LEF58_EOLENCLOSURE STRING ;
  LAYER LEF58_TYPE STRING ;
END PROPERTYDEFINITIONS

MANUFACTURINGGRID 0.0050 ;
CLEARANCEMEASURE EUCLIDEAN ;
USEMINSPACING OBS ON ;

LAYER MT1
    TYPE ROUTING ;
    DIRECTION HORIZONTAL ;

    PITCH 1 ;
    OFFSET 0.0 ;  

    MINWIDTH 0.230 ;                   # Mn.1  (n=1)
    WIDTH 0.230 ;                      # Mn.1  (n=1)
    SPACING 0.230  ;                   # Mn.2a (n=1)
    SPACING 0.300 RANGE 10.005 999.00 ; # Mn.2b
    AREA 0.1444 ;                      # Mn.3

    THICKNESS 0.54 ;
    ANTENNAMODEL OXIDE1 ;
    ANTENNASIDEAREARATIO 400 ;

    DCCURRENTDENSITY AVERAGE 0.67 ;
    ACCURRENTDENSITY AVERAGE 1.00 ;

    CAPACITANCE CPERSQDIST 0.0000394 ;
    RESISTANCE RPERSQ 0.090000 ;

    MINIMUMDENSITY 30.0 ;
    DENSITYCHECKWINDOW 200.0 200.0 ;
    DENSITYCHECKSTEP 100.0 ;

END MT1


LAYER Via1
  TYPE CUT ;
  SPACING 0.26 ;
  WIDTH   0.26 ;

  ENCLOSURE BELOW 0.00 0.06 ;
  ENCLOSURE ABOVE 0.01 0.06 ;
  PROPERTY LEF58_EOLENCLOSURE "
  	EOLENCLOSURE 0.34 0.06 ;" ; 

  ARRAYSPACING CUTSPACING 0.36 ARRAYCUTS 4 SPACING 0.36 ; # Vn.2b

  ACCURRENTDENSITY AVERAGE 0.28 ;
  DCCURRENTDENSITY AVERAGE 0.18 ;
  ANTENNAMODEL OXIDE1 ;
  ANTENNAAREARATIO 20.0 ;
END Via1


LAYER MT2
    TYPE ROUTING ;
    DIRECTION VERTICAL ;

    PITCH 2 ;
    OFFSET 0.0 ;  

    MINWIDTH 0.280 ;
    WIDTH 0.350 ;                        # Mn.1  (n>1)
    SPACING 0.280 ;                      # Mn.2a (n>1)
    SPACING 0.300 RANGE 10.005 999.00 ;  # Mn.2b
    AREA 0.1444 ;                        # Mn.3

    THICKNESS 0.54 ;
    ANTENNAMODEL OXIDE1 ;
    ANTENNADIFFSIDEAREARATIO 400 ;
    ANTENNAGATEPLUSDIFF 2 ;

    DCCURRENTDENSITY AVERAGE 0.67 ;
    ACCURRENTDENSITY AVERAGE 1.00 ;

    CAPACITANCE CPERSQDIST 0.0000394 ;
    RESISTANCE RPERSQ 0.090000 ;

    MINIMUMDENSITY 30.0 ;
    DENSITYCHECKWINDOW 200.0 200.0 ;
    DENSITYCHECKSTEP 100.0 ;

END MT2

#------------------------------------------------------------
#  Via1 VIA SECTION 
#------------------------------------------------------------
 VIA Via1_HH  DEFAULT
 RESISTANCE 4.500 ;
 LAYER Via1 ;
 RECT -0.130 -0.130 0.130 0.130 ;
 LAYER MT1 ;
 RECT -0.190 -0.130 0.190 0.130 ;
 LAYER MT2 ;
 RECT -0.190 -0.140 0.190 0.140 ;
 END Via1_HH 
 
 VIA Via1_HV  DEFAULT
 RESISTANCE 4.500 ;
 LAYER Via1 ;
 RECT -0.15 -0.15 0.15 0.15 ;
 LAYER MT1 ;
 RECT -0.2 -0.2 0.2 0.2 ;
 LAYER MT2 ;
 RECT -0.2 -0.2 0.2 0.2 ;
 END Via1_HV 
 
 VIA Via1_VH  DEFAULT
 RESISTANCE 4.500 ;
 LAYER Via1 ;
 RECT -0.15 -0.15 0.15 0.15 ;
 LAYER MT1 ;
 RECT -0.2 -0.2 0.2 0.2 ;
 LAYER MT2 ;
 RECT -0.2 -0.2 0.2 0.2 ;
 END Via1_VH 
 
 VIA Via1_VV  DEFAULT
 RESISTANCE 4.500 ;
 LAYER Via1 ;
 RECT -0.15 -0.15 0.15 0.15 ;
 LAYER MT1 ;
 RECT -0.2 -0.2 0.2 0.2 ;
 LAYER MT2 ;
 RECT -0.2 -0.2 0.2 0.2 ;
 END Via1_VV 
 
 VIA Via1_2CUT_H
 LAYER Via1 ;
 RECT -0.390 -0.130 -0.130 0.130 ;
 RECT 0.130 -0.130 0.390 0.130 ;
 LAYER MT1 ;
 RECT -0.450 -0.130 0.450 0.130 ;
 LAYER MT2 ;
 RECT -0.400 -0.190 0.400 0.190 ;
 END Via1_2CUT_H
 
 VIA Via1_2CUT_V
 LAYER Via1 ;
 RECT -0.130 -0.390 0.130 -0.130 ;
 RECT -0.130 0.130 0.130 0.390 ;
 LAYER MT1 ;
 RECT -0.190 -0.390 0.190 0.390 ;
 LAYER MT2 ;
 RECT -0.140 -0.450 0.140 0.450 ;
 END Via1_2CUT_V
 
 VIA Via1_2X2_0_60_10_60_H_H  DEFAULT
 LAYER Via1 ;
 RECT -0.390 -0.390 -0.130 -0.130 ;
 RECT 0.130 -0.390 0.390 -0.130 ;
 RECT -0.390 0.130 -0.130 0.390 ;
 RECT 0.130 0.130 0.390 0.390 ;
 LAYER MT1 ;
 RECT -0.450 -0.390 0.450 0.390 ;
 LAYER MT2 ;
 RECT -0.450 -0.400 0.450 0.400 ;
 END Via1_2X2_0_60_10_60_H_H 
 
 VIA Via1_2X2_0_60_10_60_H_V  DEFAULT
 LAYER Via1 ;
 RECT -0.390 -0.390 -0.130 -0.130 ;
 RECT 0.130 -0.390 0.390 -0.130 ;
 RECT -0.390 0.130 -0.130 0.390 ;
 RECT 0.130 0.130 0.390 0.390 ;
 LAYER MT1 ;
 RECT -0.450 -0.390 0.450 0.390 ;
 LAYER MT2 ;
 RECT -0.400 -0.450 0.400 0.450 ;
 END Via1_2X2_0_60_10_60_H_V 
 
 VIA Via1_2X2_0_60_10_60_V_H  DEFAULT
 LAYER Via1 ;
 RECT -0.390 -0.390 -0.130 -0.130 ;
 RECT 0.130 -0.390 0.390 -0.130 ;
 RECT -0.390 0.130 -0.130 0.390 ;
 RECT 0.130 0.130 0.390 0.390 ;
 LAYER MT1 ;
 RECT -0.390 -0.450 0.390 0.450 ;
 LAYER MT2 ;
 RECT -0.450 -0.400 0.450 0.400 ;
 END Via1_2X2_0_60_10_60_V_H 
 
 VIA Via1_2X2_0_60_10_60_V_V  DEFAULT
 LAYER Via1 ;
 RECT -0.390 -0.390 -0.130 -0.130 ;
 RECT 0.130 -0.390 0.390 -0.130 ;
 RECT -0.390 0.130 -0.130 0.390 ;
 RECT 0.130 0.130 0.390 0.390 ;
 LAYER MT1 ;
 RECT -0.390 -0.450 0.390 0.450 ;
 LAYER MT2 ;
 RECT -0.400 -0.450 0.400 0.450 ;
 END Via1_2X2_0_60_10_60_V_V 
 
VIARULE Via1_GEN_HH GENERATE
  LAYER MT1 ;
    ENCLOSURE 0.060 0.000 ;
  LAYER MT2 ;
    ENCLOSURE 0.060 0.010 ;
  LAYER Via1 ;
    RECT -0.130 -0.130 0.130 0.130 ;
    SPACING 0.520 BY 0.520 ;
END Via1_GEN_HH

VIARULE Via1_GEN_HV GENERATE
  LAYER MT1 ;
    ENCLOSURE 0.060 0.000 ;
  LAYER MT2 ;
    ENCLOSURE 0.010 0.060 ;
  LAYER Via1 ;
    RECT -0.130 -0.130 0.130 0.130 ;
    SPACING 0.520 BY 0.520 ;
END Via1_GEN_HV

VIARULE Via1_GEN_VH GENERATE
  LAYER MT1 ;
    ENCLOSURE 0.000 0.060 ;
  LAYER MT2 ;
    ENCLOSURE 0.060 0.010 ;
  LAYER Via1 ;
    RECT -0.130 -0.130 0.130 0.130 ;
    SPACING 0.520 BY 0.520 ;
END Via1_GEN_VH

VIARULE Via1_GEN_VV GENERATE
  LAYER MT1 ;
    ENCLOSURE 0.000 0.060 ;
  LAYER MT2 ;
    ENCLOSURE 0.010 0.060 ;
  LAYER Via1 ;
    RECT -0.130 -0.130 0.130 0.130 ;
    SPACING 0.520 BY 0.520 ;
END Via1_GEN_VV

 VIA Via1_4X4H_HH_DEFAULT  DEFAULT
 LAYER Via1 ;
 RECT -1.060 -1.060 -0.800 -0.800 ;
 RECT -0.440 -1.060 -0.180 -0.800 ;
 RECT 0.180 -1.060 0.440 -0.800 ;
 RECT 0.800 -1.060 1.060 -0.800 ;
 RECT -1.060 -0.440 -0.800 -0.180 ;
 RECT -0.440 -0.440 -0.180 -0.180 ;
 RECT 0.180 -0.440 0.440 -0.180 ;
 RECT 0.800 -0.440 1.060 -0.180 ;
 RECT -1.060 0.180 -0.800 0.440 ;
 RECT -0.440 0.180 -0.180 0.440 ;
 RECT 0.180 0.180 0.440 0.440 ;
 RECT 0.800 0.180 1.060 0.440 ;
 RECT -1.060 0.800 -0.800 1.060 ;
 RECT -0.440 0.800 -0.180 1.060 ;
 RECT 0.180 0.800 0.440 1.060 ;
 RECT 0.800 0.800 1.060 1.060 ;
 LAYER MT1 ;
 RECT -1.120 -1.060 1.120 1.060 ;
 LAYER MT2 ;
 RECT -1.120 -1.070 1.120 1.070 ;
 END Via1_4X4H_HH_DEFAULT 
 
 VIA Via1_4X4H_HV_DEFAULT  DEFAULT
 LAYER Via1 ;
 RECT -1.060 -1.060 -0.800 -0.800 ;
 RECT -0.440 -1.060 -0.180 -0.800 ;
 RECT 0.180 -1.060 0.440 -0.800 ;
 RECT 0.800 -1.060 1.060 -0.800 ;
 RECT -1.060 -0.440 -0.800 -0.180 ;
 RECT -0.440 -0.440 -0.180 -0.180 ;
 RECT 0.180 -0.440 0.440 -0.180 ;
 RECT 0.800 -0.440 1.060 -0.180 ;
 RECT -1.060 0.180 -0.800 0.440 ;
 RECT -0.440 0.180 -0.180 0.440 ;
 RECT 0.180 0.180 0.440 0.440 ;
 RECT 0.800 0.180 1.060 0.440 ;
 RECT -1.060 0.800 -0.800 1.060 ;
 RECT -0.440 0.800 -0.180 1.060 ;
 RECT 0.180 0.800 0.440 1.060 ;
 RECT 0.800 0.800 1.060 1.060 ;
 LAYER MT1 ;
 RECT -1.120 -1.060 1.120 1.060 ;
 LAYER MT2 ;
 RECT -1.070 -1.120 1.070 1.120 ;
 END Via1_4X4H_HV_DEFAULT 
 
 VIA Via1_4X4H_VH_DEFAULT  DEFAULT
 LAYER Via1 ;
 RECT -1.060 -1.060 -0.800 -0.800 ;
 RECT -0.440 -1.060 -0.180 -0.800 ;
 RECT 0.180 -1.060 0.440 -0.800 ;
 RECT 0.800 -1.060 1.060 -0.800 ;
 RECT -1.060 -0.440 -0.800 -0.180 ;
 RECT -0.440 -0.440 -0.180 -0.180 ;
 RECT 0.180 -0.440 0.440 -0.180 ;
 RECT 0.800 -0.440 1.060 -0.180 ;
 RECT -1.060 0.180 -0.800 0.440 ;
 RECT -0.440 0.180 -0.180 0.440 ;
 RECT 0.180 0.180 0.440 0.440 ;
 RECT 0.800 0.180 1.060 0.440 ;
 RECT -1.060 0.800 -0.800 1.060 ;
 RECT -0.440 0.800 -0.180 1.060 ;
 RECT 0.180 0.800 0.440 1.060 ;
 RECT 0.800 0.800 1.060 1.060 ;
 LAYER MT1 ;
 RECT -1.060 -1.120 1.060 1.120 ;
 LAYER MT2 ;
 RECT -1.120 -1.070 1.120 1.070 ;
 END Via1_4X4H_VH_DEFAULT 
 
 VIA Via1_4X4H_VV_DEFAULT  DEFAULT
 LAYER Via1 ;
 RECT -1.060 -1.060 -0.800 -0.800 ;
 RECT -0.440 -1.060 -0.180 -0.800 ;
 RECT 0.180 -1.060 0.440 -0.800 ;
 RECT 0.800 -1.060 1.060 -0.800 ;
 RECT -1.060 -0.440 -0.800 -0.180 ;
 RECT -0.440 -0.440 -0.180 -0.180 ;
 RECT 0.180 -0.440 0.440 -0.180 ;
 RECT 0.800 -0.440 1.060 -0.180 ;
 RECT -1.060 0.180 -0.800 0.440 ;
 RECT -0.440 0.180 -0.180 0.440 ;
 RECT 0.180 0.180 0.440 0.440 ;
 RECT 0.800 0.180 1.060 0.440 ;
 RECT -1.060 0.800 -0.800 1.060 ;
 RECT -0.440 0.800 -0.180 1.060 ;
 RECT 0.180 0.800 0.440 1.060 ;
 RECT 0.800 0.800 1.060 1.060 ;
 LAYER MT1 ;
 RECT -1.060 -1.120 1.060 1.120 ;
 LAYER MT2 ;
 RECT -1.070 -1.120 1.070 1.120 ;
 END Via1_4X4H_VV_DEFAULT

This is my amf_tech.lef file defining the MT1, Via1 and MT2 layers, it is really similar to the gf180mcu technology because I started from there.
I aim to change theses values to my foundries values (i.e. bigger tolerances) but I wanted to check if it was working before doing so.

pars97 Feb 27, 2025
Author

What I do see though is that my cells are glued together without space, and smaller that they are in the gds. They should not be touching. This is the KLayout view of the buffer_2 :

The brown layer is MT1. As we can see, the VDD/VSS rails extends past the Input and output squares. The squares are there to accomodate a via according to the tech values.

maliberty · 2025-02-27T03:55:05Z

maliberty
Feb 27, 2025
Maintainer

Likely you have a bad LEF abstract then. Is this something where you can share a test case?

5 replies

pars97 Feb 27, 2025
Author

I imagine you mean the LEF of the cells themselves, I can share a .gds file with it's LEF.

Example BUF_2.zip

I do have a longer file that appends all the LEF I create together, in the .zip, only the macro of the cell is present.

If you need the whole tech folder :
Tech_changes.zip

The .gds are generated by coding on GDSFactory and the LEF files are generated via a python coding that extracs the MT1 layer (with GDSFactory) and assign names sucha s VDD/VSS/I/Z/OBS to each metal entity.

I'll take a look at that LEF generation on my side today.

pars97 Feb 27, 2025
Author

I did some modifications to the fill cells. The LEF definition was wrong as I was not correctly naming CLASS core SPACER ;

This fix is making the cells not to be glued together no more :

Although, I still have the same problem at step 5.2, minus the warning :

==========================================================================
global route report_design_area
--------------------------------------------------------------------------
Design area 3773 u^2 13% utilization.
[INFO FLW-0007] clock core_clock period 10.000000
[INFO FLW-0008] Clock core_clock period 4.427
[INFO FLW-0009] Clock core_clock slack 5.340
[WARNING STA-0450] virtual clock core_clock can not be propagated.
[INFO FLW-0011] Path endpoint path count 1
Elapsed time: 0:01.12[h:]min:sec. CPU time: user 0.94 sys 0.24 (106%). Peak memory: 501436KB.
Running detail_route.tcl, stage 5_2_route
Signal 11 received
Stack trace:
 0# 0x0000559F977F1DF3 in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 1# 0x00007EFC717A0330 in /lib/x86_64-linux-gnu/libc.so.6
 2# odb::dbTrackGrid::getTechLayer() in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 3# odb::dbTrackGrid::getAverageTrackSpacing(int&, int&, int&) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 4# grt::GlobalRouter::initGrid(int) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 5# grt::GlobalRouter::initCoreGrid(int) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 6# grt::GlobalRouter::initGridAndNets() in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 7# 0x0000559F99C560B8 in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 8# grt::GlobalRouter::haveRoutes() in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
 9# 0x0000559F98017EF4 in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
10# TclNRRunCallbacks in /lib/x86_64-linux-gnu/libtcl8.6.so
11# 0x00007EFC760986BC in /lib/x86_64-linux-gnu/libtcl8.6.so
12# Tcl_EvalEx in /lib/x86_64-linux-gnu/libtcl8.6.so
13# Tcl_Eval in /lib/x86_64-linux-gnu/libtcl8.6.so
14# sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
15# 0x0000559F977F153F in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
16# Tcl_MainEx in /lib/x86_64-linux-gnu/libtcl8.6.so
17# main in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
18# 0x00007EFC717851CA in /lib/x86_64-linux-gnu/libc.so.6
19# __libc_start_main in /lib/x86_64-linux-gnu/libc.so.6
20# _start in /home/phars10/OPENROAD/OpenROAD-flow-scripts/tools/install/OpenROAD/bin/openroad
Command terminated by signal 11
Elapsed time: 0:01.58[h:]min:sec. CPU time: user 0.58 sys 0.13 (45%). Peak memory: 135520KB.
make[1]: *** [Makefile:764: do-5_2_route] Error 139
make: *** [Makefile:762: results/amf/nand2_1/base/5_2_route.odb] Error 2

pars97 Feb 27, 2025
Author

Looking further into it, i've noticed the Tieh and tiel cells were not classed correctly (similar to antenna). Furthermore, in amf_tech.lef, I was missing the END LIBRARY tag at the end of the file.

Sadly theses changes did not fix the issue I'm experiencing. I will continue to update this thread with the changes I've made and whether it changed the result or not.

pars97 Feb 27, 2025
Author

Another error in the .LEF that didnt change the output : the description of all VSS was incorrect.

PIN VSS
DIRECTION INOUT ;
USE ground ; is the correct thing instead of USE power ;

pars97 Feb 27, 2025
Author

Reviewing the step 5.1 I have this particular Warning :
[INFO GRT-0043] No OR_DEFAULT vias defined.

Does it mean it is not sure at what via to use between MT1 and MT2?

maliberty · 2025-02-27T03:57:17Z

maliberty
Feb 27, 2025
Maintainer

Two layer routing harkens back to the days of channel routing. I don't know that it is your problem here but I expect routing will be difficult on this process.

1 reply

pars97 Feb 27, 2025
Author

I've successfully routed that design on 2 layers of metal using GF180mcu technology (see attached) ... it shouldn't be an issue. You are quite right that routing will be difficult on the process, and not just because of the metal layers. Tolerances are not on par with standard electronics tech because this is mainly a photonic process that I try to make electronics work in.

GF180MCU_2layers.zip

pars97 · 2025-03-03T16:55:39Z

pars97
Mar 3, 2025
Author

I was reading this discussion here :#4165

I discovered that leaving a third metal layer that doesnt really exists in the LEF definition (with the via to access it) makes it that the routing is going more smoothly and the error is no more.

It does seem that the router is not able to take only to layer as an input but is able to route on only 2 layers.

2 replies

pars97 Mar 4, 2025
Author

To finalize my answer. I added a third fake metal layer and a via to it with the same spacing/width/pitch as of my last metal.
The router is now able to recognize and route my design, and produce a GDS. Thank you Mat for posting in the other discussion.

maliberty Mar 4, 2025
Maintainer

Glad it works. @osamahammad21 any thoughts on why this was necessary?

Troubles with triton route with new technology #6779

Uh oh!

pars97 Feb 26, 2025

Replies: 4 comments · 10 replies

Uh oh!

maliberty Feb 26, 2025 Maintainer

Uh oh!

pars97 Feb 27, 2025 Author

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pars97 Feb 27, 2025 Author

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maliberty Feb 27, 2025 Maintainer

Uh oh!

pars97 Feb 27, 2025 Author

Uh oh!

pars97 Feb 27, 2025 Author

Uh oh!

pars97 Feb 27, 2025 Author

Uh oh!

pars97 Feb 27, 2025 Author

Uh oh!

pars97 Feb 27, 2025 Author

Uh oh!

maliberty Feb 27, 2025 Maintainer

Uh oh!

pars97 Feb 27, 2025 Author

Uh oh!

pars97 Mar 3, 2025 Author

Uh oh!

pars97 Mar 4, 2025 Author

Uh oh!

maliberty Mar 4, 2025 Maintainer

pars97
Feb 26, 2025

Replies: 4 comments 10 replies

maliberty
Feb 26, 2025
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pars97 Feb 27, 2025
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pars97 Feb 27, 2025
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maliberty
Feb 27, 2025
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pars97 Feb 27, 2025
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pars97 Feb 27, 2025
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pars97 Feb 27, 2025
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pars97 Feb 27, 2025
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pars97 Feb 27, 2025
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maliberty
Feb 27, 2025
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pars97 Feb 27, 2025
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pars97
Mar 3, 2025
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pars97 Mar 4, 2025
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maliberty Mar 4, 2025
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